2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
47 #include <linux/list.h>
48 #include <linux/dma-mapping.h>
50 #include <linux/usb/ch9.h>
51 #include <linux/usb/gadget.h>
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
66 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
70 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
71 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
85 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
95 * Caller should take care of locking. This function will
96 * return 0 on success or -ETIMEDOUT.
98 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
104 * Wait until device controller is ready. Only applies to 1.94a and
107 if (dwc->revision >= DWC3_REVISION_194A) {
109 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
110 if (reg & DWC3_DSTS_DCNRD)
120 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
121 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
123 /* set requested state */
124 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
125 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
128 * The following code is racy when called from dwc3_gadget_wakeup,
129 * and is not needed, at least on newer versions
131 if (dwc->revision >= DWC3_REVISION_194A)
134 /* wait for a change in DSTS */
137 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
139 if (DWC3_DSTS_USBLNKST(reg) == state)
145 dev_vdbg(dwc->dev, "link state change request timed out\n");
151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
152 * @dwc: pointer to our context structure
154 * This function will a best effort FIFO allocation in order
155 * to improve FIFO usage and throughput, while still allowing
156 * us to enable as many endpoints as possible.
158 * Keep in mind that this operation will be highly dependent
159 * on the configured size for RAM1 - which contains TxFifo -,
160 * the amount of endpoints enabled on coreConsultant tool, and
161 * the width of the Master Bus.
163 * In the ideal world, we would always be able to satisfy the
164 * following equation:
166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
169 * Unfortunately, due to many variables that's not always the case.
171 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
173 int last_fifo_depth = 0;
179 if (!dwc->needs_fifo_resize)
182 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
183 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
185 /* MDWIDTH is represented in bits, we need it in bytes */
189 * FIXME For now we will only allocate 1 wMaxPacketSize space
190 * for each enabled endpoint, later patches will come to
191 * improve this algorithm so that we better use the internal
194 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
195 struct dwc3_ep *dep = dwc->eps[num];
196 int fifo_number = dep->number >> 1;
200 if (!(dep->number & 1))
203 if (!(dep->flags & DWC3_EP_ENABLED))
206 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
207 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
211 * REVISIT: the following assumes we will always have enough
212 * space available on the FIFO RAM for all possible use cases.
213 * Make sure that's true somehow and change FIFO allocation
216 * If we have Bulk or Isochronous endpoints, we want
217 * them to be able to be very, very fast. So we're giving
218 * those endpoints a fifo_size which is enough for 3 full
221 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
224 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
226 fifo_size |= (last_fifo_depth << 16);
228 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
229 dep->name, last_fifo_depth, fifo_size & 0xffff);
231 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
234 last_fifo_depth += (fifo_size & 0xffff);
240 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
243 struct dwc3 *dwc = dep->dwc;
246 if (req->request.num_mapped_sgs)
247 dep->busy_slot += req->request.num_mapped_sgs;
252 * Skip LINK TRB. We can't use req->trb and check for
253 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
254 * completed (not the LINK TRB).
256 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
257 usb_endpoint_xfer_isoc(dep->endpoint.desc))
260 list_del(&req->list);
263 if (req->request.status == -EINPROGRESS)
264 req->request.status = status;
266 if (dwc->ep0_bounced && dep->number == 0)
267 dwc->ep0_bounced = false;
269 usb_gadget_unmap_request(&dwc->gadget, &req->request,
272 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
273 req, dep->name, req->request.actual,
274 req->request.length, status);
276 spin_unlock(&dwc->lock);
277 req->request.complete(&dep->endpoint, &req->request);
278 spin_lock(&dwc->lock);
281 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
284 case DWC3_DEPCMD_DEPSTARTCFG:
285 return "Start New Configuration";
286 case DWC3_DEPCMD_ENDTRANSFER:
287 return "End Transfer";
288 case DWC3_DEPCMD_UPDATETRANSFER:
289 return "Update Transfer";
290 case DWC3_DEPCMD_STARTTRANSFER:
291 return "Start Transfer";
292 case DWC3_DEPCMD_CLEARSTALL:
293 return "Clear Stall";
294 case DWC3_DEPCMD_SETSTALL:
296 case DWC3_DEPCMD_GETEPSTATE:
297 return "Get Endpoint State";
298 case DWC3_DEPCMD_SETTRANSFRESOURCE:
299 return "Set Endpoint Transfer Resource";
300 case DWC3_DEPCMD_SETEPCONFIG:
301 return "Set Endpoint Configuration";
303 return "UNKNOWN command";
307 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
312 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
313 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
316 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
317 if (!(reg & DWC3_DGCMD_CMDACT)) {
318 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
319 DWC3_DGCMD_STATUS(reg));
324 * We can't sleep here, because it's also called from
334 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
335 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
337 struct dwc3_ep *dep = dwc->eps[ep];
341 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
343 dwc3_gadget_ep_cmd_string(cmd), params->param0,
344 params->param1, params->param2);
346 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
347 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
348 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
350 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
352 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
353 if (!(reg & DWC3_DEPCMD_CMDACT)) {
354 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
355 DWC3_DEPCMD_STATUS(reg));
360 * We can't sleep here, because it is also called from
371 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
372 struct dwc3_trb *trb)
374 u32 offset = (char *) trb - (char *) dep->trb_pool;
376 return dep->trb_pool_dma + offset;
379 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
381 struct dwc3 *dwc = dep->dwc;
386 if (dep->number == 0 || dep->number == 1)
389 dep->trb_pool = dma_alloc_coherent(dwc->dev,
390 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
391 &dep->trb_pool_dma, GFP_KERNEL);
392 if (!dep->trb_pool) {
393 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
401 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
403 struct dwc3 *dwc = dep->dwc;
405 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
406 dep->trb_pool, dep->trb_pool_dma);
408 dep->trb_pool = NULL;
409 dep->trb_pool_dma = 0;
412 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
414 struct dwc3_gadget_ep_cmd_params params;
417 memset(¶ms, 0x00, sizeof(params));
419 if (dep->number != 1) {
420 cmd = DWC3_DEPCMD_DEPSTARTCFG;
421 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
422 if (dep->number > 1) {
423 if (dwc->start_config_issued)
425 dwc->start_config_issued = true;
426 cmd |= DWC3_DEPCMD_PARAM(2);
429 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
435 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
436 const struct usb_endpoint_descriptor *desc,
437 const struct usb_ss_ep_comp_descriptor *comp_desc,
440 struct dwc3_gadget_ep_cmd_params params;
442 memset(¶ms, 0x00, sizeof(params));
444 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
445 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
447 /* Burst size is only needed in SuperSpeed mode */
448 if (dwc->gadget.speed == USB_SPEED_SUPER) {
449 u32 burst = dep->endpoint.maxburst - 1;
451 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
455 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
457 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
458 | DWC3_DEPCFG_XFER_NOT_READY_EN;
460 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
461 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
462 | DWC3_DEPCFG_STREAM_EVENT_EN;
463 dep->stream_capable = true;
466 if (usb_endpoint_xfer_isoc(desc))
467 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
470 * We are doing 1:1 mapping for endpoints, meaning
471 * Physical Endpoints 2 maps to Logical Endpoint 2 and
472 * so on. We consider the direction bit as part of the physical
473 * endpoint number. So USB endpoint 0x81 is 0x03.
475 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
478 * We must use the lower 16 TX FIFOs even though
482 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
484 if (desc->bInterval) {
485 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
486 dep->interval = 1 << (desc->bInterval - 1);
489 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
490 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
493 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
495 struct dwc3_gadget_ep_cmd_params params;
497 memset(¶ms, 0x00, sizeof(params));
499 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
501 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
502 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
506 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
507 * @dep: endpoint to be initialized
508 * @desc: USB Endpoint Descriptor
510 * Caller should take care of locking
512 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
513 const struct usb_endpoint_descriptor *desc,
514 const struct usb_ss_ep_comp_descriptor *comp_desc,
517 struct dwc3 *dwc = dep->dwc;
521 if (!(dep->flags & DWC3_EP_ENABLED)) {
522 ret = dwc3_gadget_start_config(dwc, dep);
527 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore);
531 if (!(dep->flags & DWC3_EP_ENABLED)) {
532 struct dwc3_trb *trb_st_hw;
533 struct dwc3_trb *trb_link;
535 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
539 dep->endpoint.desc = desc;
540 dep->comp_desc = comp_desc;
541 dep->type = usb_endpoint_type(desc);
542 dep->flags |= DWC3_EP_ENABLED;
544 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
545 reg |= DWC3_DALEPENA_EP(dep->number);
546 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
548 if (!usb_endpoint_xfer_isoc(desc))
551 memset(&trb_link, 0, sizeof(trb_link));
553 /* Link TRB for ISOC. The HWO bit is never reset */
554 trb_st_hw = &dep->trb_pool[0];
556 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
558 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
559 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
560 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
561 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
567 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
568 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
570 struct dwc3_request *req;
572 if (!list_empty(&dep->req_queued)) {
573 dwc3_stop_active_transfer(dwc, dep->number);
575 /* - giveback all requests to gadget driver */
576 while (!list_empty(&dep->req_queued)) {
577 req = next_request(&dep->req_queued);
579 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
583 while (!list_empty(&dep->request_list)) {
584 req = next_request(&dep->request_list);
586 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
591 * __dwc3_gadget_ep_disable - Disables a HW endpoint
592 * @dep: the endpoint to disable
594 * This function also removes requests which are currently processed ny the
595 * hardware and those which are not yet scheduled.
596 * Caller should take care of locking.
598 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
600 struct dwc3 *dwc = dep->dwc;
603 dwc3_remove_requests(dwc, dep);
605 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
606 reg &= ~DWC3_DALEPENA_EP(dep->number);
607 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
609 dep->stream_capable = false;
610 dep->endpoint.desc = NULL;
611 dep->comp_desc = NULL;
618 /* -------------------------------------------------------------------------- */
620 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
621 const struct usb_endpoint_descriptor *desc)
626 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
631 /* -------------------------------------------------------------------------- */
633 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
634 const struct usb_endpoint_descriptor *desc)
641 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
642 pr_debug("dwc3: invalid parameters\n");
646 if (!desc->wMaxPacketSize) {
647 pr_debug("dwc3: missing wMaxPacketSize\n");
651 dep = to_dwc3_ep(ep);
654 if (dep->flags & DWC3_EP_ENABLED) {
655 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
660 switch (usb_endpoint_type(desc)) {
661 case USB_ENDPOINT_XFER_CONTROL:
662 strlcat(dep->name, "-control", sizeof(dep->name));
664 case USB_ENDPOINT_XFER_ISOC:
665 strlcat(dep->name, "-isoc", sizeof(dep->name));
667 case USB_ENDPOINT_XFER_BULK:
668 strlcat(dep->name, "-bulk", sizeof(dep->name));
670 case USB_ENDPOINT_XFER_INT:
671 strlcat(dep->name, "-int", sizeof(dep->name));
674 dev_err(dwc->dev, "invalid endpoint transfer type\n");
677 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
679 spin_lock_irqsave(&dwc->lock, flags);
680 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false);
681 spin_unlock_irqrestore(&dwc->lock, flags);
686 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
694 pr_debug("dwc3: invalid parameters\n");
698 dep = to_dwc3_ep(ep);
701 if (!(dep->flags & DWC3_EP_ENABLED)) {
702 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
707 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
709 (dep->number & 1) ? "in" : "out");
711 spin_lock_irqsave(&dwc->lock, flags);
712 ret = __dwc3_gadget_ep_disable(dep);
713 spin_unlock_irqrestore(&dwc->lock, flags);
718 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
721 struct dwc3_request *req;
722 struct dwc3_ep *dep = to_dwc3_ep(ep);
723 struct dwc3 *dwc = dep->dwc;
725 req = kzalloc(sizeof(*req), gfp_flags);
727 dev_err(dwc->dev, "not enough memory\n");
731 req->epnum = dep->number;
734 return &req->request;
737 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
738 struct usb_request *request)
740 struct dwc3_request *req = to_dwc3_request(request);
746 * dwc3_prepare_one_trb - setup one TRB from one request
747 * @dep: endpoint for which this request is prepared
748 * @req: dwc3_request pointer
750 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
751 struct dwc3_request *req, dma_addr_t dma,
752 unsigned length, unsigned last, unsigned chain)
754 struct dwc3 *dwc = dep->dwc;
755 struct dwc3_trb *trb;
757 unsigned int cur_slot;
759 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
760 dep->name, req, (unsigned long long) dma,
761 length, last ? " last" : "",
762 chain ? " chain" : "");
764 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
765 cur_slot = dep->free_slot;
768 /* Skip the LINK-TRB on ISOC */
769 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
770 usb_endpoint_xfer_isoc(dep->endpoint.desc))
774 dwc3_gadget_move_request_queued(req);
776 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
779 trb->size = DWC3_TRB_SIZE_LENGTH(length);
780 trb->bpl = lower_32_bits(dma);
781 trb->bph = upper_32_bits(dma);
783 switch (usb_endpoint_type(dep->endpoint.desc)) {
784 case USB_ENDPOINT_XFER_CONTROL:
785 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
788 case USB_ENDPOINT_XFER_ISOC:
789 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
791 if (!req->request.no_interrupt)
792 trb->ctrl |= DWC3_TRB_CTRL_IOC;
795 case USB_ENDPOINT_XFER_BULK:
796 case USB_ENDPOINT_XFER_INT:
797 trb->ctrl = DWC3_TRBCTL_NORMAL;
801 * This is only possible with faulty memory because we
802 * checked it already :)
807 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
808 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
809 trb->ctrl |= DWC3_TRB_CTRL_CSP;
812 trb->ctrl |= DWC3_TRB_CTRL_CHN;
815 trb->ctrl |= DWC3_TRB_CTRL_LST;
818 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
819 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
821 trb->ctrl |= DWC3_TRB_CTRL_HWO;
825 * dwc3_prepare_trbs - setup TRBs from requests
826 * @dep: endpoint for which requests are being prepared
827 * @starting: true if the endpoint is idle and no requests are queued.
829 * The function goes through the requests list and sets up TRBs for the
830 * transfers. The function returns once there are no more TRBs available or
831 * it runs out of requests.
833 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
835 struct dwc3_request *req, *n;
838 unsigned int last_one = 0;
840 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
842 /* the first request must not be queued */
843 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
845 /* Can't wrap around on a non-isoc EP since there's no link TRB */
846 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
847 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
853 * If busy & slot are equal than it is either full or empty. If we are
854 * starting to process requests then we are empty. Otherwise we are
855 * full and don't do anything
860 trbs_left = DWC3_TRB_NUM;
862 * In case we start from scratch, we queue the ISOC requests
863 * starting from slot 1. This is done because we use ring
864 * buffer and have no LST bit to stop us. Instead, we place
865 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
866 * after the first request so we start at slot 1 and have
867 * 7 requests proceed before we hit the first IOC.
868 * Other transfer types don't use the ring buffer and are
869 * processed from the first TRB until the last one. Since we
870 * don't wrap around we have to start at the beginning.
872 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
881 /* The last TRB is a link TRB, not used for xfer */
882 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
885 list_for_each_entry_safe(req, n, &dep->request_list, list) {
889 if (req->request.num_mapped_sgs > 0) {
890 struct usb_request *request = &req->request;
891 struct scatterlist *sg = request->sg;
892 struct scatterlist *s;
895 for_each_sg(sg, s, request->num_mapped_sgs, i) {
896 unsigned chain = true;
898 length = sg_dma_len(s);
899 dma = sg_dma_address(s);
901 if (i == (request->num_mapped_sgs - 1) ||
914 dwc3_prepare_one_trb(dep, req, dma, length,
921 dma = req->request.dma;
922 length = req->request.length;
928 /* Is this the last request? */
929 if (list_is_last(&req->list, &dep->request_list))
932 dwc3_prepare_one_trb(dep, req, dma, length,
941 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
944 struct dwc3_gadget_ep_cmd_params params;
945 struct dwc3_request *req;
946 struct dwc3 *dwc = dep->dwc;
950 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
951 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
954 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
957 * If we are getting here after a short-out-packet we don't enqueue any
958 * new requests as we try to set the IOC bit only on the last request.
961 if (list_empty(&dep->req_queued))
962 dwc3_prepare_trbs(dep, start_new);
964 /* req points to the first request which will be sent */
965 req = next_request(&dep->req_queued);
967 dwc3_prepare_trbs(dep, start_new);
970 * req points to the first request where HWO changed from 0 to 1
972 req = next_request(&dep->req_queued);
975 dep->flags |= DWC3_EP_PENDING_REQUEST;
979 memset(¶ms, 0, sizeof(params));
980 params.param0 = upper_32_bits(req->trb_dma);
981 params.param1 = lower_32_bits(req->trb_dma);
984 cmd = DWC3_DEPCMD_STARTTRANSFER;
986 cmd = DWC3_DEPCMD_UPDATETRANSFER;
988 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
989 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
991 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
994 * FIXME we need to iterate over the list of requests
995 * here and stop, unmap, free and del each of the linked
996 * requests instead of what we do now.
998 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1000 list_del(&req->list);
1004 dep->flags |= DWC3_EP_BUSY;
1007 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1009 WARN_ON_ONCE(!dep->resource_index);
1015 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1016 struct dwc3_ep *dep, u32 cur_uf)
1020 if (list_empty(&dep->request_list)) {
1021 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1023 dep->flags |= DWC3_EP_PENDING_REQUEST;
1027 /* 4 micro frames in the future */
1028 uf = cur_uf + dep->interval * 4;
1030 __dwc3_gadget_kick_transfer(dep, uf, 1);
1033 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1034 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1038 mask = ~(dep->interval - 1);
1039 cur_uf = event->parameters & mask;
1041 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1044 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1046 struct dwc3 *dwc = dep->dwc;
1049 req->request.actual = 0;
1050 req->request.status = -EINPROGRESS;
1051 req->direction = dep->direction;
1052 req->epnum = dep->number;
1055 * We only add to our list of requests now and
1056 * start consuming the list once we get XferNotReady
1059 * That way, we avoid doing anything that we don't need
1060 * to do now and defer it until the point we receive a
1061 * particular token from the Host side.
1063 * This will also avoid Host cancelling URBs due to too
1066 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1071 list_add_tail(&req->list, &dep->request_list);
1074 * There are a few special cases:
1076 * 1. XferNotReady with empty list of requests. We need to kick the
1077 * transfer here in that situation, otherwise we will be NAKing
1078 * forever. If we get XferNotReady before gadget driver has a
1079 * chance to queue a request, we will ACK the IRQ but won't be
1080 * able to receive the data until the next request is queued.
1081 * The following code is handling exactly that.
1084 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1088 * If xfernotready is already elapsed and it is a case
1089 * of isoc transfer, then issue END TRANSFER, so that
1090 * you can receive xfernotready again and can have
1091 * notion of current microframe.
1093 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1094 dwc3_stop_active_transfer(dwc, dep->number);
1098 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1099 if (ret && ret != -EBUSY)
1100 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1105 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1106 * kick the transfer here after queuing a request, otherwise the
1107 * core may not see the modified TRB(s).
1109 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1110 (dep->flags & DWC3_EP_BUSY) &&
1111 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1112 WARN_ON_ONCE(!dep->resource_index);
1113 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1115 if (ret && ret != -EBUSY)
1116 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1121 * 3. Missed ISOC Handling. We need to start isoc transfer on the saved
1124 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1125 (dep->flags & DWC3_EP_MISSED_ISOC)) {
1126 __dwc3_gadget_start_isoc(dwc, dep, dep->current_uf);
1127 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1133 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1136 struct dwc3_request *req = to_dwc3_request(request);
1137 struct dwc3_ep *dep = to_dwc3_ep(ep);
1138 struct dwc3 *dwc = dep->dwc;
1140 unsigned long flags;
1144 if (!dep->endpoint.desc) {
1145 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1150 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1151 request, ep->name, request->length);
1153 spin_lock_irqsave(&dwc->lock, flags);
1154 ret = __dwc3_gadget_ep_queue(dep, req);
1155 spin_unlock_irqrestore(&dwc->lock, flags);
1160 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1161 struct usb_request *request)
1163 struct dwc3_request *req = to_dwc3_request(request);
1164 struct dwc3_request *r = NULL;
1166 struct dwc3_ep *dep = to_dwc3_ep(ep);
1167 struct dwc3 *dwc = dep->dwc;
1169 unsigned long flags;
1172 spin_lock_irqsave(&dwc->lock, flags);
1174 list_for_each_entry(r, &dep->request_list, list) {
1180 list_for_each_entry(r, &dep->req_queued, list) {
1185 /* wait until it is processed */
1186 dwc3_stop_active_transfer(dwc, dep->number);
1189 dev_err(dwc->dev, "request %p was not queued to %s\n",
1196 /* giveback the request */
1197 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1200 spin_unlock_irqrestore(&dwc->lock, flags);
1205 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1207 struct dwc3_gadget_ep_cmd_params params;
1208 struct dwc3 *dwc = dep->dwc;
1211 memset(¶ms, 0x00, sizeof(params));
1214 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1215 DWC3_DEPCMD_SETSTALL, ¶ms);
1217 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1218 value ? "set" : "clear",
1221 dep->flags |= DWC3_EP_STALL;
1223 if (dep->flags & DWC3_EP_WEDGE)
1226 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1227 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1229 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1230 value ? "set" : "clear",
1233 dep->flags &= ~DWC3_EP_STALL;
1239 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1241 struct dwc3_ep *dep = to_dwc3_ep(ep);
1242 struct dwc3 *dwc = dep->dwc;
1244 unsigned long flags;
1248 spin_lock_irqsave(&dwc->lock, flags);
1250 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1251 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1256 ret = __dwc3_gadget_ep_set_halt(dep, value);
1258 spin_unlock_irqrestore(&dwc->lock, flags);
1263 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1265 struct dwc3_ep *dep = to_dwc3_ep(ep);
1266 struct dwc3 *dwc = dep->dwc;
1267 unsigned long flags;
1269 spin_lock_irqsave(&dwc->lock, flags);
1270 dep->flags |= DWC3_EP_WEDGE;
1271 spin_unlock_irqrestore(&dwc->lock, flags);
1273 if (dep->number == 0 || dep->number == 1)
1274 return dwc3_gadget_ep0_set_halt(ep, 1);
1276 return dwc3_gadget_ep_set_halt(ep, 1);
1279 /* -------------------------------------------------------------------------- */
1281 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1282 .bLength = USB_DT_ENDPOINT_SIZE,
1283 .bDescriptorType = USB_DT_ENDPOINT,
1284 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1287 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1288 .enable = dwc3_gadget_ep0_enable,
1289 .disable = dwc3_gadget_ep0_disable,
1290 .alloc_request = dwc3_gadget_ep_alloc_request,
1291 .free_request = dwc3_gadget_ep_free_request,
1292 .queue = dwc3_gadget_ep0_queue,
1293 .dequeue = dwc3_gadget_ep_dequeue,
1294 .set_halt = dwc3_gadget_ep0_set_halt,
1295 .set_wedge = dwc3_gadget_ep_set_wedge,
1298 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1299 .enable = dwc3_gadget_ep_enable,
1300 .disable = dwc3_gadget_ep_disable,
1301 .alloc_request = dwc3_gadget_ep_alloc_request,
1302 .free_request = dwc3_gadget_ep_free_request,
1303 .queue = dwc3_gadget_ep_queue,
1304 .dequeue = dwc3_gadget_ep_dequeue,
1305 .set_halt = dwc3_gadget_ep_set_halt,
1306 .set_wedge = dwc3_gadget_ep_set_wedge,
1309 /* -------------------------------------------------------------------------- */
1311 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1313 struct dwc3 *dwc = gadget_to_dwc(g);
1316 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1317 return DWC3_DSTS_SOFFN(reg);
1320 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1322 struct dwc3 *dwc = gadget_to_dwc(g);
1324 unsigned long timeout;
1325 unsigned long flags;
1334 spin_lock_irqsave(&dwc->lock, flags);
1337 * According to the Databook Remote wakeup request should
1338 * be issued only when the device is in early suspend state.
1340 * We can check that via USB Link State bits in DSTS register.
1342 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1344 speed = reg & DWC3_DSTS_CONNECTSPD;
1345 if (speed == DWC3_DSTS_SUPERSPEED) {
1346 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1351 link_state = DWC3_DSTS_USBLNKST(reg);
1353 switch (link_state) {
1354 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1355 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1358 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1364 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1366 dev_err(dwc->dev, "failed to put link in Recovery\n");
1370 /* Recent versions do this automatically */
1371 if (dwc->revision < DWC3_REVISION_194A) {
1372 /* write zeroes to Link Change Request */
1373 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1374 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1375 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1378 /* poll until Link State changes to ON */
1379 timeout = jiffies + msecs_to_jiffies(100);
1381 while (!time_after(jiffies, timeout)) {
1382 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1384 /* in HS, means ON */
1385 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1389 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1390 dev_err(dwc->dev, "failed to send remote wakeup\n");
1395 spin_unlock_irqrestore(&dwc->lock, flags);
1400 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1403 struct dwc3 *dwc = gadget_to_dwc(g);
1404 unsigned long flags;
1406 spin_lock_irqsave(&dwc->lock, flags);
1407 dwc->is_selfpowered = !!is_selfpowered;
1408 spin_unlock_irqrestore(&dwc->lock, flags);
1413 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1418 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1420 if (dwc->revision <= DWC3_REVISION_187A) {
1421 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1422 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1425 if (dwc->revision >= DWC3_REVISION_194A)
1426 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1427 reg |= DWC3_DCTL_RUN_STOP;
1429 reg &= ~DWC3_DCTL_RUN_STOP;
1432 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1435 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1437 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1440 if (reg & DWC3_DSTS_DEVCTRLHLT)
1449 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1451 ? dwc->gadget_driver->function : "no-function",
1452 is_on ? "connect" : "disconnect");
1457 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1459 struct dwc3 *dwc = gadget_to_dwc(g);
1460 unsigned long flags;
1465 spin_lock_irqsave(&dwc->lock, flags);
1466 ret = dwc3_gadget_run_stop(dwc, is_on);
1467 spin_unlock_irqrestore(&dwc->lock, flags);
1472 static int dwc3_gadget_start(struct usb_gadget *g,
1473 struct usb_gadget_driver *driver)
1475 struct dwc3 *dwc = gadget_to_dwc(g);
1476 struct dwc3_ep *dep;
1477 unsigned long flags;
1481 spin_lock_irqsave(&dwc->lock, flags);
1483 if (dwc->gadget_driver) {
1484 dev_err(dwc->dev, "%s is already bound to %s\n",
1486 dwc->gadget_driver->driver.name);
1491 dwc->gadget_driver = driver;
1492 dwc->gadget.dev.driver = &driver->driver;
1494 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1495 reg &= ~(DWC3_DCFG_SPEED_MASK);
1498 * WORKAROUND: DWC3 revision < 2.20a have an issue
1499 * which would cause metastability state on Run/Stop
1500 * bit if we try to force the IP to USB2-only mode.
1502 * Because of that, we cannot configure the IP to any
1503 * speed other than the SuperSpeed
1507 * STAR#9000525659: Clock Domain Crossing on DCTL in
1510 if (dwc->revision < DWC3_REVISION_220A)
1511 reg |= DWC3_DCFG_SUPERSPEED;
1513 reg |= dwc->maximum_speed;
1514 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1516 dwc->start_config_issued = false;
1518 /* Start with SuperSpeed Default */
1519 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1522 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1524 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1529 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1531 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1535 /* begin to receive SETUP packets */
1536 dwc->ep0state = EP0_SETUP_PHASE;
1537 dwc3_ep0_out_start(dwc);
1539 spin_unlock_irqrestore(&dwc->lock, flags);
1544 __dwc3_gadget_ep_disable(dwc->eps[0]);
1547 spin_unlock_irqrestore(&dwc->lock, flags);
1552 static int dwc3_gadget_stop(struct usb_gadget *g,
1553 struct usb_gadget_driver *driver)
1555 struct dwc3 *dwc = gadget_to_dwc(g);
1556 unsigned long flags;
1558 spin_lock_irqsave(&dwc->lock, flags);
1560 __dwc3_gadget_ep_disable(dwc->eps[0]);
1561 __dwc3_gadget_ep_disable(dwc->eps[1]);
1563 dwc->gadget_driver = NULL;
1564 dwc->gadget.dev.driver = NULL;
1566 spin_unlock_irqrestore(&dwc->lock, flags);
1571 static const struct usb_gadget_ops dwc3_gadget_ops = {
1572 .get_frame = dwc3_gadget_get_frame,
1573 .wakeup = dwc3_gadget_wakeup,
1574 .set_selfpowered = dwc3_gadget_set_selfpowered,
1575 .pullup = dwc3_gadget_pullup,
1576 .udc_start = dwc3_gadget_start,
1577 .udc_stop = dwc3_gadget_stop,
1580 /* -------------------------------------------------------------------------- */
1582 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1584 struct dwc3_ep *dep;
1587 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1589 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1590 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1592 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1598 dep->number = epnum;
1599 dwc->eps[epnum] = dep;
1601 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1602 (epnum & 1) ? "in" : "out");
1603 dep->endpoint.name = dep->name;
1604 dep->direction = (epnum & 1);
1606 if (epnum == 0 || epnum == 1) {
1607 dep->endpoint.maxpacket = 512;
1608 dep->endpoint.maxburst = 1;
1609 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1611 dwc->gadget.ep0 = &dep->endpoint;
1615 dep->endpoint.maxpacket = 1024;
1616 dep->endpoint.max_streams = 15;
1617 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1618 list_add_tail(&dep->endpoint.ep_list,
1619 &dwc->gadget.ep_list);
1621 ret = dwc3_alloc_trb_pool(dep);
1626 INIT_LIST_HEAD(&dep->request_list);
1627 INIT_LIST_HEAD(&dep->req_queued);
1633 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1635 struct dwc3_ep *dep;
1638 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1639 dep = dwc->eps[epnum];
1640 dwc3_free_trb_pool(dep);
1642 if (epnum != 0 && epnum != 1)
1643 list_del(&dep->endpoint.ep_list);
1649 static void dwc3_gadget_release(struct device *dev)
1651 dev_dbg(dev, "%s\n", __func__);
1654 /* -------------------------------------------------------------------------- */
1655 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1656 const struct dwc3_event_depevt *event, int status)
1658 struct dwc3_request *req;
1659 struct dwc3_trb *trb;
1661 unsigned int s_pkt = 0;
1662 unsigned int trb_status;
1665 req = next_request(&dep->req_queued);
1673 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1675 * We continue despite the error. There is not much we
1676 * can do. If we don't clean it up we loop forever. If
1677 * we skip the TRB then it gets overwritten after a
1678 * while since we use them in a ring buffer. A BUG()
1679 * would help. Lets hope that if this occurs, someone
1680 * fixes the root cause instead of looking away :)
1682 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1683 dep->name, req->trb);
1684 count = trb->size & DWC3_TRB_SIZE_MASK;
1686 if (dep->direction) {
1688 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1689 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1690 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1692 dep->current_uf = event->parameters &
1693 ~(dep->interval - 1);
1694 dep->flags |= DWC3_EP_MISSED_ISOC;
1696 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1698 status = -ECONNRESET;
1702 if (count && (event->status & DEPEVT_STATUS_SHORT))
1707 * We assume here we will always receive the entire data block
1708 * which we should receive. Meaning, if we program RX to
1709 * receive 4K but we receive only 2K, we assume that's all we
1710 * should receive and we simply bounce the request back to the
1711 * gadget driver for further processing.
1713 req->request.actual += req->request.length - count;
1714 dwc3_gadget_giveback(dep, req, status);
1717 if ((event->status & DEPEVT_STATUS_LST) &&
1718 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1719 DWC3_TRB_CTRL_HWO)))
1721 if ((event->status & DEPEVT_STATUS_IOC) &&
1722 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1726 if ((event->status & DEPEVT_STATUS_IOC) &&
1727 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1732 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1733 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1736 unsigned status = 0;
1739 if (event->status & DEPEVT_STATUS_BUSERR)
1740 status = -ECONNRESET;
1742 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1744 dep->flags &= ~DWC3_EP_BUSY;
1747 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1748 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1750 if (dwc->revision < DWC3_REVISION_183A) {
1754 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1757 if (!(dep->flags & DWC3_EP_ENABLED))
1760 if (!list_empty(&dep->req_queued))
1764 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1766 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1772 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1773 const struct dwc3_event_depevt *event)
1775 struct dwc3_ep *dep;
1776 u8 epnum = event->endpoint_number;
1778 dep = dwc->eps[epnum];
1780 if (!(dep->flags & DWC3_EP_ENABLED))
1783 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1784 dwc3_ep_event_string(event->endpoint_event));
1786 if (epnum == 0 || epnum == 1) {
1787 dwc3_ep0_interrupt(dwc, event);
1791 switch (event->endpoint_event) {
1792 case DWC3_DEPEVT_XFERCOMPLETE:
1793 dep->resource_index = 0;
1795 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1796 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1801 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1803 case DWC3_DEPEVT_XFERINPROGRESS:
1804 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1805 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1810 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1812 case DWC3_DEPEVT_XFERNOTREADY:
1813 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1814 dwc3_gadget_start_isoc(dwc, dep, event);
1818 dev_vdbg(dwc->dev, "%s: reason %s\n",
1819 dep->name, event->status &
1820 DEPEVT_STATUS_TRANSFER_ACTIVE
1822 : "Transfer Not Active");
1824 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1825 if (!ret || ret == -EBUSY)
1828 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1833 case DWC3_DEPEVT_STREAMEVT:
1834 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1835 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1840 switch (event->status) {
1841 case DEPEVT_STREAMEVT_FOUND:
1842 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1846 case DEPEVT_STREAMEVT_NOTFOUND:
1849 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1852 case DWC3_DEPEVT_RXTXFIFOEVT:
1853 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1855 case DWC3_DEPEVT_EPCMDCMPLT:
1856 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1861 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1863 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1864 spin_unlock(&dwc->lock);
1865 dwc->gadget_driver->disconnect(&dwc->gadget);
1866 spin_lock(&dwc->lock);
1870 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1872 struct dwc3_ep *dep;
1873 struct dwc3_gadget_ep_cmd_params params;
1877 dep = dwc->eps[epnum];
1879 if (!dep->resource_index)
1883 * NOTICE: We are violating what the Databook says about the
1884 * EndTransfer command. Ideally we would _always_ wait for the
1885 * EndTransfer Command Completion IRQ, but that's causing too
1886 * much trouble synchronizing between us and gadget driver.
1888 * We have discussed this with the IP Provider and it was
1889 * suggested to giveback all requests here, but give HW some
1890 * extra time to synchronize with the interconnect. We're using
1891 * an arbitraty 100us delay for that.
1893 * Note also that a similar handling was tested by Synopsys
1894 * (thanks a lot Paul) and nothing bad has come out of it.
1895 * In short, what we're doing is:
1897 * - Issue EndTransfer WITH CMDIOC bit set
1901 cmd = DWC3_DEPCMD_ENDTRANSFER;
1902 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1903 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1904 memset(¶ms, 0, sizeof(params));
1905 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1907 dep->resource_index = 0;
1908 dep->flags &= ~DWC3_EP_BUSY;
1912 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1916 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1917 struct dwc3_ep *dep;
1919 dep = dwc->eps[epnum];
1920 if (!(dep->flags & DWC3_EP_ENABLED))
1923 dwc3_remove_requests(dwc, dep);
1927 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1931 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1932 struct dwc3_ep *dep;
1933 struct dwc3_gadget_ep_cmd_params params;
1936 dep = dwc->eps[epnum];
1938 if (!(dep->flags & DWC3_EP_STALL))
1941 dep->flags &= ~DWC3_EP_STALL;
1943 memset(¶ms, 0, sizeof(params));
1944 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1945 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1950 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1954 dev_vdbg(dwc->dev, "%s\n", __func__);
1956 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1957 reg &= ~DWC3_DCTL_INITU1ENA;
1958 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1960 reg &= ~DWC3_DCTL_INITU2ENA;
1961 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1963 dwc3_disconnect_gadget(dwc);
1964 dwc->start_config_issued = false;
1966 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1967 dwc->setup_packet_pending = false;
1970 static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
1974 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1977 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1979 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1981 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1984 static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
1988 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1991 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1993 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1995 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1998 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2002 dev_vdbg(dwc->dev, "%s\n", __func__);
2005 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2006 * would cause a missing Disconnect Event if there's a
2007 * pending Setup Packet in the FIFO.
2009 * There's no suggested workaround on the official Bug
2010 * report, which states that "unless the driver/application
2011 * is doing any special handling of a disconnect event,
2012 * there is no functional issue".
2014 * Unfortunately, it turns out that we _do_ some special
2015 * handling of a disconnect event, namely complete all
2016 * pending transfers, notify gadget driver of the
2017 * disconnection, and so on.
2019 * Our suggested workaround is to follow the Disconnect
2020 * Event steps here, instead, based on a setup_packet_pending
2021 * flag. Such flag gets set whenever we have a XferNotReady
2022 * event on EP0 and gets cleared on XferComplete for the
2027 * STAR#9000466709: RTL: Device : Disconnect event not
2028 * generated if setup packet pending in FIFO
2030 if (dwc->revision < DWC3_REVISION_188A) {
2031 if (dwc->setup_packet_pending)
2032 dwc3_gadget_disconnect_interrupt(dwc);
2035 /* after reset -> Default State */
2036 dwc->dev_state = DWC3_DEFAULT_STATE;
2038 /* Recent versions support automatic phy suspend and don't need this */
2039 if (dwc->revision < DWC3_REVISION_194A) {
2041 dwc3_gadget_usb2_phy_suspend(dwc, false);
2042 dwc3_gadget_usb3_phy_suspend(dwc, false);
2045 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2046 dwc3_disconnect_gadget(dwc);
2048 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2049 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2050 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2051 dwc->test_mode = false;
2053 dwc3_stop_active_transfers(dwc);
2054 dwc3_clear_stall_all_ep(dwc);
2055 dwc->start_config_issued = false;
2057 /* Reset device address to zero */
2058 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2059 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2060 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2063 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2066 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2069 * We change the clock only at SS but I dunno why I would want to do
2070 * this. Maybe it becomes part of the power saving plan.
2073 if (speed != DWC3_DSTS_SUPERSPEED)
2077 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2078 * each time on Connect Done.
2083 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2084 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2085 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2088 static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
2091 case USB_SPEED_SUPER:
2092 dwc3_gadget_usb2_phy_suspend(dwc, true);
2094 case USB_SPEED_HIGH:
2095 case USB_SPEED_FULL:
2097 dwc3_gadget_usb3_phy_suspend(dwc, true);
2102 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2104 struct dwc3_gadget_ep_cmd_params params;
2105 struct dwc3_ep *dep;
2110 dev_vdbg(dwc->dev, "%s\n", __func__);
2112 memset(¶ms, 0x00, sizeof(params));
2114 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2115 speed = reg & DWC3_DSTS_CONNECTSPD;
2118 dwc3_update_ram_clk_sel(dwc, speed);
2121 case DWC3_DCFG_SUPERSPEED:
2123 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2124 * would cause a missing USB3 Reset event.
2126 * In such situations, we should force a USB3 Reset
2127 * event by calling our dwc3_gadget_reset_interrupt()
2132 * STAR#9000483510: RTL: SS : USB3 reset event may
2133 * not be generated always when the link enters poll
2135 if (dwc->revision < DWC3_REVISION_190A)
2136 dwc3_gadget_reset_interrupt(dwc);
2138 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2139 dwc->gadget.ep0->maxpacket = 512;
2140 dwc->gadget.speed = USB_SPEED_SUPER;
2142 case DWC3_DCFG_HIGHSPEED:
2143 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2144 dwc->gadget.ep0->maxpacket = 64;
2145 dwc->gadget.speed = USB_SPEED_HIGH;
2147 case DWC3_DCFG_FULLSPEED2:
2148 case DWC3_DCFG_FULLSPEED1:
2149 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2150 dwc->gadget.ep0->maxpacket = 64;
2151 dwc->gadget.speed = USB_SPEED_FULL;
2153 case DWC3_DCFG_LOWSPEED:
2154 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2155 dwc->gadget.ep0->maxpacket = 8;
2156 dwc->gadget.speed = USB_SPEED_LOW;
2160 /* Recent versions support automatic phy suspend and don't need this */
2161 if (dwc->revision < DWC3_REVISION_194A) {
2162 /* Suspend unneeded PHY */
2163 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);
2167 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2169 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2174 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2176 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2181 * Configure PHY via GUSB3PIPECTLn if required.
2183 * Update GTXFIFOSIZn
2185 * In both cases reset values should be sufficient.
2189 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2191 dev_vdbg(dwc->dev, "%s\n", __func__);
2194 * TODO take core out of low power mode when that's
2198 dwc->gadget_driver->resume(&dwc->gadget);
2201 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2202 unsigned int evtinfo)
2204 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2207 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2208 * on the link partner, the USB session might do multiple entry/exit
2209 * of low power states before a transfer takes place.
2211 * Due to this problem, we might experience lower throughput. The
2212 * suggested workaround is to disable DCTL[12:9] bits if we're
2213 * transitioning from U1/U2 to U0 and enable those bits again
2214 * after a transfer completes and there are no pending transfers
2215 * on any of the enabled endpoints.
2217 * This is the first half of that workaround.
2221 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2222 * core send LGO_Ux entering U0
2224 if (dwc->revision < DWC3_REVISION_183A) {
2225 if (next == DWC3_LINK_STATE_U0) {
2229 switch (dwc->link_state) {
2230 case DWC3_LINK_STATE_U1:
2231 case DWC3_LINK_STATE_U2:
2232 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2233 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2234 | DWC3_DCTL_ACCEPTU2ENA
2235 | DWC3_DCTL_INITU1ENA
2236 | DWC3_DCTL_ACCEPTU1ENA);
2239 dwc->u1u2 = reg & u1u2;
2243 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2252 dwc->link_state = next;
2254 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2257 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2258 const struct dwc3_event_devt *event)
2260 switch (event->type) {
2261 case DWC3_DEVICE_EVENT_DISCONNECT:
2262 dwc3_gadget_disconnect_interrupt(dwc);
2264 case DWC3_DEVICE_EVENT_RESET:
2265 dwc3_gadget_reset_interrupt(dwc);
2267 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2268 dwc3_gadget_conndone_interrupt(dwc);
2270 case DWC3_DEVICE_EVENT_WAKEUP:
2271 dwc3_gadget_wakeup_interrupt(dwc);
2273 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2274 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2276 case DWC3_DEVICE_EVENT_EOPF:
2277 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2279 case DWC3_DEVICE_EVENT_SOF:
2280 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2282 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2283 dev_vdbg(dwc->dev, "Erratic Error\n");
2285 case DWC3_DEVICE_EVENT_CMD_CMPL:
2286 dev_vdbg(dwc->dev, "Command Complete\n");
2288 case DWC3_DEVICE_EVENT_OVERFLOW:
2289 dev_vdbg(dwc->dev, "Overflow\n");
2292 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2296 static void dwc3_process_event_entry(struct dwc3 *dwc,
2297 const union dwc3_event *event)
2299 /* Endpoint IRQ, handle it and return early */
2300 if (event->type.is_devspec == 0) {
2302 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2305 switch (event->type.type) {
2306 case DWC3_EVENT_TYPE_DEV:
2307 dwc3_gadget_interrupt(dwc, &event->devt);
2309 /* REVISIT what to do with Carkit and I2C events ? */
2311 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2315 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2317 struct dwc3_event_buffer *evt;
2321 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2322 count &= DWC3_GEVNTCOUNT_MASK;
2326 evt = dwc->ev_buffs[buf];
2330 union dwc3_event event;
2332 event.raw = *(u32 *) (evt->buf + evt->lpos);
2334 dwc3_process_event_entry(dwc, &event);
2336 * XXX we wrap around correctly to the next entry as almost all
2337 * entries are 4 bytes in size. There is one entry which has 12
2338 * bytes which is a regular entry followed by 8 bytes data. ATM
2339 * I don't know how things are organized if were get next to the
2340 * a boundary so I worry about that once we try to handle that.
2342 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2345 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2351 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2353 struct dwc3 *dwc = _dwc;
2355 irqreturn_t ret = IRQ_NONE;
2357 spin_lock(&dwc->lock);
2359 for (i = 0; i < dwc->num_event_buffers; i++) {
2362 status = dwc3_process_event_buf(dwc, i);
2363 if (status == IRQ_HANDLED)
2367 spin_unlock(&dwc->lock);
2373 * dwc3_gadget_init - Initializes gadget related registers
2374 * @dwc: pointer to our controller context structure
2376 * Returns 0 on success otherwise negative errno.
2378 int dwc3_gadget_init(struct dwc3 *dwc)
2384 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2385 &dwc->ctrl_req_addr, GFP_KERNEL);
2386 if (!dwc->ctrl_req) {
2387 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2392 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2393 &dwc->ep0_trb_addr, GFP_KERNEL);
2394 if (!dwc->ep0_trb) {
2395 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2400 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2401 if (!dwc->setup_buf) {
2402 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2407 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2408 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2410 if (!dwc->ep0_bounce) {
2411 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2416 dev_set_name(&dwc->gadget.dev, "gadget");
2418 dwc->gadget.ops = &dwc3_gadget_ops;
2419 dwc->gadget.max_speed = USB_SPEED_SUPER;
2420 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2421 dwc->gadget.dev.parent = dwc->dev;
2422 dwc->gadget.sg_supported = true;
2424 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2426 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
2427 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
2428 dwc->gadget.dev.release = dwc3_gadget_release;
2429 dwc->gadget.name = "dwc3-gadget";
2432 * REVISIT: Here we should clear all pending IRQs to be
2433 * sure we're starting from a well known location.
2436 ret = dwc3_gadget_init_endpoints(dwc);
2440 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2442 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2445 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2450 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2451 reg |= DWC3_DCFG_LPM_CAP;
2452 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2454 /* Enable all but Start and End of Frame IRQs */
2455 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2456 DWC3_DEVTEN_EVNTOVERFLOWEN |
2457 DWC3_DEVTEN_CMDCMPLTEN |
2458 DWC3_DEVTEN_ERRTICERREN |
2459 DWC3_DEVTEN_WKUPEVTEN |
2460 DWC3_DEVTEN_ULSTCNGEN |
2461 DWC3_DEVTEN_CONNECTDONEEN |
2462 DWC3_DEVTEN_USBRSTEN |
2463 DWC3_DEVTEN_DISCONNEVTEN);
2464 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2466 /* Enable USB2 LPM and automatic phy suspend only on recent versions */
2467 if (dwc->revision >= DWC3_REVISION_194A) {
2468 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2469 reg |= DWC3_DCFG_LPM_CAP;
2470 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2472 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2473 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2475 /* TODO: This should be configurable */
2476 reg |= DWC3_DCTL_HIRD_THRES(28);
2478 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2480 dwc3_gadget_usb2_phy_suspend(dwc, false);
2481 dwc3_gadget_usb3_phy_suspend(dwc, false);
2484 ret = device_register(&dwc->gadget.dev);
2486 dev_err(dwc->dev, "failed to register gadget device\n");
2487 put_device(&dwc->gadget.dev);
2491 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2493 dev_err(dwc->dev, "failed to register udc\n");
2500 device_unregister(&dwc->gadget.dev);
2503 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2507 dwc3_gadget_free_endpoints(dwc);
2510 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2511 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2514 kfree(dwc->setup_buf);
2517 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2518 dwc->ep0_trb, dwc->ep0_trb_addr);
2521 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2522 dwc->ctrl_req, dwc->ctrl_req_addr);
2528 void dwc3_gadget_exit(struct dwc3 *dwc)
2532 usb_del_gadget_udc(&dwc->gadget);
2533 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2535 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2538 dwc3_gadget_free_endpoints(dwc);
2540 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2541 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2543 kfree(dwc->setup_buf);
2545 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2546 dwc->ep0_trb, dwc->ep0_trb_addr);
2548 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2549 dwc->ctrl_req, dwc->ctrl_req_addr);
2551 device_unregister(&dwc->gadget.dev);