2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
84 return DWC3_DSTS_USBLNKST(reg);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc->revision >= DWC3_REVISION_194A) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc->revision >= DWC3_REVISION_194A)
131 /* wait for a change in DSTS */
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
136 if (DWC3_DSTS_USBLNKST(reg) == state)
142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
149 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
150 * @dwc: pointer to our context structure
152 * This function will a best effort FIFO allocation in order
153 * to improve FIFO usage and throughput, while still allowing
154 * us to enable as many endpoints as possible.
156 * Keep in mind that this operation will be highly dependent
157 * on the configured size for RAM1 - which contains TxFifo -,
158 * the amount of endpoints enabled on coreConsultant tool, and
159 * the width of the Master Bus.
161 * In the ideal world, we would always be able to satisfy the
162 * following equation:
164 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
165 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
167 * Unfortunately, due to many variables that's not always the case.
169 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
171 int last_fifo_depth = 0;
177 if (!dwc->needs_fifo_resize)
180 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
181 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
183 /* MDWIDTH is represented in bits, we need it in bytes */
187 * FIXME For now we will only allocate 1 wMaxPacketSize space
188 * for each enabled endpoint, later patches will come to
189 * improve this algorithm so that we better use the internal
192 for (num = 0; num < dwc->num_in_eps; num++) {
193 /* bit0 indicates direction; 1 means IN ep */
194 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
198 if (!(dep->flags & DWC3_EP_ENABLED))
201 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
202 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
206 * REVISIT: the following assumes we will always have enough
207 * space available on the FIFO RAM for all possible use cases.
208 * Make sure that's true somehow and change FIFO allocation
211 * If we have Bulk or Isochronous endpoints, we want
212 * them to be able to be very, very fast. So we're giving
213 * those endpoints a fifo_size which is enough for 3 full
216 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
219 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
221 fifo_size |= (last_fifo_depth << 16);
223 dwc3_trace(trace_dwc3_gadget, "%s: Fifo Addr %04x Size %d",
224 dep->name, last_fifo_depth, fifo_size & 0xffff);
226 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
228 last_fifo_depth += (fifo_size & 0xffff);
234 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
237 struct dwc3 *dwc = dep->dwc;
245 * Skip LINK TRB. We can't use req->trb and check for
246 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
247 * just completed (not the LINK TRB).
249 if (((dep->busy_slot & DWC3_TRB_MASK) ==
251 usb_endpoint_xfer_isoc(dep->endpoint.desc))
253 } while(++i < req->request.num_mapped_sgs);
256 list_del(&req->list);
259 if (req->request.status == -EINPROGRESS)
260 req->request.status = status;
262 if (dwc->ep0_bounced && dep->number == 0)
263 dwc->ep0_bounced = false;
265 usb_gadget_unmap_request(&dwc->gadget, &req->request,
268 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
269 req, dep->name, req->request.actual,
270 req->request.length, status);
271 trace_dwc3_gadget_giveback(req);
273 spin_unlock(&dwc->lock);
274 usb_gadget_giveback_request(&dep->endpoint, &req->request);
275 spin_lock(&dwc->lock);
278 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
283 trace_dwc3_gadget_generic_cmd(cmd, param);
285 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
286 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
289 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
290 if (!(reg & DWC3_DGCMD_CMDACT)) {
291 dwc3_trace(trace_dwc3_gadget,
292 "Command Complete --> %d",
293 DWC3_DGCMD_STATUS(reg));
294 if (DWC3_DGCMD_STATUS(reg))
300 * We can't sleep here, because it's also called from
305 dwc3_trace(trace_dwc3_gadget,
306 "Command Timed Out");
313 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
314 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
316 struct dwc3_ep *dep = dwc->eps[ep];
320 trace_dwc3_gadget_ep_cmd(dep, cmd, params);
322 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
323 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
324 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
326 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
328 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
329 if (!(reg & DWC3_DEPCMD_CMDACT)) {
330 dwc3_trace(trace_dwc3_gadget,
331 "Command Complete --> %d",
332 DWC3_DEPCMD_STATUS(reg));
333 if (DWC3_DEPCMD_STATUS(reg))
339 * We can't sleep here, because it is also called from
344 dwc3_trace(trace_dwc3_gadget,
345 "Command Timed Out");
353 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
354 struct dwc3_trb *trb)
356 u32 offset = (char *) trb - (char *) dep->trb_pool;
358 return dep->trb_pool_dma + offset;
361 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
363 struct dwc3 *dwc = dep->dwc;
368 dep->trb_pool = dma_alloc_coherent(dwc->dev,
369 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
370 &dep->trb_pool_dma, GFP_KERNEL);
371 if (!dep->trb_pool) {
372 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
380 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
382 struct dwc3 *dwc = dep->dwc;
384 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
385 dep->trb_pool, dep->trb_pool_dma);
387 dep->trb_pool = NULL;
388 dep->trb_pool_dma = 0;
391 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
393 struct dwc3_gadget_ep_cmd_params params;
396 memset(¶ms, 0x00, sizeof(params));
398 if (dep->number != 1) {
399 cmd = DWC3_DEPCMD_DEPSTARTCFG;
400 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
401 if (dep->number > 1) {
402 if (dwc->start_config_issued)
404 dwc->start_config_issued = true;
405 cmd |= DWC3_DEPCMD_PARAM(2);
408 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
414 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
415 const struct usb_endpoint_descriptor *desc,
416 const struct usb_ss_ep_comp_descriptor *comp_desc,
417 bool ignore, bool restore)
419 struct dwc3_gadget_ep_cmd_params params;
421 memset(¶ms, 0x00, sizeof(params));
423 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
424 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
426 /* Burst size is only needed in SuperSpeed mode */
427 if (dwc->gadget.speed == USB_SPEED_SUPER) {
428 u32 burst = dep->endpoint.maxburst - 1;
430 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
434 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
437 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
438 params.param2 |= dep->saved_state;
441 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
442 | DWC3_DEPCFG_XFER_NOT_READY_EN;
444 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
445 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
446 | DWC3_DEPCFG_STREAM_EVENT_EN;
447 dep->stream_capable = true;
450 if (!usb_endpoint_xfer_control(desc))
451 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
454 * We are doing 1:1 mapping for endpoints, meaning
455 * Physical Endpoints 2 maps to Logical Endpoint 2 and
456 * so on. We consider the direction bit as part of the physical
457 * endpoint number. So USB endpoint 0x81 is 0x03.
459 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
462 * We must use the lower 16 TX FIFOs even though
466 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
468 if (desc->bInterval) {
469 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
470 dep->interval = 1 << (desc->bInterval - 1);
473 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
474 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
477 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
479 struct dwc3_gadget_ep_cmd_params params;
481 memset(¶ms, 0x00, sizeof(params));
483 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
485 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
486 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
490 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
491 * @dep: endpoint to be initialized
492 * @desc: USB Endpoint Descriptor
494 * Caller should take care of locking
496 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
497 const struct usb_endpoint_descriptor *desc,
498 const struct usb_ss_ep_comp_descriptor *comp_desc,
499 bool ignore, bool restore)
501 struct dwc3 *dwc = dep->dwc;
505 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
507 if (!(dep->flags & DWC3_EP_ENABLED)) {
508 ret = dwc3_gadget_start_config(dwc, dep);
513 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
518 if (!(dep->flags & DWC3_EP_ENABLED)) {
519 struct dwc3_trb *trb_st_hw;
520 struct dwc3_trb *trb_link;
522 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
526 dep->endpoint.desc = desc;
527 dep->comp_desc = comp_desc;
528 dep->type = usb_endpoint_type(desc);
529 dep->flags |= DWC3_EP_ENABLED;
531 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
532 reg |= DWC3_DALEPENA_EP(dep->number);
533 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
535 if (!usb_endpoint_xfer_isoc(desc))
538 /* Link TRB for ISOC. The HWO bit is never reset */
539 trb_st_hw = &dep->trb_pool[0];
541 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
542 memset(trb_link, 0, sizeof(*trb_link));
544 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
545 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
546 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
547 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
550 switch (usb_endpoint_type(desc)) {
551 case USB_ENDPOINT_XFER_CONTROL:
552 strlcat(dep->name, "-control", sizeof(dep->name));
554 case USB_ENDPOINT_XFER_ISOC:
555 strlcat(dep->name, "-isoc", sizeof(dep->name));
557 case USB_ENDPOINT_XFER_BULK:
558 strlcat(dep->name, "-bulk", sizeof(dep->name));
560 case USB_ENDPOINT_XFER_INT:
561 strlcat(dep->name, "-int", sizeof(dep->name));
564 dev_err(dwc->dev, "invalid endpoint transfer type\n");
570 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
571 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
573 struct dwc3_request *req;
575 if (!list_empty(&dep->req_queued)) {
576 dwc3_stop_active_transfer(dwc, dep->number, true);
578 /* - giveback all requests to gadget driver */
579 while (!list_empty(&dep->req_queued)) {
580 req = next_request(&dep->req_queued);
582 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
586 while (!list_empty(&dep->request_list)) {
587 req = next_request(&dep->request_list);
589 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
594 * __dwc3_gadget_ep_disable - Disables a HW endpoint
595 * @dep: the endpoint to disable
597 * This function also removes requests which are currently processed ny the
598 * hardware and those which are not yet scheduled.
599 * Caller should take care of locking.
601 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
603 struct dwc3 *dwc = dep->dwc;
606 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
608 dwc3_remove_requests(dwc, dep);
610 /* make sure HW endpoint isn't stalled */
611 if (dep->flags & DWC3_EP_STALL)
612 __dwc3_gadget_ep_set_halt(dep, 0, false);
614 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
615 reg &= ~DWC3_DALEPENA_EP(dep->number);
616 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
618 dep->stream_capable = false;
619 dep->endpoint.desc = NULL;
620 dep->comp_desc = NULL;
624 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
626 (dep->number & 1) ? "in" : "out");
631 /* -------------------------------------------------------------------------- */
633 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
634 const struct usb_endpoint_descriptor *desc)
639 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
644 /* -------------------------------------------------------------------------- */
646 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
647 const struct usb_endpoint_descriptor *desc)
654 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
655 pr_debug("dwc3: invalid parameters\n");
659 if (!desc->wMaxPacketSize) {
660 pr_debug("dwc3: missing wMaxPacketSize\n");
664 dep = to_dwc3_ep(ep);
667 if (dep->flags & DWC3_EP_ENABLED) {
668 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
673 spin_lock_irqsave(&dwc->lock, flags);
674 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
675 spin_unlock_irqrestore(&dwc->lock, flags);
680 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
688 pr_debug("dwc3: invalid parameters\n");
692 dep = to_dwc3_ep(ep);
695 if (!(dep->flags & DWC3_EP_ENABLED)) {
696 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
701 spin_lock_irqsave(&dwc->lock, flags);
702 ret = __dwc3_gadget_ep_disable(dep);
703 spin_unlock_irqrestore(&dwc->lock, flags);
708 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
711 struct dwc3_request *req;
712 struct dwc3_ep *dep = to_dwc3_ep(ep);
714 req = kzalloc(sizeof(*req), gfp_flags);
718 req->epnum = dep->number;
721 trace_dwc3_alloc_request(req);
723 return &req->request;
726 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
727 struct usb_request *request)
729 struct dwc3_request *req = to_dwc3_request(request);
731 trace_dwc3_free_request(req);
736 * dwc3_prepare_one_trb - setup one TRB from one request
737 * @dep: endpoint for which this request is prepared
738 * @req: dwc3_request pointer
740 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
741 struct dwc3_request *req, dma_addr_t dma,
742 unsigned length, unsigned last, unsigned chain, unsigned node)
744 struct dwc3_trb *trb;
746 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
747 dep->name, req, (unsigned long long) dma,
748 length, last ? " last" : "",
749 chain ? " chain" : "");
752 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
755 dwc3_gadget_move_request_queued(req);
757 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
758 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
762 /* Skip the LINK-TRB on ISOC */
763 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
764 usb_endpoint_xfer_isoc(dep->endpoint.desc))
767 trb->size = DWC3_TRB_SIZE_LENGTH(length);
768 trb->bpl = lower_32_bits(dma);
769 trb->bph = upper_32_bits(dma);
771 switch (usb_endpoint_type(dep->endpoint.desc)) {
772 case USB_ENDPOINT_XFER_CONTROL:
773 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
776 case USB_ENDPOINT_XFER_ISOC:
778 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
780 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
783 case USB_ENDPOINT_XFER_BULK:
784 case USB_ENDPOINT_XFER_INT:
785 trb->ctrl = DWC3_TRBCTL_NORMAL;
789 * This is only possible with faulty memory because we
790 * checked it already :)
795 if (!req->request.no_interrupt && !chain)
796 trb->ctrl |= DWC3_TRB_CTRL_IOC;
798 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
799 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
800 trb->ctrl |= DWC3_TRB_CTRL_CSP;
802 trb->ctrl |= DWC3_TRB_CTRL_LST;
806 trb->ctrl |= DWC3_TRB_CTRL_CHN;
808 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
809 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
811 trb->ctrl |= DWC3_TRB_CTRL_HWO;
813 trace_dwc3_prepare_trb(dep, trb);
817 * dwc3_prepare_trbs - setup TRBs from requests
818 * @dep: endpoint for which requests are being prepared
819 * @starting: true if the endpoint is idle and no requests are queued.
821 * The function goes through the requests list and sets up TRBs for the
822 * transfers. The function returns once there are no more TRBs available or
823 * it runs out of requests.
825 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
827 struct dwc3_request *req, *n;
830 unsigned int last_one = 0;
832 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
834 /* the first request must not be queued */
835 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
837 /* Can't wrap around on a non-isoc EP since there's no link TRB */
838 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
839 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
845 * If busy & slot are equal than it is either full or empty. If we are
846 * starting to process requests then we are empty. Otherwise we are
847 * full and don't do anything
852 trbs_left = DWC3_TRB_NUM;
854 * In case we start from scratch, we queue the ISOC requests
855 * starting from slot 1. This is done because we use ring
856 * buffer and have no LST bit to stop us. Instead, we place
857 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
858 * after the first request so we start at slot 1 and have
859 * 7 requests proceed before we hit the first IOC.
860 * Other transfer types don't use the ring buffer and are
861 * processed from the first TRB until the last one. Since we
862 * don't wrap around we have to start at the beginning.
864 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
873 /* The last TRB is a link TRB, not used for xfer */
874 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
877 list_for_each_entry_safe(req, n, &dep->request_list, list) {
882 if (req->request.num_mapped_sgs > 0) {
883 struct usb_request *request = &req->request;
884 struct scatterlist *sg = request->sg;
885 struct scatterlist *s;
888 for_each_sg(sg, s, request->num_mapped_sgs, i) {
889 unsigned chain = true;
891 length = sg_dma_len(s);
892 dma = sg_dma_address(s);
894 if (i == (request->num_mapped_sgs - 1) ||
896 if (list_empty(&dep->request_list))
908 dwc3_prepare_one_trb(dep, req, dma, length,
918 dma = req->request.dma;
919 length = req->request.length;
925 /* Is this the last request? */
926 if (list_is_last(&req->list, &dep->request_list))
929 dwc3_prepare_one_trb(dep, req, dma, length,
938 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
941 struct dwc3_gadget_ep_cmd_params params;
942 struct dwc3_request *req;
943 struct dwc3 *dwc = dep->dwc;
947 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
948 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
953 * If we are getting here after a short-out-packet we don't enqueue any
954 * new requests as we try to set the IOC bit only on the last request.
957 if (list_empty(&dep->req_queued))
958 dwc3_prepare_trbs(dep, start_new);
960 /* req points to the first request which will be sent */
961 req = next_request(&dep->req_queued);
963 dwc3_prepare_trbs(dep, start_new);
966 * req points to the first request where HWO changed from 0 to 1
968 req = next_request(&dep->req_queued);
971 dep->flags |= DWC3_EP_PENDING_REQUEST;
975 memset(¶ms, 0, sizeof(params));
978 params.param0 = upper_32_bits(req->trb_dma);
979 params.param1 = lower_32_bits(req->trb_dma);
980 cmd = DWC3_DEPCMD_STARTTRANSFER;
982 cmd = DWC3_DEPCMD_UPDATETRANSFER;
985 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
986 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
988 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
991 * FIXME we need to iterate over the list of requests
992 * here and stop, unmap, free and del each of the linked
993 * requests instead of what we do now.
995 usb_gadget_unmap_request(&dwc->gadget, &req->request,
997 list_del(&req->list);
1001 dep->flags |= DWC3_EP_BUSY;
1004 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1006 WARN_ON_ONCE(!dep->resource_index);
1012 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1013 struct dwc3_ep *dep, u32 cur_uf)
1017 if (list_empty(&dep->request_list)) {
1018 dwc3_trace(trace_dwc3_gadget,
1019 "ISOC ep %s run out for requests",
1021 dep->flags |= DWC3_EP_PENDING_REQUEST;
1025 /* 4 micro frames in the future */
1026 uf = cur_uf + dep->interval * 4;
1028 __dwc3_gadget_kick_transfer(dep, uf, 1);
1031 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1032 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1036 mask = ~(dep->interval - 1);
1037 cur_uf = event->parameters & mask;
1039 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1042 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1044 struct dwc3 *dwc = dep->dwc;
1047 req->request.actual = 0;
1048 req->request.status = -EINPROGRESS;
1049 req->direction = dep->direction;
1050 req->epnum = dep->number;
1052 trace_dwc3_ep_queue(req);
1055 * We only add to our list of requests now and
1056 * start consuming the list once we get XferNotReady
1059 * That way, we avoid doing anything that we don't need
1060 * to do now and defer it until the point we receive a
1061 * particular token from the Host side.
1063 * This will also avoid Host cancelling URBs due to too
1066 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1071 list_add_tail(&req->list, &dep->request_list);
1074 * If there are no pending requests and the endpoint isn't already
1075 * busy, we will just start the request straight away.
1077 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1078 * little bit faster.
1080 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1081 !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1082 !(dep->flags & DWC3_EP_BUSY)) {
1083 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1088 * There are a few special cases:
1090 * 1. XferNotReady with empty list of requests. We need to kick the
1091 * transfer here in that situation, otherwise we will be NAKing
1092 * forever. If we get XferNotReady before gadget driver has a
1093 * chance to queue a request, we will ACK the IRQ but won't be
1094 * able to receive the data until the next request is queued.
1095 * The following code is handling exactly that.
1098 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1100 * If xfernotready is already elapsed and it is a case
1101 * of isoc transfer, then issue END TRANSFER, so that
1102 * you can receive xfernotready again and can have
1103 * notion of current microframe.
1105 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1106 if (list_empty(&dep->req_queued)) {
1107 dwc3_stop_active_transfer(dwc, dep->number, true);
1108 dep->flags = DWC3_EP_ENABLED;
1113 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1115 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1121 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1122 * kick the transfer here after queuing a request, otherwise the
1123 * core may not see the modified TRB(s).
1125 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1126 (dep->flags & DWC3_EP_BUSY) &&
1127 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1128 WARN_ON_ONCE(!dep->resource_index);
1129 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1135 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1136 * right away, otherwise host will not know we have streams to be
1139 if (dep->stream_capable)
1140 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1143 if (ret && ret != -EBUSY)
1144 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1152 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1155 struct dwc3_request *req = to_dwc3_request(request);
1156 struct dwc3_ep *dep = to_dwc3_ep(ep);
1157 struct dwc3 *dwc = dep->dwc;
1159 unsigned long flags;
1163 spin_lock_irqsave(&dwc->lock, flags);
1164 if (!dep->endpoint.desc) {
1165 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1171 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1172 request, req->dep->name)) {
1177 ret = __dwc3_gadget_ep_queue(dep, req);
1180 spin_unlock_irqrestore(&dwc->lock, flags);
1185 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1186 struct usb_request *request)
1188 struct dwc3_request *req = to_dwc3_request(request);
1189 struct dwc3_request *r = NULL;
1191 struct dwc3_ep *dep = to_dwc3_ep(ep);
1192 struct dwc3 *dwc = dep->dwc;
1194 unsigned long flags;
1197 trace_dwc3_ep_dequeue(req);
1199 spin_lock_irqsave(&dwc->lock, flags);
1201 list_for_each_entry(r, &dep->request_list, list) {
1207 list_for_each_entry(r, &dep->req_queued, list) {
1212 /* wait until it is processed */
1213 dwc3_stop_active_transfer(dwc, dep->number, true);
1216 dev_err(dwc->dev, "request %p was not queued to %s\n",
1223 /* giveback the request */
1224 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1227 spin_unlock_irqrestore(&dwc->lock, flags);
1232 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1234 struct dwc3_gadget_ep_cmd_params params;
1235 struct dwc3 *dwc = dep->dwc;
1238 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1239 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1243 memset(¶ms, 0x00, sizeof(params));
1246 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1247 (!list_empty(&dep->req_queued) ||
1248 !list_empty(&dep->request_list)))) {
1249 dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1254 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1255 DWC3_DEPCMD_SETSTALL, ¶ms);
1257 dev_err(dwc->dev, "failed to set STALL on %s\n",
1260 dep->flags |= DWC3_EP_STALL;
1262 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1263 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1265 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1268 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1274 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1276 struct dwc3_ep *dep = to_dwc3_ep(ep);
1277 struct dwc3 *dwc = dep->dwc;
1279 unsigned long flags;
1283 spin_lock_irqsave(&dwc->lock, flags);
1284 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1285 spin_unlock_irqrestore(&dwc->lock, flags);
1290 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1292 struct dwc3_ep *dep = to_dwc3_ep(ep);
1293 struct dwc3 *dwc = dep->dwc;
1294 unsigned long flags;
1297 spin_lock_irqsave(&dwc->lock, flags);
1298 dep->flags |= DWC3_EP_WEDGE;
1300 if (dep->number == 0 || dep->number == 1)
1301 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1303 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1304 spin_unlock_irqrestore(&dwc->lock, flags);
1309 /* -------------------------------------------------------------------------- */
1311 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1312 .bLength = USB_DT_ENDPOINT_SIZE,
1313 .bDescriptorType = USB_DT_ENDPOINT,
1314 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1317 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1318 .enable = dwc3_gadget_ep0_enable,
1319 .disable = dwc3_gadget_ep0_disable,
1320 .alloc_request = dwc3_gadget_ep_alloc_request,
1321 .free_request = dwc3_gadget_ep_free_request,
1322 .queue = dwc3_gadget_ep0_queue,
1323 .dequeue = dwc3_gadget_ep_dequeue,
1324 .set_halt = dwc3_gadget_ep0_set_halt,
1325 .set_wedge = dwc3_gadget_ep_set_wedge,
1328 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1329 .enable = dwc3_gadget_ep_enable,
1330 .disable = dwc3_gadget_ep_disable,
1331 .alloc_request = dwc3_gadget_ep_alloc_request,
1332 .free_request = dwc3_gadget_ep_free_request,
1333 .queue = dwc3_gadget_ep_queue,
1334 .dequeue = dwc3_gadget_ep_dequeue,
1335 .set_halt = dwc3_gadget_ep_set_halt,
1336 .set_wedge = dwc3_gadget_ep_set_wedge,
1339 /* -------------------------------------------------------------------------- */
1341 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1343 struct dwc3 *dwc = gadget_to_dwc(g);
1346 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1347 return DWC3_DSTS_SOFFN(reg);
1350 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1352 struct dwc3 *dwc = gadget_to_dwc(g);
1354 unsigned long timeout;
1355 unsigned long flags;
1364 spin_lock_irqsave(&dwc->lock, flags);
1367 * According to the Databook Remote wakeup request should
1368 * be issued only when the device is in early suspend state.
1370 * We can check that via USB Link State bits in DSTS register.
1372 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1374 speed = reg & DWC3_DSTS_CONNECTSPD;
1375 if (speed == DWC3_DSTS_SUPERSPEED) {
1376 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1381 link_state = DWC3_DSTS_USBLNKST(reg);
1383 switch (link_state) {
1384 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1385 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1388 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1394 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1396 dev_err(dwc->dev, "failed to put link in Recovery\n");
1400 /* Recent versions do this automatically */
1401 if (dwc->revision < DWC3_REVISION_194A) {
1402 /* write zeroes to Link Change Request */
1403 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1404 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1405 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1408 /* poll until Link State changes to ON */
1409 timeout = jiffies + msecs_to_jiffies(100);
1411 while (!time_after(jiffies, timeout)) {
1412 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1414 /* in HS, means ON */
1415 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1419 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1420 dev_err(dwc->dev, "failed to send remote wakeup\n");
1425 spin_unlock_irqrestore(&dwc->lock, flags);
1430 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1433 struct dwc3 *dwc = gadget_to_dwc(g);
1434 unsigned long flags;
1436 spin_lock_irqsave(&dwc->lock, flags);
1437 g->is_selfpowered = !!is_selfpowered;
1438 spin_unlock_irqrestore(&dwc->lock, flags);
1443 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1448 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1450 if (dwc->revision <= DWC3_REVISION_187A) {
1451 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1452 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1455 if (dwc->revision >= DWC3_REVISION_194A)
1456 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1457 reg |= DWC3_DCTL_RUN_STOP;
1459 if (dwc->has_hibernation)
1460 reg |= DWC3_DCTL_KEEP_CONNECT;
1462 dwc->pullups_connected = true;
1464 reg &= ~DWC3_DCTL_RUN_STOP;
1466 if (dwc->has_hibernation && !suspend)
1467 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1469 dwc->pullups_connected = false;
1472 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1475 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1477 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1480 if (reg & DWC3_DSTS_DEVCTRLHLT)
1489 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1491 ? dwc->gadget_driver->function : "no-function",
1492 is_on ? "connect" : "disconnect");
1497 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1499 struct dwc3 *dwc = gadget_to_dwc(g);
1500 unsigned long flags;
1505 spin_lock_irqsave(&dwc->lock, flags);
1506 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1507 spin_unlock_irqrestore(&dwc->lock, flags);
1512 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1516 /* Enable all but Start and End of Frame IRQs */
1517 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1518 DWC3_DEVTEN_EVNTOVERFLOWEN |
1519 DWC3_DEVTEN_CMDCMPLTEN |
1520 DWC3_DEVTEN_ERRTICERREN |
1521 DWC3_DEVTEN_WKUPEVTEN |
1522 DWC3_DEVTEN_ULSTCNGEN |
1523 DWC3_DEVTEN_CONNECTDONEEN |
1524 DWC3_DEVTEN_USBRSTEN |
1525 DWC3_DEVTEN_DISCONNEVTEN);
1527 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1530 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1532 /* mask all interrupts */
1533 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1536 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1537 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1539 static int dwc3_gadget_start(struct usb_gadget *g,
1540 struct usb_gadget_driver *driver)
1542 struct dwc3 *dwc = gadget_to_dwc(g);
1543 struct dwc3_ep *dep;
1544 unsigned long flags;
1549 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1550 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1551 IRQF_SHARED, "dwc3", dwc);
1553 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1558 spin_lock_irqsave(&dwc->lock, flags);
1560 if (dwc->gadget_driver) {
1561 dev_err(dwc->dev, "%s is already bound to %s\n",
1563 dwc->gadget_driver->driver.name);
1568 dwc->gadget_driver = driver;
1570 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1571 reg &= ~(DWC3_DCFG_SPEED_MASK);
1574 * WORKAROUND: DWC3 revision < 2.20a have an issue
1575 * which would cause metastability state on Run/Stop
1576 * bit if we try to force the IP to USB2-only mode.
1578 * Because of that, we cannot configure the IP to any
1579 * speed other than the SuperSpeed
1583 * STAR#9000525659: Clock Domain Crossing on DCTL in
1586 if (dwc->revision < DWC3_REVISION_220A) {
1587 reg |= DWC3_DCFG_SUPERSPEED;
1589 switch (dwc->maximum_speed) {
1591 reg |= DWC3_DSTS_LOWSPEED;
1593 case USB_SPEED_FULL:
1594 reg |= DWC3_DSTS_FULLSPEED1;
1596 case USB_SPEED_HIGH:
1597 reg |= DWC3_DSTS_HIGHSPEED;
1599 case USB_SPEED_SUPER: /* FALLTHROUGH */
1600 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1602 reg |= DWC3_DSTS_SUPERSPEED;
1605 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1607 dwc->start_config_issued = false;
1609 /* Start with SuperSpeed Default */
1610 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1613 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1616 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1621 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1624 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1628 /* begin to receive SETUP packets */
1629 dwc->ep0state = EP0_SETUP_PHASE;
1630 dwc3_ep0_out_start(dwc);
1632 dwc3_gadget_enable_irq(dwc);
1634 spin_unlock_irqrestore(&dwc->lock, flags);
1639 __dwc3_gadget_ep_disable(dwc->eps[0]);
1642 dwc->gadget_driver = NULL;
1645 spin_unlock_irqrestore(&dwc->lock, flags);
1653 static int dwc3_gadget_stop(struct usb_gadget *g)
1655 struct dwc3 *dwc = gadget_to_dwc(g);
1656 unsigned long flags;
1659 spin_lock_irqsave(&dwc->lock, flags);
1661 dwc3_gadget_disable_irq(dwc);
1662 __dwc3_gadget_ep_disable(dwc->eps[0]);
1663 __dwc3_gadget_ep_disable(dwc->eps[1]);
1665 dwc->gadget_driver = NULL;
1667 spin_unlock_irqrestore(&dwc->lock, flags);
1669 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1675 static const struct usb_gadget_ops dwc3_gadget_ops = {
1676 .get_frame = dwc3_gadget_get_frame,
1677 .wakeup = dwc3_gadget_wakeup,
1678 .set_selfpowered = dwc3_gadget_set_selfpowered,
1679 .pullup = dwc3_gadget_pullup,
1680 .udc_start = dwc3_gadget_start,
1681 .udc_stop = dwc3_gadget_stop,
1684 /* -------------------------------------------------------------------------- */
1686 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1687 u8 num, u32 direction)
1689 struct dwc3_ep *dep;
1692 for (i = 0; i < num; i++) {
1693 u8 epnum = (i << 1) | (!!direction);
1695 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1700 dep->number = epnum;
1701 dep->direction = !!direction;
1702 dwc->eps[epnum] = dep;
1704 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1705 (epnum & 1) ? "in" : "out");
1707 dep->endpoint.name = dep->name;
1709 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1711 if (epnum == 0 || epnum == 1) {
1712 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1713 dep->endpoint.maxburst = 1;
1714 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1716 dwc->gadget.ep0 = &dep->endpoint;
1720 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1721 dep->endpoint.max_streams = 15;
1722 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1723 list_add_tail(&dep->endpoint.ep_list,
1724 &dwc->gadget.ep_list);
1726 ret = dwc3_alloc_trb_pool(dep);
1731 if (epnum == 0 || epnum == 1) {
1732 dep->endpoint.caps.type_control = true;
1734 dep->endpoint.caps.type_iso = true;
1735 dep->endpoint.caps.type_bulk = true;
1736 dep->endpoint.caps.type_int = true;
1739 dep->endpoint.caps.dir_in = !!direction;
1740 dep->endpoint.caps.dir_out = !direction;
1742 INIT_LIST_HEAD(&dep->request_list);
1743 INIT_LIST_HEAD(&dep->req_queued);
1749 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1753 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1755 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1757 dwc3_trace(trace_dwc3_gadget,
1758 "failed to allocate OUT endpoints");
1762 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1764 dwc3_trace(trace_dwc3_gadget,
1765 "failed to allocate IN endpoints");
1772 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1774 struct dwc3_ep *dep;
1777 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1778 dep = dwc->eps[epnum];
1782 * Physical endpoints 0 and 1 are special; they form the
1783 * bi-directional USB endpoint 0.
1785 * For those two physical endpoints, we don't allocate a TRB
1786 * pool nor do we add them the endpoints list. Due to that, we
1787 * shouldn't do these two operations otherwise we would end up
1788 * with all sorts of bugs when removing dwc3.ko.
1790 if (epnum != 0 && epnum != 1) {
1791 dwc3_free_trb_pool(dep);
1792 list_del(&dep->endpoint.ep_list);
1799 /* -------------------------------------------------------------------------- */
1801 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1802 struct dwc3_request *req, struct dwc3_trb *trb,
1803 const struct dwc3_event_depevt *event, int status)
1806 unsigned int s_pkt = 0;
1807 unsigned int trb_status;
1809 trace_dwc3_complete_trb(dep, trb);
1811 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1813 * We continue despite the error. There is not much we
1814 * can do. If we don't clean it up we loop forever. If
1815 * we skip the TRB then it gets overwritten after a
1816 * while since we use them in a ring buffer. A BUG()
1817 * would help. Lets hope that if this occurs, someone
1818 * fixes the root cause instead of looking away :)
1820 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1822 count = trb->size & DWC3_TRB_SIZE_MASK;
1824 if (dep->direction) {
1826 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1827 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1828 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1831 * If missed isoc occurred and there is
1832 * no request queued then issue END
1833 * TRANSFER, so that core generates
1834 * next xfernotready and we will issue
1835 * a fresh START TRANSFER.
1836 * If there are still queued request
1837 * then wait, do not issue either END
1838 * or UPDATE TRANSFER, just attach next
1839 * request in request_list during
1840 * giveback.If any future queued request
1841 * is successfully transferred then we
1842 * will issue UPDATE TRANSFER for all
1843 * request in the request_list.
1845 dep->flags |= DWC3_EP_MISSED_ISOC;
1847 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1849 status = -ECONNRESET;
1852 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1855 if (count && (event->status & DEPEVT_STATUS_SHORT))
1860 * We assume here we will always receive the entire data block
1861 * which we should receive. Meaning, if we program RX to
1862 * receive 4K but we receive only 2K, we assume that's all we
1863 * should receive and we simply bounce the request back to the
1864 * gadget driver for further processing.
1866 req->request.actual += req->request.length - count;
1869 if ((event->status & DEPEVT_STATUS_LST) &&
1870 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1871 DWC3_TRB_CTRL_HWO)))
1873 if ((event->status & DEPEVT_STATUS_IOC) &&
1874 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1879 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1880 const struct dwc3_event_depevt *event, int status)
1882 struct dwc3_request *req;
1883 struct dwc3_trb *trb;
1889 req = next_request(&dep->req_queued);
1896 slot = req->start_slot + i;
1897 if ((slot == DWC3_TRB_NUM - 1) &&
1898 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1900 slot %= DWC3_TRB_NUM;
1901 trb = &dep->trb_pool[slot];
1903 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1907 } while (++i < req->request.num_mapped_sgs);
1909 dwc3_gadget_giveback(dep, req, status);
1915 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1916 list_empty(&dep->req_queued)) {
1917 if (list_empty(&dep->request_list)) {
1919 * If there is no entry in request list then do
1920 * not issue END TRANSFER now. Just set PENDING
1921 * flag, so that END TRANSFER is issued when an
1922 * entry is added into request list.
1924 dep->flags = DWC3_EP_PENDING_REQUEST;
1926 dwc3_stop_active_transfer(dwc, dep->number, true);
1927 dep->flags = DWC3_EP_ENABLED;
1935 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1936 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1938 unsigned status = 0;
1940 u32 is_xfer_complete;
1942 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
1944 if (event->status & DEPEVT_STATUS_BUSERR)
1945 status = -ECONNRESET;
1947 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1948 if (clean_busy && (is_xfer_complete ||
1949 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
1950 dep->flags &= ~DWC3_EP_BUSY;
1953 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1954 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1956 if (dwc->revision < DWC3_REVISION_183A) {
1960 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1963 if (!(dep->flags & DWC3_EP_ENABLED))
1966 if (!list_empty(&dep->req_queued))
1970 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1972 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1977 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1980 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
1981 if (!ret || ret == -EBUSY)
1986 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1987 const struct dwc3_event_depevt *event)
1989 struct dwc3_ep *dep;
1990 u8 epnum = event->endpoint_number;
1992 dep = dwc->eps[epnum];
1994 if (!(dep->flags & DWC3_EP_ENABLED))
1997 if (epnum == 0 || epnum == 1) {
1998 dwc3_ep0_interrupt(dwc, event);
2002 switch (event->endpoint_event) {
2003 case DWC3_DEPEVT_XFERCOMPLETE:
2004 dep->resource_index = 0;
2006 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2007 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
2012 dwc3_endpoint_transfer_complete(dwc, dep, event);
2014 case DWC3_DEPEVT_XFERINPROGRESS:
2015 dwc3_endpoint_transfer_complete(dwc, dep, event);
2017 case DWC3_DEPEVT_XFERNOTREADY:
2018 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2019 dwc3_gadget_start_isoc(dwc, dep, event);
2024 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2026 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2027 dep->name, active ? "Transfer Active"
2028 : "Transfer Not Active");
2030 ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
2031 if (!ret || ret == -EBUSY)
2034 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
2039 case DWC3_DEPEVT_STREAMEVT:
2040 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2041 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2046 switch (event->status) {
2047 case DEPEVT_STREAMEVT_FOUND:
2048 dwc3_trace(trace_dwc3_gadget,
2049 "Stream %d found and started",
2053 case DEPEVT_STREAMEVT_NOTFOUND:
2056 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
2059 case DWC3_DEPEVT_RXTXFIFOEVT:
2060 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
2062 case DWC3_DEPEVT_EPCMDCMPLT:
2063 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2068 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2070 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2071 spin_unlock(&dwc->lock);
2072 dwc->gadget_driver->disconnect(&dwc->gadget);
2073 spin_lock(&dwc->lock);
2077 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2079 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2080 spin_unlock(&dwc->lock);
2081 dwc->gadget_driver->suspend(&dwc->gadget);
2082 spin_lock(&dwc->lock);
2086 static void dwc3_resume_gadget(struct dwc3 *dwc)
2088 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2089 spin_unlock(&dwc->lock);
2090 dwc->gadget_driver->resume(&dwc->gadget);
2091 spin_lock(&dwc->lock);
2095 static void dwc3_reset_gadget(struct dwc3 *dwc)
2097 if (!dwc->gadget_driver)
2100 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2101 spin_unlock(&dwc->lock);
2102 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2103 spin_lock(&dwc->lock);
2107 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2109 struct dwc3_ep *dep;
2110 struct dwc3_gadget_ep_cmd_params params;
2114 dep = dwc->eps[epnum];
2116 if (!dep->resource_index)
2120 * NOTICE: We are violating what the Databook says about the
2121 * EndTransfer command. Ideally we would _always_ wait for the
2122 * EndTransfer Command Completion IRQ, but that's causing too
2123 * much trouble synchronizing between us and gadget driver.
2125 * We have discussed this with the IP Provider and it was
2126 * suggested to giveback all requests here, but give HW some
2127 * extra time to synchronize with the interconnect. We're using
2128 * an arbitrary 100us delay for that.
2130 * Note also that a similar handling was tested by Synopsys
2131 * (thanks a lot Paul) and nothing bad has come out of it.
2132 * In short, what we're doing is:
2134 * - Issue EndTransfer WITH CMDIOC bit set
2138 cmd = DWC3_DEPCMD_ENDTRANSFER;
2139 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2140 cmd |= DWC3_DEPCMD_CMDIOC;
2141 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2142 memset(¶ms, 0, sizeof(params));
2143 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
2145 dep->resource_index = 0;
2146 dep->flags &= ~DWC3_EP_BUSY;
2150 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2154 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2155 struct dwc3_ep *dep;
2157 dep = dwc->eps[epnum];
2161 if (!(dep->flags & DWC3_EP_ENABLED))
2164 dwc3_remove_requests(dwc, dep);
2168 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2172 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2173 struct dwc3_ep *dep;
2174 struct dwc3_gadget_ep_cmd_params params;
2177 dep = dwc->eps[epnum];
2181 if (!(dep->flags & DWC3_EP_STALL))
2184 dep->flags &= ~DWC3_EP_STALL;
2186 memset(¶ms, 0, sizeof(params));
2187 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2188 DWC3_DEPCMD_CLEARSTALL, ¶ms);
2193 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2197 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2198 reg &= ~DWC3_DCTL_INITU1ENA;
2199 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2201 reg &= ~DWC3_DCTL_INITU2ENA;
2202 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2204 dwc3_disconnect_gadget(dwc);
2205 dwc->start_config_issued = false;
2207 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2208 dwc->setup_packet_pending = false;
2209 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2212 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2217 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2218 * would cause a missing Disconnect Event if there's a
2219 * pending Setup Packet in the FIFO.
2221 * There's no suggested workaround on the official Bug
2222 * report, which states that "unless the driver/application
2223 * is doing any special handling of a disconnect event,
2224 * there is no functional issue".
2226 * Unfortunately, it turns out that we _do_ some special
2227 * handling of a disconnect event, namely complete all
2228 * pending transfers, notify gadget driver of the
2229 * disconnection, and so on.
2231 * Our suggested workaround is to follow the Disconnect
2232 * Event steps here, instead, based on a setup_packet_pending
2233 * flag. Such flag gets set whenever we have a XferNotReady
2234 * event on EP0 and gets cleared on XferComplete for the
2239 * STAR#9000466709: RTL: Device : Disconnect event not
2240 * generated if setup packet pending in FIFO
2242 if (dwc->revision < DWC3_REVISION_188A) {
2243 if (dwc->setup_packet_pending)
2244 dwc3_gadget_disconnect_interrupt(dwc);
2247 dwc3_reset_gadget(dwc);
2249 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2250 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2251 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2252 dwc->test_mode = false;
2254 dwc3_stop_active_transfers(dwc);
2255 dwc3_clear_stall_all_ep(dwc);
2256 dwc->start_config_issued = false;
2258 /* Reset device address to zero */
2259 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2260 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2261 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2264 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2267 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2270 * We change the clock only at SS but I dunno why I would want to do
2271 * this. Maybe it becomes part of the power saving plan.
2274 if (speed != DWC3_DSTS_SUPERSPEED)
2278 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2279 * each time on Connect Done.
2284 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2285 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2286 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2289 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2291 struct dwc3_ep *dep;
2296 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2297 speed = reg & DWC3_DSTS_CONNECTSPD;
2300 dwc3_update_ram_clk_sel(dwc, speed);
2303 case DWC3_DCFG_SUPERSPEED:
2305 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2306 * would cause a missing USB3 Reset event.
2308 * In such situations, we should force a USB3 Reset
2309 * event by calling our dwc3_gadget_reset_interrupt()
2314 * STAR#9000483510: RTL: SS : USB3 reset event may
2315 * not be generated always when the link enters poll
2317 if (dwc->revision < DWC3_REVISION_190A)
2318 dwc3_gadget_reset_interrupt(dwc);
2320 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2321 dwc->gadget.ep0->maxpacket = 512;
2322 dwc->gadget.speed = USB_SPEED_SUPER;
2324 case DWC3_DCFG_HIGHSPEED:
2325 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2326 dwc->gadget.ep0->maxpacket = 64;
2327 dwc->gadget.speed = USB_SPEED_HIGH;
2329 case DWC3_DCFG_FULLSPEED2:
2330 case DWC3_DCFG_FULLSPEED1:
2331 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2332 dwc->gadget.ep0->maxpacket = 64;
2333 dwc->gadget.speed = USB_SPEED_FULL;
2335 case DWC3_DCFG_LOWSPEED:
2336 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2337 dwc->gadget.ep0->maxpacket = 8;
2338 dwc->gadget.speed = USB_SPEED_LOW;
2342 /* Enable USB2 LPM Capability */
2344 if ((dwc->revision > DWC3_REVISION_194A)
2345 && (speed != DWC3_DCFG_SUPERSPEED)) {
2346 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2347 reg |= DWC3_DCFG_LPM_CAP;
2348 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2350 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2351 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2353 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2356 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2357 * DCFG.LPMCap is set, core responses with an ACK and the
2358 * BESL value in the LPM token is less than or equal to LPM
2361 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2362 && dwc->has_lpm_erratum,
2363 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2365 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2366 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2368 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2370 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2371 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2372 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2376 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2379 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2384 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2387 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2392 * Configure PHY via GUSB3PIPECTLn if required.
2394 * Update GTXFIFOSIZn
2396 * In both cases reset values should be sufficient.
2400 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2403 * TODO take core out of low power mode when that's
2407 dwc->gadget_driver->resume(&dwc->gadget);
2410 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2411 unsigned int evtinfo)
2413 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2414 unsigned int pwropt;
2417 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2418 * Hibernation mode enabled which would show up when device detects
2419 * host-initiated U3 exit.
2421 * In that case, device will generate a Link State Change Interrupt
2422 * from U3 to RESUME which is only necessary if Hibernation is
2425 * There are no functional changes due to such spurious event and we
2426 * just need to ignore it.
2430 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2433 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2434 if ((dwc->revision < DWC3_REVISION_250A) &&
2435 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2436 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2437 (next == DWC3_LINK_STATE_RESUME)) {
2438 dwc3_trace(trace_dwc3_gadget,
2439 "ignoring transition U3 -> Resume");
2445 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2446 * on the link partner, the USB session might do multiple entry/exit
2447 * of low power states before a transfer takes place.
2449 * Due to this problem, we might experience lower throughput. The
2450 * suggested workaround is to disable DCTL[12:9] bits if we're
2451 * transitioning from U1/U2 to U0 and enable those bits again
2452 * after a transfer completes and there are no pending transfers
2453 * on any of the enabled endpoints.
2455 * This is the first half of that workaround.
2459 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2460 * core send LGO_Ux entering U0
2462 if (dwc->revision < DWC3_REVISION_183A) {
2463 if (next == DWC3_LINK_STATE_U0) {
2467 switch (dwc->link_state) {
2468 case DWC3_LINK_STATE_U1:
2469 case DWC3_LINK_STATE_U2:
2470 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2471 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2472 | DWC3_DCTL_ACCEPTU2ENA
2473 | DWC3_DCTL_INITU1ENA
2474 | DWC3_DCTL_ACCEPTU1ENA);
2477 dwc->u1u2 = reg & u1u2;
2481 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2491 case DWC3_LINK_STATE_U1:
2492 if (dwc->speed == USB_SPEED_SUPER)
2493 dwc3_suspend_gadget(dwc);
2495 case DWC3_LINK_STATE_U2:
2496 case DWC3_LINK_STATE_U3:
2497 dwc3_suspend_gadget(dwc);
2499 case DWC3_LINK_STATE_RESUME:
2500 dwc3_resume_gadget(dwc);
2507 dwc->link_state = next;
2510 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2511 unsigned int evtinfo)
2513 unsigned int is_ss = evtinfo & BIT(4);
2516 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2517 * have a known issue which can cause USB CV TD.9.23 to fail
2520 * Because of this issue, core could generate bogus hibernation
2521 * events which SW needs to ignore.
2525 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2526 * Device Fallback from SuperSpeed
2528 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2531 /* enter hibernation here */
2534 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2535 const struct dwc3_event_devt *event)
2537 switch (event->type) {
2538 case DWC3_DEVICE_EVENT_DISCONNECT:
2539 dwc3_gadget_disconnect_interrupt(dwc);
2541 case DWC3_DEVICE_EVENT_RESET:
2542 dwc3_gadget_reset_interrupt(dwc);
2544 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2545 dwc3_gadget_conndone_interrupt(dwc);
2547 case DWC3_DEVICE_EVENT_WAKEUP:
2548 dwc3_gadget_wakeup_interrupt(dwc);
2550 case DWC3_DEVICE_EVENT_HIBER_REQ:
2551 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2552 "unexpected hibernation event\n"))
2555 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2557 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2558 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2560 case DWC3_DEVICE_EVENT_EOPF:
2561 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2563 case DWC3_DEVICE_EVENT_SOF:
2564 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2566 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2567 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2569 case DWC3_DEVICE_EVENT_CMD_CMPL:
2570 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2572 case DWC3_DEVICE_EVENT_OVERFLOW:
2573 dwc3_trace(trace_dwc3_gadget, "Overflow");
2576 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2580 static void dwc3_process_event_entry(struct dwc3 *dwc,
2581 const union dwc3_event *event)
2583 trace_dwc3_event(event->raw);
2585 /* Endpoint IRQ, handle it and return early */
2586 if (event->type.is_devspec == 0) {
2588 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2591 switch (event->type.type) {
2592 case DWC3_EVENT_TYPE_DEV:
2593 dwc3_gadget_interrupt(dwc, &event->devt);
2595 /* REVISIT what to do with Carkit and I2C events ? */
2597 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2601 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2603 struct dwc3_event_buffer *evt;
2604 irqreturn_t ret = IRQ_NONE;
2608 evt = dwc->ev_buffs[buf];
2611 if (!(evt->flags & DWC3_EVENT_PENDING))
2615 union dwc3_event event;
2617 event.raw = *(u32 *) (evt->buf + evt->lpos);
2619 dwc3_process_event_entry(dwc, &event);
2622 * FIXME we wrap around correctly to the next entry as
2623 * almost all entries are 4 bytes in size. There is one
2624 * entry which has 12 bytes which is a regular entry
2625 * followed by 8 bytes data. ATM I don't know how
2626 * things are organized if we get next to the a
2627 * boundary so I worry about that once we try to handle
2630 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2633 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2637 evt->flags &= ~DWC3_EVENT_PENDING;
2640 /* Unmask interrupt */
2641 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2642 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2643 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2648 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2650 struct dwc3 *dwc = _dwc;
2651 unsigned long flags;
2652 irqreturn_t ret = IRQ_NONE;
2655 spin_lock_irqsave(&dwc->lock, flags);
2657 for (i = 0; i < dwc->num_event_buffers; i++)
2658 ret |= dwc3_process_event_buf(dwc, i);
2660 spin_unlock_irqrestore(&dwc->lock, flags);
2665 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2667 struct dwc3_event_buffer *evt;
2671 evt = dwc->ev_buffs[buf];
2673 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2674 count &= DWC3_GEVNTCOUNT_MASK;
2679 evt->flags |= DWC3_EVENT_PENDING;
2681 /* Mask interrupt */
2682 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2683 reg |= DWC3_GEVNTSIZ_INTMASK;
2684 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2686 return IRQ_WAKE_THREAD;
2689 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2691 struct dwc3 *dwc = _dwc;
2693 irqreturn_t ret = IRQ_NONE;
2695 for (i = 0; i < dwc->num_event_buffers; i++) {
2698 status = dwc3_check_event_buf(dwc, i);
2699 if (status == IRQ_WAKE_THREAD)
2707 * dwc3_gadget_init - Initializes gadget related registers
2708 * @dwc: pointer to our controller context structure
2710 * Returns 0 on success otherwise negative errno.
2712 int dwc3_gadget_init(struct dwc3 *dwc)
2716 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2717 &dwc->ctrl_req_addr, GFP_KERNEL);
2718 if (!dwc->ctrl_req) {
2719 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2724 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2725 &dwc->ep0_trb_addr, GFP_KERNEL);
2726 if (!dwc->ep0_trb) {
2727 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2732 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2733 if (!dwc->setup_buf) {
2738 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2739 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2741 if (!dwc->ep0_bounce) {
2742 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2747 dwc->gadget.ops = &dwc3_gadget_ops;
2748 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2749 dwc->gadget.sg_supported = true;
2750 dwc->gadget.name = "dwc3-gadget";
2753 * FIXME We might be setting max_speed to <SUPER, however versions
2754 * <2.20a of dwc3 have an issue with metastability (documented
2755 * elsewhere in this driver) which tells us we can't set max speed to
2756 * anything lower than SUPER.
2758 * Because gadget.max_speed is only used by composite.c and function
2759 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2760 * to happen so we avoid sending SuperSpeed Capability descriptor
2761 * together with our BOS descriptor as that could confuse host into
2762 * thinking we can handle super speed.
2764 * Note that, in fact, we won't even support GetBOS requests when speed
2765 * is less than super speed because we don't have means, yet, to tell
2766 * composite.c that we are USB 2.0 + LPM ECN.
2768 if (dwc->revision < DWC3_REVISION_220A)
2769 dwc3_trace(trace_dwc3_gadget,
2770 "Changing max_speed on rev %08x\n",
2773 dwc->gadget.max_speed = dwc->maximum_speed;
2776 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2779 dwc->gadget.quirk_ep_out_aligned_size = true;
2782 * REVISIT: Here we should clear all pending IRQs to be
2783 * sure we're starting from a well known location.
2786 ret = dwc3_gadget_init_endpoints(dwc);
2790 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2792 dev_err(dwc->dev, "failed to register udc\n");
2799 dwc3_gadget_free_endpoints(dwc);
2800 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2801 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2804 kfree(dwc->setup_buf);
2807 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2808 dwc->ep0_trb, dwc->ep0_trb_addr);
2811 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2812 dwc->ctrl_req, dwc->ctrl_req_addr);
2818 /* -------------------------------------------------------------------------- */
2820 void dwc3_gadget_exit(struct dwc3 *dwc)
2822 usb_del_gadget_udc(&dwc->gadget);
2824 dwc3_gadget_free_endpoints(dwc);
2826 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2827 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2829 kfree(dwc->setup_buf);
2831 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2832 dwc->ep0_trb, dwc->ep0_trb_addr);
2834 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2835 dwc->ctrl_req, dwc->ctrl_req_addr);
2838 int dwc3_gadget_suspend(struct dwc3 *dwc)
2840 if (dwc->pullups_connected) {
2841 dwc3_gadget_disable_irq(dwc);
2842 dwc3_gadget_run_stop(dwc, true, true);
2845 __dwc3_gadget_ep_disable(dwc->eps[0]);
2846 __dwc3_gadget_ep_disable(dwc->eps[1]);
2848 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2853 int dwc3_gadget_resume(struct dwc3 *dwc)
2855 struct dwc3_ep *dep;
2858 /* Start with SuperSpeed Default */
2859 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2862 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2868 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2873 /* begin to receive SETUP packets */
2874 dwc->ep0state = EP0_SETUP_PHASE;
2875 dwc3_ep0_out_start(dwc);
2877 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2879 if (dwc->pullups_connected) {
2880 dwc3_gadget_enable_irq(dwc);
2881 dwc3_gadget_run_stop(dwc, true, false);
2887 __dwc3_gadget_ep_disable(dwc->eps[0]);