drivers/usb/dwc_otg/dwc_otg_driver.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $
   3  * $Revision: #12 $
   4  * $Date: 2007/02/07 $
   5  * $Change: 791271 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33
  34 /** @file
  35  * The dwc_otg_driver module provides the initialization and cleanup entry
  36  * points for the DWC_otg driver. This module will be dynamically installed
  37  * after Linux is booted using the insmod command. When the module is
  38  * installed, the dwc_otg_driver_init function is called. When the module is
  39  * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
  40  *
  41  * This module also defines a data structure for the dwc_otg_driver, which is
  42  * used in conjunction with the standard ARM lm_device structure. These
  43  * structures allow the OTG driver to comply with the standard Linux driver
  44  * model in which devices and drivers are registered with a bus driver. This
  45  * has the benefit that Linux can expose attributes of the driver and device
  46  * in its special sysfs file system. Users can then read or write files in
  47  * this file system to perform diagnostics on the driver components or the
  48  * device.
  49  */
  50
  51 #include <linux/kernel.h>
  52 #include <linux/module.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/init.h>
  55 #include <linux/device.h>
  56 #include <linux/errno.h>
  57 #include <linux/types.h>
  58 #include <linux/stat.h>  /* permission constants */
  59
  60 #include <asm/io.h>
  61 #include <asm/sizes.h>
  62
  63 #include "linux/dwc_otg_plat.h"
  64 #include <linux/platform_device.h>
  65 #include "dwc_otg_attr.h"
  66 #include "dwc_otg_driver.h"
  67 #include "dwc_otg_cil.h"
  68 #include "dwc_otg_pcd.h"
  69 #include "dwc_otg_hcd.h"
  70
  71 #include "usbdev_rk.h"
  72 //#define DWC_DRIVER_VERSION    "2.60a 22-NOV-2006"
  73 //#define DWC_DRIVER_VERSION    "2.70 2009-12-31"
  74 #define DWC_DRIVER_VERSION      "3.00 2010-12-12 rockchip"
  75
  76 #define DWC_DRIVER_DESC         "HS OTG USB Controller driver"
  77
  78 static const char dwc_driver_name[] = "usb20_otg";
  79
  80 dwc_otg_device_t* g_otgdev = NULL;
  81
  82 /*-------------------------------------------------------------------------*/
  83 /* Encapsulate the module parameter settings */
  84
  85 static dwc_otg_core_params_t dwc_otg_module_params = {
  86         .opt = -1,
  87         .otg_cap = -1,
  88         .dma_enable = -1,
  89         .dma_burst_size = -1,
  90         .speed = -1,
  91         .host_support_fs_ls_low_power = -1,
  92         .host_ls_low_power_phy_clk = -1,
  93         .enable_dynamic_fifo = -1,
  94         .data_fifo_size = -1,
  95         .dev_rx_fifo_size = -1,
  96         .dev_nperio_tx_fifo_size = -1,
  97         .dev_perio_tx_fifo_size =
  98         {       /* dev_perio_tx_fifo_size_1 */
  99                         -1,
 100                         -1,
 101                         -1,
 102                         -1,
 103                         -1,
 104                         -1,
 105                         -1,
 106                         -1,
 107                         -1,
 108                         -1,
 109                         -1,
 110                         -1,
 111                         -1,
 112                         -1,
 113                         -1
 114         },      /* 15 */
 115         .host_rx_fifo_size = -1,
 116         .host_nperio_tx_fifo_size = -1,
 117         //.host_perio_tx_fifo_size = 512,
 118         .host_perio_tx_fifo_size = -1,
 119         .max_transfer_size = -1,
 120         .max_packet_count = -1,
 121         .host_channels = -1,
 122         .dev_endpoints = -1,
 123         .phy_type = -1,
 124         .phy_utmi_width = -1,
 125         .phy_ulpi_ddr = -1,
 126         .phy_ulpi_ext_vbus = -1,
 127         .i2c_enable = -1,
 128         .ulpi_fs_ls = -1,
 129         .ts_dline = -1,
 130         .en_multiple_tx_fifo = -1,
 131         .dev_tx_fifo_size =
 132         {       /* dev_tx_fifo_size */
 133                         -1,
 134                         -1,
 135                         -1,
 136                         -1,
 137                         -1,
 138                         -1,
 139                         -1,
 140                         -1,
 141                         -1,
 142                         -1,
 143                         -1,
 144                         -1,
 145                         -1,
 146                         -1,
 147                         -1
 148         },      /* 15 */
 149         .thr_ctl = -1,
 150         .tx_thr_length = -1,
 151         .rx_thr_length = -1,
 152 };
 153
 154 #ifdef CONFIG_USB11_HOST
 155
 156 dwc_otg_device_t* g_host11 = NULL;
 157
 158 static dwc_otg_core_params_t host11_module_params = {
 159         .opt = -1,
 160         .otg_cap = -1,
 161         .dma_enable = -1,
 162         .dma_burst_size = -1,
 163         .speed = -1,
 164         .host_support_fs_ls_low_power = 1,
 165         .host_ls_low_power_phy_clk = -1,
 166         .enable_dynamic_fifo = -1,
 167         .data_fifo_size = -1,
 168         .dev_rx_fifo_size = -1,
 169         .dev_nperio_tx_fifo_size = -1,
 170         .dev_perio_tx_fifo_size =
 171         {       /* dev_perio_tx_fifo_size_1 */
 172                         -1,
 173                         -1,
 174                         -1,
 175                         -1,
 176                         -1,
 177                         -1,
 178                         -1,
 179                         -1,
 180                         -1,
 181                         -1,
 182                         -1,
 183                         -1,
 184                         -1,
 185                         -1,
 186                         -1
 187         },      /* 15 */
 188         .host_rx_fifo_size = -1,
 189         .host_nperio_tx_fifo_size = -1,
 190         //.host_perio_tx_fifo_size = 512,
 191         .host_perio_tx_fifo_size = -1,
 192         .max_transfer_size = -1,
 193         .max_packet_count = -1,
 194         .host_channels = -1,
 195         .dev_endpoints = -1,
 196         .phy_type = -1,
 197         .phy_utmi_width = -1,
 198         .phy_ulpi_ddr = -1,
 199         .phy_ulpi_ext_vbus = -1,
 200         .i2c_enable = -1,
 201         .ulpi_fs_ls = -1,
 202         .ts_dline = -1,
 203         .en_multiple_tx_fifo = -1,
 204         .dev_tx_fifo_size =
 205         {       /* dev_tx_fifo_size */
 206                         -1,
 207                         -1,
 208                         -1,
 209                         -1,
 210                         -1,
 211                         -1,
 212                         -1,
 213                         -1,
 214                         -1,
 215                         -1,
 216                         -1,
 217                         -1,
 218                         -1,
 219                         -1,
 220                         -1
 221         },      /* 15 */
 222         .thr_ctl = -1,
 223         .tx_thr_length = -1,
 224         .rx_thr_length = -1,
 225 };
 226 #endif
 227
 228 #ifdef CONFIG_USB20_HOST
 229 dwc_otg_device_t* g_host20 = NULL;
 230
 231 static dwc_otg_core_params_t host20_module_params = {
 232         .opt = -1,
 233         .otg_cap = -1,
 234         .dma_enable = -1,
 235         .dma_burst_size = -1,
 236         .speed = -1,
 237         .host_support_fs_ls_low_power = -1,
 238         .host_ls_low_power_phy_clk = -1,
 239         .enable_dynamic_fifo = -1,
 240         .data_fifo_size = -1,
 241         .dev_rx_fifo_size = -1,
 242         .dev_nperio_tx_fifo_size = -1,
 243         .dev_perio_tx_fifo_size =
 244         {       /* dev_perio_tx_fifo_size_1 */
 245                         -1,
 246                         -1,
 247                         -1,
 248                         -1,
 249                         -1,
 250                         -1,
 251                         -1,
 252                         -1,
 253                         -1,
 254                         -1,
 255                         -1,
 256                         -1,
 257                         -1,
 258                         -1,
 259                         -1
 260         },      /* 15 */
 261         .host_rx_fifo_size = -1,
 262         .host_nperio_tx_fifo_size = -1,
 263         //.host_perio_tx_fifo_size = 512,
 264         .host_perio_tx_fifo_size = -1,
 265         .max_transfer_size = -1,
 266         .max_packet_count = -1,
 267         .host_channels = -1,
 268         .dev_endpoints = -1,
 269         .phy_type = -1,
 270         .phy_utmi_width = -1,
 271         .phy_ulpi_ddr = -1,
 272         .phy_ulpi_ext_vbus = -1,
 273         .i2c_enable = -1,
 274         .ulpi_fs_ls = -1,
 275         .ts_dline = -1,
 276         .en_multiple_tx_fifo = -1,
 277         .dev_tx_fifo_size =
 278         {       /* dev_tx_fifo_size */
 279                         -1,
 280                         -1,
 281                         -1,
 282                         -1,
 283                         -1,
 284                         -1,
 285                         -1,
 286                         -1,
 287                         -1,
 288                         -1,
 289                         -1,
 290                         -1,
 291                         -1,
 292                         -1,
 293                         -1
 294         },      /* 15 */
 295         .thr_ctl = -1,
 296         .tx_thr_length = -1,
 297         .rx_thr_length = -1,
 298 };
 299 #endif
 300
 301 /**
 302  * This function shows the Driver Version.
 303  */
 304 static ssize_t version_show(struct device_driver *dev, char *buf)
 305 {
 306         return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2,"%s\n",
 307                 DWC_DRIVER_VERSION);
 308 }
 309 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
 310
 311 /**
 312  * Global Debug Level Mask.
 313  */
 314 uint32_t g_dbg_lvl = DBG_OFF;//0xFFFF;//DBG_CIL|DBG_CILV|DBG_PCDV|DBG_HCDV|DBG_HCD|DBG_HCD_URB; /* OFF */
 315
 316 /**
 317  * This function shows the driver Debug Level.
 318  */
 319 static ssize_t dbg_level_show(struct device_driver *_drv, char *_buf)
 320 {
 321         return sprintf(_buf, "0x%0x\n", g_dbg_lvl);
 322 }
 323 /**
 324  * This function stores the driver Debug Level.
 325  */
 326 static ssize_t dbg_level_store(struct device_driver *_drv, const char *_buf,
 327                                                            size_t _count)
 328 {
 329         g_dbg_lvl = simple_strtoul(_buf, NULL, 16);
 330                 return _count;
 331 }
 332 static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store);
 333 #ifdef CONFIG_USB
 334
 335 extern struct usb_hub *g_root_hub20;
 336 #ifdef DWC_BOTH_HOST_SLAVE
 337 extern void hcd_start( dwc_otg_core_if_t *_core_if );
 338
 339 extern void hub_disconnect_device(struct usb_hub *hub);
 340
 341 static ssize_t force_usb_mode_show(struct device_driver *_drv, char *_buf)
 342 {
 343     dwc_otg_device_t *otg_dev = g_otgdev;
 344     dwc_otg_core_if_t *core_if = otg_dev->core_if;
 345
 346     return sprintf (_buf, "%d\n", core_if->usb_mode);
 347 }
 348
 349 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
 350 {
 351     dwc_otg_device_t *otg_dev = g_otgdev;
 352     dctl_data_t dctl = {.d32=0};
 353         struct dwc_otg_platform_data *pldata = otg_dev->pldata;
 354     if(core_if->op_state == A_HOST)
 355     {
 356         printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
 357         return;
 358     }
 359     del_timer(&otg_dev->pcd->check_vbus_timer);
 360     // force disconnect
 361     /* soft disconnect */
 362     dctl.d32 = dwc_read_reg32( &core_if->dev_if->dev_global_regs->dctl );
 363     dctl.b.sftdiscon = 1;
 364     dwc_write_reg32( &core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
 365
 366     if (core_if->pcd_cb && core_if->pcd_cb->stop ) {
 367             core_if->pcd_cb->stop( core_if->pcd_cb->p );
 368     }
 369
 370     //core_if->op_state = A_HOST;
 371     /*
 372      * Initialize the Core for Host mode.
 373      */
 374         dwc_otg_core_init(core_if);
 375         dwc_otg_enable_global_interrupts(core_if);
 376     hcd_start( core_if );
 377
 378 }
 379 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
 380 {
 381     dwc_otg_device_t *otg_dev = g_otgdev;
 382     dwc_otg_disable_global_interrupts( core_if );
 383     if (core_if->hcd_cb && core_if->hcd_cb->stop) {
 384         core_if->hcd_cb->stop( core_if->hcd_cb->p );
 385     }
 386     if(core_if->op_state == B_PERIPHERAL)
 387     {
 388         printk("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
 389         return;
 390     }
 391         hub_disconnect_device(g_root_hub20);
 392     otg_dev->core_if->op_state = B_PERIPHERAL;
 393         /* Reset the Controller */
 394         dwc_otg_core_reset( core_if );
 395     otg_dev->pcd->vbus_status = 0;
 396     dwc_otg_pcd_start_vbus_timer( otg_dev->pcd );
 397
 398 }
 399 static void dwc_otg_set_gusbcfg(dwc_otg_core_if_t *core_if, int mode)
 400 {
 401         gusbcfg_data_t usbcfg = { .d32 = 0 };
 402
 403     usbcfg.d32 = dwc_read_reg32( &core_if->core_global_regs->gusbcfg);
 404     switch(mode)
 405     {
 406     case USB_MODE_FORCE_HOST:
 407         usbcfg.b.force_hst_mode = 1;
 408         usbcfg.b.force_dev_mode = 0;
 409         break;
 410     case USB_MODE_FORCE_DEVICE:
 411         usbcfg.b.force_hst_mode = 0;
 412         usbcfg.b.force_dev_mode = 1;
 413         break;
 414     case USB_MODE_NORMAL:
 415         usbcfg.b.force_hst_mode = 0;
 416         usbcfg.b.force_dev_mode = 0;
 417         break;
 418     }
 419     dwc_write_reg32( &core_if->core_global_regs->gusbcfg, usbcfg.d32 );
 420 }
 421
 422 static ssize_t force_usb_mode_store(struct device_driver *_drv, const char *_buf,
 423                           size_t _count )
 424 {
 425     int new_mode = simple_strtoul(_buf, NULL, 16);
 426     dwc_otg_device_t *otg_dev = g_otgdev;
 427     dwc_otg_core_if_t *core_if = otg_dev->core_if;
 428         struct dwc_otg_platform_data *pldata = otg_dev->pldata;
 429     DWC_PRINT("%s %d->%d\n",__func__, core_if->usb_mode, new_mode);
 430     if(core_if->usb_mode == new_mode)
 431     {
 432         return _count;
 433     }
 434
 435     if(pldata->phy_status==USB_PHY_SUSPEND){
 436         pldata->clock_enable(pldata, 1);
 437         pldata->phy_suspend(pldata,USB_PHY_ENABLED);
 438     }
 439
 440         switch(new_mode)
 441         {
 442                 case USB_MODE_FORCE_HOST:
 443                         if(USB_MODE_FORCE_DEVICE == core_if->usb_mode)
 444                         {/* device-->host */
 445                                 core_if->usb_mode = new_mode;
 446                                 dwc_otg_force_host(core_if);
 447                         }
 448                         else if(USB_MODE_NORMAL == core_if->usb_mode)
 449                         {
 450                                 core_if->usb_mode = new_mode;
 451                                 if(dwc_otg_is_host_mode(core_if))
 452                                 {
 453                                         dwc_otg_set_gusbcfg(core_if, new_mode);
 454                                 }
 455                                 else
 456                                 {
 457                                         dwc_otg_force_host(core_if);
 458                                 }
 459                         }
 460                         else
 461                             core_if->usb_mode = new_mode;
 462                         break;
 463                 case USB_MODE_FORCE_DEVICE:
 464                         if(USB_MODE_FORCE_HOST == core_if->usb_mode)
 465                         {
 466                                 core_if->usb_mode = new_mode;
 467                                 dwc_otg_force_device(core_if);
 468                         }
 469                         else if(USB_MODE_NORMAL == core_if->usb_mode)
 470                         {
 471                                 core_if->usb_mode = new_mode;
 472                                 if(dwc_otg_is_device_mode(core_if))
 473                                 {
 474                                         dwc_otg_set_gusbcfg(core_if, new_mode);
 475                                 }
 476                                 else
 477                                 {
 478                                         dwc_otg_force_device(core_if);
 479                                 }
 480                         }
 481                         break;
 482                 case USB_MODE_NORMAL:
 483                         #if 1
 484                         if(USB_MODE_FORCE_DEVICE == core_if->usb_mode)
 485                         {
 486                                 core_if->usb_mode = new_mode;
 487                                 del_timer(&otg_dev->pcd->check_vbus_timer);
 488                                 dwc_otg_set_gusbcfg(core_if, new_mode);
 489                                 msleep(50);
 490                                 if(dwc_otg_is_host_mode(core_if))
 491                                 {
 492                                         dwc_otg_force_host(core_if);
 493                                 }
 494                                 else
 495                                 {
 496                                         dwc_otg_pcd_start_vbus_timer( otg_dev->pcd );
 497                                 }
 498                                 //mdelay(10);
 499                                 //core_if->usb_mode = new_mode;
 500                                 //if(!dwc_otg_connid(core_if))
 501                                 //      dwc_otg_force_host(core_if);
 502                         }
 503                         else if(USB_MODE_FORCE_HOST == core_if->usb_mode)
 504                         {
 505                                 core_if->usb_mode = new_mode;
 506                                 dwc_otg_set_gusbcfg(core_if, new_mode);
 507                                 msleep(100);
 508                                 if(dwc_otg_is_device_mode(core_if))
 509                                 {
 510                                         dwc_otg_force_device(core_if);
 511                                 }
 512                                 //if(dwc_otg_connid(core_if))
 513                                 //      hub_disconnect_device();
 514                                 //core_if->usb_mode = new_mode;
 515                                 //      dwc_otg_force_device(core_if);
 516                         }
 517                         #endif
 518                         break;
 519                 default:
 520                         break;
 521         }
 522         return _count;
 523 }
 524 static DRIVER_ATTR(force_usb_mode, 0666/*S_IRUGO|S_IWUSR*/, force_usb_mode_show, force_usb_mode_store);
 525 #endif
 526 static ssize_t dwc_otg_enable_show( struct device *_dev,
 527                                                                 struct device_attribute *attr, char *buf)
 528 {
 529     dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)_dev->platform_data));
 530     return sprintf (buf, "%d\n", otg_dev->hcd->host_enabled);
 531 }
 532
 533 static ssize_t dwc_otg_enable_store( struct device *_dev,
 534                                                                 struct device_attribute *attr,
 535                                                                 const char *buf, size_t count )
 536 {
 537     dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)_dev->platform_data));
 538     dwc_otg_core_if_t *_core_if = otg_dev->core_if;
 539     struct platform_device *pdev = to_platform_device(_dev);
 540         uint32_t val = simple_strtoul(buf, NULL, 16);
 541         struct dwc_otg_platform_data *pldata = _dev->platform_data;
 542         if(otg_dev->hcd->host_enabled == val)
 543             return count;
 544
 545         otg_dev->hcd->host_enabled = val;
 546         if(val == 0)    // enable -> disable
 547         {
 548             DWC_PRINT("disable host controller:%s,id:%d\n",pdev->name,pdev->id);
 549             #if 1
 550         if (_core_if->hcd_cb && _core_if->hcd_cb->disconnect) {
 551                 _core_if->hcd_cb->disconnect( _core_if->hcd_cb->p );
 552         }
 553         #endif
 554         if (_core_if->hcd_cb && _core_if->hcd_cb->stop) {
 555                 _core_if->hcd_cb->stop( _core_if->hcd_cb->p );
 556         }
 557         if(pldata->phy_status==USB_PHY_ENABLED){
 558             pldata->phy_suspend(pldata,USB_PHY_SUSPEND);
 559             udelay(3);
 560             pldata->clock_enable(pldata, 0);
 561         }
 562         }
 563         else if(val == 1)
 564         {
 565             DWC_PRINT("enable host controller:%s\n",pdev->name);
 566         if( pldata->phy_status == USB_PHY_SUSPEND ){
 567             pldata->clock_enable( pldata, 1);
 568             pldata->phy_suspend(pldata, USB_PHY_ENABLED);
 569         }
 570         mdelay(5);
 571         if (_core_if->hcd_cb && _core_if->hcd_cb->start) {
 572                 _core_if->hcd_cb->start( _core_if->hcd_cb->p );
 573         }
 574         }
 575
 576     return count;
 577 }
 578 static DEVICE_ATTR(enable, S_IRUGO|S_IWUSR, dwc_otg_enable_show, dwc_otg_enable_store);
 579 #endif
 580 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
 581 {
 582 #ifndef CONFIG_DWC_OTG_HOST_ONLY
 583     dwc_otg_device_t *otg_dev = g_otgdev;
 584     dwc_otg_pcd_t *_pcd = otg_dev->pcd;
 585     return sprintf (_buf, "%d\n", _pcd->conn_en);
 586 #else
 587     return sprintf(_buf, "0\n");
 588 #endif
 589 }
 590
 591 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv, const char *_buf,
 592                                      size_t _count)
 593 {
 594 #ifndef CONFIG_DWC_OTG_HOST_ONLY
 595     int enable = simple_strtoul(_buf, NULL, 10);
 596     dwc_otg_device_t *otg_dev = g_otgdev;
 597     dwc_otg_pcd_t *_pcd = otg_dev->pcd;
 598     DWC_PRINT("%s %d->%d\n",__func__, _pcd->conn_en, enable);
 599
 600     _pcd->conn_en = enable;
 601 #endif
 602     return _count;
 603 }
 604 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO|S_IWUSR, dwc_otg_conn_en_show, dwc_otg_conn_en_store);
 605
 606 #ifdef CONFIG_RK_USB_UART
 607
 608 extern int get_gadget_connect_flag(void);
 609 extern int dwc_vbus_status(void);
 610
 611 /*
 612
 613 write 1 to /sys/bus/platform/drivers/usb20_otg/dwc_otg_force_uart
 614 can stop check_vbus_timer and force usb_phy bypass to uart mode
 615
 616 write 0 comes back to normal usb operate mode
 617
 618 */
 619 static ssize_t dwc_otg_force_uart_store(struct device_driver *_drv, const char *_buf,
 620                                      size_t _count)
 621 {
 622     int enable = simple_strtoul(_buf, NULL, 10);
 623     dwc_otg_device_t *otg_dev = g_otgdev;
 624     dwc_otg_pcd_t *_pcd = otg_dev->pcd;
 625     struct dwc_otg_platform_data *pldata = otg_dev->pldata;
 626
 627     if(1 == enable)
 628     {
 629         if(!get_gadget_connect_flag() &&
 630             dwc_otg_is_device_mode(otg_dev->core_if))
 631         {
 632             disable_irq(IRQ_OTG_BVALID);
 633             del_timer(&_pcd->check_vbus_timer);
 634             pldata->phy_suspend(pldata,USB_PHY_SUSPEND);
 635             pldata->dwc_otg_uart_mode(pldata,PHY_UART_MODE);
 636             _pcd->vbus_status = 2;
 637         }
 638         else
 639             printk("mode mismatch!\n");
 640     }
 641
 642     if(0 == enable)
 643     {
 644         _pcd->vbus_status == 0;
 645         _pcd->vbus_status = 0;
 646         pldata->dwc_otg_uart_mode(pldata,PHY_USB_MODE);
 647         dwc_otg_pcd_start_vbus_timer(_pcd);
 648         enable_irq(IRQ_OTG_BVALID);
 649     }
 650     return _count;
 651 }
 652 static DRIVER_ATTR(dwc_otg_force_uart, S_IRUGO|S_IWUSR, NULL, dwc_otg_force_uart_store);
 653 #endif
 654 #ifndef CONFIG_DWC_OTG_HOST_ONLY
 655 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
 656 {
 657     dwc_otg_device_t *otg_dev = g_otgdev;
 658     dwc_otg_pcd_t *_pcd = otg_dev->pcd;
 659     return sprintf (_buf, "%d\n", _pcd->vbus_status);
 660 }
 661 static DRIVER_ATTR(vbus_status, S_IRUGO|S_IWUSR, vbus_status_show, NULL);
 662 #endif
 663 volatile depctl_data_t depctl_ep0 = {.d32 = 0};
 664 volatile depctl_data_t depctl_ep2 = {.d32 = 0};
 665 volatile depctl_data_t depctl_ep4 = {.d32 = 0};
 666 void dwc_otg_epout_save(void)
 667 {
 668     dwc_otg_device_t *otg_dev = g_otgdev;
 669         dwc_otg_dev_if_t *dev_if = otg_dev->core_if->dev_if;
 670     volatile depctl_data_t depctl = {.d32 = 0};
 671     volatile grstctl_t grstctl = {.d32 = 0};
 672     grstctl.d32 = dwc_read_reg32(&otg_dev->core_if->core_global_regs->grstctl);
 673
 674     while(grstctl.b.ahbidle != 1)
 675     {
 676         grstctl.d32 = dwc_read_reg32(&otg_dev->core_if->core_global_regs->grstctl);
 677     }
 678     depctl_ep0.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl);
 679     depctl.d32 = depctl_ep0.d32;
 680     if(depctl.b.epena)
 681     {
 682         depctl.b.epena = 0;
 683         dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, depctl.d32);
 684     }
 685     depctl_ep2.d32 = dwc_read_reg32(&dev_if->out_ep_regs[2]->doepctl);
 686     depctl.d32 = depctl_ep2.d32;
 687     if(depctl.b.epena)
 688     {
 689         depctl.b.epena = 0;
 690         dwc_write_reg32(&dev_if->out_ep_regs[2]->doepctl, depctl.d32);
 691     }
 692     depctl_ep4.d32 = dwc_read_reg32(&dev_if->out_ep_regs[4]->doepctl);
 693     depctl.d32 = depctl_ep4.d32;
 694     if(depctl.b.epena)
 695     {
 696         depctl.b.epena = 0;
 697         dwc_write_reg32(&dev_if->out_ep_regs[4]->doepctl, depctl.d32);
 698     }
 699 }
 700 void dwc_otg_epout_restore(void)
 701 {
 702     dwc_otg_device_t *otg_dev = g_otgdev;
 703         dwc_otg_dev_if_t *dev_if = otg_dev->core_if->dev_if;
 704     dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, depctl_ep0.d32);
 705     dwc_write_reg32(&dev_if->out_ep_regs[2]->doepctl, depctl_ep2.d32);
 706     dwc_write_reg32(&dev_if->out_ep_regs[4]->doepctl, depctl_ep4.d32);
 707 }
 708
 709 /**
 710  * This function is called during module intialization to verify that
 711  * the module parameters are in a valid state.
 712  */
 713 static int check_parameters(dwc_otg_core_if_t *core_if)
 714 {
 715         int i;
 716         int retval = 0;
 717         dwc_otg_core_params_t      *core_params;
 718         core_params = core_if->core_params;
 719 /* Checks if the parameter is outside of its valid range of values */
 720 #define DWC_OTG_PARAM_TEST(_param_,_low_,_high_) \
 721                 ((core_params->_param_ < (_low_)) || \
 722                 (core_params->_param_ > (_high_)))
 723
 724 /* If the parameter has been set by the user, check that the parameter value is
 725  * within the value range of values.  If not, report a module error. */
 726 #define DWC_OTG_PARAM_ERR(_param_,_low_,_high_,_string_) \
 727                 do { \
 728                         if (core_params->_param_ != -1) { \
 729                                 if (DWC_OTG_PARAM_TEST(_param_,(_low_),(_high_))) { \
 730                                         DWC_ERROR("`%d' invalid for parameter `%s'\n", \
 731                                                 core_params->_param_, _string_); \
 732                                         core_params->_param_ = dwc_param_##_param_##_default; \
 733                                         retval ++; \
 734                                 } \
 735                         } \
 736                 } while (0)
 737
 738         DWC_OTG_PARAM_ERR(opt,0,1,"opt");
 739         DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap");
 740         DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable");
 741         DWC_OTG_PARAM_ERR(speed,0,1,"speed");
 742         DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power");
 743         DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk");
 744         DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo");
 745         DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size");
 746         DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size");
 747         DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size");
 748         DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size");
 749         DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size");
 750         DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size");
 751         DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size");
 752         DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count");
 753         DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels");
 754         DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints");
 755         DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type");
 756         DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr");
 757         DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus");
 758         DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable");
 759         DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls");
 760         DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline");
 761
 762         if (core_params->dma_burst_size != -1)
 763         {
 764                 if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) &&
 765                         DWC_OTG_PARAM_TEST(dma_burst_size,4,4) &&
 766                         DWC_OTG_PARAM_TEST(dma_burst_size,8,8) &&
 767                         DWC_OTG_PARAM_TEST(dma_burst_size,16,16) &&
 768                         DWC_OTG_PARAM_TEST(dma_burst_size,32,32) &&
 769                         DWC_OTG_PARAM_TEST(dma_burst_size,64,64) &&
 770                         DWC_OTG_PARAM_TEST(dma_burst_size,128,128) &&
 771                         DWC_OTG_PARAM_TEST(dma_burst_size,256,256))
 772                 {
 773                         DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
 774                                   core_params->dma_burst_size);
 775                         core_params->dma_burst_size = 32;
 776                         retval ++;
 777                 }
 778         }
 779
 780         if (core_params->phy_utmi_width != -1)
 781         {
 782                 if (DWC_OTG_PARAM_TEST(phy_utmi_width,8,8) &&
 783                         DWC_OTG_PARAM_TEST(phy_utmi_width,16,16))
 784                 {
 785                         DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n",
 786                                   core_params->phy_utmi_width);
 787                         core_params->phy_utmi_width = 16;
 788                         retval ++;
 789                 }
 790         }
 791
 792         for (i=0; i<15; i++)
 793         {
 794                 /** @todo should be like above */
 795                 //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i],4,768,"dev_perio_tx_fifo_size");
 796                 if (core_params->dev_perio_tx_fifo_size[i] != -1)
 797                 {
 798                         if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i],4,768))
 799                         {
 800                                 DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
 801                                           core_params->dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i);
 802                                 core_params->dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
 803                                 retval ++;
 804                         }
 805                 }
 806         }
 807
 808         DWC_OTG_PARAM_ERR(en_multiple_tx_fifo,0,1,"en_multiple_tx_fifo");
 809
 810         for (i=0; i<15; i++)
 811         {
 812                 /** @todo should be like above */
 813                 //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i],4,768,"dev_tx_fifo_size");
 814                 if (core_params->dev_tx_fifo_size[i] != -1)
 815                 {
 816                         if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i],4,768))
 817                         {
 818                                 DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
 819                                           core_params->dev_tx_fifo_size[i], "dev_tx_fifo_size", i);
 820                                 core_params->dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
 821                                 retval ++;
 822                         }
 823                 }
 824         }
 825
 826         DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl");
 827         DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length");
 828         DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length");
 829
 830
 831         /* At this point, all module parameters that have been set by the user
 832          * are valid, and those that have not are left unset.  Now set their
 833          * default values and/or check the parameters against the hardware
 834          * configurations of the OTG core. */
 835
 836
 837
 838 /* This sets the parameter to the default value if it has not been set by the
 839  * user */
 840 #define DWC_OTG_PARAM_SET_DEFAULT(_param_) \
 841         ({ \
 842                 int changed = 1; \
 843                 if (core_params->_param_ == -1) { \
 844                         changed = 0; \
 845                         core_params->_param_ = dwc_param_##_param_##_default; \
 846                 } \
 847                 changed; \
 848         })
 849
 850 /* This checks the macro agains the hardware configuration to see if it is
 851  * valid.  It is possible that the default value could be invalid.      In this
 852  * case, it will report a module error if the user touched the parameter.
 853  * Otherwise it will adjust the value without any error. */
 854 #define DWC_OTG_PARAM_CHECK_VALID(_param_,_str_,_is_valid_,_set_valid_) \
 855         ({ \
 856                         int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
 857                 int error = 0; \
 858                 if (!(_is_valid_)) { \
 859                         if (changed) { \
 860                                 DWC_ERROR("`%d' invalid for parameter `%s'.      Check HW configuration.\n", core_params->_param_,_str_); \
 861                                 error = 1; \
 862                         } \
 863                         core_params->_param_ = (_set_valid_); \
 864                 } \
 865                 error; \
 866         })
 867
 868         /* OTG Cap */
 869         retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap,"otg_cap",
 870                                   ({
 871                                           int valid;
 872                                           valid = 1;
 873                                           switch (core_params->otg_cap) {
 874                                           case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
 875                                                   if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) valid = 0;
 876                                                   break;
 877                                           case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
 878                                                   if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) &&
 879                                                           (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) &&
 880                                                           (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) &&
 881                                                           (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST))
 882                                                   {
 883                                                           valid = 0;
 884                                                   }
 885                                                   break;
 886                                           case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
 887                                                   /* always valid */
 888                                                   break;
 889                                           }
 890                                           valid;
 891                           }),
 892                                         (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
 893                                         (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ||
 894                                         (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
 895                                         (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
 896                                         DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
 897                                         DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE));
 898
 899         retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable,"dma_enable",
 900                                 ((core_params->dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
 901                                 0);
 902
 903         retval += DWC_OTG_PARAM_CHECK_VALID(opt,"opt",
 904                                 1,
 905                                 0);
 906
 907         DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size);
 908
 909         retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power,
 910                                 "host_support_fs_ls_low_power",
 911                                 1, 0);
 912
 913         retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo,
 914                                         "enable_dynamic_fifo",
 915                                         ((core_params->enable_dynamic_fifo == 0) ||
 916                                         (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
 917
 918
 919         retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size,
 920                                         "data_fifo_size",
 921                                         (core_params->data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
 922                                         core_if->hwcfg3.b.dfifo_depth);
 923
 924         retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size,
 925                                         "dev_rx_fifo_size",
 926                                         (core_params->dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
 927                                         dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
 928
 929         retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size,
 930                                         "dev_nperio_tx_fifo_size",
 931                                         (core_params->dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
 932                                         (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
 933
 934         retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size,
 935                                         "host_rx_fifo_size",
 936                                         (core_params->host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
 937                                         dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
 938
 939
 940         retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size,
 941                                         "host_nperio_tx_fifo_size",
 942                                         (core_params->host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
 943                                         (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
 944         retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size,
 945                                         "host_perio_tx_fifo_size",
 946                                         (core_params->host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
 947                                         ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16)));
 948
 949         retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size,
 950                                         "max_transfer_size",
 951                                         (core_params->max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
 952                                         ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1));
 953
 954         retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count,
 955                                         "max_packet_count",
 956                                         (core_params->max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
 957                                         ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1));
 958
 959         retval += DWC_OTG_PARAM_CHECK_VALID(host_channels,
 960                                         "host_channels",
 961                                         (core_params->host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
 962                                         (core_if->hwcfg2.b.num_host_chan + 1));
 963
 964         retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints,
 965                                         "dev_endpoints",
 966                                         (core_params->dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
 967                                         core_if->hwcfg2.b.num_dev_ep);
 968
 969 /*
 970  * Define the following to disable the FS PHY Hardware checking.  This is for
 971  * internal testing only.
 972  *
 973  * #define NO_FS_PHY_HW_CHECKS
 974  */
 975
 976 #ifdef NO_FS_PHY_HW_CHECKS
 977         retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
 978                                 "phy_type", 1, 0);
 979 #else
 980         retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
 981                                 "phy_type",
 982                                 ({
 983                                         int valid = 0;
 984                                         if ((core_params->phy_type == DWC_PHY_TYPE_PARAM_UTMI) &&
 985                                         ((core_if->hwcfg2.b.hs_phy_type == 1) ||
 986                                          (core_if->hwcfg2.b.hs_phy_type == 3)))
 987                                         {
 988                                                 valid = 1;
 989                                         }
 990                                         else if ((core_params->phy_type == DWC_PHY_TYPE_PARAM_ULPI) &&
 991                                                  ((core_if->hwcfg2.b.hs_phy_type == 2) ||
 992                                                   (core_if->hwcfg2.b.hs_phy_type == 3)))
 993                                         {
 994                                                 valid = 1;
 995                                         }
 996                                         else if ((core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
 997                                                  (core_if->hwcfg2.b.fs_phy_type == 1))
 998                                         {
 999                                                 valid = 1;
1000                                         }
1001                                         valid;
1002                                 }),
1003                                 ({
1004                                         int set = DWC_PHY_TYPE_PARAM_FS;
1005                                         if (core_if->hwcfg2.b.hs_phy_type) {
1006                                                 if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
1007                                                 (core_if->hwcfg2.b.hs_phy_type == 1)) {
1008                                                         set = DWC_PHY_TYPE_PARAM_UTMI;
1009                                                 }
1010                                                 else {
1011                                                         set = DWC_PHY_TYPE_PARAM_ULPI;
1012                                                 }
1013                                         }
1014                                         set;
1015                                 }));
1016 #endif
1017
1018         retval += DWC_OTG_PARAM_CHECK_VALID(speed,"speed",
1019                                 (core_params->speed == 0) && (core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
1020                                 core_params->phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
1021
1022         retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk,
1023                                 "host_ls_low_power_phy_clk",
1024                                 ((core_params->host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
1025                                 ((core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
1026
1027         DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr);
1028         DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus);
1029         DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width);
1030         DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls);
1031         DWC_OTG_PARAM_SET_DEFAULT(ts_dline);
1032
1033 #ifdef NO_FS_PHY_HW_CHECKS
1034         retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
1035                                 "i2c_enable", 1, 0);
1036 #else
1037         retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
1038                                 "i2c_enable",
1039                                 (core_params->i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
1040                                 0);
1041 #endif
1042
1043         for (i=0; i<15; i++)
1044         {
1045                 int changed = 1;
1046                 int error = 0;
1047
1048                 if (core_params->dev_perio_tx_fifo_size[i] == -1)
1049                 {
1050                         changed = 0;
1051                         core_params->dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
1052                 }
1053                 if (!(core_params->dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]))))
1054                 {
1055                         if (changed)
1056                         {
1057                                 DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'.  Check HW configuration.\n", core_params->dev_perio_tx_fifo_size[i],i);
1058                                 error = 1;
1059                         }
1060                         core_params->dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
1061                 }
1062                 retval += error;
1063         }
1064
1065
1066         retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo,"en_multiple_tx_fifo",
1067                                                 ((core_params->en_multiple_tx_fifo == 1) && (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1,
1068                                                 0);
1069
1070
1071         for (i=0; i<15; i++)
1072         {
1073
1074                 int changed = 1;
1075                 int error = 0;
1076
1077                 if (core_params->dev_tx_fifo_size[i] == -1)
1078                 {
1079                         changed = 0;
1080                         core_params->dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
1081                 }
1082                 if (!(core_params->dev_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]))))
1083                 {
1084                         if (changed)
1085                         {
1086                                 DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'.  Check HW configuration.\n", core_params->dev_tx_fifo_size[i],i);
1087                                 error = 1;
1088                         }
1089                         core_params->dev_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
1090                 }
1091                 retval += error;
1092
1093
1094         }
1095
1096         DWC_OTG_PARAM_SET_DEFAULT(thr_ctl);
1097         DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length);
1098         DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length);
1099
1100         return retval;
1101 }
1102 /**
1103  * This function is the top level interrupt handler for the Common
1104  * (Device and host modes) interrupts.
1105  */
1106 static irqreturn_t dwc_otg_common_irq(int _irq, void *_dev)
1107 {
1108         dwc_otg_device_t *otg_dev = _dev;
1109         int32_t retval = IRQ_NONE;
1110
1111         retval = dwc_otg_handle_common_intr( otg_dev->core_if );
1112         return IRQ_RETVAL(retval);
1113 }
1114
1115 /**
1116  * This function is called when a lm_device is unregistered with the
1117  * dwc_otg_driver. This happens, for example, when the rmmod command is
1118  * executed. The device may or may not be electrically present. If it is
1119  * present, the driver stops device processing. Any resources used on behalf
1120  * of this device are freed.
1121  *
1122  * @param[in] pdev
1123  */
1124 static int dwc_otg_driver_remove(struct platform_device *pdev)
1125 {
1126         struct device *dev = &pdev->dev;
1127         dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
1128         DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, pdev);
1129
1130         if (otg_dev == NULL)
1131         {
1132                 /* Memory allocation for the dwc_otg_device failed. */
1133                 return 0;
1134         }
1135
1136         /*
1137          * Free the IRQ
1138          */
1139         if (otg_dev->common_irq_installed)
1140         {
1141                 free_irq( platform_get_irq(to_platform_device(dev),0), otg_dev );
1142         }
1143
1144 #ifndef CONFIG_DWC_OTG_DEVICE_ONLY
1145         if (otg_dev->hcd != NULL)
1146         {
1147                 dwc_otg_hcd_remove(dev);
1148         }
1149 #endif
1150
1151 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1152         if (otg_dev->pcd != NULL)
1153         {
1154                 dwc_otg_pcd_remove(dev);
1155         }
1156 #endif
1157         if (otg_dev->core_if != NULL)
1158         {
1159                 dwc_otg_cil_remove( otg_dev->core_if );
1160         }
1161
1162         /*
1163          * Remove the device attributes
1164          */
1165         dwc_otg_attr_remove(dev);
1166
1167         /*
1168          * Return the memory.
1169          */
1170         if (otg_dev->base != NULL)
1171         {
1172                 iounmap(otg_dev->base);
1173         }
1174         kfree(otg_dev);
1175
1176         /*
1177          * Clear the drvdata pointer.
1178          */
1179 //      dev->platform_data = 0;
1180
1181 #ifdef DWC_BOTH_HOST_SLAVE
1182         dwc_otg_module_params.host_rx_fifo_size = -1;
1183         dwc_otg_module_params.dev_nperio_tx_fifo_size = -1;
1184         dwc_otg_module_params.host_nperio_tx_fifo_size = -1;
1185         dwc_otg_module_params.dev_rx_fifo_size = -1;
1186 #endif
1187         return 0;
1188 }
1189
1190 /**
1191  * This function is called when an lm_device is bound to a
1192  * dwc_otg_driver. It creates the driver components required to
1193  * control the device (CIL, HCD, and PCD) and it initializes the
1194  * device. The driver components are stored in a dwc_otg_device
1195  * structure. A reference to the dwc_otg_device is saved in the
1196  * lm_device. This allows the driver to access the dwc_otg_device
1197  * structure on subsequent calls to driver methods for this device.
1198  *
1199  * @param[in] pdev  platform_device definition
1200  */
1201 static __devinit int dwc_otg_driver_probe(struct platform_device *pdev)
1202 {
1203         int retval = 0;
1204         struct resource *res_base;
1205         struct device *dev = &pdev->dev;
1206         dwc_otg_device_t *dwc_otg_device;
1207         int32_t snpsid;
1208         int irq;
1209         struct dwc_otg_platform_data *pldata = dev->platform_data;
1210
1211     // clock and hw init
1212     if(pldata->hw_init)
1213         pldata->hw_init();
1214
1215
1216     if(pldata->clock_init){
1217         pldata->clock_init(pldata);
1218         pldata->clock_enable(pldata, 1);
1219         }
1220
1221     if(pldata->phy_suspend)
1222         pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1223
1224     if(pldata->soft_reset)
1225         pldata->soft_reset();
1226
1227         dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
1228
1229         if (dwc_otg_device == 0)
1230         {
1231                 dev_err(dev, "kmalloc of dwc_otg_device failed\n");
1232                 retval = -ENOMEM;
1233                 goto fail;
1234         }
1235
1236         memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1237         dwc_otg_device->reg_offset = 0xFFFFFFFF;
1238
1239         /*
1240          * Map the DWC_otg Core memory into virtual address space.
1241          */
1242
1243         res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1244         if (!res_base)
1245                 goto fail;
1246
1247         dwc_otg_device->base =  ioremap(res_base->start,res_base->end-res_base->start+1);
1248         if (dwc_otg_device->base == NULL)
1249         {
1250                 dev_err(dev, "ioremap() failed\n");
1251                 retval = -ENOMEM;
1252                 goto fail;
1253         }
1254 #if 0
1255         dwc_otg_device->base = (void*)(USB_OTG_BASE_ADDR_VA);
1256
1257         if (dwc_otg_device->base == NULL)
1258         {
1259                 dev_err(dev, "ioremap() failed\n");
1260                 retval = -ENOMEM;
1261                 goto fail;
1262         }
1263 #endif
1264         dev_dbg(dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base);
1265         /*
1266          * Attempt to ensure this device is really a DWC_otg Controller.
1267          * Read and verify the SNPSID register contents. The value should be
1268          * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
1269          */
1270         snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40));
1271         if ((snpsid & 0xFFFFF000) != 0x4F542000)
1272         {
1273                 dev_err(dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
1274                 retval = -EINVAL;
1275                 goto fail;
1276         }
1277
1278         /*
1279          * Initialize driver data to point to the global DWC_otg
1280          * Device structure.
1281          */
1282     //dev->platform_data = dwc_otg_device;
1283         pldata->privdata =  dwc_otg_device;
1284         dwc_otg_device->pldata = (void *)pldata;
1285
1286         dev_dbg(dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1287
1288         g_otgdev = dwc_otg_device;
1289
1290         dwc_otg_device->core_if = dwc_otg_cil_init( dwc_otg_device->base,
1291                                                         &dwc_otg_module_params);
1292         if (dwc_otg_device->core_if == 0)
1293         {
1294                 dev_err(dev, "CIL initialization failed!\n");
1295                 retval = -ENOMEM;
1296                 goto fail;
1297         }
1298         dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1299         /*
1300          * Validate parameter values.
1301          */
1302         if (check_parameters(dwc_otg_device->core_if) != 0)
1303         {
1304                 retval = -EINVAL;
1305                 goto fail;
1306         }
1307
1308         /*
1309          * Create Device Attributes in sysfs
1310          */
1311         dwc_otg_attr_create(dev);
1312 #ifndef CONFIG_DWC_OTG_DEVICE_ONLY
1313         retval |= device_create_file(dev, &dev_attr_enable);
1314 #endif
1315
1316         /*
1317          * Disable the global interrupt until all the interrupt
1318          * handlers are installed.
1319          */
1320         dwc_otg_disable_global_interrupts( dwc_otg_device->core_if );
1321         /*
1322          * Install the interrupt handler for the common interrupts before
1323          * enabling common interrupts in core_init below.
1324          */
1325         irq = platform_get_irq(to_platform_device(dev),0);
1326         DWC_DEBUGPL( DBG_CIL, "registering (common) handler for irq%d\n",
1327                          irq);
1328         retval = request_irq(irq, dwc_otg_common_irq,
1329                                  IRQF_SHARED, "dwc_otg", dwc_otg_device );
1330         if (retval != 0)
1331         {
1332                 DWC_ERROR("request of irq%d failed\n", irq);
1333                 retval = -EBUSY;
1334                 goto fail;
1335         }
1336         else
1337         {
1338                 dwc_otg_device->common_irq_installed = 1;
1339         }
1340
1341 #ifdef CONFIG_MACH_IPMATE
1342         set_irq_type(irq, IRQT_LOW);
1343 #endif
1344
1345 #ifdef CONFIG_DWC_OTG_DEVICE_ONLY
1346         dwc_otg_device->core_if->usb_mode = USB_MODE_FORCE_DEVICE;
1347 #else
1348 #ifdef CONFIG_DWC_OTG_HOST_ONLY
1349         dwc_otg_device->core_if->usb_mode = USB_MODE_FORCE_HOST;
1350 #else
1351
1352 #ifdef CONFIG_DWC_OTG_DEFAULT_HOST
1353         dwc_otg_device->core_if->usb_mode = USB_MODE_FORCE_HOST;
1354 #else
1355         dwc_otg_device->core_if->usb_mode = USB_MODE_NORMAL;
1356 #ifdef CONFIG_DWC_OTG_DEFAULT_DEVICE
1357         dwc_otg_device->core_if->usb_mode = USB_MODE_FORCE_DEVICE;
1358 #endif
1359 #endif
1360
1361 #endif
1362 #endif
1363
1364         /*
1365          * Initialize the DWC_otg core.
1366          */
1367         dwc_otg_core_init( dwc_otg_device->core_if );
1368
1369 /* Initialize the bus state.  If the core is in Device Mode
1370  * HALT the USB bus and return. */
1371 #ifndef CONFIG_DWC_OTG_DEVICE_ONLY
1372         /*
1373          * Initialize the HCD
1374          */
1375         retval = dwc_otg_hcd_init(dev);
1376         if (retval != 0)
1377         {
1378                 DWC_ERROR("dwc_otg_hcd_init failed\n");
1379                 dwc_otg_device->hcd = NULL;
1380                 goto fail;
1381         }
1382 #endif
1383 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1384         /*
1385          * Initialize the PCD
1386          */
1387         retval = dwc_otg_pcd_init(dev);
1388         if (retval != 0)
1389         {
1390                 DWC_ERROR("dwc_otg_pcd_init failed\n");
1391                 dwc_otg_device->pcd = NULL;
1392                 goto fail;
1393         }
1394 #endif
1395
1396
1397         /*
1398          * Enable the global interrupt after all the interrupt
1399          * handlers are installed.
1400          */
1401         dwc_otg_enable_global_interrupts( dwc_otg_device->core_if );
1402         return 0;
1403  fail:
1404         devm_kfree(&pdev->dev, dwc_otg_device);
1405         DWC_PRINT("dwc_otg_driver_probe fail,everest\n");
1406         return retval;
1407 }
1408
1409 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1410 static int dwc_otg_driver_suspend(struct platform_device *_dev , pm_message_t state )
1411 {
1412         struct device *dev = &_dev->dev;
1413         dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
1414     dwc_otg_core_if_t *core_if = otg_dev->core_if;
1415         struct dwc_otg_platform_data *pldata = dev->platform_data;
1416     if(core_if->op_state == A_HOST)
1417     {
1418         DWC_PRINT("%s,A_HOST mode\n", __func__);
1419         return 0;
1420     }
1421     /* Clear any pending interrupts */
1422     dwc_write_reg32( &core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1423 //    dwc_otg_disable_global_interrupts(core_if);
1424     if( pldata->phy_status == 0 ){
1425         /* no vbus detect here , close usb phy  */
1426         pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1427         udelay(3);
1428         pldata->clock_enable( pldata, 0);
1429     }
1430 //    del_timer(&otg_dev->pcd->check_vbus_timer);
1431
1432     return 0;
1433 }
1434 #else
1435 static int dwc_otg_driver_suspend(struct platform_device *_dev , pm_message_t state )
1436 {
1437     return 0;
1438 }
1439 #endif
1440
1441 static int dwc_otg_driver_resume(struct platform_device *_dev )
1442 {
1443         struct device *dev = &_dev->dev;
1444         dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
1445     dwc_otg_core_if_t *core_if = otg_dev->core_if;
1446     dctl_data_t dctl = {.d32=0};
1447         struct dwc_otg_platform_data *pldata = dev->platform_data;
1448
1449     dwc_otg_core_global_regs_t *global_regs =
1450         core_if->core_global_regs;
1451     if(core_if->op_state == A_HOST)
1452     {
1453         DWC_PRINT("%s,A_HOST mode\n", __func__);
1454         return 0;
1455     }
1456     return 0;
1457 }
1458
1459 static void dwc_otg_driver_shutdown(struct platform_device *_dev )
1460 {
1461         struct device *dev = &_dev->dev;
1462         dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
1463     dwc_otg_core_if_t *core_if = otg_dev->core_if;
1464     dctl_data_t dctl = {.d32=0};
1465
1466     DWC_PRINT("%s:: disconnect USB\n" , __func__ );
1467     if(core_if->op_state == A_HOST)
1468     {
1469         if (core_if->hcd_cb && core_if->hcd_cb->stop) {
1470                 core_if->hcd_cb->stop( core_if->hcd_cb->p );
1471         }
1472     }
1473     else{
1474         /* soft disconnect */
1475         dctl.d32 = dwc_read_reg32( &core_if->dev_if->dev_global_regs->dctl );
1476         dctl.b.sftdiscon = 1;
1477         dwc_write_reg32( &core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
1478     }
1479     /* Clear any pending interrupts */
1480     dwc_write_reg32( &core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1481
1482 }
1483
1484 /**
1485  * This structure defines the methods to be called by a bus driver
1486  * during the lifecycle of a device on that bus. Both drivers and
1487  * devices are registered with a bus driver. The bus driver matches
1488  * devices to drivers based on information in the device and driver
1489  * structures.
1490  *
1491  * The probe function is called when the bus driver matches a device
1492  * to this driver. The remove function is called when a device is
1493  * unregistered with the bus driver.
1494  */
1495 static struct platform_driver dwc_otg_driver = {
1496         .probe = dwc_otg_driver_probe,
1497         .remove = dwc_otg_driver_remove,
1498         .suspend = dwc_otg_driver_suspend,
1499         .resume = dwc_otg_driver_resume,
1500         .shutdown = dwc_otg_driver_shutdown,
1501         .driver = {
1502                    .name = dwc_driver_name,
1503                    .owner = THIS_MODULE},
1504 };
1505
1506
1507 #ifdef CONFIG_USB20_HOST
1508 extern void dwc_otg_hcd_remove(struct device *dev);
1509 extern int __devinit host20_hcd_init(struct device *_dev);
1510
1511
1512 static int host20_driver_remove(struct platform_device *pdev)
1513 {
1514         struct device *dev = &pdev->dev;
1515         dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
1516         DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, pdev);
1517
1518         if (otg_dev == NULL)
1519         {
1520                 /* Memory allocation for the dwc_otg_device failed. */
1521                 return 0;
1522         }
1523
1524         /*
1525          * Free the IRQ
1526          */
1527         if (otg_dev->common_irq_installed)
1528         {
1529                 free_irq( platform_get_irq(to_platform_device(dev),0), otg_dev );
1530         }
1531
1532         if (otg_dev->hcd != NULL)
1533         {
1534                 dwc_otg_hcd_remove(dev);
1535         }
1536
1537         if (otg_dev->core_if != NULL)
1538         {
1539                 dwc_otg_cil_remove( otg_dev->core_if );
1540         }
1541
1542         /*
1543          * Remove the device attributes
1544          */
1545         //dwc_otg_attr_remove(dev);
1546
1547         /*
1548          * Return the memory.
1549          */
1550         if (otg_dev->base != NULL)
1551         {
1552                 iounmap(otg_dev->base);
1553         }
1554         kfree(otg_dev);
1555
1556         /*
1557          * Clear the drvdata pointer.
1558          */
1559 //      dev->platform_data = 0;
1560
1561
1562         return 0;
1563 }
1564
1565 /**
1566  * This function is called when an lm_device is bound to a
1567  * dwc_otg_driver. It creates the driver components required to
1568  * control the device (CIL, HCD, and PCD) and it initializes the
1569  * device. The driver components are stored in a dwc_otg_device
1570  * structure. A reference to the dwc_otg_device is saved in the
1571  * lm_device. This allows the driver to access the dwc_otg_device
1572  * structure on subsequent calls to driver methods for this device.
1573  *
1574  * @param[in] pdev  platform_device definition
1575  */
1576 static __devinit int host20_driver_probe(struct platform_device *pdev)
1577 {
1578         struct resource *res_base;
1579         int retval = 0;
1580         struct device *dev = &pdev->dev;
1581         dwc_otg_device_t *dwc_otg_device;
1582         int32_t snpsid;
1583         int irq;
1584         struct dwc_otg_platform_data *pldata = dev->platform_data;
1585
1586     // clock and hw init
1587     if(pldata->hw_init)
1588         pldata->hw_init();
1589
1590     if(pldata->clock_init){
1591         pldata->clock_init(pldata);
1592         pldata->clock_enable(pldata, 1);
1593         }
1594
1595     if(pldata->phy_suspend)
1596         pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1597
1598     if(pldata->soft_reset)
1599         pldata->soft_reset();
1600
1601         /*
1602          *Enable usb phy
1603          */
1604
1605         dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
1606
1607         if (dwc_otg_device == 0)
1608         {
1609                 dev_err(dev, "kmalloc of dwc_otg_device failed\n");
1610                 retval = -ENOMEM;
1611                 goto fail;
1612         }
1613
1614         memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1615         dwc_otg_device->reg_offset = 0xFFFFFFFF;
1616
1617         /*
1618          * Map the DWC_otg Core memory into virtual address space.
1619          */
1620
1621         res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1622         if (!res_base)
1623                 goto fail;
1624
1625         dwc_otg_device->base =
1626                 ioremap(res_base->start,res_base->end-res_base->start+1);
1627     DWC_PRINT("%s host2.0 reg addr: 0x%x remap:0x%x\n",__func__,
1628                 (unsigned)res_base->start, (unsigned)dwc_otg_device->base);
1629         if (dwc_otg_device->base == NULL)
1630         {
1631                 DWC_ERROR("ioremap() failed\n");
1632                 retval = -ENOMEM;
1633                 goto fail;
1634         }
1635         DWC_DEBUGPL( DBG_CIL, "base addr for rk29 host20:0x%x\n", (unsigned)dwc_otg_device->base);
1636         /*
1637          * Attempt to ensure this device is really a DWC_otg Controller.
1638          * Read and verify the SNPSID register contents. The value should be
1639          * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
1640          */
1641         snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40));
1642         if ((snpsid & 0xFFFFF000) != 0x4F542000)
1643         {
1644                         DWC_PRINT("%s::snpsid=0x%x,want 0x%x" , __func__ , snpsid , 0x4F542000 );
1645                 dev_err(dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
1646                 retval = -EINVAL;
1647                 goto fail;
1648         }
1649
1650         /*
1651          * Initialize driver data to point to the global DWC_otg
1652          * Device structure.
1653          */
1654         pldata->privdata = dwc_otg_device;
1655         dwc_otg_device->pldata = (void *)pldata;
1656
1657         DWC_DEBUGPL(DBG_CIL, "dwc_otg_device=0x%p\n", dwc_otg_device);
1658         g_host20 = dwc_otg_device;
1659
1660         dwc_otg_device->core_if = dwc_otg_cil_init( dwc_otg_device->base,
1661                                                         &host20_module_params);
1662         if (dwc_otg_device->core_if == 0)
1663         {
1664                 dev_err(dev, "CIL initialization failed!\n");
1665                 retval = -ENOMEM;
1666                 goto fail;
1667         }
1668
1669         dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1670         /*
1671          * Validate parameter values.
1672          */
1673         if (check_parameters(dwc_otg_device->core_if) != 0)
1674         {
1675                 retval = -EINVAL;
1676                 goto fail;
1677         }
1678
1679         /*
1680          * Create Device Attributes in sysfs
1681          */
1682         dwc_otg_attr_create(dev);
1683         retval |= device_create_file(dev, &dev_attr_enable);
1684
1685         /*
1686          * Disable the global interrupt until all the interrupt
1687          * handlers are installed.
1688          */
1689         dwc_otg_disable_global_interrupts( dwc_otg_device->core_if );
1690         /*
1691          * Install the interrupt handler for the common interrupts before
1692          * enabling common interrupts in core_init below.
1693          */
1694         irq = platform_get_irq(to_platform_device(dev),0);
1695         DWC_DEBUGPL( DBG_CIL, "registering (common) handler for irq%d\n",
1696                          irq);
1697         retval = request_irq(irq, dwc_otg_common_irq,
1698                                  IRQF_SHARED, "dwc_otg", dwc_otg_device );
1699         if (retval != 0)
1700         {
1701                 DWC_ERROR("request of irq%d failed\n", irq);
1702                 retval = -EBUSY;
1703                 goto fail;
1704         }
1705         else
1706         {
1707                 dwc_otg_device->common_irq_installed = 1;
1708         }
1709
1710         /*
1711          * Initialize the DWC_otg core.
1712          */
1713         dwc_otg_core_init( dwc_otg_device->core_if );
1714
1715         /*
1716          * Initialize the HCD
1717          */
1718         retval = host20_hcd_init(dev);
1719         if (retval != 0)
1720         {
1721                 DWC_ERROR("host20_hcd_init failed\n");
1722                 dwc_otg_device->hcd = NULL;
1723                 goto fail;
1724         }
1725         /*
1726          * Enable the global interrupt after all the interrupt
1727          * handlers are installed.
1728          */
1729         dwc_otg_enable_global_interrupts( dwc_otg_device->core_if );
1730
1731         return 0;
1732
1733  fail:
1734         devm_kfree(&pdev->dev, dwc_otg_device);
1735         DWC_PRINT("host20_driver_probe fail,everest\n");
1736         return retval;
1737 }
1738
1739 static struct platform_driver host20_driver = {
1740         .probe = host20_driver_probe,
1741         .remove = host20_driver_remove,
1742         .driver = {
1743                    .name = "usb20_host",
1744                    .owner = THIS_MODULE},
1745 };
1746 #endif
1747
1748 /**
1749  * This function is called when the dwc_otg_driver is installed with the
1750  * insmod command. It registers the dwc_otg_driver structure with the
1751  * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1752  * to be called. In addition, the bus driver will automatically expose
1753  * attributes defined for the device and driver in the special sysfs file
1754  * system.
1755  *
1756  * @return
1757  */
1758 static int __init dwc_otg_driver_init(void)
1759 {
1760         int retval = 0;
1761     /*
1762      *  USB2.0 OTG controller
1763      */
1764         retval = platform_driver_register(&dwc_otg_driver);
1765         if (retval < 0)
1766         {
1767                 DWC_ERROR("%s retval=%d\n", __func__, retval);
1768                 return retval;
1769         }
1770         if (driver_create_file(&dwc_otg_driver.driver, &driver_attr_version))
1771                 pr_warning("DWC_OTG: Failed to create driver version file\n");
1772         if (driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel))
1773                 pr_warning("DWC_OTG: Failed to create driver debug level file\n");
1774 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1775         if(driver_create_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_conn_en))
1776                 pr_warning("DWC_OTG: Failed to create driver dwc_otg_conn_en file");
1777 #endif
1778
1779 #ifdef CONFIG_RK_USB_UART
1780 if(driver_create_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_force_uart))
1781     pr_warning("DWC_OTG: Failed to create driver dwc_otg_force_uart file");
1782 #endif
1783 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1784         if(driver_create_file(&dwc_otg_driver.driver, &driver_attr_vbus_status))
1785                 pr_warning("DWC_OTG: Failed to create driver vbus status file");
1786 #endif
1787 #ifdef DWC_BOTH_HOST_SLAVE
1788     if(driver_create_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode))
1789                 pr_warning("DWC_OTG: Failed to create driver force usb mode file\n");
1790 #endif
1791
1792     /*
1793      *  USB2.0 host controller
1794      */
1795 #ifdef CONFIG_USB20_HOST
1796     retval = platform_driver_register(&host20_driver);
1797     if (retval < 0)
1798     {
1799         DWC_ERROR("%s retval=%d\n", __func__, retval);
1800         return retval;
1801     }
1802 #endif
1803
1804     /*
1805      *  USB1.1 host controller
1806      */
1807
1808 #ifdef CONFIG_USB11_HOST
1809         retval = platform_driver_register(&host11_driver);
1810         if (retval < 0)
1811         {
1812                 DWC_ERROR("%s retval=%d\n", __func__, retval);
1813                 return retval;
1814         }
1815 //      retval = driver_create_file(&host11_driver.driver, &driver_attr_enable_usb11);
1816 #endif
1817
1818         return retval;
1819 }
1820 module_init(dwc_otg_driver_init);
1821
1822 /**
1823  * This function is called when the driver is removed from the kernel
1824  * with the rmmod command. The driver unregisters itself with its bus
1825  * driver.
1826  *
1827  */
1828 static void __exit dwc_otg_driver_cleanup(void)
1829 {
1830         DWC_PRINT("dwc_otg_driver_cleanup()\n");
1831
1832         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1833         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1834
1835 #ifdef DWC_BOTH_HOST_SLAVE
1836         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1837 #endif
1838 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1839     driver_remove_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_conn_en);
1840 #endif
1841
1842 #ifdef CONFIG_RK_USB_UART
1843     driver_remove_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_force_uart);
1844 #endif
1845
1846 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1847     driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1848 #endif
1849
1850         platform_driver_unregister(&dwc_otg_driver);
1851
1852 #ifdef CONFIG_USB11_HOST
1853         platform_driver_unregister(&host11_driver);
1854 #endif
1855
1856 #ifdef CONFIG_USB20_HOST
1857         platform_driver_unregister(&host20_driver);
1858 #endif
1859         DWC_PRINT("%s module removed\n", dwc_driver_name);
1860 }
1861 module_exit(dwc_otg_driver_cleanup);
1862
1863 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1864 MODULE_AUTHOR("Synopsys Inc.");
1865 MODULE_LICENSE("GPL");
1866
1867 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1868 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1869 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1870 MODULE_PARM_DESC(opt, "OPT Mode");
1871 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1872 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1873 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444);
1874 MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1875 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1876 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1877 module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444);
1878 MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1879 module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1880 MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1881 module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1882 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1883 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444);
1884 MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
1885 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444);
1886 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1887 module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1888 MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
1889 module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1890 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768");
1891 module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1892 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768");
1893 module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1894 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768");
1895 module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1896 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768");
1897 module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1898 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768");
1899 module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1900 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768");
1901 module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1902 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768");
1903 module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1904 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768");
1905 module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1906 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768");
1907 module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1908 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768");
1909 module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1910 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768");
1911 module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1912 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768");
1913 module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1914 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768");
1915 module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1916 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768");
1917 module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1918 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768");
1919 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444);
1920 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1921 module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1922 MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
1923 module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1924 MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
1925 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444);
1926 /** @todo Set the max to 512K, modify checks */
1927 MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
1928 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444);
1929 MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
1930 module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444);
1931 MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
1932 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444);
1933 MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
1934 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1935 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1936 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444);
1937 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1938 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1939 MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double");
1940 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444);
1941 MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal");
1942 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1943 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1944 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1945 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1946 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1947 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1948 module_param_named(debug, g_dbg_lvl, int, 0444);
1949 MODULE_PARM_DESC(debug, "");
1950
1951 module_param_named(en_multiple_tx_fifo, dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1952 MODULE_PARM_DESC(en_multiple_tx_fifo, "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1953 module_param_named(dev_tx_fifo_size_1, dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1954 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1955 module_param_named(dev_tx_fifo_size_2, dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1956 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1957 module_param_named(dev_tx_fifo_size_3, dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1958 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1959 module_param_named(dev_tx_fifo_size_4, dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1960 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1961 module_param_named(dev_tx_fifo_size_5, dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1962 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1963 module_param_named(dev_tx_fifo_size_6, dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1964 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1965 module_param_named(dev_tx_fifo_size_7, dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1966 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1967 module_param_named(dev_tx_fifo_size_8, dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1968 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1969 module_param_named(dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1970 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1971 module_param_named(dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1972 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
1973 module_param_named(dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1974 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
1975 module_param_named(dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1976 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
1977 module_param_named(dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1978 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
1979 module_param_named(dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
1980 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
1981 module_param_named(dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
1982 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
1983
1984 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
1985 MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
1986 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444);
1987 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
1988 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444);
1989 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
1990 /** @page "Module Parameters"
1991  *
1992  * The following parameters may be specified when starting the module.
1993  * These parameters define how the DWC_otg controller should be
1994  * configured.  Parameter values are passed to the CIL initialization
1995  * function dwc_otg_cil_init
1996  *
1997  * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
1998  *
1999
2000  <table>
2001  <tr><td>Parameter Name</td><td>Meaning</td></tr>
2002
2003  <tr>
2004  <td>otg_cap</td>
2005  <td>Specifies the OTG capabilities. The driver will automatically detect the
2006  value for this parameter if none is specified.
2007  - 0: HNP and SRP capable (default, if available)
2008  - 1: SRP Only capable
2009  - 2: No HNP/SRP capable
2010  </td></tr>
2011
2012  <tr>
2013  <td>dma_enable</td>
2014  <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2015  The driver will automatically detect the value for this parameter if none is
2016  specified.
2017  - 0: Slave
2018  - 1: DMA (default, if available)
2019  </td></tr>
2020
2021  <tr>
2022  <td>dma_burst_size</td>
2023  <td>The DMA Burst size (applicable only for External DMA Mode).
2024  - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2025  </td></tr>
2026
2027  <tr>
2028  <td>speed</td>
2029  <td>Specifies the maximum speed of operation in host and device mode. The
2030  actual speed depends on the speed of the attached device and the value of
2031  phy_type.
2032  - 0: High Speed (default)
2033  - 1: Full Speed
2034  </td></tr>
2035
2036  <tr>
2037  <td>host_support_fs_ls_low_power</td>
2038  <td>Specifies whether low power mode is supported when attached to a Full
2039  Speed or Low Speed device in host mode.
2040  - 0: Don't support low power mode (default)
2041  - 1: Support low power mode
2042  </td></tr>
2043
2044  <tr>
2045  <td>host_ls_low_power_phy_clk</td>
2046  <td>Specifies the PHY clock rate in low power mode when connected to a Low
2047  Speed device in host mode. This parameter is applicable only if
2048  HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2049  - 0: 48 MHz (default)
2050  - 1: 6 MHz
2051  </td></tr>
2052
2053  <tr>
2054  <td>enable_dynamic_fifo</td>
2055  <td> Specifies whether FIFOs may be resized by the driver software.
2056  - 0: Use cC FIFO size parameters
2057  - 1: Allow dynamic FIFO sizing (default)
2058  </td></tr>
2059
2060  <tr>
2061  <td>data_fifo_size</td>
2062  <td>Total number of 4-byte words in the data FIFO memory. This memory
2063  includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2064  - Values: 32 to 32768 (default 8192)
2065
2066  Note: The total FIFO memory depth in the FPGA configuration is 8192.
2067  </td></tr>
2068
2069  <tr>
2070  <td>dev_rx_fifo_size</td>
2071  <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2072  FIFO sizing is enabled.
2073  - Values: 16 to 32768 (default 1064)
2074  </td></tr>
2075
2076  <tr>
2077  <td>dev_nperio_tx_fifo_size</td>
2078  <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2079  dynamic FIFO sizing is enabled.
2080  - Values: 16 to 32768 (default 1024)
2081  </td></tr>
2082
2083  <tr>
2084  <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2085  <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2086  when dynamic FIFO sizing is enabled.
2087  - Values: 4 to 768 (default 256)
2088  </td></tr>
2089
2090  <tr>
2091  <td>host_rx_fifo_size</td>
2092  <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2093  sizing is enabled.
2094  - Values: 16 to 32768 (default 1024)
2095  </td></tr>
2096
2097  <tr>
2098  <td>host_nperio_tx_fifo_size</td>
2099  <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2100  dynamic FIFO sizing is enabled in the core.
2101  - Values: 16 to 32768 (default 1024)
2102  </td></tr>
2103
2104  <tr>
2105  <td>host_perio_tx_fifo_size</td>
2106  <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2107  sizing is enabled.
2108  - Values: 16 to 32768 (default 1024)
2109  </td></tr>
2110
2111  <tr>
2112  <td>max_transfer_size</td>
2113  <td>The maximum transfer size supported in bytes.
2114  - Values: 2047 to 65,535 (default 65,535)
2115  </td></tr>
2116
2117  <tr>
2118  <td>max_packet_count</td>
2119  <td>The maximum number of packets in a transfer.
2120  - Values: 15 to 511 (default 511)
2121  </td></tr>
2122
2123  <tr>
2124  <td>host_channels</td>
2125  <td>The number of host channel registers to use.
2126  - Values: 1 to 16 (default 12)
2127
2128  Note: The FPGA configuration supports a maximum of 12 host channels.
2129  </td></tr>
2130
2131  <tr>
2132  <td>dev_endpoints</td>
2133  <td>The number of endpoints in addition to EP0 available for device mode
2134  operations.
2135  - Values: 1 to 15 (default 6 IN and OUT)
2136
2137  Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2138  addition to EP0.
2139  </td></tr>
2140
2141  <tr>
2142  <td>phy_type</td>
2143  <td>Specifies the type of PHY interface to use. By default, the driver will
2144  automatically detect the phy_type.
2145  - 0: Full Speed
2146  - 1: UTMI+ (default, if available)
2147  - 2: ULPI
2148  </td></tr>
2149
2150  <tr>
2151  <td>phy_utmi_width</td>
2152  <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2153  phy_type of UTMI+. Also, this parameter is applicable only if the
2154  OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2155  core has been configured to work at either data path width.
2156  - Values: 8 or 16 bits (default 16)
2157  </td></tr>
2158
2159  <tr>
2160  <td>phy_ulpi_ddr</td>
2161  <td>Specifies whether the ULPI operates at double or single data rate. This
2162  parameter is only applicable if phy_type is ULPI.
2163  - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2164  - 1: double data rate ULPI interface with 4 bit wide data bus
2165  </td></tr>
2166
2167  <tr>
2168  <td>i2c_enable</td>
2169  <td>Specifies whether to use the I2C interface for full speed PHY. This
2170  parameter is only applicable if PHY_TYPE is FS.
2171  - 0: Disabled (default)
2172  - 1: Enabled
2173  </td></tr>
2174
2175  <tr>
2176  <td>otg_en_multiple_tx_fifo</td>
2177  <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2178  The driver will automatically detect the value for this parameter if none is
2179  specified.
2180  - 0: Disabled
2181  - 1: Enabled (default, if available)
2182  </td></tr>
2183
2184  <tr>
2185  <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2186  <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2187  when dynamic FIFO sizing is enabled.
2188  - Values: 4 to 768 (default 256)
2189  </td></tr>
2190
2191 */