1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
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14 * redistribute this Software in source and binary forms, with or without
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19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
38 * This file contains the functions to manage Queue Heads and Queue
39 * Transfer Descriptors.
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/device.h>
46 #include <linux/errno.h>
47 #include <linux/list.h>
48 #include <linux/interrupt.h>
49 #include <linux/string.h>
50 #include <linux/irq.h>
52 #include "dwc_otg_driver.h"
53 #include "dwc_otg_hcd.h"
54 #include "dwc_otg_regs.h"
57 * This function allocates and initializes a QH.
59 * @param _hcd The HCD state structure for the DWC OTG controller.
60 * @param[in] _urb Holds the information about the device/endpoint that we need
61 * to initialize the QH.
63 * @return Returns pointer to the newly allocated QH, or NULL on error. */
64 dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb)
69 /** @todo add memflags argument */
70 qh = dwc_otg_hcd_qh_alloc ();
75 dwc_otg_hcd_qh_init (_hcd, qh, _urb);
79 /** Free each QTD in the QH's QTD-list then free the QH. QH should already be
80 * removed from a list. QTD list should already be empty if called from URB
83 * @param[in] _qh The QH to free.
85 void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh)
88 struct list_head *pos;
92 local_irq_save(flags);
94 /* Free each QTD in the QTD list */
95 for (pos = _qh->qtd_list.next;
96 pos != &_qh->qtd_list;
97 pos = _qh->qtd_list.next)
100 qtd = dwc_list_to_qtd (pos);
103 qtd->urb->hcpriv =NULL;
104 qtd->urb->ep->hcpriv = NULL;
106 dwc_otg_hcd_qtd_free (qtd);
112 local_irq_restore(flags);
116 /** Initializes a QH structure.
118 * @param[in] _hcd The HCD state structure for the DWC OTG controller.
119 * @param[in] _qh The QH to init.
120 * @param[in] _urb Holds the information about the device/endpoint that we need
121 * to initialize the QH. */
122 #define SCHEDULE_SLOP 10
123 void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb)
125 memset (_qh, 0, sizeof (dwc_otg_qh_t));
127 switch (usb_pipetype(_urb->pipe)) {
129 _qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
132 _qh->ep_type = USB_ENDPOINT_XFER_BULK;
134 case PIPE_ISOCHRONOUS:
135 _qh->ep_type = USB_ENDPOINT_XFER_ISOC;
138 _qh->ep_type = USB_ENDPOINT_XFER_INT;
142 _qh->ep_is_in = usb_pipein(_urb->pipe) ? 1 : 0;
144 _qh->data_toggle = DWC_OTG_HC_PID_DATA0;
145 _qh->maxp = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe)));
146 INIT_LIST_HEAD(&_qh->qtd_list);
147 INIT_LIST_HEAD(&_qh->qh_list_entry);
149 /* FS/LS Enpoint on HS Hub
150 * NOT virtual root hub */
153 if (((_urb->dev->speed == USB_SPEED_LOW) ||
154 (_urb->dev->speed == USB_SPEED_FULL)) &&
155 (_urb->dev->tt) && (_urb->dev->tt->hub)&&
156 (_urb->dev->tt->hub->devnum != 1))
158 DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
159 usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum,
164 if (_qh->ep_type == USB_ENDPOINT_XFER_INT ||
165 _qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
166 /* Compute scheduling parameters once and save them. */
169 /** @todo Account for split transfers in the bus time. */
170 int bytecount = dwc_hb_mult(_qh->maxp) * dwc_max_packet(_qh->maxp);
172 * The results from usb_calc_bus_time are in nanosecs,
173 * so divide the result by 1000 to convert to
174 * microsecs expected by this driver
176 _qh->usecs = usb_calc_bus_time(_urb->dev->speed,
177 usb_pipein(_urb->pipe),
178 (_qh->ep_type == USB_ENDPOINT_XFER_ISOC),
181 /* Start in a slightly future (micro)frame. */
182 _qh->sched_frame = dwc_frame_num_inc(_hcd->frame_number,
184 _qh->interval = _urb->interval;
186 /* Increase interrupt polling rate for debugging. */
187 if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
191 hprt.d32 = dwc_read_reg32(_hcd->core_if->host_if->hprt0);
192 if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
193 ((_urb->dev->speed == USB_SPEED_LOW) ||
194 (_urb->dev->speed == USB_SPEED_FULL)))
197 _qh->sched_frame |= 0x7;
198 _qh->start_split_frame = _qh->sched_frame;
203 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
204 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", _qh);
205 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
207 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
208 usb_pipeendpoint(_urb->pipe),
209 usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
210 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n",
211 ({ char *speed; switch (_urb->dev->speed) {
212 case USB_SPEED_LOW: speed = "low"; break;
213 case USB_SPEED_FULL: speed = "full"; break;
214 case USB_SPEED_HIGH: speed = "high"; break;
215 default: speed = "?"; break;
217 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",
218 ({ char *type; switch (_qh->ep_type) {
219 case USB_ENDPOINT_XFER_ISOC: type = "isochronous"; break;
220 case USB_ENDPOINT_XFER_INT: type = "interrupt"; break;
221 case USB_ENDPOINT_XFER_CONTROL: type = "control"; break;
222 case USB_ENDPOINT_XFER_BULK: type = "bulk"; break;
223 default: type = "?"; break;
226 if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
227 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
229 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
238 * Checks that a channel is available for a periodic transfer.
240 * @return 0 if successful, negative error code otherise.
242 static int periodic_channel_available(dwc_otg_hcd_t *_hcd)
245 * Currently assuming that there is a dedicated host channnel for each
246 * periodic transaction plus at least one host channel for
247 * non-periodic transactions.
250 #if defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK3188)
253 num_channels = _hcd->core_if->core_params->host_channels;
254 if ((_hcd->periodic_channels + _hcd->non_periodic_channels < num_channels) &&
255 (_hcd->periodic_channels < num_channels - 1)) {
259 DWC_NOTICE("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
260 __func__, num_channels, _hcd->periodic_channels,
261 _hcd->non_periodic_channels);
271 * Checks that there is sufficient bandwidth for the specified QH in the
272 * periodic schedule. For simplicity, this calculation assumes that all the
273 * transfers in the periodic schedule may occur in the same (micro)frame.
275 * @param _hcd The HCD state structure for the DWC OTG controller.
276 * @param _qh QH containing periodic bandwidth required.
278 * @return 0 if successful, negative error code otherwise.
280 static int check_periodic_bandwidth(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
283 uint16_t max_claimed_usecs;
287 if (_hcd->core_if->core_params->speed == DWC_SPEED_PARAM_HIGH) {
290 * Max periodic usecs is 80% x 125 usec = 100 usec.
292 max_claimed_usecs = 100 - _qh->usecs;
296 * Max periodic usecs is 90% x 1000 usec = 900 usec.
298 max_claimed_usecs = 900 - _qh->usecs;
301 if (_hcd->periodic_usecs > max_claimed_usecs) {
302 DWC_NOTICE("%s: already claimed usecs %d, required usecs %d\n",
303 __func__, _hcd->periodic_usecs, _qh->usecs);
311 * Checks that the max transfer size allowed in a host channel is large enough
312 * to handle the maximum data transfer in a single (micro)frame for a periodic
315 * @param _hcd The HCD state structure for the DWC OTG controller.
316 * @param _qh QH for a periodic endpoint.
318 * @return 0 if successful, negative error code otherwise.
320 static int check_max_xfer_size(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
323 uint32_t max_xfer_size;
324 uint32_t max_channel_xfer_size;
328 max_xfer_size = dwc_max_packet(_qh->maxp) * dwc_hb_mult(_qh->maxp);
329 max_channel_xfer_size = _hcd->core_if->core_params->max_transfer_size;
331 if (max_xfer_size > max_channel_xfer_size) {
332 DWC_NOTICE("%s: Periodic xfer length %d > "
333 "max xfer length for channel %d\n",
334 __func__, max_xfer_size, max_channel_xfer_size);
342 * Schedules an interrupt or isochronous transfer in the periodic schedule.
344 * @param _hcd The HCD state structure for the DWC OTG controller.
345 * @param _qh QH for the periodic transfer. The QH should already contain the
346 * scheduling information.
348 * @return 0 if successful, negative error code otherwise.
350 static int schedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
354 status = periodic_channel_available(_hcd);
356 DWC_NOTICE("%s: No host channel available for periodic "
357 "transfer.\n", __func__);
361 status = check_periodic_bandwidth(_hcd, _qh);
363 DWC_NOTICE("%s: Insufficient periodic bandwidth for "
364 "periodic transfer.\n", __func__);
368 status = check_max_xfer_size(_hcd, _qh);
370 DWC_NOTICE("%s: Channel max transfer size too small "
371 "for periodic transfer.\n", __func__);
375 /* Always start in the inactive schedule. */
376 list_add_tail(&_qh->qh_list_entry, &_hcd->periodic_sched_inactive);
377 _qh->qh_state = QH_INACTIVE;
379 /* Reserve the periodic channel. */
380 _hcd->periodic_channels++;
382 /* Update claimed usecs per (micro)frame. */
383 _hcd->periodic_usecs += _qh->usecs;
385 /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
386 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated += _qh->usecs / _qh->interval;
387 if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
388 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs++;
389 DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n",
390 _qh, _qh->usecs, _qh->interval);
392 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs++;
393 DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n",
394 _qh, _qh->usecs, _qh->interval);
401 * This function adds a QH to either the non periodic or periodic schedule if
402 * it is not already in the schedule. If the QH is already in the schedule, no
405 * @return 0 if successful, negative error code otherwise.
407 int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
412 local_irq_save(flags);
414 if (!list_empty(&_qh->qh_list_entry)) {
415 /* QH already in a schedule. */
419 /* Add the new QH to the appropriate schedule */
420 if (dwc_qh_is_non_per(_qh)) {
421 /* Always start in the inactive schedule. */
422 list_add_tail(&_qh->qh_list_entry, &_hcd->non_periodic_sched_inactive);
424 status = schedule_periodic(_hcd, _qh);
428 local_irq_restore(flags);
434 * Removes an interrupt or isochronous transfer from the periodic schedule.
436 * @param _hcd The HCD state structure for the DWC OTG controller.
437 * @param _qh QH for the periodic transfer.
439 static void deschedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
441 list_del_init(&_qh->qh_list_entry);
443 /* Release the periodic channel reservation. */
444 _hcd->periodic_channels--;
446 /* Update claimed usecs per (micro)frame. */
447 _hcd->periodic_usecs -= _qh->usecs;
449 /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
450 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated -= _qh->usecs / _qh->interval;
452 if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
453 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs--;
454 DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n",
455 _qh, _qh->usecs, _qh->interval);
457 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs--;
458 DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n",
459 _qh, _qh->usecs, _qh->interval);
464 * Removes a QH from either the non-periodic or periodic schedule. Memory is
467 * @param[in] _hcd The HCD state structure.
468 * @param[in] _qh QH to remove from schedule. */
469 void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
473 local_irq_save(flags);
475 if (list_empty(&_qh->qh_list_entry)) {
476 /* QH is not in a schedule. */
480 if (dwc_qh_is_non_per(_qh)) {
481 if (_hcd->non_periodic_qh_ptr == &_qh->qh_list_entry) {
482 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
484 list_del_init(&_qh->qh_list_entry);
486 deschedule_periodic(_hcd, _qh);
490 local_irq_restore(flags);
494 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
495 * non-periodic schedule. The QH is added to the inactive non-periodic
496 * schedule if any QTDs are still attached to the QH.
498 * For periodic QHs, the QH is removed from the periodic queued schedule. If
499 * there are any QTDs still attached to the QH, the QH is added to either the
500 * periodic inactive schedule or the periodic ready schedule and its next
501 * scheduled frame is calculated. The QH is placed in the ready schedule if
502 * the scheduled frame has been reached already. Otherwise it's placed in the
503 * inactive schedule. If there are no QTDs attached to the QH, the QH is
504 * completely removed from the periodic schedule.
506 void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_next_periodic_split)
509 local_irq_save(flags);
511 if (dwc_qh_is_non_per(_qh)) {
512 dwc_otg_hcd_qh_remove(_hcd, _qh);
513 if (!list_empty(&_qh->qtd_list)) {
514 /* Add back to inactive non-periodic schedule. */
515 dwc_otg_hcd_qh_add(_hcd, _qh);
519 uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd));
522 /* Schedule the next continuing periodic split transfer */
523 if (sched_next_periodic_split) {
525 _qh->sched_frame = frame_number;
526 if (dwc_frame_num_le(frame_number,
527 dwc_frame_num_inc(_qh->start_split_frame, 1))) {
529 * Allow one frame to elapse after start
530 * split microframe before scheduling
531 * complete split, but DONT if we are
532 * doing the next start split in the
533 * same frame for an ISOC out.
535 if ((_qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (_qh->ep_is_in != 0)) {
536 _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, 1);
540 _qh->sched_frame = dwc_frame_num_inc(_qh->start_split_frame,
542 if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
543 _qh->sched_frame = frame_number;
545 _qh->sched_frame |= 0x7;
546 _qh->start_split_frame = _qh->sched_frame;
549 _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, _qh->interval);
550 if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
551 _qh->sched_frame = frame_number;
555 if (list_empty(&_qh->qtd_list)) {
556 dwc_otg_hcd_qh_remove(_hcd, _qh);
559 * Remove from periodic_sched_queued and move to
562 if (_qh->sched_frame == frame_number) {
563 //list_move_tail(&_qh->qh_list_entry,
564 // &_hcd->periodic_sched_ready);
565 _qh->qh_state = QH_READY;
567 //list_move_tail(&_qh->qh_list_entry,
568 // &_hcd->periodic_sched_inactive);
569 _qh->qh_state = QH_INACTIVE;
574 local_irq_restore(flags);
578 * This function allocates and initializes a QTD.
580 * @param[in] _urb The URB to create a QTD from. Each URB-QTD pair will end up
581 * pointing to each other so each pair should have a unique correlation.
583 * @return Returns pointer to the newly allocated QTD, or NULL on error. */
584 dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *_urb)
588 qtd = dwc_otg_hcd_qtd_alloc ();
593 dwc_otg_hcd_qtd_init (qtd, _urb);
598 * Initializes a QTD structure.
600 * @param[in] _qtd The QTD to initialize.
601 * @param[in] _urb The URB to use for initialization. */
602 void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *_qtd, struct urb *_urb)
604 memset (_qtd, 0, sizeof (dwc_otg_qtd_t));
606 if (usb_pipecontrol(_urb->pipe)) {
608 * The only time the QTD data toggle is used is on the data
609 * phase of control transfers. This phase always starts with
612 _qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
613 _qtd->control_phase = DWC_OTG_CONTROL_SETUP;
617 _qtd->complete_split = 0;
618 _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
619 _qtd->isoc_split_offset = 0;
621 /* Store the qtd ptr in the urb to reference what QTD. */
627 * This function adds a QTD to the QTD-list of a QH. It will find the correct
628 * QH to place the QTD into. If it does not find a QH, then it will create a
629 * new QH. If the QH to which the QTD is added is not currently scheduled, it
630 * is placed into the proper schedule based on its EP type.
632 * @param[in] _qtd The QTD to add
633 * @param[in] _dwc_otg_hcd The DWC HCD structure
635 * @return 0 if successful, negative error code otherwise.
637 int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *_qtd,
638 dwc_otg_hcd_t *_dwc_otg_hcd)
640 struct usb_host_endpoint *ep;
645 struct urb *urb = _qtd->urb;
648 * Get the QH which holds the QTD-list to insert to. Create QH if it
651 ep = dwc_urb_to_endpoint(urb);
652 qh = (dwc_otg_qh_t *) ep->hcpriv;
654 qh = dwc_otg_hcd_qh_create (_dwc_otg_hcd, urb);
661 spin_lock_irqsave(&_dwc_otg_hcd->global_lock, flags);
662 retval = dwc_otg_hcd_qh_add(_dwc_otg_hcd, qh);
664 list_add_tail(&_qtd->qtd_list_entry, &qh->qtd_list);
667 spin_unlock_irqrestore(&_dwc_otg_hcd->global_lock, flags);
673 #endif /* DWC_DEVICE_ONLY */