1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
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18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
38 * This file contains the functions to manage Queue Heads and Queue
39 * Transfer Descriptors.
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/device.h>
46 #include <linux/errno.h>
47 #include <linux/list.h>
48 #include <linux/interrupt.h>
49 #include <linux/string.h>
50 #include <linux/irq.h>
52 #include "dwc_otg_driver.h"
53 #include "dwc_otg_hcd.h"
54 #include "dwc_otg_regs.h"
57 * This function allocates and initializes a QH.
59 * @param _hcd The HCD state structure for the DWC OTG controller.
60 * @param[in] _urb Holds the information about the device/endpoint that we need
61 * to initialize the QH.
63 * @return Returns pointer to the newly allocated QH, or NULL on error. */
64 dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb)
69 /** @todo add memflags argument */
70 qh = dwc_otg_hcd_qh_alloc ();
75 dwc_otg_hcd_qh_init (_hcd, qh, _urb);
79 /** Free each QTD in the QH's QTD-list then free the QH. QH should already be
80 * removed from a list. QTD list should already be empty if called from URB
83 * @param[in] _qh The QH to free.
85 void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh)
88 struct list_head *pos;
90 /* Free each QTD in the QTD list */
91 for (pos = _qh->qtd_list.next;
92 pos != &_qh->qtd_list;
93 pos = _qh->qtd_list.next)
96 qtd = dwc_list_to_qtd (pos);
97 dwc_otg_hcd_qtd_free (qtd);
104 /** Initializes a QH structure.
106 * @param[in] _hcd The HCD state structure for the DWC OTG controller.
107 * @param[in] _qh The QH to init.
108 * @param[in] _urb Holds the information about the device/endpoint that we need
109 * to initialize the QH. */
110 #define SCHEDULE_SLOP 10
111 void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb)
113 memset (_qh, 0, sizeof (dwc_otg_qh_t));
115 switch (usb_pipetype(_urb->pipe)) {
117 _qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
120 _qh->ep_type = USB_ENDPOINT_XFER_BULK;
122 case PIPE_ISOCHRONOUS:
123 _qh->ep_type = USB_ENDPOINT_XFER_ISOC;
126 _qh->ep_type = USB_ENDPOINT_XFER_INT;
130 _qh->ep_is_in = usb_pipein(_urb->pipe) ? 1 : 0;
132 _qh->data_toggle = DWC_OTG_HC_PID_DATA0;
133 _qh->maxp = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe)));
134 INIT_LIST_HEAD(&_qh->qtd_list);
135 INIT_LIST_HEAD(&_qh->qh_list_entry);
138 /* FS/LS Enpoint on HS Hub
139 * NOT virtual root hub */
143 * _urb->dev->tt->hub may be null
145 if((_urb->dev->tt)&&(!_urb->dev->tt->hub))
146 DWC_PRINT("%s tt->hub null!\n",__func__);
147 if (((_urb->dev->speed == USB_SPEED_LOW) ||
148 (_urb->dev->speed == USB_SPEED_FULL)) &&
149 (_urb->dev->tt) && (_urb->dev->tt->hub)&&
150 (_urb->dev->tt->hub->devnum != 1))
152 DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
153 usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum,
158 if (_qh->ep_type == USB_ENDPOINT_XFER_INT ||
159 _qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
160 /* Compute scheduling parameters once and save them. */
163 /** @todo Account for split transfers in the bus time. */
164 int bytecount = dwc_hb_mult(_qh->maxp) * dwc_max_packet(_qh->maxp);
166 * The results from usb_calc_bus_time are in nanosecs,
167 * so divide the result by 1000 to convert to
168 * microsecs expected by this driver
170 _qh->usecs = usb_calc_bus_time(_urb->dev->speed,
171 usb_pipein(_urb->pipe),
172 (_qh->ep_type == USB_ENDPOINT_XFER_ISOC),
175 /* Start in a slightly future (micro)frame. */
176 _qh->sched_frame = dwc_frame_num_inc(_hcd->frame_number,
178 _qh->interval = _urb->interval;
180 /* Increase interrupt polling rate for debugging. */
181 if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
185 hprt.d32 = dwc_read_reg32(_hcd->core_if->host_if->hprt0);
186 if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
187 ((_urb->dev->speed == USB_SPEED_LOW) ||
188 (_urb->dev->speed == USB_SPEED_FULL)))
191 _qh->sched_frame |= 0x7;
192 _qh->start_split_frame = _qh->sched_frame;
197 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
198 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", _qh);
199 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
201 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
202 usb_pipeendpoint(_urb->pipe),
203 usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
204 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n",
205 ({ char *speed; switch (_urb->dev->speed) {
206 case USB_SPEED_LOW: speed = "low"; break;
207 case USB_SPEED_FULL: speed = "full"; break;
208 case USB_SPEED_HIGH: speed = "high"; break;
209 default: speed = "?"; break;
211 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",
212 ({ char *type; switch (_qh->ep_type) {
213 case USB_ENDPOINT_XFER_ISOC: type = "isochronous"; break;
214 case USB_ENDPOINT_XFER_INT: type = "interrupt"; break;
215 case USB_ENDPOINT_XFER_CONTROL: type = "control"; break;
216 case USB_ENDPOINT_XFER_BULK: type = "bulk"; break;
217 default: type = "?"; break;
220 if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
221 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
223 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
232 * Checks that a channel is available for a periodic transfer.
234 * @return 0 if successful, negative error code otherise.
236 static int periodic_channel_available(dwc_otg_hcd_t *_hcd)
239 * Currently assuming that there is a dedicated host channnel for each
240 * periodic transaction plus at least one host channel for
241 * non-periodic transactions.
247 num_channels = _hcd->core_if->core_params->host_channels;
248 if ((_hcd->periodic_channels + _hcd->non_periodic_channels < num_channels) &&
249 (_hcd->periodic_channels < num_channels - 1)) {
253 DWC_NOTICE("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
254 __func__, num_channels, _hcd->periodic_channels,
255 _hcd->non_periodic_channels);
265 * Checks that there is sufficient bandwidth for the specified QH in the
266 * periodic schedule. For simplicity, this calculation assumes that all the
267 * transfers in the periodic schedule may occur in the same (micro)frame.
269 * @param _hcd The HCD state structure for the DWC OTG controller.
270 * @param _qh QH containing periodic bandwidth required.
272 * @return 0 if successful, negative error code otherwise.
274 static int check_periodic_bandwidth(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
277 uint16_t max_claimed_usecs;
281 if (_hcd->core_if->core_params->speed == DWC_SPEED_PARAM_HIGH) {
284 * Max periodic usecs is 80% x 125 usec = 100 usec.
286 max_claimed_usecs = 100 - _qh->usecs;
290 * Max periodic usecs is 90% x 1000 usec = 900 usec.
292 max_claimed_usecs = 900 - _qh->usecs;
295 if (_hcd->periodic_usecs > max_claimed_usecs) {
296 DWC_NOTICE("%s: already claimed usecs %d, required usecs %d\n",
297 __func__, _hcd->periodic_usecs, _qh->usecs);
305 * Checks that the max transfer size allowed in a host channel is large enough
306 * to handle the maximum data transfer in a single (micro)frame for a periodic
309 * @param _hcd The HCD state structure for the DWC OTG controller.
310 * @param _qh QH for a periodic endpoint.
312 * @return 0 if successful, negative error code otherwise.
314 static int check_max_xfer_size(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
317 uint32_t max_xfer_size;
318 uint32_t max_channel_xfer_size;
322 max_xfer_size = dwc_max_packet(_qh->maxp) * dwc_hb_mult(_qh->maxp);
323 max_channel_xfer_size = _hcd->core_if->core_params->max_transfer_size;
325 if (max_xfer_size > max_channel_xfer_size) {
326 DWC_NOTICE("%s: Periodic xfer length %d > "
327 "max xfer length for channel %d\n",
328 __func__, max_xfer_size, max_channel_xfer_size);
336 * Schedules an interrupt or isochronous transfer in the periodic schedule.
338 * @param _hcd The HCD state structure for the DWC OTG controller.
339 * @param _qh QH for the periodic transfer. The QH should already contain the
340 * scheduling information.
342 * @return 0 if successful, negative error code otherwise.
344 static int schedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
348 status = periodic_channel_available(_hcd);
350 DWC_NOTICE("%s: No host channel available for periodic "
351 "transfer.\n", __func__);
355 status = check_periodic_bandwidth(_hcd, _qh);
357 DWC_NOTICE("%s: Insufficient periodic bandwidth for "
358 "periodic transfer.\n", __func__);
362 status = check_max_xfer_size(_hcd, _qh);
364 DWC_NOTICE("%s: Channel max transfer size too small "
365 "for periodic transfer.\n", __func__);
369 /* Always start in the inactive schedule. */
370 list_add_tail(&_qh->qh_list_entry, &_hcd->periodic_sched_inactive);
372 /* Reserve the periodic channel. */
373 _hcd->periodic_channels++;
375 /* Update claimed usecs per (micro)frame. */
376 _hcd->periodic_usecs += _qh->usecs;
378 /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
379 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated += _qh->usecs / _qh->interval;
380 if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
381 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs++;
382 DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n",
383 _qh, _qh->usecs, _qh->interval);
385 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs++;
386 DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n",
387 _qh, _qh->usecs, _qh->interval);
394 * This function adds a QH to either the non periodic or periodic schedule if
395 * it is not already in the schedule. If the QH is already in the schedule, no
398 * @return 0 if successful, negative error code otherwise.
400 int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
404 if (!spin_is_locked(&_hcd->global_lock)) {
405 //pr_err("%s don't have hcd->global_lock\n", __func__);
409 if (!list_empty(&_qh->qh_list_entry)) {
410 /* QH already in a schedule. */
414 /* Add the new QH to the appropriate schedule */
415 if (dwc_qh_is_non_per(_qh)) {
416 /* Always start in the inactive schedule. */
417 list_add_tail(&_qh->qh_list_entry, &_hcd->non_periodic_sched_inactive);
419 status = schedule_periodic(_hcd, _qh);
423 //local_irq_restore(flags);
429 * Removes an interrupt or isochronous transfer from the periodic schedule.
431 * @param _hcd The HCD state structure for the DWC OTG controller.
432 * @param _qh QH for the periodic transfer.
434 static void deschedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
436 list_del_init(&_qh->qh_list_entry);
438 /* Release the periodic channel reservation. */
439 _hcd->periodic_channels--;
441 /* Update claimed usecs per (micro)frame. */
442 _hcd->periodic_usecs -= _qh->usecs;
444 /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
445 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated -= _qh->usecs / _qh->interval;
447 if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
448 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs--;
449 DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n",
450 _qh, _qh->usecs, _qh->interval);
452 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs--;
453 DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n",
454 _qh, _qh->usecs, _qh->interval);
459 * Removes a QH from either the non-periodic or periodic schedule. Memory is
462 * @param[in] _hcd The HCD state structure.
463 * @param[in] _qh QH to remove from schedule. */
464 void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
466 if (!spin_is_locked(&_hcd->global_lock)) {
467 //pr_err("%s don't have hcd->global_lock\n", __func__);
471 if (list_empty(&_qh->qh_list_entry)) {
472 /* QH is not in a schedule. */
476 if (dwc_qh_is_non_per(_qh)) {
477 if (_hcd->non_periodic_qh_ptr == &_qh->qh_list_entry) {
478 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
480 list_del_init(&_qh->qh_list_entry);
482 deschedule_periodic(_hcd, _qh);
490 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
491 * non-periodic schedule. The QH is added to the inactive non-periodic
492 * schedule if any QTDs are still attached to the QH.
494 * For periodic QHs, the QH is removed from the periodic queued schedule. If
495 * there are any QTDs still attached to the QH, the QH is added to either the
496 * periodic inactive schedule or the periodic ready schedule and its next
497 * scheduled frame is calculated. The QH is placed in the ready schedule if
498 * the scheduled frame has been reached already. Otherwise it's placed in the
499 * inactive schedule. If there are no QTDs attached to the QH, the QH is
500 * completely removed from the periodic schedule.
502 void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_next_periodic_split)
504 if (!spin_is_locked(&_hcd->global_lock)) {
505 //pr_err("%s don't have hcd->global_lock\n", __func__);
508 if (dwc_qh_is_non_per(_qh)) {
509 dwc_otg_hcd_qh_remove(_hcd, _qh);
510 if (!list_empty(&_qh->qtd_list)) {
511 /* Add back to inactive non-periodic schedule. */
512 dwc_otg_hcd_qh_add(_hcd, _qh);
516 uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd));
519 /* Schedule the next continuing periodic split transfer */
520 if (sched_next_periodic_split) {
522 _qh->sched_frame = frame_number;
523 if (dwc_frame_num_le(frame_number,
524 dwc_frame_num_inc(_qh->start_split_frame, 1))) {
526 * Allow one frame to elapse after start
527 * split microframe before scheduling
528 * complete split, but DONT if we are
529 * doing the next start split in the
530 * same frame for an ISOC out.
532 if ((_qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (_qh->ep_is_in != 0)) {
533 _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, 1);
537 _qh->sched_frame = dwc_frame_num_inc(_qh->start_split_frame,
539 if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
540 _qh->sched_frame = frame_number;
542 _qh->sched_frame |= 0x7;
543 _qh->start_split_frame = _qh->sched_frame;
546 _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, _qh->interval);
547 if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
548 _qh->sched_frame = frame_number;
552 if (list_empty(&_qh->qtd_list)) {
553 dwc_otg_hcd_qh_remove(_hcd, _qh);
556 * Remove from periodic_sched_queued and move to
559 if (_qh->sched_frame == frame_number) {
560 list_move(&_qh->qh_list_entry,
561 &_hcd->periodic_sched_ready);
563 list_move(&_qh->qh_list_entry,
564 &_hcd->periodic_sched_inactive);
573 * This function allocates and initializes a QTD.
575 * @param[in] _urb The URB to create a QTD from. Each URB-QTD pair will end up
576 * pointing to each other so each pair should have a unique correlation.
578 * @return Returns pointer to the newly allocated QTD, or NULL on error. */
579 dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *_urb)
583 qtd = dwc_otg_hcd_qtd_alloc ();
588 dwc_otg_hcd_qtd_init (qtd, _urb);
593 * Initializes a QTD structure.
595 * @param[in] _qtd The QTD to initialize.
596 * @param[in] _urb The URB to use for initialization. */
597 void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *_qtd, struct urb *_urb)
599 memset (_qtd, 0, sizeof (dwc_otg_qtd_t));
601 if (usb_pipecontrol(_urb->pipe)) {
603 * The only time the QTD data toggle is used is on the data
604 * phase of control transfers. This phase always starts with
607 _qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
608 _qtd->control_phase = DWC_OTG_CONTROL_SETUP;
612 _qtd->complete_split = 0;
613 _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
614 _qtd->isoc_split_offset = 0;
616 /* Store the qtd ptr in the urb to reference what QTD. */
622 * This function adds a QTD to the QTD-list of a QH. It will find the correct
623 * QH to place the QTD into. If it does not find a QH, then it will create a
624 * new QH. If the QH to which the QTD is added is not currently scheduled, it
625 * is placed into the proper schedule based on its EP type.
627 * @param[in] _qtd The QTD to add
628 * @param[in] _dwc_otg_hcd The DWC HCD structure
630 * @return 0 if successful, negative error code otherwise.
632 int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *_qtd,
633 dwc_otg_hcd_t *_dwc_otg_hcd)
635 struct usb_host_endpoint *ep;
637 //unsigned long flags;
640 struct urb *urb = _qtd->urb;
642 //local_irq_save(flags);
645 * Get the QH which holds the QTD-list to insert to. Create QH if it
648 ep = dwc_urb_to_endpoint(urb);
649 qh = (dwc_otg_qh_t *) ep->hcpriv;
651 qh = dwc_otg_hcd_qh_create (_dwc_otg_hcd, urb);
659 retval = dwc_otg_hcd_qh_add(_dwc_otg_hcd, qh);
661 list_add_tail(&_qtd->qtd_list_entry, &qh->qtd_list);
665 //local_irq_restore(flags);
669 #endif /* DWC_DEVICE_ONLY */