1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
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19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
38 * This file contains the functions to manage Queue Heads and Queue
39 * Transfer Descriptors.
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/device.h>
46 #include <linux/errno.h>
47 #include <linux/list.h>
48 #include <linux/interrupt.h>
49 #include <linux/string.h>
50 #include <linux/irq.h>
52 #include "dwc_otg_driver.h"
53 #include "dwc_otg_hcd.h"
54 #include "dwc_otg_regs.h"
57 * This function allocates and initializes a QH.
59 * @param _hcd The HCD state structure for the DWC OTG controller.
60 * @param[in] _urb Holds the information about the device/endpoint that we need
61 * to initialize the QH.
63 * @return Returns pointer to the newly allocated QH, or NULL on error. */
64 dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb)
69 /** @todo add memflags argument */
70 qh = dwc_otg_hcd_qh_alloc ();
75 dwc_otg_hcd_qh_init (_hcd, qh, _urb);
79 /** Free each QTD in the QH's QTD-list then free the QH. QH should already be
80 * removed from a list. QTD list should already be empty if called from URB
83 * @param[in] _qh The QH to free.
85 void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh)
88 struct list_head *pos;
92 local_irq_save(flags);
94 /* Free each QTD in the QTD list */
95 for (pos = _qh->qtd_list.next;
96 pos != &_qh->qtd_list;
97 pos = _qh->qtd_list.next)
100 qtd = dwc_list_to_qtd (pos);
103 qtd->urb->hcpriv =NULL;
104 qtd->urb->ep->hcpriv = NULL;
106 dwc_otg_hcd_qtd_free (qtd);
112 local_irq_restore(flags);
116 /** Initializes a QH structure.
118 * @param[in] _hcd The HCD state structure for the DWC OTG controller.
119 * @param[in] _qh The QH to init.
120 * @param[in] _urb Holds the information about the device/endpoint that we need
121 * to initialize the QH. */
122 #define SCHEDULE_SLOP 10
123 void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb)
125 memset (_qh, 0, sizeof (dwc_otg_qh_t));
127 switch (usb_pipetype(_urb->pipe)) {
129 _qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
132 _qh->ep_type = USB_ENDPOINT_XFER_BULK;
134 case PIPE_ISOCHRONOUS:
135 _qh->ep_type = USB_ENDPOINT_XFER_ISOC;
138 _qh->ep_type = USB_ENDPOINT_XFER_INT;
142 _qh->ep_is_in = usb_pipein(_urb->pipe) ? 1 : 0;
144 _qh->data_toggle = DWC_OTG_HC_PID_DATA0;
145 _qh->maxp = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe)));
146 INIT_LIST_HEAD(&_qh->qtd_list);
147 INIT_LIST_HEAD(&_qh->qh_list_entry);
150 /* FS/LS Enpoint on HS Hub
151 * NOT virtual root hub */
155 * _urb->dev->tt->hub may be null
157 if((_urb->dev->tt)&&(!_urb->dev->tt->hub))
158 DWC_PRINT("%s tt->hub null!\n",__func__);
159 if (((_urb->dev->speed == USB_SPEED_LOW) ||
160 (_urb->dev->speed == USB_SPEED_FULL)) &&
161 (_urb->dev->tt) && (_urb->dev->tt->hub)&&
162 (_urb->dev->tt->hub->devnum != 1))
164 DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
165 usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum,
170 if (_qh->ep_type == USB_ENDPOINT_XFER_INT ||
171 _qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
172 /* Compute scheduling parameters once and save them. */
175 /** @todo Account for split transfers in the bus time. */
176 int bytecount = dwc_hb_mult(_qh->maxp) * dwc_max_packet(_qh->maxp);
178 * The results from usb_calc_bus_time are in nanosecs,
179 * so divide the result by 1000 to convert to
180 * microsecs expected by this driver
182 _qh->usecs = usb_calc_bus_time(_urb->dev->speed,
183 usb_pipein(_urb->pipe),
184 (_qh->ep_type == USB_ENDPOINT_XFER_ISOC),
187 /* Start in a slightly future (micro)frame. */
188 _qh->sched_frame = dwc_frame_num_inc(_hcd->frame_number,
190 _qh->interval = _urb->interval;
192 /* Increase interrupt polling rate for debugging. */
193 if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
197 hprt.d32 = dwc_read_reg32(_hcd->core_if->host_if->hprt0);
198 if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
199 ((_urb->dev->speed == USB_SPEED_LOW) ||
200 (_urb->dev->speed == USB_SPEED_FULL)))
203 _qh->sched_frame |= 0x7;
204 _qh->start_split_frame = _qh->sched_frame;
209 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
210 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", _qh);
211 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
213 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
214 usb_pipeendpoint(_urb->pipe),
215 usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
216 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n",
217 ({ char *speed; switch (_urb->dev->speed) {
218 case USB_SPEED_LOW: speed = "low"; break;
219 case USB_SPEED_FULL: speed = "full"; break;
220 case USB_SPEED_HIGH: speed = "high"; break;
221 default: speed = "?"; break;
223 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",
224 ({ char *type; switch (_qh->ep_type) {
225 case USB_ENDPOINT_XFER_ISOC: type = "isochronous"; break;
226 case USB_ENDPOINT_XFER_INT: type = "interrupt"; break;
227 case USB_ENDPOINT_XFER_CONTROL: type = "control"; break;
228 case USB_ENDPOINT_XFER_BULK: type = "bulk"; break;
229 default: type = "?"; break;
232 if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
233 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
235 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
244 * Checks that a channel is available for a periodic transfer.
246 * @return 0 if successful, negative error code otherise.
248 static int periodic_channel_available(dwc_otg_hcd_t *_hcd)
251 * Currently assuming that there is a dedicated host channnel for each
252 * periodic transaction plus at least one host channel for
253 * non-periodic transactions.
259 num_channels = _hcd->core_if->core_params->host_channels;
260 if ((_hcd->periodic_channels + _hcd->non_periodic_channels < num_channels) &&
261 (_hcd->periodic_channels < num_channels - 1)) {
265 DWC_NOTICE("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
266 __func__, num_channels, _hcd->periodic_channels,
267 _hcd->non_periodic_channels);
277 * Checks that there is sufficient bandwidth for the specified QH in the
278 * periodic schedule. For simplicity, this calculation assumes that all the
279 * transfers in the periodic schedule may occur in the same (micro)frame.
281 * @param _hcd The HCD state structure for the DWC OTG controller.
282 * @param _qh QH containing periodic bandwidth required.
284 * @return 0 if successful, negative error code otherwise.
286 static int check_periodic_bandwidth(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
289 uint16_t max_claimed_usecs;
293 if (_hcd->core_if->core_params->speed == DWC_SPEED_PARAM_HIGH) {
296 * Max periodic usecs is 80% x 125 usec = 100 usec.
298 max_claimed_usecs = 100 - _qh->usecs;
302 * Max periodic usecs is 90% x 1000 usec = 900 usec.
304 max_claimed_usecs = 900 - _qh->usecs;
307 if (_hcd->periodic_usecs > max_claimed_usecs) {
308 DWC_NOTICE("%s: already claimed usecs %d, required usecs %d\n",
309 __func__, _hcd->periodic_usecs, _qh->usecs);
317 * Checks that the max transfer size allowed in a host channel is large enough
318 * to handle the maximum data transfer in a single (micro)frame for a periodic
321 * @param _hcd The HCD state structure for the DWC OTG controller.
322 * @param _qh QH for a periodic endpoint.
324 * @return 0 if successful, negative error code otherwise.
326 static int check_max_xfer_size(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
329 uint32_t max_xfer_size;
330 uint32_t max_channel_xfer_size;
334 max_xfer_size = dwc_max_packet(_qh->maxp) * dwc_hb_mult(_qh->maxp);
335 max_channel_xfer_size = _hcd->core_if->core_params->max_transfer_size;
337 if (max_xfer_size > max_channel_xfer_size) {
338 DWC_NOTICE("%s: Periodic xfer length %d > "
339 "max xfer length for channel %d\n",
340 __func__, max_xfer_size, max_channel_xfer_size);
348 * Schedules an interrupt or isochronous transfer in the periodic schedule.
350 * @param _hcd The HCD state structure for the DWC OTG controller.
351 * @param _qh QH for the periodic transfer. The QH should already contain the
352 * scheduling information.
354 * @return 0 if successful, negative error code otherwise.
356 static int schedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
360 status = periodic_channel_available(_hcd);
362 DWC_NOTICE("%s: No host channel available for periodic "
363 "transfer.\n", __func__);
367 status = check_periodic_bandwidth(_hcd, _qh);
369 DWC_NOTICE("%s: Insufficient periodic bandwidth for "
370 "periodic transfer.\n", __func__);
374 status = check_max_xfer_size(_hcd, _qh);
376 DWC_NOTICE("%s: Channel max transfer size too small "
377 "for periodic transfer.\n", __func__);
381 /* Always start in the inactive schedule. */
382 list_add_tail(&_qh->qh_list_entry, &_hcd->periodic_sched_inactive);
384 /* Reserve the periodic channel. */
385 _hcd->periodic_channels++;
387 /* Update claimed usecs per (micro)frame. */
388 _hcd->periodic_usecs += _qh->usecs;
390 /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
391 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated += _qh->usecs / _qh->interval;
392 if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
393 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs++;
394 DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n",
395 _qh, _qh->usecs, _qh->interval);
397 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs++;
398 DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n",
399 _qh, _qh->usecs, _qh->interval);
406 * This function adds a QH to either the non periodic or periodic schedule if
407 * it is not already in the schedule. If the QH is already in the schedule, no
410 * @return 0 if successful, negative error code otherwise.
412 int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
416 if (!spin_is_locked(&_hcd->global_lock)) {
417 //pr_err("%s don't have hcd->global_lock\n", __func__);
421 if (!list_empty(&_qh->qh_list_entry)) {
422 /* QH already in a schedule. */
426 /* Add the new QH to the appropriate schedule */
427 if (dwc_qh_is_non_per(_qh)) {
428 /* Always start in the inactive schedule. */
429 list_add_tail(&_qh->qh_list_entry, &_hcd->non_periodic_sched_inactive);
431 status = schedule_periodic(_hcd, _qh);
435 //local_irq_restore(flags);
441 * Removes an interrupt or isochronous transfer from the periodic schedule.
443 * @param _hcd The HCD state structure for the DWC OTG controller.
444 * @param _qh QH for the periodic transfer.
446 static void deschedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
448 list_del_init(&_qh->qh_list_entry);
450 /* Release the periodic channel reservation. */
451 _hcd->periodic_channels--;
453 /* Update claimed usecs per (micro)frame. */
454 _hcd->periodic_usecs -= _qh->usecs;
456 /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
457 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated -= _qh->usecs / _qh->interval;
459 if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
460 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs--;
461 DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n",
462 _qh, _qh->usecs, _qh->interval);
464 hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs--;
465 DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n",
466 _qh, _qh->usecs, _qh->interval);
471 * Removes a QH from either the non-periodic or periodic schedule. Memory is
474 * @param[in] _hcd The HCD state structure.
475 * @param[in] _qh QH to remove from schedule. */
476 void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
478 if (!spin_is_locked(&_hcd->global_lock)) {
479 //pr_err("%s don't have hcd->global_lock\n", __func__);
483 if (list_empty(&_qh->qh_list_entry)) {
484 /* QH is not in a schedule. */
488 if (dwc_qh_is_non_per(_qh)) {
489 if (_hcd->non_periodic_qh_ptr == &_qh->qh_list_entry) {
490 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
492 list_del_init(&_qh->qh_list_entry);
494 deschedule_periodic(_hcd, _qh);
502 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
503 * non-periodic schedule. The QH is added to the inactive non-periodic
504 * schedule if any QTDs are still attached to the QH.
506 * For periodic QHs, the QH is removed from the periodic queued schedule. If
507 * there are any QTDs still attached to the QH, the QH is added to either the
508 * periodic inactive schedule or the periodic ready schedule and its next
509 * scheduled frame is calculated. The QH is placed in the ready schedule if
510 * the scheduled frame has been reached already. Otherwise it's placed in the
511 * inactive schedule. If there are no QTDs attached to the QH, the QH is
512 * completely removed from the periodic schedule.
514 void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_next_periodic_split)
516 if (!spin_is_locked(&_hcd->global_lock)) {
517 //pr_err("%s don't have hcd->global_lock\n", __func__);
520 if (dwc_qh_is_non_per(_qh)) {
521 dwc_otg_hcd_qh_remove(_hcd, _qh);
522 if (!list_empty(&_qh->qtd_list)) {
523 /* Add back to inactive non-periodic schedule. */
524 dwc_otg_hcd_qh_add(_hcd, _qh);
528 uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd));
531 /* Schedule the next continuing periodic split transfer */
532 if (sched_next_periodic_split) {
534 _qh->sched_frame = frame_number;
535 if (dwc_frame_num_le(frame_number,
536 dwc_frame_num_inc(_qh->start_split_frame, 1))) {
538 * Allow one frame to elapse after start
539 * split microframe before scheduling
540 * complete split, but DONT if we are
541 * doing the next start split in the
542 * same frame for an ISOC out.
544 if ((_qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (_qh->ep_is_in != 0)) {
545 _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, 1);
549 _qh->sched_frame = dwc_frame_num_inc(_qh->start_split_frame,
551 if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
552 _qh->sched_frame = frame_number;
554 _qh->sched_frame |= 0x7;
555 _qh->start_split_frame = _qh->sched_frame;
558 _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, _qh->interval);
559 if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
560 _qh->sched_frame = frame_number;
564 if (list_empty(&_qh->qtd_list)) {
565 dwc_otg_hcd_qh_remove(_hcd, _qh);
568 * Remove from periodic_sched_queued and move to
571 if (_qh->sched_frame == frame_number) {
572 list_move_tail(&_qh->qh_list_entry,
573 &_hcd->periodic_sched_ready);
575 list_move_tail(&_qh->qh_list_entry,
576 &_hcd->periodic_sched_inactive);
585 * This function allocates and initializes a QTD.
587 * @param[in] _urb The URB to create a QTD from. Each URB-QTD pair will end up
588 * pointing to each other so each pair should have a unique correlation.
590 * @return Returns pointer to the newly allocated QTD, or NULL on error. */
591 dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *_urb)
595 qtd = dwc_otg_hcd_qtd_alloc ();
600 dwc_otg_hcd_qtd_init (qtd, _urb);
605 * Initializes a QTD structure.
607 * @param[in] _qtd The QTD to initialize.
608 * @param[in] _urb The URB to use for initialization. */
609 void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *_qtd, struct urb *_urb)
611 memset (_qtd, 0, sizeof (dwc_otg_qtd_t));
613 if (usb_pipecontrol(_urb->pipe)) {
615 * The only time the QTD data toggle is used is on the data
616 * phase of control transfers. This phase always starts with
619 _qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
620 _qtd->control_phase = DWC_OTG_CONTROL_SETUP;
624 _qtd->complete_split = 0;
625 _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
626 _qtd->isoc_split_offset = 0;
628 /* Store the qtd ptr in the urb to reference what QTD. */
634 * This function adds a QTD to the QTD-list of a QH. It will find the correct
635 * QH to place the QTD into. If it does not find a QH, then it will create a
636 * new QH. If the QH to which the QTD is added is not currently scheduled, it
637 * is placed into the proper schedule based on its EP type.
639 * @param[in] _qtd The QTD to add
640 * @param[in] _dwc_otg_hcd The DWC HCD structure
642 * @return 0 if successful, negative error code otherwise.
644 int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *_qtd,
645 dwc_otg_hcd_t *_dwc_otg_hcd)
647 struct usb_host_endpoint *ep;
649 //unsigned long flags;
652 struct urb *urb = _qtd->urb;
654 //local_irq_save(flags);
657 * Get the QH which holds the QTD-list to insert to. Create QH if it
660 ep = dwc_urb_to_endpoint(urb);
661 qh = (dwc_otg_qh_t *) ep->hcpriv;
663 qh = dwc_otg_hcd_qh_create (_dwc_otg_hcd, urb);
671 retval = dwc_otg_hcd_qh_add(_dwc_otg_hcd, qh);
673 list_add_tail(&_qtd->qtd_list_entry, &qh->qtd_list);
677 //local_irq_restore(flags);
681 #endif /* DWC_DEVICE_ONLY */