1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
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32 * ========================================================================== */
34 #if !defined(__DWC_CIL_H__)
37 #include "common_port/dwc_list.h"
38 #include "dwc_otg_dbg.h"
39 #include "dwc_otg_regs.h"
41 #include "dwc_otg_core_if.h"
42 #include "dwc_otg_adp.h"
46 * This file contains the interface to the Core Interface Layer.
51 #define MAX_DMA_DESCS_PER_EP 256
54 * Enumeration for the data buffer mode
56 typedef enum _data_buffer_mode {
57 BM_STANDARD = 0, /* data buffer is in normal mode */
58 BM_SG = 1, /* data buffer uses the scatter/gather mode */
59 BM_CONCAT = 2, /* data buffer uses the concatenation mode */
60 BM_CIRCULAR = 3, /* data buffer uses the circular DMA mode */
61 BM_ALIGN = 4 /* data buffer is in buffer alignment mode */
63 #endif /* DWC_UTE_CFI */
65 /** Macros defined for DWC OTG HW Release version */
67 #define OTG_CORE_REV_2_60a 0x4F54260A
68 #define OTG_CORE_REV_2_71a 0x4F54271A
69 #define OTG_CORE_REV_2_72a 0x4F54272A
70 #define OTG_CORE_REV_2_80a 0x4F54280A
71 #define OTG_CORE_REV_2_81a 0x4F54281A
72 #define OTG_CORE_REV_2_90a 0x4F54290A
73 #define OTG_CORE_REV_2_91a 0x4F54291A
74 #define OTG_CORE_REV_2_92a 0x4F54292A
75 #define OTG_CORE_REV_2_93a 0x4F54293A
76 #define OTG_CORE_REV_2_94a 0x4F54294A
77 #define OTG_CORE_REV_3_00a 0x4F54300A
78 #define OTG_CORE_REV_3_10a 0x4F54310A
81 * Information for each ISOC packet.
83 typedef struct iso_pkt_info {
90 * The <code>dwc_ep</code> structure represents the state of a single
91 * endpoint when acting in device mode. It contains the data items
92 * needed for an endpoint to be activated and transfer packets.
94 typedef struct dwc_ep {
95 /** EP number used for register address lookup */
97 /** EP direction 0 = OUT */
103 * Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic
104 * Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/
105 unsigned tx_fifo_num:4;
106 /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
108 #define DWC_OTG_EP_TYPE_CONTROL 0
109 #define DWC_OTG_EP_TYPE_ISOC 1
110 #define DWC_OTG_EP_TYPE_BULK 2
111 #define DWC_OTG_EP_TYPE_INTR 3
113 /** DATA start PID for INTR and BULK EP */
114 unsigned data_pid_start:1;
115 /** Frame (even/odd) for ISOC EP */
116 unsigned even_odd_frame:1;
117 /** Max Packet bytes */
118 unsigned maxpacket:11;
120 /** Max Transfer size */
123 /** @name Transfer state */
127 * Pointer to the beginning of the transfer buffer -- do not modify
133 dwc_dma_t dma_desc_addr;
134 dwc_otg_dev_dma_desc_t *desc_addr;
136 uint8_t *start_xfer_buff;
137 /** pointer to the transfer buffer */
139 /** Number of bytes to transfer */
140 unsigned xfer_len:19;
141 /** Number of bytes transferred. */
142 unsigned xfer_count:19;
145 /** Total len for control transfer */
146 unsigned total_len:19;
148 /** stall clear flag */
149 unsigned stall_clear_flag:1;
151 /** SETUP pkt cnt rollover flag for EP0 out*/
152 unsigned stp_rollover;
155 /* The buffer mode */
156 data_buffer_mode_e buff_mode;
158 /* The chain of DMA descriptors.
159 * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.
161 dwc_otg_dma_desc_t *descs;
163 /* The DMA address of the descriptors chain start */
164 dma_addr_t descs_dma_addr;
165 /** This variable stores the length of the last enqueued request */
166 uint32_t cfi_req_len;
167 #endif/* DWC_UTE_CFI */
169 /** Max DMA Descriptor count for any EP */
170 #define MAX_DMA_DESC_CNT 256
171 /** Allocated DMA Desc count */
176 /** Next frame num to setup next ISOC transfer */
178 /** Indicates SOF number overrun in DSTS */
181 #ifdef DWC_UTE_PER_IO
182 /** Next frame num for which will be setup DMA Desc */
183 uint32_t xiso_frame_num;
185 uint32_t xiso_bInterval;
186 /** Count of currently active transfers - shall be either 0 or 1 */
187 int xiso_active_xfers;
188 int xiso_queued_xfers;
192 * Variables specific for ISOC EPs
195 /** DMA addresses of ISOC buffers */
199 dwc_dma_t iso_dma_desc_addr;
200 dwc_otg_dev_dma_desc_t *iso_desc_addr;
202 /** pointer to the transfer buffers */
206 /** number of ISOC Buffer is processing */
207 uint32_t proc_buf_num;
208 /** Interval of ISOC Buffer processing */
209 uint32_t buf_proc_intrvl;
210 /** Data size for regular frame */
211 uint32_t data_per_frame;
213 /* todo - pattern data support is to be implemented in the future */
214 /** Data size for pattern frame */
215 uint32_t data_pattern_frame;
216 /** Frame number of pattern data */
221 /** ISO Packet number per frame */
222 uint32_t pkt_per_frm;
223 /** Next frame num for which will be setup DMA Desc */
225 /** Number of packets per buffer processing */
227 /** Info for all isoc packets */
228 iso_pkt_info_t *pkt_info;
229 /** current pkt number */
231 /** current pkt number */
232 uint8_t *cur_pkt_addr;
233 /** current pkt number */
234 uint32_t cur_pkt_dma_addr;
235 #endif /* DWC_EN_ISOC */
241 * Reasons for halting a host channel.
243 typedef enum dwc_otg_halt_status {
244 DWC_OTG_HC_XFER_NO_HALT_STATUS,
245 DWC_OTG_HC_XFER_COMPLETE,
246 DWC_OTG_HC_XFER_URB_COMPLETE,
249 DWC_OTG_HC_XFER_NYET,
250 DWC_OTG_HC_XFER_STALL,
251 DWC_OTG_HC_XFER_XACT_ERR,
252 DWC_OTG_HC_XFER_FRAME_OVERRUN,
253 DWC_OTG_HC_XFER_BABBLE_ERR,
254 DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
255 DWC_OTG_HC_XFER_AHB_ERR,
256 DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
257 DWC_OTG_HC_XFER_URB_DEQUEUE
258 } dwc_otg_halt_status_e;
261 * Host channel descriptor. This structure represents the state of a single
262 * host channel when acting in host mode. It contains the data items needed to
263 * transfer packets to an endpoint via a host channel.
265 typedef struct dwc_hc {
266 /** Host channel number used for register address lookup */
269 /** Device to access */
275 /** EP direction. 0: OUT, 1: IN */
280 * One of the following values:
281 * - DWC_OTG_EP_SPEED_LOW
282 * - DWC_OTG_EP_SPEED_FULL
283 * - DWC_OTG_EP_SPEED_HIGH
286 #define DWC_OTG_EP_SPEED_LOW 0
287 #define DWC_OTG_EP_SPEED_FULL 1
288 #define DWC_OTG_EP_SPEED_HIGH 2
292 * One of the following values:
293 * - DWC_OTG_EP_TYPE_CONTROL: 0
294 * - DWC_OTG_EP_TYPE_ISOC: 1
295 * - DWC_OTG_EP_TYPE_BULK: 2
296 * - DWC_OTG_EP_TYPE_INTR: 3
300 /** Max packet size in bytes */
301 unsigned max_packet:11;
304 * PID for initial transaction.
308 * 3: MDATA (non-Control EP),
311 unsigned data_pid_start:2;
312 #define DWC_OTG_HC_PID_DATA0 0
313 #define DWC_OTG_HC_PID_DATA2 1
314 #define DWC_OTG_HC_PID_DATA1 2
315 #define DWC_OTG_HC_PID_MDATA 3
316 #define DWC_OTG_HC_PID_SETUP 3
318 /** Number of periodic transactions per (micro)frame */
319 unsigned multi_count:2;
321 /** @name Transfer State */
324 /** Pointer to the current transfer buffer position. */
327 * In Buffer DMA mode this buffer will be used
328 * if xfer_buff is not DWORD aligned.
330 dwc_dma_t align_buff;
331 /** Total number of bytes to transfer. */
333 /** Number of bytes transferred so far. */
335 /** Packet count at start of transfer.*/
336 uint16_t start_pkt_count;
339 * Flag to indicate whether the transfer has been started. Set to 1 if
340 * it has been started, 0 otherwise.
342 uint8_t xfer_started;
345 * Set to 1 to indicate that a PING request should be issued on this
346 * channel. If 0, process normally.
351 * Set to 1 to indicate that the error count for this transaction is
352 * non-zero. Set to 0 if the error count is 0.
357 * Set to 1 to indicate that this channel should be halted the next
358 * time a request is queued for the channel. This is necessary in
359 * slave mode if no request queue space is available when an attempt
360 * is made to halt the channel.
362 uint8_t halt_on_queue;
365 * Set to 1 if the host channel has been halted, but the core is not
366 * finished flushing queued requests. Otherwise 0.
368 uint8_t halt_pending;
371 * Reason for halting the host channel.
373 dwc_otg_halt_status_e halt_status;
376 * Split settings for the host channel
378 uint8_t do_split; /**< Enable split for the channel */
379 uint8_t complete_split; /**< Enable complete split */
381 uint8_t hub_addr; /**< Address of high speed hub */
383 uint8_t port_addr; /**< Port of the low/full speed device */
384 /** Split transaction position
385 * One of the following values:
386 * - DWC_HCSPLIT_XACTPOS_MID
387 * - DWC_HCSPLIT_XACTPOS_BEGIN
388 * - DWC_HCSPLIT_XACTPOS_END
389 * - DWC_HCSPLIT_XACTPOS_ALL */
392 /** Set when the host channel does a short read. */
396 * Number of requests issued for this channel since it was assigned to
397 * the current transfer (not counting PINGs).
402 * Queue Head for the transfer being processed by this channel.
404 struct dwc_otg_qh *qh;
408 /** Entry in list of host channels. */
409 DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
411 /** @name Descriptor DMA support */
414 /** Number of Transfer Descriptors */
417 /** Descriptor List DMA address */
418 dwc_dma_t desc_list_addr;
420 /** Scheduling micro-frame bitmap. */
427 * The following parameters may be specified when starting the module. These
428 * parameters define how the DWC_otg controller should be configured.
430 typedef struct dwc_otg_core_params {
434 * Specifies the OTG capabilities. The driver will automatically
435 * detect the value for this parameter if none is specified.
436 * 0 - HNP and SRP capable (default)
437 * 1 - SRP Only capable
438 * 2 - No HNP/SRP capable
443 * Specifies whether to use slave or DMA mode for accessing the data
444 * FIFOs. The driver will automatically detect the value for this
445 * parameter if none is specified.
447 * 1 - DMA (default, if available)
452 * When DMA mode is enabled specifies whether to use address DMA or DMA
453 * Descriptor mode for accessing the data FIFOs in device mode. The driver
454 * will automatically detect the value for this if none is specified.
456 * 1 - DMA Descriptor(default, if available)
458 int32_t dma_desc_enable;
459 /** The DMA Burst size (applicable only for External DMA
460 * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
462 int32_t dma_burst_size; /* Translate this to GAHBCFG values */
465 * Specifies the maximum speed of operation in host and device mode.
466 * The actual speed depends on the speed of the attached device and
467 * the value of phy_type. The actual speed depends on the speed of the
469 * 0 - High Speed (default)
473 /** Specifies whether low power mode is supported when attached
474 * to a Full Speed or Low Speed device in host mode.
475 * 0 - Don't support low power mode (default)
476 * 1 - Support low power mode
478 int32_t host_support_fs_ls_low_power;
480 /** Specifies the PHY clock rate in low power mode when connected to a
481 * Low Speed device in host mode. This parameter is applicable only if
482 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
483 * then defaults to 6 MHZ otherwise 48 MHZ.
488 int32_t host_ls_low_power_phy_clk;
491 * 0 - Use cC FIFO size parameters
492 * 1 - Allow dynamic FIFO sizing (default)
494 int32_t enable_dynamic_fifo;
496 /** Total number of 4-byte words in the data FIFO memory. This
497 * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
499 * 32 to 32768 (default 8192)
500 * Note: The total FIFO memory depth in the FPGA configuration is 8192.
502 int32_t data_fifo_size;
504 /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
505 * FIFO sizing is enabled.
506 * 16 to 32768 (default 1064)
508 int32_t dev_rx_fifo_size;
510 /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
511 * when dynamic FIFO sizing is enabled.
512 * 16 to 32768 (default 1024)
514 int32_t dev_nperio_tx_fifo_size;
516 /** Number of 4-byte words in each of the periodic Tx FIFOs in device
517 * mode when dynamic FIFO sizing is enabled.
518 * 4 to 768 (default 256)
520 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
522 /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
523 * FIFO sizing is enabled.
524 * 16 to 32768 (default 1024)
526 int32_t host_rx_fifo_size;
528 /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
529 * when Dynamic FIFO sizing is enabled in the core.
530 * 16 to 32768 (default 1024)
532 int32_t host_nperio_tx_fifo_size;
534 /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
535 * FIFO sizing is enabled.
536 * 16 to 32768 (default 1024)
538 int32_t host_perio_tx_fifo_size;
540 /** The maximum transfer size supported in bytes.
541 * 2047 to 65,535 (default 65,535)
543 int32_t max_transfer_size;
545 /** The maximum number of packets in a transfer.
546 * 15 to 511 (default 511)
548 int32_t max_packet_count;
550 /** The number of host channel registers to use.
551 * 1 to 16 (default 12)
552 * Note: The FPGA configuration supports a maximum of 12 host channels.
554 int32_t host_channels;
556 /** The number of endpoints in addition to EP0 available for device
558 * 1 to 15 (default 6 IN and OUT)
559 * Note: The FPGA configuration supports a maximum of 6 IN and OUT
560 * endpoints in addition to EP0.
562 int32_t dev_endpoints;
565 * Specifies the type of PHY interface to use. By default, the driver
566 * will automatically detect the phy_type.
569 * 1 - UTMI+ (default)
575 * Specifies the UTMI+ Data Width. This parameter is
576 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
577 * PHY_TYPE, this parameter indicates the data width between
578 * the MAC and the ULPI Wrapper.) Also, this parameter is
579 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
580 * to "8 and 16 bits", meaning that the core has been
581 * configured to work at either data path width.
583 * 8 or 16 bits (default 16)
585 int32_t phy_utmi_width;
588 * Specifies whether the ULPI operates at double or single
589 * data rate. This parameter is only applicable if PHY_TYPE is
592 * 0 - single data rate ULPI interface with 8 bit wide data
594 * 1 - double data rate ULPI interface with 4 bit wide data
597 int32_t phy_ulpi_ddr;
600 * Specifies whether to use the internal or external supply to
601 * drive the vbus with a ULPI phy.
603 int32_t phy_ulpi_ext_vbus;
606 * Specifies whether to use the I2Cinterface for full speed PHY. This
607 * parameter is only applicable if PHY_TYPE is FS.
618 * Specifies whether dedicated transmit FIFOs are
619 * enabled for non periodic IN endpoints in device mode
623 int32_t en_multiple_tx_fifo;
625 /** Number of 4-byte words in each of the Tx FIFOs in device
626 * mode when dynamic FIFO sizing is enabled.
627 * 4 to 768 (default 256)
629 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
631 /** Thresholding enable flag-
632 * bit 0 - enable non-ISO Tx thresholding
633 * bit 1 - enable ISO Tx thresholding
634 * bit 2 - enable Rx thresholding
638 /** Thresholding length for Tx
639 * FIFOs in 32 bit DWORDs
641 uint32_t tx_thr_length;
643 /** Thresholding length for Rx
644 * FIFOs in 32 bit DWORDs
646 uint32_t rx_thr_length;
649 * Specifies whether LPM (Link Power Management) support is enabled
654 * Specifies whether LPM Errata (Link Power Management) support is enabled
659 * Specifies the baseline besl value
661 int32_t baseline_besl;
664 * Specifies the deep besl value
667 /** Per Transfer Interrupt
674 /** Multi Processor Interrupt
681 /** IS_USB Capability
687 /** AHB Threshold Ratio
688 * 2'b00 AHB Threshold = MAC Threshold
689 * 2'b01 AHB Threshold = 1/2 MAC Threshold
690 * 2'b10 AHB Threshold = 1/4 MAC Threshold
691 * 2'b11 AHB Threshold = 1/8 MAC Threshold
693 int32_t ahb_thr_ratio;
699 int32_t adp_supp_enable;
701 /** HFIR Reload Control
702 * 0 - The HFIR cannot be reloaded dynamically.
703 * 1 - Allow dynamic reloading of the HFIR register during runtime.
707 /** DCFG: Enable device Out NAK
708 * 0 - The core does not set NAK after Bulk Out transfer complete.
709 * 1 - The core sets NAK after Bulk OUT transfer complete.
713 /** DCFG: Enable Continue on BNA
714 * After receiving BNA interrupt the core disables the endpoint,when the
715 * endpoint is re-enabled by the application the core starts processing
716 * 0 - from the DOEPDMA descriptor
717 * 1 - from the descriptor which received the BNA.
721 /** GAHBCFG: AHB Single Support
722 * This bit when programmed supports SINGLE transfers for remainder
723 * data in a transfer for DMA mode of operation.
724 * 0 - in this case the remainder data will be sent using INCR burst size.
725 * 1 - in this case the remainder data will be sent using SINGLE burst size.
729 /** Core Power down mode
730 * 0 - No Power Down is enabled
732 * 2 - Complete Power Down (Hibernation)
736 /** OTG revision supported
737 * 0 - OTG 1.3 revision
738 * 1 - OTG 2.0 revision
742 } dwc_otg_core_params_t;
745 struct dwc_otg_core_if;
746 typedef struct hc_xfer_info {
747 struct dwc_otg_core_if *core_if;
752 typedef struct ep_xfer_info {
753 struct dwc_otg_core_if *core_if;
760 typedef enum dwc_otg_lx_state {
763 /** LPM sleep state*/
765 /** USB suspend state*/
769 } dwc_otg_lx_state_e;
771 struct dwc_otg_global_regs_backup {
772 uint32_t gotgctl_local;
773 uint32_t gintmsk_local;
774 uint32_t gahbcfg_local;
775 uint32_t gusbcfg_local;
776 uint32_t grxfsiz_local;
777 uint32_t gnptxfsiz_local;
778 #ifdef CONFIG_USB_DWC_OTG_LPM
779 uint32_t glpmcfg_local;
781 uint32_t gi2cctl_local;
782 uint32_t hptxfsiz_local;
783 uint32_t pcgcctl_local;
784 uint32_t gdfifocfg_local;
785 uint32_t dtxfsiz_local[MAX_EPS_CHANNELS];
786 uint32_t gpwrdn_local;
787 uint32_t xhib_pcgcctl;
788 uint32_t xhib_gpwrdn;
791 struct dwc_otg_host_regs_backup {
793 uint32_t haintmsk_local;
794 uint32_t hcintmsk_local[MAX_EPS_CHANNELS];
795 uint32_t hprt0_local;
799 struct dwc_otg_dev_regs_backup {
805 uint32_t diepctl[MAX_EPS_CHANNELS];
806 uint32_t dieptsiz[MAX_EPS_CHANNELS];
807 uint32_t diepdma[MAX_EPS_CHANNELS];
810 * The <code>dwc_otg_core_if</code> structure contains information needed to manage
811 * the DWC_otg controller acting in either host or device mode. It
812 * represents the programming view of the controller as a whole.
814 struct dwc_otg_core_if {
815 /** Parameters that define how the core should be configured.*/
816 dwc_otg_core_params_t *core_params;
818 /** Core Global registers starting at offset 000h. */
819 dwc_otg_core_global_regs_t *core_global_regs;
821 /** Device-specific information */
822 dwc_otg_dev_if_t *dev_if;
823 /** Host-specific information */
824 dwc_otg_host_if_t *host_if;
826 /** Value from SNPSID register */
829 /** The DWC otg device pointer. */
830 struct dwc_otg_device *otg_dev;
833 * Set to 1 if the core PHY interface bits in USBCFG have been
836 uint8_t phy_init_done;
839 * SRP Success flag, set by srp success interrupt in FS I2C mode
842 uint8_t srp_timer_started;
843 /** Timer for SRP. If it expires before SRP is successful
845 dwc_timer_t *srp_timer;
848 #define USB_MODE_NORMAL (0)
849 #define USB_MODE_FORCE_HOST (1)
850 #define USB_MODE_FORCE_DEVICE (2)
852 /* Indicate USB get VBUS 5V from PMIC(e.g. rk81x) */
855 #ifdef DWC_DEV_SRPCAP
856 /* This timer is needed to power on the hibernated host core if SRP is not
857 * initiated on connected SRP capable device for limited period of time
859 uint8_t pwron_timer_started;
860 dwc_timer_t *pwron_timer;
862 /* Common configuration information */
863 /** Power and Clock Gating Control Register */
864 volatile uint32_t *pcgcctl;
865 #define DWC_OTG_PCGCCTL_OFFSET 0xE00
867 /** Push/pop addresses for endpoints or host channels.*/
868 uint32_t *data_fifo[MAX_EPS_CHANNELS];
869 #define DWC_OTG_DATA_FIFO_OFFSET 0x1000
870 #define DWC_OTG_DATA_FIFO_SIZE 0x1000
872 /** Total RAM for FIFOs (Bytes) */
873 uint16_t total_fifo_size;
874 /** Size of Rx FIFO (Bytes) */
875 uint16_t rx_fifo_size;
876 /** Size of Non-periodic Tx FIFO (Bytes) */
877 uint16_t nperio_tx_fifo_size;
879 /** 1 if DMA is enabled, 0 otherwise. */
882 /** 1 if DMA descriptor is enabled, 0 otherwise. */
883 uint8_t dma_desc_enable;
885 /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
886 uint8_t pti_enh_enable;
888 /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
889 uint8_t multiproc_int_enable;
891 /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
892 uint8_t en_multiple_tx_fifo;
894 /** Set to 1 if multiple packets of a high-bandwidth transfer is in
895 * process of being queued */
896 uint8_t queuing_high_bandwidth;
898 /** Hardware Configuration -- stored here for convenience.*/
899 hwcfg1_data_t hwcfg1;
900 hwcfg2_data_t hwcfg2;
901 hwcfg3_data_t hwcfg3;
902 hwcfg4_data_t hwcfg4;
903 fifosize_data_t hptxfsiz;
905 /** Host and Device Configuration -- stored here for convenience.*/
909 /** The operational State, during transations
910 * (a_host>>a_peripherial and b_device=>b_host) this may not
911 * match the core but allows the software to determine
916 /** Test mode for PET testing */
920 * Set to 1 if the HCD needs to be restarted on a session request
921 * interrupt. This is required if no connector ID status change has
922 * occurred since the HCD was last disconnected.
924 uint8_t restart_hcd_on_session_req;
927 /** A-Device is a_host */
929 /** A-Device is a_suspend */
930 #define A_SUSPEND (2)
931 /** A-Device is a_peripherial */
932 #define A_PERIPHERAL (3)
933 /** B-Device is operating as a Peripheral. */
934 #define B_PERIPHERAL (4)
935 /** B-Device is operating as a Host. */
939 struct dwc_otg_cil_callbacks *hcd_cb;
942 struct dwc_otg_cil_callbacks *pcd_cb;
944 /** Device mode Periodic Tx FIFO Mask */
946 /** Device mode Periodic Tx FIFO Mask */
949 /** Workqueue object used for handling several interrupts */
952 /** Tasklet used for handling "Wakeup Detected" Interrupt*/
953 dwc_tasklet_t *wkp_tasklet;
954 /** This arrays used for debug purposes for DEV OUT NAK enhancement */
955 uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS];
956 ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS];
957 dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS];
959 uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
961 hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
962 dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
964 uint32_t hfnum_7_samples;
965 uint64_t hfnum_7_frrem_accum;
966 uint32_t hfnum_0_samples;
967 uint64_t hfnum_0_frrem_accum;
968 uint32_t hfnum_other_samples;
969 uint64_t hfnum_other_frrem_accum;
973 uint16_t pwron_rxfsiz;
974 uint16_t pwron_gnptxfsiz;
975 uint16_t pwron_txfsiz[15];
977 uint16_t init_rxfsiz;
978 uint16_t init_gnptxfsiz;
979 uint16_t init_txfsiz[15];
982 /** Lx state of device */
983 dwc_otg_lx_state_e lx_state;
985 /** Saved Core Global registers */
986 struct dwc_otg_global_regs_backup *gr_backup;
987 /** Saved Host registers */
988 struct dwc_otg_host_regs_backup *hr_backup;
989 /** Saved Device registers */
990 struct dwc_otg_dev_regs_backup *dr_backup;
992 /** Power Down Enable */
995 /** ADP support Enable */
998 /** ADP structure object */
1001 /** hibernation/suspend flag */
1002 int hibernation_suspend;
1004 /** Device mode extended hibernation flag */
1007 /** OTG revision supported */
1010 /** OTG status flag used for HNP polling */
1013 /** Pointer to either hcd->lock or pcd->lock */
1014 dwc_spinlock_t *lock;
1016 /** Start predict NextEP based on Learning Queue if equal 1,
1017 * also used as counter of disabled NP IN EP's */
1018 uint8_t start_predict;
1020 /** NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and
1021 * active, 0xff otherwise */
1022 uint8_t nextep_seq[MAX_EPS_CHANNELS];
1024 /** Index of fisrt EP in nextep_seq array which should be re-enabled **/
1025 uint8_t first_in_nextep_seq;
1027 /** Frame number while entering to ISR - needed for ISOCs **/
1030 /** Flag to not perform ADP probing if IDSTS event happened */
1031 uint8_t stop_adpprb;
1037 * This function is called when transfer is timed out.
1039 extern void hc_xfer_timeout(void *ptr);
1043 * This function is called when transfer is timed out on endpoint.
1045 extern void ep_xfer_timeout(void *ptr);
1048 * The following functions are functions for works
1049 * using during handling some interrupts
1051 extern void w_conn_id_status_change(void *p);
1053 extern void w_wakeup_detected(void *data);
1055 /** Saves global register values into system memory. */
1056 extern int dwc_otg_save_global_regs(dwc_otg_core_if_t *core_if);
1057 /** Saves device register values into system memory. */
1058 extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t *core_if);
1059 /** Saves host register values into system memory. */
1060 extern int dwc_otg_save_host_regs(dwc_otg_core_if_t *core_if);
1061 /** Restore global register values. */
1062 extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if);
1063 /** Restore host register values. */
1064 extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t *core_if, int reset);
1065 /** Restore device register values. */
1066 extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t *core_if,
1068 extern int restore_lpm_i2c_regs(dwc_otg_core_if_t *core_if);
1069 extern int restore_essential_regs(dwc_otg_core_if_t *core_if, int rmode,
1072 extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t *core_if,
1073 int restore_mode, int reset);
1074 extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t *core_if,
1075 int rem_wakeup, int reset);
1078 * The following functions support initialization of the CIL driver component
1079 * and the DWC_otg controller.
1081 extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if);
1082 extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if);
1084 /** @name Device CIL Functions
1085 * The following functions support managing the DWC_otg controller in device
1089 extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if);
1090 extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t *_core_if,
1092 extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if);
1093 extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
1094 extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
1095 extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
1096 extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if,
1098 extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *_core_if,
1100 extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if,
1102 extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if,
1104 extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if,
1105 dwc_ep_t *_ep, int _dma);
1106 extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
1107 extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if,
1109 extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if);
1112 extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if,
1114 extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t *core_if,
1116 #endif /* DWC_EN_ISOC */
1119 /** @name Host CIL Functions
1120 * The following functions support managing the DWC_otg controller in host
1124 extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
1125 extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
1126 dwc_hc_t *_hc, dwc_otg_halt_status_e _halt_status);
1127 extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
1128 extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if,
1130 extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if,
1132 extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
1133 extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if,
1135 extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if);
1136 extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if);
1138 extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t *core_if,
1141 extern uint32_t calc_frame_interval(dwc_otg_core_if_t *core_if);
1142 extern int dwc_otg_check_haps_status(dwc_otg_core_if_t *core_if);
1144 /* Macro used to clear one channel interrupt */
1145 #define clear_hc_int(_hc_regs_, _intr_) \
1147 hcint_data_t hcint_clear = {.d32 = 0}; \
1148 hcint_clear.b._intr_ = 1; \
1149 DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \
1153 * Macro used to disable one channel interrupt. Channel interrupts are
1154 * disabled when the channel is halted or released by the interrupt handler.
1155 * There is no need to handle further interrupts of that type until the
1156 * channel is re-assigned. In fact, subsequent handling may cause crashes
1157 * because the channel structures are cleaned up when the channel is released.
1159 #define disable_hc_int(_hc_regs_, _intr_) \
1161 hcintmsk_data_t hcintmsk = {.d32 = 0}; \
1162 hcintmsk.b._intr_ = 1; \
1163 DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
1167 * This function Reads HPRT0 in preparation to modify. It keeps the
1168 * WC bits 0 so that if they are read as 1, they won't clear when you
1171 static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if)
1174 hprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0);
1176 hprt0.b.prtconndet = 0;
1177 hprt0.b.prtenchng = 0;
1178 hprt0.b.prtovrcurrchng = 0;
1184 /** @name Common CIL Functions
1185 * The following functions support managing the DWC_otg controller in either
1186 * device or host mode.
1190 extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
1191 uint8_t *dest, uint16_t bytes);
1193 extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t *_core_if, const int _num);
1194 extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t *_core_if);
1195 extern void dwc_otg_core_reset(dwc_otg_core_if_t *_core_if);
1198 * This function returns the Core Interrupt register.
1200 static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *core_if)
1203 retval = DWC_READ_REG32(&core_if->core_global_regs->gintsts) &
1204 DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
1209 * This function returns the OTG Interrupt register.
1211 static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t *core_if)
1214 retval = DWC_READ_REG32(&core_if->core_global_regs->gotgint);
1219 * This function reads the Device All Endpoints Interrupt register and
1220 * returns the IN endpoint interrupt bits.
1222 static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t
1228 if (core_if->multiproc_int_enable) {
1229 v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
1230 deachint) & DWC_READ_REG32(&core_if->dev_if->
1234 v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
1235 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
1242 * This function reads the Device All Endpoints Interrupt register and
1243 * returns the OUT endpoint interrupt bits.
1245 static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t
1250 if (core_if->multiproc_int_enable) {
1251 v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
1252 deachint) & DWC_READ_REG32(&core_if->dev_if->
1256 v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
1257 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
1260 v = (v & 0xffff0000) >> 16;
1265 * This function returns the Device IN EP Interrupt register
1267 static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *core_if,
1270 dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1271 uint32_t v, msk, emp;
1273 if (core_if->multiproc_int_enable) {
1275 DWC_READ_REG32(&dev_if->dev_global_regs->
1276 diepeachintmsk[ep->num]);
1278 DWC_READ_REG32(&dev_if->dev_global_regs->
1279 dtknqr4_fifoemptymsk);
1280 msk |= ((emp >> ep->num) & 0x1) << 7;
1281 v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
1283 msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk);
1285 DWC_READ_REG32(&dev_if->dev_global_regs->
1286 dtknqr4_fifoemptymsk);
1287 msk |= ((emp >> ep->num) & 0x1) << 7;
1288 v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
1295 * This function returns the Device OUT EP Interrupt register
1297 static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
1298 _core_if, dwc_ep_t *_ep)
1300 dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
1302 doepmsk_data_t msk = {.d32 = 0 };
1304 if (_core_if->multiproc_int_enable) {
1306 DWC_READ_REG32(&dev_if->dev_global_regs->
1307 doepeachintmsk[_ep->num]);
1308 if (_core_if->pti_enh_enable) {
1309 msk.b.pktdrpsts = 1;
1311 v = DWC_READ_REG32(&dev_if->out_ep_regs[_ep->num]->
1314 msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk);
1315 if (_core_if->pti_enh_enable) {
1316 msk.b.pktdrpsts = 1;
1318 v = DWC_READ_REG32(&dev_if->out_ep_regs[_ep->num]->
1325 * This function returns the Host All Channel Interrupt register
1327 static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
1331 retval = DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint);
1335 static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
1336 _core_if, dwc_hc_t *_hc)
1339 retval = DWC_READ_REG32(&_core_if->host_if->hc_regs[_hc->hc_num]->hcint);
1344 * This function returns the mode of the operation, host or device.
1346 * @return 0 - Device Mode, 1 - Host Mode
1348 static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if)
1351 retval = DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1;
1358 * DWC_otg CIL callback structure. This structure allows the HCD and
1359 * PCD to register functions used for starting and stopping the PCD
1360 * and HCD for role change on for a DRD.
1362 typedef struct dwc_otg_cil_callbacks {
1363 /** Start function for role change */
1364 int (*start) (void *_p);
1365 /** Stop Function for role change */
1366 int (*stop) (void *_p);
1367 /** Disconnect Function for role change */
1368 int (*disconnect) (void *_p);
1369 /** Resume/Remote wakeup Function */
1370 int (*resume_wakeup) (void *_p);
1371 /** Suspend function */
1372 int (*suspend) (void *_p);
1373 /** Session Start (SRP) */
1374 int (*session_start) (void *_p);
1375 #ifdef CONFIG_USB_DWC_OTG_LPM
1376 /** Sleep (switch to L0 state) */
1377 int (*sleep) (void *_p);
1379 /** Pointer passed to start() and stop() */
1381 } dwc_otg_cil_callbacks_t;
1383 extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t *_core_if,
1384 dwc_otg_cil_callbacks_t *_cb,
1386 extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t *_core_if,
1387 dwc_otg_cil_callbacks_t *_cb,
1390 void dwc_otg_initiate_srp(void *core_if);
1392 /** Start the HCD. Helper function for using the HCD callbacks.
1394 * @param core_if Programming view of DWC_otg controller.
1396 static inline void cil_hcd_start(dwc_otg_core_if_t *core_if)
1398 if (core_if->hcd_cb && core_if->hcd_cb->start) {
1399 core_if->hcd_cb->start(core_if->hcd_cb_p);
1403 /** Stop the HCD. Helper function for using the HCD callbacks.
1405 * @param core_if Programming view of DWC_otg controller.
1407 static inline void cil_hcd_stop(dwc_otg_core_if_t *core_if)
1409 if (core_if->hcd_cb && core_if->hcd_cb->stop) {
1410 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1414 /** Disconnect the HCD. Helper function for using the HCD callbacks.
1416 * @param core_if Programming view of DWC_otg controller.
1418 static inline void cil_hcd_disconnect(dwc_otg_core_if_t *core_if)
1420 if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
1421 core_if->hcd_cb->disconnect(core_if->hcd_cb_p);
1425 /** Inform the HCD the a New Session has begun. Helper function for
1426 * using the HCD callbacks.
1428 * @param core_if Programming view of DWC_otg controller.
1430 static inline void cil_hcd_session_start(dwc_otg_core_if_t *core_if)
1432 if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
1433 core_if->hcd_cb->session_start(core_if->hcd_cb_p);
1437 #ifdef CONFIG_USB_DWC_OTG_LPM
1439 * Inform the HCD about LPM sleep.
1440 * Helper function for using the HCD callbacks.
1442 * @param core_if Programming view of DWC_otg controller.
1444 static inline void cil_hcd_sleep(dwc_otg_core_if_t *core_if)
1446 if (core_if->hcd_cb && core_if->hcd_cb->sleep) {
1447 core_if->hcd_cb->sleep(core_if->hcd_cb_p);
1452 /** Resume the HCD. Helper function for using the HCD callbacks.
1454 * @param core_if Programming view of DWC_otg controller.
1456 static inline void cil_hcd_resume(dwc_otg_core_if_t *core_if)
1458 if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {
1459 core_if->hcd_cb->resume_wakeup(core_if->hcd_cb_p);
1463 /** Start the PCD. Helper function for using the PCD callbacks.
1465 * @param core_if Programming view of DWC_otg controller.
1467 static inline void cil_pcd_start(dwc_otg_core_if_t *core_if)
1469 if (core_if->pcd_cb && core_if->pcd_cb->start) {
1470 core_if->pcd_cb->start(core_if->pcd_cb->p);
1474 /** Stop the PCD. Helper function for using the PCD callbacks.
1476 * @param core_if Programming view of DWC_otg controller.
1478 static inline void cil_pcd_stop(dwc_otg_core_if_t *core_if)
1480 if (core_if->pcd_cb && core_if->pcd_cb->stop) {
1481 core_if->pcd_cb->stop(core_if->pcd_cb->p);
1485 /** Suspend the PCD. Helper function for using the PCD callbacks.
1487 * @param core_if Programming view of DWC_otg controller.
1489 static inline void cil_pcd_suspend(dwc_otg_core_if_t *core_if)
1491 if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
1492 core_if->pcd_cb->suspend(core_if->pcd_cb->p);
1496 /** Resume the PCD. Helper function for using the PCD callbacks.
1498 * @param core_if Programming view of DWC_otg controller.
1500 static inline void cil_pcd_resume(dwc_otg_core_if_t *core_if)
1502 if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
1503 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
1507 void dwc_otg_set_force_mode(dwc_otg_core_if_t *core_if, int mode);