drivers/usb/dwc_otg_310/dwc_otg_cil_intr.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
   3  * $Revision: #35 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33
  34 /** @file
  35  *
  36  * The Core Interface Layer provides basic services for accessing and
  37  * managing the DWC_otg hardware. These services are used by both the
  38  * Host Controller Driver and the Peripheral Controller Driver.
  39  *
  40  * This file contains the Common Interrupt handlers.
  41  */
  42 #include "common_port/dwc_os.h"
  43 #include "dwc_otg_regs.h"
  44 #include "dwc_otg_cil.h"
  45 #include "dwc_otg_driver.h"
  46 #include "dwc_otg_pcd.h"
  47 #include "dwc_otg_hcd.h"
  48 #include "usbdev_rk.h"
  49
  50 #ifdef DEBUG
  51 inline const char *op_state_str(dwc_otg_core_if_t * core_if)
  52 {
  53         return (core_if->op_state == A_HOST ? "a_host" :
  54                 (core_if->op_state == A_SUSPEND ? "a_suspend" :
  55                  (core_if->op_state == A_PERIPHERAL ? "a_peripheral" :
  56                   (core_if->op_state == B_PERIPHERAL ? "b_peripheral" :
  57                    (core_if->op_state == B_HOST ? "b_host" : "unknown")))));
  58 }
  59 #endif
  60
  61 /** This function will log a debug message
  62  *
  63  * @param core_if Programming view of DWC_otg controller.
  64  */
  65 int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if)
  66 {
  67         gintsts_data_t gintsts;
  68         DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
  69                  dwc_otg_mode(core_if) ? "Host" : "Device");
  70
  71         /* Clear interrupt */
  72         gintsts.d32 = 0;
  73         gintsts.b.modemismatch = 1;
  74         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
  75         return 1;
  76 }
  77
  78 /**
  79  * This function handles the OTG Interrupts. It reads the OTG
  80  * Interrupt Register (GOTGINT) to determine what interrupt has
  81  * occurred.
  82  *
  83  * @param core_if Programming view of DWC_otg controller.
  84  */
  85 int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if)
  86 {
  87         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
  88         gotgint_data_t gotgint;
  89         gotgctl_data_t gotgctl;
  90         gintmsk_data_t gintmsk;
  91         gpwrdn_data_t gpwrdn;
  92         dctl_data_t dctl = {.d32=0};
  93
  94         gotgint.d32 = DWC_READ_REG32(&global_regs->gotgint);
  95         gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
  96         DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
  97                     op_state_str(core_if));
  98
  99         if (gotgint.b.sesenddet) {
 100                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
 101                             "Session End Detected++ (%s)\n",
 102                             op_state_str(core_if));
 103
 104                 /* do soft disconnect */
 105                 dctl.d32= DWC_READ_REG32( &core_if->dev_if->dev_global_regs->dctl );
 106                 dctl.b.sftdiscon = 1;
 107                 DWC_WRITE_REG32( &core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
 108                 dwc_otg_disable_global_interrupts(core_if);
 109                 core_if->otg_dev->pcd->vbus_status = USB_BC_TYPE_DISCNT;
 110                 DWC_PRINTF("********session end ,soft disconnect************************\n");
 111
 112                 gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
 113
 114                 if (core_if->op_state == B_HOST) {
 115                         cil_pcd_start(core_if);
 116                         core_if->op_state = B_PERIPHERAL;
 117                 } else {
 118                         /* If not B_HOST and Device HNP still set. HNP
 119                          * Did not succeed!*/
 120                         if (gotgctl.b.devhnpen) {
 121                                 DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
 122                                 __DWC_ERROR("Device Not Connected/Responding!\n");
 123                         }
 124
 125                         /* If Session End Detected the B-Cable has
 126                          * been disconnected. */
 127                         /* Reset PCD and Gadget driver to a
 128                          * clean state. */
 129                         core_if->lx_state = DWC_OTG_L0;
 130                         DWC_SPINUNLOCK(core_if->lock);
 131                         cil_pcd_stop(core_if);
 132                         DWC_SPINLOCK(core_if->lock);
 133
 134                         if (core_if->otg_ver) {
 135                                 /** PET testing*/
 136                                 gotgctl.d32 = 0;
 137                                 gotgctl.b.devhnpen = 1;
 138                                 DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
 139                                 if (core_if->test_mode == 6) {
 140                                         DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,     dwc_otg_initiate_srp,
 141                                                                 core_if, 3000, "initate SRP"); //manukz: old value was 50
 142                                         core_if->test_mode = 0;
 143                                 } else  if (core_if->adp_enable) {
 144                                         if (core_if->power_down == 2) {
 145                                                 gpwrdn.d32 = 0;
 146                                                 gpwrdn.b.pwrdnswtch = 1;
 147                                                 DWC_MODIFY_REG32(&core_if->
 148                                                                  core_global_regs->
 149                                                                  gpwrdn, gpwrdn.d32, 0);
 150                                         }
 151
 152                                         gpwrdn.d32 = 0;
 153                                         gpwrdn.b.pmuintsel = 1;
 154                                         gpwrdn.b.pmuactv = 1;
 155                                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 156                                         dwc_otg_adp_sense_start(core_if);
 157                                 }
 158                         }
 159                 }
 160                 if (core_if->otg_ver == 0) {
 161                         gotgctl.d32 = 0;
 162                         gotgctl.b.devhnpen = 1;
 163                         DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
 164                 }
 165         }
 166         if (gotgint.b.sesreqsucstschng) {
 167                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
 168                             "Session Reqeust Success Status Change++\n");
 169                 gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
 170                 if (gotgctl.b.sesreqscs) {
 171
 172                         if ((core_if->core_params->phy_type ==
 173                              DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) {
 174                                 core_if->srp_success = 1;
 175                         } else {
 176                                 DWC_SPINUNLOCK(core_if->lock);
 177                                 cil_pcd_resume(core_if);
 178                                 DWC_SPINLOCK(core_if->lock);
 179                                 /* Clear Session Request */
 180                                 gotgctl.d32 = 0;
 181                                 gotgctl.b.sesreq = 1;
 182                                 DWC_MODIFY_REG32(&global_regs->gotgctl,
 183                                                  gotgctl.d32, 0);
 184                         }
 185                 }
 186         }
 187         if (gotgint.b.hstnegsucstschng) {
 188                 /* Print statements during the HNP interrupt handling
 189                  * can cause it to fail.*/
 190                 gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
 191                 /* WA for 3.00a- HW is not setting cur_mode, even sometimes
 192                  * this does not help*/
 193                 if (core_if->snpsid >= OTG_CORE_REV_3_00a)
 194                         dwc_udelay(100);
 195                 if (gotgctl.b.hstnegscs) {
 196                         if (dwc_otg_is_host_mode(core_if)) {
 197                                 core_if->op_state = B_HOST;
 198                                 /*
 199                                  * Need to disable SOF interrupt immediately.
 200                                  * When switching from device to host, the PCD
 201                                  * interrupt handler won't handle the
 202                                  * interrupt if host mode is already set. The
 203                                  * HCD interrupt handler won't get called if
 204                                  * the HCD state is HALT. This means that the
 205                                  * interrupt does not get handled and Linux
 206                                  * complains loudly.
 207                                  */
 208                                 gintmsk.d32 = 0;
 209                                 gintmsk.b.sofintr = 1;
 210                                 //gintmsk.b.usbsuspend = 1; // vahrama !!!!!!
 211                                 DWC_MODIFY_REG32(&global_regs->gintmsk,
 212                                                  gintmsk.d32, 0);
 213                                 /* Call callback function with spin lock released */
 214                                 DWC_SPINUNLOCK(core_if->lock);
 215                                 cil_pcd_stop(core_if);
 216                                 /*
 217                                  * Initialize the Core for Host mode.
 218                                  */
 219                                 cil_hcd_start(core_if);
 220                                 DWC_SPINLOCK(core_if->lock);
 221                         }
 222                 } else {
 223                         gotgctl.d32 = 0;
 224                         gotgctl.b.hnpreq = 1;
 225                         gotgctl.b.devhnpen = 1;
 226                         DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
 227                         DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
 228                         __DWC_ERROR("Device Not Connected/Responding\n");
 229                 }
 230         }
 231         if (gotgint.b.hstnegdet) {
 232                 /* The disconnect interrupt is set at the same time as
 233                  * Host Negotiation Detected.  During the mode
 234                  * switch all interrupts are cleared so the disconnect
 235                  * interrupt handler will not get executed.
 236                  */
 237                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
 238                             "Host Negotiation Detected++ (%s)\n",
 239                             (dwc_otg_is_host_mode(core_if) ? "Host" :
 240                              "Device"));
 241                 if (dwc_otg_is_device_mode(core_if)) {
 242                         DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",
 243                                     core_if->op_state);
 244                         DWC_SPINUNLOCK(core_if->lock);
 245                         cil_hcd_disconnect(core_if);
 246                         cil_pcd_start(core_if);
 247                         DWC_SPINLOCK(core_if->lock);
 248                         core_if->op_state = A_PERIPHERAL;
 249                 } else {
 250                         /*
 251                          * Need to disable SOF interrupt immediately. When
 252                          * switching from device to host, the PCD interrupt
 253                          * handler won't handle the interrupt if host mode is
 254                          * already set. The HCD interrupt handler won't get
 255                          * called if the HCD state is HALT. This means that
 256                          * the interrupt does not get handled and Linux
 257                          * complains loudly.
 258                          */
 259                         gintmsk.d32 = 0;
 260                         gintmsk.b.sofintr = 1;
 261                         DWC_MODIFY_REG32(&global_regs->gintmsk, gintmsk.d32, 0);
 262                         DWC_SPINUNLOCK(core_if->lock);
 263                         cil_pcd_stop(core_if);
 264                         cil_hcd_start(core_if);
 265                         DWC_SPINLOCK(core_if->lock);
 266                         core_if->op_state = A_HOST;
 267                 }
 268         }
 269         if (gotgint.b.adevtoutchng) {
 270                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
 271                             "A-Device Timeout Change++\n");
 272         }
 273         if (gotgint.b.debdone) {
 274                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n");
 275                 /* Need to power off VBUS after 10s if OTG2 non-hnp capable host*/
 276                 if(core_if->otg_ver == 1)
 277                         cil_hcd_session_start(core_if);
 278         }
 279
 280         /* Clear GOTGINT */
 281         DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, gotgint.d32);
 282
 283         return 1;
 284 }
 285
 286 void w_conn_id_status_change(void *p)
 287 {
 288         dwc_otg_core_if_t *core_if = p;
 289         uint32_t count = 0;
 290         gotgctl_data_t gotgctl = {.d32 = 0 };
 291         dwc_otg_pcd_t *pcd = core_if->otg_dev->pcd;
 292
 293         gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
 294         DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
 295         DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
 296
 297         /* B-Device connector (Device Mode) */
 298         if (gotgctl.b.conidsts) {
 299                 gotgctl_data_t gotgctl_local;
 300
 301                 /* Wait for switch to device mode. */
 302                 while (!dwc_otg_is_device_mode(core_if)) {
 303                         gotgctl_local.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
 304                         DWC_DEBUGPL(DBG_ANY, "Waiting for Peripheral Mode, Mode=%s count = %d gotgctl=%08x\n",
 305                                    (dwc_otg_is_host_mode(core_if) ? "Host" :
 306                                     "Peripheral"), count, gotgctl_local.d32);
 307                         dwc_mdelay(1); //vahrama previous value was 100
 308                         if(!gotgctl_local.b.conidsts)
 309                                 goto host;
 310                         if (++count > 10000)
 311                                 break;
 312                 }
 313                 DWC_ASSERT(++count < 10000,
 314                            "Connection id status change timed out");
 315                 core_if->op_state = B_PERIPHERAL;
 316                 cil_hcd_stop(core_if);;
 317                 //pcd->phy_suspend = 1;
 318                 pcd->vbus_status = 0;
 319                 dwc_otg_pcd_start_check_vbus_work(pcd);
 320                 if(core_if->otg_ver == 0)
 321                         dwc_otg_core_init(core_if);
 322                 dwc_otg_enable_global_interrupts(core_if);
 323                 cil_pcd_start(core_if);
 324         } else {
 325 host:
 326                 /* A-Device connector (Host Mode) */
 327                 while (!dwc_otg_is_host_mode(core_if)) {
 328                 DWC_DEBUGPL(DBG_ANY,"Waiting for Host Mode, Mode=%s\n",
 329                                    (dwc_otg_is_host_mode(core_if) ? "Host" :
 330                                     "Peripheral"));
 331                         dwc_mdelay(1);  //vahrama previously was 100
 332                         if (++count > 10000)
 333                                 break;
 334                 }
 335                 DWC_ASSERT(++count < 10000,
 336                            "Connection id status change timed out");
 337                 core_if->op_state = A_HOST;
 338
 339                 cancel_delayed_work(&pcd->check_vbus_work);
 340
 341                 /*
 342                  * Initialize the Core for Host mode.
 343                  */
 344                 if (core_if->otg_ver)
 345                         /* To power off the bus in 10s from the beginning
 346                          * of test while denounce has not come yet */
 347                         cil_hcd_session_start(core_if);
 348                 else
 349                         dwc_otg_core_init(core_if);
 350                 dwc_otg_enable_global_interrupts(core_if);
 351                 cil_hcd_start(core_if);
 352         }
 353 }
 354
 355 /**
 356  * This function handles the Connector ID Status Change Interrupt.  It
 357  * reads the OTG Interrupt Register (GOTCTL) to determine whether this
 358  * is a Device to Host Mode transition or a Host Mode to Device
 359  * Transition.
 360  *
 361  * This only occurs when the cable is connected/removed from the PHY
 362  * connector.
 363  *
 364  * @param core_if Programming view of DWC_otg controller.
 365  */
 366 int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
 367 {
 368
 369         /*
 370          * Need to disable SOF interrupt immediately. If switching from device
 371          * to host, the PCD interrupt handler won't handle the interrupt if
 372          * host mode is already set. The HCD interrupt handler won't get
 373          * called if the HCD state is HALT. This means that the interrupt does
 374          * not get handled and Linux complains loudly.
 375          */
 376         gintmsk_data_t gintmsk = {.d32 = 0 };
 377         gintsts_data_t gintsts = {.d32 = 0 };
 378
 379         if(core_if->usb_mode != USB_MODE_NORMAL)
 380                 goto out;
 381
 382         gintmsk.b.sofintr = 1;
 383         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
 384         DWC_DEBUGPL(DBG_CIL,
 385                     " ++Connector ID Status Change Interrupt++  (%s)\n",
 386                     (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
 387
 388         DWC_SPINUNLOCK(core_if->lock);
 389
 390         /*
 391          * Need to schedule a work, as there are possible DELAY function calls
 392          * Release lock before scheduling workq as it holds spinlock during scheduling
 393          */
 394
 395         DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
 396                            core_if, "connection id status change");
 397         DWC_SPINLOCK(core_if->lock);
 398 out:
 399         /* Set flag and clear interrupt */
 400         gintsts.b.conidstschng = 1;
 401         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
 402
 403         return 1;
 404 }
 405
 406 /**
 407  * This interrupt indicates that a device is initiating the Session
 408  * Request Protocol to request the host to turn on bus power so a new
 409  * session can begin. The handler responds by turning on bus power. If
 410  * the DWC_otg controller is in low power mode, the handler brings the
 411  * controller out of low power mode before turning on bus power.
 412  *
 413  * @param core_if Programming view of DWC_otg controller.
 414  */
 415 int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
 416 {
 417         gintsts_data_t gintsts;
 418
 419 #ifndef DWC_HOST_ONLY
 420         DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
 421         if (dwc_otg_is_device_mode(core_if)) {
 422                 gotgctl_data_t gotgctl = {.d32 = 0 };
 423                 DWC_PRINTF("SRP: Device mode\n");
 424                 gotgctl.d32 =
 425                         DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
 426                 if (gotgctl.b.sesreqscs)
 427                         DWC_PRINTF("SRP Success\n");
 428                 else
 429                         DWC_PRINTF("SRP Fail\n");
 430                 if (core_if->otg_ver) {
 431                         gotgctl.d32 = 0 ;
 432                         gotgctl.b.devhnpen = 1;
 433                         DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, gotgctl.d32, 0);
 434                 }
 435         } else {
 436                 hprt0_data_t hprt0;
 437                 DWC_PRINTF("SRP: Host mode\n");
 438
 439                 /* Turn on the port power bit. */
 440                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
 441                 hprt0.b.prtpwr = 1;
 442                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 443
 444                 /* Start the Connection timer. So a message can be displayed
 445                  * if connect does not occur within 10 seconds. */
 446                 cil_hcd_session_start(core_if);
 447         }
 448 #endif
 449
 450         /* Clear interrupt */
 451         gintsts.d32 = 0;
 452         gintsts.b.sessreqintr = 1;
 453         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
 454
 455         return 1;
 456 }
 457
 458 void w_wakeup_detected(void *data)
 459 {
 460         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *)data;
 461         /*
 462          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
 463          * so that OPT tests pass with all PHYs).
 464          */
 465         hprt0_data_t hprt0 = {.d32 = 0 };
 466 #if 0
 467         pcgcctl_data_t pcgcctl = {.d32 = 0 };
 468         /* Restart the Phy Clock */
 469         pcgcctl.b.stoppclk = 1;
 470         DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
 471         dwc_udelay(10);
 472 #endif //0
 473         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 474         DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
 475         dwc_mdelay(70);
 476         hprt0.b.prtres = 0;     /* Resume */
 477         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 478         DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
 479                     DWC_READ_REG32(core_if->host_if->hprt0));
 480
 481         cil_hcd_resume(core_if);
 482
 483         /** Change to L0 state*/
 484         core_if->lx_state = DWC_OTG_L0;
 485 }
 486
 487 /**
 488  * This interrupt indicates that the DWC_otg controller has detected a
 489  * resume or remote wakeup sequence. If the DWC_otg controller is in
 490  * low power mode, the handler must brings the controller out of low
 491  * power mode. The controller automatically begins resume
 492  * signaling. The handler schedules a time to stop resume signaling.
 493  */
 494 int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
 495 {
 496         gintsts_data_t gintsts;
 497
 498         DWC_DEBUGPL(DBG_ANY,
 499                     "++Resume and Remote Wakeup Detected Interrupt++\n");
 500
 501         DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state);
 502
 503         if (dwc_otg_is_device_mode(core_if)) {
 504                 dctl_data_t dctl = {.d32 = 0 };
 505                 DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
 506                             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
 507                                            dsts));
 508                 if (core_if->lx_state == DWC_OTG_L2) {
 509 #ifdef PARTIAL_POWER_DOWN
 510                         if (core_if->hwcfg4.b.power_optimiz) {
 511                                 pcgcctl_data_t power = {.d32 = 0 };
 512
 513                                 power.d32 = DWC_READ_REG32(core_if->pcgcctl);
 514                                 DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
 515                                             power.d32);
 516
 517                                 power.b.stoppclk = 0;
 518                                 DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
 519
 520                                 power.b.pwrclmp = 0;
 521                                 DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
 522
 523                                 power.b.rstpdwnmodule = 0;
 524                                 DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
 525                         }
 526 #endif
 527                         /* Clear the Remote Wakeup Signaling */
 528                         dctl.b.rmtwkupsig = 1;
 529                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
 530                                          dctl, dctl.d32, 0);
 531
 532                         DWC_SPINUNLOCK(core_if->lock);
 533                         if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
 534                                 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
 535                         }
 536                         DWC_SPINLOCK(core_if->lock);
 537                 } else {
 538                         glpmcfg_data_t lpmcfg;
 539                         pcgcctl_data_t pcgcctl = {.d32 = 0 };
 540
 541                         lpmcfg.d32 =
 542                             DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
 543                         lpmcfg.b.hird_thres &= (~(1 << 4));
 544                 lpmcfg.b.en_utmi_sleep = 0;
 545
 546                         /* Clear Enbl_L1Gating bit. */
 547                         pcgcctl.b.enbl_sleep_gating = 1;
 548                         DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,0);
 549
 550                         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
 551                                         lpmcfg.d32);
 552                 }
 553                 /** Change to L0 state*/
 554                 core_if->lx_state = DWC_OTG_L0;
 555         } else {
 556                 if (core_if->lx_state != DWC_OTG_L1) {
 557                         pcgcctl_data_t pcgcctl = {.d32 = 0 };
 558
 559                         /* Restart the Phy Clock */
 560                         pcgcctl.b.stoppclk = 1;
 561                         DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
 562                         DWC_TASK_SCHEDULE(core_if->wkp_tasklet);
 563                 } else {
 564                         /** Change to L0 state*/
 565                         core_if->lx_state = DWC_OTG_L0;
 566                 }
 567         }
 568
 569         /* Clear interrupt */
 570         gintsts.d32 = 0;
 571         gintsts.b.wkupintr = 1;
 572         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
 573
 574         return 1;
 575 }
 576
 577 /**
 578  * This interrupt indicates that the Wakeup Logic has detected a
 579  * Device disconnect.
 580  */
 581 static int32_t dwc_otg_handle_pwrdn_disconnect_intr(dwc_otg_core_if_t * core_if)
 582 {
 583         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 584         gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
 585         gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
 586
 587         DWC_PRINTF("%s called\n", __FUNCTION__);
 588
 589         if (!core_if->hibernation_suspend) {
 590                 DWC_PRINTF("Already exited from Hibernation\n");
 591                 return 1;
 592         }
 593
 594         /* Switch on the voltage to the core */
 595         gpwrdn.b.pwrdnswtch = 1;
 596         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 597         dwc_udelay(10);
 598
 599         /* Reset the core */
 600         gpwrdn.d32 = 0;
 601         gpwrdn.b.pwrdnrstn = 1;
 602         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 603         dwc_udelay(10);
 604
 605         /* Disable power clamps */
 606         gpwrdn.d32 = 0;
 607         gpwrdn.b.pwrdnclmp = 1;
 608         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 609
 610         /* Remove reset the core signal */
 611         gpwrdn.d32 = 0;
 612         gpwrdn.b.pwrdnrstn = 1;
 613         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 614         dwc_udelay(10);
 615
 616         /* Disable PMU interrupt */
 617         gpwrdn.d32 = 0;
 618         gpwrdn.b.pmuintsel = 1;
 619         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 620
 621         core_if->hibernation_suspend = 0;
 622
 623         /* Disable PMU */
 624         gpwrdn.d32 = 0;
 625         gpwrdn.b.pmuactv = 1;
 626         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 627         dwc_udelay(10);
 628
 629         if (gpwrdn_temp.b.idsts) {
 630                 core_if->op_state = B_PERIPHERAL;
 631                 dwc_otg_core_init(core_if);
 632                 dwc_otg_enable_global_interrupts(core_if);
 633                 cil_pcd_start(core_if);
 634         } else {
 635                 core_if->op_state = A_HOST;
 636                 dwc_otg_core_init(core_if);
 637                 dwc_otg_enable_global_interrupts(core_if);
 638                 cil_hcd_start(core_if);
 639         }
 640
 641         return 1;
 642 }
 643
 644 /**
 645  * This interrupt indicates that the Wakeup Logic has detected a
 646  * remote wakeup sequence.
 647  */
 648 static int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
 649 {
 650         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 651         DWC_DEBUGPL(DBG_ANY,
 652                     "++Powerdown Remote Wakeup Detected Interrupt++\n");
 653
 654         if (!core_if->hibernation_suspend) {
 655                 DWC_PRINTF("Already exited from Hibernation\n");
 656                 return 1;
 657         }
 658
 659         gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
 660         if (gpwrdn.b.idsts) {   // Device Mode
 661                 if ((core_if->power_down == 2)
 662                     && (core_if->hibernation_suspend == 1)) {
 663                         dwc_otg_device_hibernation_restore(core_if, 0, 0);
 664                 }
 665         } else {
 666                 if ((core_if->power_down == 2)
 667                     && (core_if->hibernation_suspend == 1)) {
 668                         dwc_otg_host_hibernation_restore(core_if, 1, 0);
 669                 }
 670         }
 671         return 1;
 672 }
 673
 674 static int32_t dwc_otg_handle_pwrdn_idsts_change(dwc_otg_device_t * otg_dev)
 675 {
 676         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 677         gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
 678         dwc_otg_core_if_t *core_if = otg_dev->core_if;
 679
 680         DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
 681         gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
 682         if (core_if->power_down == 2) {
 683                 if (!core_if->hibernation_suspend) {
 684                         DWC_PRINTF("Already exited from Hibernation\n");
 685                         return 1;
 686                 }
 687                 DWC_DEBUGPL(DBG_ANY, "Exit from hibernation on ID sts change\n");
 688                 /* Switch on the voltage to the core */
 689                 gpwrdn.b.pwrdnswtch = 1;
 690                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 691                 dwc_udelay(10);
 692
 693                 /* Reset the core */
 694                 gpwrdn.d32 = 0;
 695                 gpwrdn.b.pwrdnrstn = 1;
 696                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 697                 dwc_udelay(10);
 698
 699                 /* Disable power clamps */
 700                 gpwrdn.d32 = 0;
 701                 gpwrdn.b.pwrdnclmp = 1;
 702                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 703
 704                 /* Remove reset the core signal */
 705                 gpwrdn.d32 = 0;
 706                 gpwrdn.b.pwrdnrstn = 1;
 707                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 708                 dwc_udelay(10);
 709
 710                 /* Disable PMU interrupt */
 711                 gpwrdn.d32 = 0;
 712                 gpwrdn.b.pmuintsel = 1;
 713                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 714
 715                 /*Indicates that we are exiting from hibernation */
 716                 core_if->hibernation_suspend = 0;
 717
 718                 /* Disable PMU */
 719                 gpwrdn.d32 = 0;
 720                 gpwrdn.b.pmuactv = 1;
 721                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 722                 dwc_udelay(10);
 723
 724                 gpwrdn.d32 = core_if->gr_backup->gpwrdn_local;
 725                 if (gpwrdn.b.dis_vbus == 1) {
 726                         gpwrdn.d32 = 0;
 727                         gpwrdn.b.dis_vbus = 1;
 728                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 729                 }
 730
 731                 if (gpwrdn_temp.b.idsts) {
 732                         core_if->op_state = B_PERIPHERAL;
 733                         dwc_otg_core_init(core_if);
 734                         dwc_otg_enable_global_interrupts(core_if);
 735                         cil_pcd_start(core_if);
 736                 } else {
 737                         core_if->op_state = A_HOST;
 738                         dwc_otg_core_init(core_if);
 739                         dwc_otg_enable_global_interrupts(core_if);
 740                         cil_hcd_start(core_if);
 741                 }
 742         }
 743
 744         if (core_if->adp_enable) {
 745                 uint8_t is_host = 0;
 746                 DWC_SPINUNLOCK(core_if->lock);
 747                 /* Change the core_if's lock to hcd/pcd lock depend on mode? */
 748 #ifndef DWC_HOST_ONLY
 749                 if (gpwrdn_temp.b.idsts)
 750                         core_if->lock = otg_dev->pcd->lock;
 751 #endif
 752 #ifndef DWC_DEVICE_ONLY
 753                 if (!gpwrdn_temp.b.idsts) {
 754                         core_if->lock = otg_dev->hcd->lock;
 755                         is_host = 1;
 756                 }
 757 #endif
 758                 DWC_PRINTF("RESTART ADP\n");
 759                 if (core_if->adp.probe_enabled)
 760                         dwc_otg_adp_probe_stop(core_if);
 761                 if (core_if->adp.sense_enabled)
 762                         dwc_otg_adp_sense_stop(core_if);
 763                 if (core_if->adp.sense_timer_started)
 764                         DWC_TIMER_CANCEL(core_if->adp.sense_timer);
 765                 if (core_if->adp.vbuson_timer_started)
 766                         DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
 767                 core_if->adp.probe_timer_values[0] = -1;
 768                 core_if->adp.probe_timer_values[1] = -1;
 769                 core_if->adp.sense_timer_started = 0;
 770                 core_if->adp.vbuson_timer_started = 0;
 771                 core_if->adp.probe_counter = 0;
 772                 core_if->adp.gpwrdn = 0;
 773
 774                 /* Disable PMU and restart ADP */
 775                 gpwrdn_temp.d32 = 0;
 776                 gpwrdn_temp.b.pmuactv = 1;
 777                 gpwrdn_temp.b.pmuintsel = 1;
 778                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 779                 DWC_PRINTF("Check point 1\n");
 780                 dwc_mdelay(110);
 781                 dwc_otg_adp_start(core_if, is_host);
 782                 DWC_SPINLOCK(core_if->lock);
 783         }
 784
 785         return 1;
 786 }
 787
 788 static int32_t dwc_otg_handle_pwrdn_session_change(dwc_otg_core_if_t * core_if)
 789 {
 790         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 791         int32_t otg_cap_param = core_if->core_params->otg_cap;
 792         DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
 793
 794         gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
 795         if (core_if->power_down == 2) {
 796                 if (!core_if->hibernation_suspend) {
 797                         DWC_PRINTF("Already exited from Hibernation\n");
 798                         return 1;
 799                 }
 800
 801                 if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
 802                      otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) &&
 803                     gpwrdn.b.bsessvld == 0) {
 804                         /* Save gpwrdn register for further usage if stschng interrupt */
 805                         core_if->gr_backup->gpwrdn_local =
 806                             DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
 807                         /*Exit from ISR and wait for stschng interrupt with bsessvld = 1 */
 808                         return 1;
 809                 }
 810
 811                 /* Switch on the voltage to the core */
 812                 gpwrdn.d32 = 0;
 813                 gpwrdn.b.pwrdnswtch = 1;
 814                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 815                 dwc_udelay(10);
 816
 817                 /* Reset the core */
 818                 gpwrdn.d32 = 0;
 819                 gpwrdn.b.pwrdnrstn = 1;
 820                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 821                 dwc_udelay(10);
 822
 823                 /* Disable power clamps */
 824                 gpwrdn.d32 = 0;
 825                 gpwrdn.b.pwrdnclmp = 1;
 826                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 827
 828                 /* Remove reset the core signal */
 829                 gpwrdn.d32 = 0;
 830                 gpwrdn.b.pwrdnrstn = 1;
 831                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 832                 dwc_udelay(10);
 833
 834                 /* Disable PMU interrupt */
 835                 gpwrdn.d32 = 0;
 836                 gpwrdn.b.pmuintsel = 1;
 837                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 838                 dwc_udelay(10);
 839
 840                 /*Indicates that we are exiting from hibernation */
 841                 core_if->hibernation_suspend = 0;
 842
 843                 /* Disable PMU */
 844                 gpwrdn.d32 = 0;
 845                 gpwrdn.b.pmuactv = 1;
 846                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 847                 dwc_udelay(10);
 848
 849                 core_if->op_state = B_PERIPHERAL;
 850                 dwc_otg_core_init(core_if);
 851                 dwc_otg_enable_global_interrupts(core_if);
 852                 cil_pcd_start(core_if);
 853
 854                 if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
 855                     otg_cap_param == DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) {
 856                         /*
 857                          * Initiate SRP after initial ADP probe.
 858                          */
 859                         dwc_otg_initiate_srp(core_if);
 860                 }
 861         } else if (core_if->adp_enable){
 862                 dwc_otg_adp_probe_stop(core_if);
 863                 if (DWC_WORKQ_PENDING(core_if->wq_otg))
 864                         core_if->stop_adpprb = 1;
 865                 /* Disable Power Down Logic */
 866                 gpwrdn.d32 = 0;
 867                 gpwrdn.b.pmuintsel = 1;
 868                 gpwrdn.b.pmuactv = 1;
 869                 DWC_MODIFY_REG32(&core_if->core_global_regs->
 870                                  gpwrdn, gpwrdn.d32, 0);
 871
 872                 /*
 873                  * Initialize the Core for Device mode.
 874                  */
 875                 core_if->op_state = B_PERIPHERAL;
 876                 cil_pcd_start(core_if);
 877                 dwc_otg_enable_global_interrupts(core_if);
 878         }
 879
 880         return 1;
 881 }
 882
 883 /**
 884  * This interrupt indicates that the Wakeup Logic has detected a
 885  * status change either on IDDIG or BSessVld.
 886  */
 887 static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t * otg_dev)
 888 {
 889         int retval;
 890         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 891         gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
 892         dwc_otg_core_if_t *core_if = otg_dev->core_if;
 893
 894         DWC_PRINTF("%s called\n", __FUNCTION__);
 895
 896         if (core_if->power_down == 2) {
 897                 if (core_if->hibernation_suspend <= 0) {
 898                         DWC_PRINTF("Already exited from Hibernation\n");
 899                         return 1;
 900                 } else
 901                         gpwrdn_temp.d32 = core_if->gr_backup->gpwrdn_local;
 902
 903         } else {
 904                 gpwrdn_temp.d32 = core_if->adp.gpwrdn;
 905         }
 906
 907         gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
 908
 909         if (gpwrdn.b.idsts ^ gpwrdn_temp.b.idsts) {
 910                 retval = dwc_otg_handle_pwrdn_idsts_change(otg_dev);
 911         } else if (gpwrdn.b.bsessvld ^ gpwrdn_temp.b.bsessvld) {
 912                 retval = dwc_otg_handle_pwrdn_session_change(core_if);
 913         }
 914
 915         return retval;
 916 }
 917
 918 /**
 919  * This interrupt indicates that the Wakeup Logic has detected a
 920  * SRP.
 921  */
 922 static int32_t dwc_otg_handle_pwrdn_srp_intr(dwc_otg_core_if_t * core_if)
 923 {
 924         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 925
 926         DWC_PRINTF("%s called\n", __FUNCTION__);
 927
 928         if (!core_if->hibernation_suspend) {
 929                 DWC_PRINTF("Already exited from Hibernation\n");
 930                 return 1;
 931         }
 932 #ifdef DWC_DEV_SRPCAP
 933         if (core_if->pwron_timer_started) {
 934                 core_if->pwron_timer_started = 0;
 935                 DWC_TIMER_CANCEL(core_if->pwron_timer);
 936         }
 937 #endif
 938
 939         /* Switch on the voltage to the core */
 940         gpwrdn.b.pwrdnswtch = 1;
 941         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 942         dwc_udelay(10);
 943
 944         /* Reset the core */
 945         gpwrdn.d32 = 0;
 946         gpwrdn.b.pwrdnrstn = 1;
 947         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 948         dwc_udelay(10);
 949
 950         /* Disable power clamps */
 951         gpwrdn.d32 = 0;
 952         gpwrdn.b.pwrdnclmp = 1;
 953         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 954
 955         /* Remove reset the core signal */
 956         gpwrdn.d32 = 0;
 957         gpwrdn.b.pwrdnrstn = 1;
 958         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 959         dwc_udelay(10);
 960
 961         /* Disable PMU interrupt */
 962         gpwrdn.d32 = 0;
 963         gpwrdn.b.pmuintsel = 1;
 964         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 965
 966         /* Indicates that we are exiting from hibernation */
 967         core_if->hibernation_suspend = 0;
 968
 969         /* Disable PMU */
 970         gpwrdn.d32 = 0;
 971         gpwrdn.b.pmuactv = 1;
 972         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 973         dwc_udelay(10);
 974
 975         /* Programm Disable VBUS to 0 */
 976         gpwrdn.d32 = 0;
 977         gpwrdn.b.dis_vbus = 1;
 978         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 979
 980         /*Initialize the core as Host */
 981         core_if->op_state = A_HOST;
 982         dwc_otg_core_init(core_if);
 983         dwc_otg_enable_global_interrupts(core_if);
 984         cil_hcd_start(core_if);
 985
 986         return 1;
 987 }
 988
 989 /** This interrupt indicates that restore command after Hibernation
 990  * was completed by the core. */
 991 int32_t dwc_otg_handle_restore_done_intr(dwc_otg_core_if_t * core_if)
 992 {
 993         pcgcctl_data_t pcgcctl;
 994         DWC_DEBUGPL(DBG_ANY, "++Restore Done Interrupt++\n");
 995
 996         //TODO De-assert restore signal. 8.a
 997         pcgcctl.d32 = DWC_READ_REG32(core_if->pcgcctl);
 998         if (pcgcctl.b.restoremode == 1) {
 999                 gintmsk_data_t gintmsk = {.d32 = 0 };
1000                 /*
1001                  * If restore mode is Remote Wakeup,
1002                  * unmask Remote Wakeup interrupt.
1003                  */
1004                 gintmsk.b.wkupintr = 1;
1005                 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
1006                                  0, gintmsk.d32);
1007         }
1008
1009         return 1;
1010 }
1011
1012 /**
1013  * This interrupt indicates that a device has been disconnected from
1014  * the root port.
1015  */
1016 int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if)
1017 {
1018         gintsts_data_t gintsts;
1019
1020         DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
1021                     (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"),
1022                     op_state_str(core_if));
1023
1024 /** @todo Consolidate this if statement. */
1025 #ifndef DWC_HOST_ONLY
1026         if (core_if->op_state == B_HOST) {
1027                 /* If in device mode Disconnect and stop the HCD, then
1028                  * start the PCD. */
1029                 DWC_SPINUNLOCK(core_if->lock);
1030                 cil_hcd_disconnect(core_if);
1031                 cil_pcd_start(core_if);
1032                 DWC_SPINLOCK(core_if->lock);
1033                 core_if->op_state = B_PERIPHERAL;
1034         } else if (dwc_otg_is_device_mode(core_if)) {
1035                 gotgctl_data_t gotgctl = {.d32 = 0 };
1036                 gotgctl.d32 =
1037                     DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
1038                 if (gotgctl.b.hstsethnpen == 1) {
1039                         /* Do nothing, if HNP in process the OTG
1040                          * interrupt "Host Negotiation Detected"
1041                          * interrupt will do the mode switch.
1042                          */
1043                 } else if (gotgctl.b.devhnpen == 0) {
1044                         /* If in device mode Disconnect and stop the HCD, then
1045                          * start the PCD. */
1046                         DWC_SPINUNLOCK(core_if->lock);
1047                         cil_hcd_disconnect(core_if);
1048                         cil_pcd_start(core_if);
1049                         DWC_SPINLOCK(core_if->lock);
1050                         core_if->op_state = B_PERIPHERAL;
1051                 } else {
1052                         DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
1053                 }
1054         } else {
1055                 if (core_if->op_state == A_HOST) {
1056                         /* A-Cable still connected but device disconnected. */
1057                         cil_hcd_disconnect(core_if);
1058                         if (core_if->adp_enable) {
1059                                 gpwrdn_data_t gpwrdn = {.d32 = 0 };
1060                                 cil_hcd_stop(core_if);
1061                                 /* Enable Power Down Logic */
1062                                 gpwrdn.b.pmuintsel = 1;
1063                                 gpwrdn.b.pmuactv = 1;
1064                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
1065                                                  gpwrdn, 0, gpwrdn.d32);
1066                                 dwc_otg_adp_probe_start(core_if);
1067
1068                                 /* Power off the core */
1069                                 if (core_if->power_down == 2) {
1070                                         gpwrdn.d32 = 0;
1071                                         gpwrdn.b.pwrdnswtch = 1;
1072                                         DWC_MODIFY_REG32
1073                                             (&core_if->core_global_regs->gpwrdn,
1074                                              gpwrdn.d32, 0);
1075                                 }
1076                         }
1077                 }
1078         }
1079 #endif
1080         /* Change to L3(OFF) state */
1081         core_if->lx_state = DWC_OTG_L3;
1082
1083         gintsts.d32 = 0;
1084         gintsts.b.disconnect = 1;
1085         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
1086         return 1;
1087 }
1088
1089 /**
1090  * This interrupt indicates that SUSPEND state has been detected on
1091  * the USB.
1092  *
1093  * For HNP the USB Suspend interrupt signals the change from
1094  * "a_peripheral" to "a_host".
1095  *
1096  * When power management is enabled the core will be put in low power
1097  * mode.
1098  */
1099 int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if)
1100 {
1101         dsts_data_t dsts;
1102         gintsts_data_t gintsts;
1103         dcfg_data_t dcfg;
1104
1105         DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");
1106
1107         if ((core_if->otg_ver == 1) && (core_if->op_state == A_PERIPHERAL))
1108                 dwc_mdelay(200); //vahrama - WA - see BU's mail
1109
1110         if (dwc_otg_is_device_mode(core_if)) {
1111                 /* Check the Device status register to determine if the Suspend
1112                  * state is active. */
1113                 dsts.d32 =
1114                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
1115                 DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
1116                 DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
1117                             "HWCFG4.power Optimize=%d\n",
1118                             dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
1119
1120 #ifdef PARTIAL_POWER_DOWN
1121 /** @todo Add a module parameter for power management. */
1122
1123                 if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
1124                         pcgcctl_data_t power = {.d32 = 0 };
1125                         DWC_DEBUGPL(DBG_CIL, "suspend\n");
1126
1127                         power.b.pwrclmp = 1;
1128                         DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
1129
1130                         power.b.rstpdwnmodule = 1;
1131                         DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
1132
1133                         power.b.stoppclk = 1;
1134                         DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
1135
1136                 } else {
1137                         DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
1138                 }
1139 #endif
1140                 /* PCD callback for suspend. Release the lock inside of callback function */
1141                 cil_pcd_suspend(core_if);
1142                 if (core_if->power_down == 2)
1143                 {
1144                         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
1145                         DWC_DEBUGPL(DBG_ANY,"lx_state = %08x\n",core_if->lx_state);
1146                         DWC_DEBUGPL(DBG_ANY," device address = %08d\n",dcfg.b.devaddr);
1147
1148                         if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
1149                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
1150                                 gpwrdn_data_t gpwrdn = {.d32 = 0 };
1151                                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
1152
1153                                 /* Change to L2(suspend) state */
1154                                 core_if->lx_state = DWC_OTG_L2;
1155
1156                                 /* Clear interrupt in gintsts */
1157                                 gintsts.d32 = 0;
1158                                 gintsts.b.usbsuspend = 1;
1159                                 DWC_WRITE_REG32(&core_if->core_global_regs->
1160                                                 gintsts, gintsts.d32);
1161                                 DWC_PRINTF("Start of hibernation completed\n");
1162                                 dwc_otg_save_global_regs(core_if);
1163                                 dwc_otg_save_dev_regs(core_if);
1164
1165                                 gusbcfg.d32 =
1166                                     DWC_READ_REG32(&core_if->core_global_regs->
1167                                                    gusbcfg);
1168                                 if (gusbcfg.b.ulpi_utmi_sel == 1) {
1169                                         /* ULPI interface */
1170                                         /* Suspend the Phy Clock */
1171                                         pcgcctl.d32 = 0;
1172                                         pcgcctl.b.stoppclk = 1;
1173                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
1174                                                          pcgcctl.d32);
1175                                         dwc_udelay(10);
1176                                         gpwrdn.b.pmuactv = 1;
1177                                         DWC_MODIFY_REG32(&core_if->
1178                                                          core_global_regs->
1179                                                          gpwrdn, 0, gpwrdn.d32);
1180                                 } else {
1181                                         /* UTMI+ Interface */
1182                                         gpwrdn.b.pmuactv = 1;
1183                                         DWC_MODIFY_REG32(&core_if->
1184                                                          core_global_regs->
1185                                                          gpwrdn, 0, gpwrdn.d32);
1186                                         dwc_udelay(10);
1187                                         pcgcctl.b.stoppclk = 1;
1188                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
1189                                                          pcgcctl.d32);
1190                                         dwc_udelay(10);
1191                                 }
1192
1193                                 /* Set flag to indicate that we are in hibernation */
1194                                 core_if->hibernation_suspend = 1;
1195                                 /* Enable interrupts from wake up logic */
1196                                 gpwrdn.d32 = 0;
1197                                 gpwrdn.b.pmuintsel = 1;
1198                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
1199                                                  gpwrdn, 0, gpwrdn.d32);
1200                                 dwc_udelay(10);
1201
1202                                 /* Unmask device mode interrupts in GPWRDN */
1203                                 gpwrdn.d32 = 0;
1204                                 gpwrdn.b.rst_det_msk = 1;
1205                                 gpwrdn.b.lnstchng_msk = 1;
1206                                 gpwrdn.b.sts_chngint_msk = 1;
1207                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
1208                                                  gpwrdn, 0, gpwrdn.d32);
1209                                 dwc_udelay(10);
1210
1211                                 /* Enable Power Down Clamp */
1212                                 gpwrdn.d32 = 0;
1213                                 gpwrdn.b.pwrdnclmp = 1;
1214                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
1215                                                  gpwrdn, 0, gpwrdn.d32);
1216                                 dwc_udelay(10);
1217
1218                                 /* Switch off VDD */
1219                                 gpwrdn.d32 = 0;
1220                                 gpwrdn.b.pwrdnswtch = 1;
1221                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
1222                                                  gpwrdn, 0, gpwrdn.d32);
1223
1224                                 /* Save gpwrdn register for further usage if stschng interrupt */
1225                                 core_if->gr_backup->gpwrdn_local =
1226                                                         DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
1227                                 DWC_PRINTF("Hibernation completed\n");
1228
1229                                 return 1;
1230                         }
1231                 } else if (core_if->power_down == 3) {
1232                         pcgcctl_data_t pcgcctl = {.d32 = 0 };
1233                         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
1234                         DWC_DEBUGPL(DBG_ANY, "lx_state = %08x\n",core_if->lx_state);
1235                         DWC_DEBUGPL(DBG_ANY, " device address = %08d\n",dcfg.b.devaddr);
1236
1237                         if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
1238                                 DWC_DEBUGPL(DBG_ANY, "Start entering to extended hibernation\n");
1239                                 core_if->xhib = 1;
1240
1241                                 /* Clear interrupt in gintsts */
1242                                 gintsts.d32 = 0;
1243                                 gintsts.b.usbsuspend = 1;
1244                                 DWC_WRITE_REG32(&core_if->core_global_regs->
1245                                         gintsts, gintsts.d32);
1246
1247                                 dwc_otg_save_global_regs(core_if);
1248                                 dwc_otg_save_dev_regs(core_if);
1249
1250                                 /* Wait for 10 PHY clocks */
1251                                 dwc_udelay(10);
1252
1253                                 /* Program GPIO register while entering to xHib */
1254                                 DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x1);
1255
1256                                 pcgcctl.b.enbl_extnd_hiber = 1;
1257                                 DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
1258                                 DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
1259
1260                                 pcgcctl.d32 = 0;
1261                                 pcgcctl.b.extnd_hiber_pwrclmp = 1;
1262                                 DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
1263
1264                                 pcgcctl.d32 = 0;
1265                                 pcgcctl.b.extnd_hiber_switch = 1;
1266                                 core_if->gr_backup->xhib_gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
1267                                 core_if->gr_backup->xhib_pcgcctl = DWC_READ_REG32(core_if->pcgcctl) | pcgcctl.d32;
1268                                 DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
1269
1270                                 DWC_DEBUGPL(DBG_ANY, "Finished entering to extended hibernation\n");
1271
1272                                 return 1;
1273                         }
1274                 }
1275                 if ((core_if->otg_ver == 1) && (core_if->core_params->otg_cap == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE)) {
1276                         gotgctl_data_t gotgctl = {.d32 = 0 };
1277                         gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
1278                         if (gotgctl.b.devhnpen && core_if->otg_ver == 1){
1279                                 gotgctl_data_t gotgctl = {.d32 = 0 };
1280                                 dwc_mdelay(5);
1281                                 /**@todo Is the gotgctl.devhnpen cleared
1282                                  * by a USB Reset? */
1283                                 gotgctl.b.devhnpen = 1;
1284                                 gotgctl.b.hnpreq = 1;
1285                                 DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl,
1286                                                 gotgctl.d32);
1287                         }
1288                 }
1289         } else {
1290                 if (core_if->op_state == A_PERIPHERAL) {
1291                         DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n");
1292                         /* Clear the a_peripheral flag, back to a_host. */
1293                         DWC_SPINUNLOCK(core_if->lock);
1294                         cil_pcd_stop(core_if);
1295                         cil_hcd_start(core_if);
1296                         DWC_SPINLOCK(core_if->lock);
1297                         core_if->op_state = A_HOST;
1298                 }
1299         }
1300
1301         /* Change to L2(suspend) state */
1302         core_if->lx_state = DWC_OTG_L2;
1303
1304         /* Clear interrupt */
1305         gintsts.d32 = 0;
1306         gintsts.b.usbsuspend = 1;
1307         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
1308
1309         return 1;
1310 }
1311
1312 static int32_t dwc_otg_handle_xhib_exit_intr(dwc_otg_core_if_t * core_if)
1313 {
1314         gpwrdn_data_t gpwrdn = {.d32 = 0 };
1315         pcgcctl_data_t pcgcctl = {.d32 = 0 };
1316         gahbcfg_data_t gahbcfg = {.d32 = 0 };
1317
1318         dwc_udelay(10);
1319
1320         /* Program GPIO register while entering to xHib */
1321         DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x0);
1322
1323         pcgcctl.d32 = core_if->gr_backup->xhib_pcgcctl;
1324         pcgcctl.b.extnd_hiber_pwrclmp = 0;
1325         DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1326         dwc_udelay(10);
1327
1328         gpwrdn.d32 = core_if->gr_backup->xhib_gpwrdn;
1329         gpwrdn.b.restore = 1;
1330         DWC_WRITE_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32);
1331         dwc_udelay(10);
1332
1333         restore_lpm_i2c_regs(core_if);
1334
1335         pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
1336         pcgcctl.b.max_xcvrselect = 1;
1337         pcgcctl.b.ess_reg_restored = 0;
1338         pcgcctl.b.extnd_hiber_switch = 0;
1339         pcgcctl.b.extnd_hiber_pwrclmp = 0;
1340         pcgcctl.b.enbl_extnd_hiber = 1;
1341         DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1342
1343         gahbcfg.d32 = core_if->gr_backup->gahbcfg_local;
1344         gahbcfg.b.glblintrmsk = 1;
1345         DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
1346
1347         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1348         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0x1 << 16);
1349
1350         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
1351                         core_if->gr_backup->gusbcfg_local);
1352         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
1353                         core_if->dr_backup->dcfg);
1354
1355         pcgcctl.d32 = 0;
1356         pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
1357         pcgcctl.b.max_xcvrselect = 1;
1358         pcgcctl.d32 |= 0x608;
1359         DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1360         dwc_udelay(10);
1361
1362         pcgcctl.d32 = 0;
1363         pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
1364         pcgcctl.b.max_xcvrselect = 1;
1365         pcgcctl.b.ess_reg_restored = 1;
1366         pcgcctl.b.enbl_extnd_hiber = 1;
1367         pcgcctl.b.rstpdwnmodule = 1;
1368         pcgcctl.b.restoremode = 1;
1369         DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1370
1371         DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
1372
1373         return 1;
1374 }
1375
1376 #ifdef CONFIG_USB_DWC_OTG_LPM
1377 /**
1378  * This function hadles LPM transaction received interrupt.
1379  */
1380 static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if)
1381 {
1382         glpmcfg_data_t lpmcfg;
1383         gintsts_data_t gintsts;
1384
1385         if (!core_if->core_params->lpm_enable) {
1386                 DWC_PRINTF("Unexpected LPM interrupt\n");
1387         }
1388
1389         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
1390         DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32);
1391
1392         if (dwc_otg_is_host_mode(core_if)) {
1393                 cil_hcd_sleep(core_if);
1394         } else {
1395
1396                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
1397
1398                 lpmcfg.b.hird_thres |= (1 << 4);
1399                 lpmcfg.b.en_utmi_sleep = 1;
1400
1401                 pcgcctl.b.enbl_sleep_gating = 1;
1402                 DWC_MODIFY_REG32(core_if->pcgcctl,0,pcgcctl.d32);
1403
1404                 if(dwc_otg_get_param_besl_enable(core_if)) {
1405                         lpmcfg.b.en_besl = 1;
1406                 }
1407
1408                 DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
1409                                 lpmcfg.d32);
1410         }
1411
1412         /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */
1413         dwc_udelay(10);
1414         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
1415         if (lpmcfg.b.prt_sleep_sts) {
1416                 /* Save the current state */
1417                 core_if->lx_state = DWC_OTG_L1;
1418         }
1419
1420         /* Clear interrupt  */
1421         gintsts.d32 = 0;
1422         gintsts.b.lpmtranrcvd = 1;
1423         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
1424         return 1;
1425 }
1426 #endif /* CONFIG_USB_DWC_OTG_LPM */
1427
1428 /**
1429  * This function returns the Core Interrupt register.
1430  */
1431 static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if)
1432 {
1433         gahbcfg_data_t gahbcfg = {.d32 = 0 };
1434         gintsts_data_t gintsts;
1435         gintmsk_data_t gintmsk;
1436         gintmsk_data_t gintmsk_common = {.d32 = 0 };
1437         gintmsk_common.b.wkupintr = 1;
1438         gintmsk_common.b.sessreqintr = 1;
1439         gintmsk_common.b.conidstschng = 1;
1440         gintmsk_common.b.otgintr = 1;
1441         gintmsk_common.b.modemismatch = 1;
1442         gintmsk_common.b.disconnect = 1;
1443         gintmsk_common.b.usbsuspend = 1;
1444 #ifdef CONFIG_USB_DWC_OTG_LPM
1445         gintmsk_common.b.lpmtranrcvd = 1;
1446 #endif
1447         gintmsk_common.b.restoredone = 1;
1448         /** @todo: The port interrupt occurs while in device
1449          * mode. Added code to CIL to clear the interrupt for now!
1450          */
1451         gintmsk_common.b.portintr = 1;
1452
1453         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
1454         gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
1455         gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
1456
1457 #ifdef DEBUG
1458         /* if any common interrupts set */
1459         if (gintsts.d32 & gintmsk_common.d32) {
1460                 DWC_DEBUGPL(DBG_ANY, "gintsts=%08x  gintmsk=%08x\n",
1461                             gintsts.d32, gintmsk.d32);
1462         }
1463 #endif
1464         if (gahbcfg.b.glblintrmsk)
1465                 return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
1466         else
1467                 return 0;
1468
1469 }
1470
1471 /* MACRO for clearing interupt bits in GPWRDN register */
1472 #define CLEAR_GPWRDN_INTR(__core_if,__intr) \
1473 do { \
1474                 gpwrdn_data_t gpwrdn = {.d32=0}; \
1475                 gpwrdn.b.__intr = 1; \
1476                 DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \
1477                 0, gpwrdn.d32); \
1478 } while (0)
1479
1480 /**
1481  * Common interrupt handler.
1482  *
1483  * The common interrupts are those that occur in both Host and Device mode.
1484  * This handler handles the following interrupts:
1485  * - Mode Mismatch Interrupt
1486  * - Disconnect Interrupt
1487  * - OTG Interrupt
1488  * - Connector ID Status Change Interrupt
1489  * - Session Request Interrupt.
1490  * - Resume / Remote Wakeup Detected Interrupt.
1491  * - LPM Transaction Received Interrupt
1492  * - ADP Transaction Received Interrupt
1493  *
1494  */
1495 int32_t dwc_otg_handle_common_intr(void *dev)
1496 {
1497         int retval = 0;
1498         gintsts_data_t gintsts;
1499         gpwrdn_data_t gpwrdn = {.d32 = 0 };
1500         dwc_otg_device_t *otg_dev = dev;
1501         dwc_otg_core_if_t *core_if = otg_dev->core_if;
1502         gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
1503
1504         if (dwc_otg_check_haps_status(core_if) == -1 ) {
1505                 DWC_WARN("HAPS is disconnected");
1506                 return retval;
1507         }
1508
1509         if (dwc_otg_is_device_mode(core_if))
1510                 core_if->frame_num = dwc_otg_get_frame_number(core_if);
1511
1512         if (core_if->lock)
1513                 DWC_SPINLOCK(core_if->lock);
1514
1515         if (core_if->power_down == 3 && core_if->xhib == 1) {
1516                 DWC_DEBUGPL(DBG_ANY, "Exiting from xHIB state\n");
1517                 retval |= dwc_otg_handle_xhib_exit_intr(core_if);
1518                 core_if->xhib = 2;
1519                 if (core_if->lock)
1520                         DWC_SPINUNLOCK(core_if->lock);
1521
1522                 return retval;
1523         }
1524
1525         if (core_if->hibernation_suspend <= 0) {
1526                 gintsts.d32 = dwc_otg_read_common_intr(core_if);
1527
1528                 if (gintsts.b.modemismatch) {
1529                         retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
1530                 }
1531                 if (gintsts.b.otgintr) {
1532                         retval |= dwc_otg_handle_otg_intr(core_if);
1533                 }
1534                 if (gintsts.b.conidstschng) {
1535                         retval |=
1536                             dwc_otg_handle_conn_id_status_change_intr(core_if);
1537                 }
1538                 if (gintsts.b.disconnect) {
1539                         retval |= dwc_otg_handle_disconnect_intr(core_if);
1540                 }
1541                 if (gintsts.b.sessreqintr) {
1542                         retval |= dwc_otg_handle_session_req_intr(core_if);
1543                 }
1544                 if (gintsts.b.wkupintr) {
1545                         retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
1546                 }
1547                 if (gintsts.b.usbsuspend) {
1548                         retval |= dwc_otg_handle_usb_suspend_intr(core_if);
1549                 }
1550 #ifdef CONFIG_USB_DWC_OTG_LPM
1551                 if (gintsts.b.lpmtranrcvd) {
1552                         retval |= dwc_otg_handle_lpm_intr(core_if);
1553                 }
1554 #endif
1555                 if (gintsts.b.restoredone) {
1556                         gintsts.d32 = 0;
1557                         if (core_if->power_down == 2)
1558                                 core_if->hibernation_suspend = -1;
1559                         else if (core_if->power_down == 3 && core_if->xhib == 2) {
1560                                 gpwrdn_data_t gpwrdn = {.d32 = 0 };
1561                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
1562                                 dctl_data_t dctl = {.d32 = 0 };
1563
1564                                 DWC_WRITE_REG32(&core_if->core_global_regs->
1565                                                 gintsts, 0xFFFFFFFF);
1566
1567                                 DWC_DEBUGPL(DBG_ANY,
1568                                             "RESTORE DONE generated\n");
1569
1570                                 gpwrdn.b.restore = 1;
1571                                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
1572                                 dwc_udelay(10);
1573
1574                                 pcgcctl.b.rstpdwnmodule = 1;
1575                                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
1576
1577                                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, core_if->gr_backup->gusbcfg_local);
1578                                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, core_if->dr_backup->dcfg);
1579                                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, core_if->dr_backup->dctl);
1580                                 dwc_udelay(50);
1581
1582                                 dctl.b.pwronprgdone = 1;
1583                                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
1584                                 dwc_udelay(10);
1585
1586                                 dwc_otg_restore_global_regs(core_if);
1587                                 dwc_otg_restore_dev_regs(core_if, 0);
1588
1589                                 dctl.d32 = 0;
1590                                 dctl.b.pwronprgdone = 1;
1591                                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
1592                                 dwc_udelay(10);
1593
1594                                 pcgcctl.d32 = 0;
1595                                 pcgcctl.b.enbl_extnd_hiber = 1;
1596                                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
1597
1598                                 /* The core will be in ON STATE */
1599                                 core_if->lx_state = DWC_OTG_L0;
1600                                 core_if->xhib = 0;
1601
1602                                 DWC_SPINUNLOCK(core_if->lock);
1603                                 if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
1604                                         core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
1605                                 }
1606                                 DWC_SPINLOCK(core_if->lock);
1607
1608                         }
1609
1610                         gintsts.b.restoredone = 1;
1611                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
1612                         DWC_PRINTF(" --Restore done interrupt received-- \n");
1613                         retval |= 1;
1614                 }
1615                 if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
1616                         /* The port interrupt occurs while in device mode with HPRT0
1617                          * Port Enable/Disable.
1618                          */
1619                         gintsts.d32 = 0;
1620                         gintsts.b.portintr = 1;
1621                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
1622                         retval |= 1;
1623
1624                 }
1625         } else {
1626                 DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32);
1627
1628                 if (gpwrdn.b.disconn_det && gpwrdn.b.disconn_det_msk) {
1629                         CLEAR_GPWRDN_INTR(core_if, disconn_det);
1630                         if (gpwrdn.b.linestate == 0) {
1631                                 dwc_otg_handle_pwrdn_disconnect_intr(core_if);
1632                         } else {
1633                                 DWC_PRINTF("Disconnect detected while linestate is not 0\n");
1634                         }
1635
1636                         retval |= 1;
1637                 }
1638                 if (gpwrdn.b.lnstschng && gpwrdn.b.lnstchng_msk) {
1639                         CLEAR_GPWRDN_INTR(core_if, lnstschng);
1640                         /* remote wakeup from hibernation */
1641                         if (gpwrdn.b.linestate == 2 || gpwrdn.b.linestate == 1) {
1642                                 dwc_otg_handle_pwrdn_wakeup_detected_intr(core_if);
1643                         } else {
1644                                 DWC_PRINTF("gpwrdn.linestate = %d\n", gpwrdn.b.linestate);
1645                         }
1646                         retval |= 1;
1647                 }
1648                 if (gpwrdn.b.rst_det && gpwrdn.b.rst_det_msk) {
1649                         CLEAR_GPWRDN_INTR(core_if, rst_det);
1650                         if (gpwrdn.b.linestate == 0) {
1651                                 DWC_PRINTF("Reset detected\n");
1652                                 retval |= dwc_otg_device_hibernation_restore(core_if, 0, 1);
1653                         }
1654                 }
1655                 if (gpwrdn.b.srp_det && gpwrdn.b.srp_det_msk) {
1656                         CLEAR_GPWRDN_INTR(core_if, srp_det);
1657                         dwc_otg_handle_pwrdn_srp_intr(core_if);
1658                         retval |= 1;
1659                 }
1660         }
1661         /* Handle ADP interrupt here */
1662         if (gpwrdn.b.adp_int) {
1663                 DWC_PRINTF("ADP interrupt\n");
1664                 CLEAR_GPWRDN_INTR(core_if, adp_int);
1665                 dwc_otg_adp_handle_intr(core_if);
1666                 retval |= 1;
1667         }
1668         if (gpwrdn.b.sts_chngint && gpwrdn.b.sts_chngint_msk) {
1669                 DWC_PRINTF("STS CHNG interrupt asserted\n");
1670                 CLEAR_GPWRDN_INTR(core_if, sts_chngint);
1671                 dwc_otg_handle_pwrdn_stschng_intr(otg_dev);
1672
1673                 retval |= 1;
1674         }
1675         if (core_if->lock)
1676                 DWC_SPINUNLOCK(core_if->lock);
1677
1678         return retval;
1679 }