1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t *g_otgdev;
73 extern int pcd_init(struct platform_device *_dev);
74 extern int otg20_hcd_init(struct platform_device *_dev);
75 extern int host20_hcd_init(struct platform_device *_dev);
76 extern int pcd_remove(struct platform_device *_dev);
77 extern void hcd_remove(struct platform_device *_dev);
78 extern void dwc_otg_adp_start(dwc_otg_core_if_t *core_if, uint8_t is_host);
81 #ifdef CONFIG_RK_USB_UART
82 static u32 usb_to_uart_status;
84 /*-------------------------------------------------------------------------*/
85 /* Encapsulate the module parameter settings */
87 struct dwc_otg_driver_module_params {
91 int32_t dma_desc_enable;
92 int32_t dma_burst_size;
94 int32_t host_support_fs_ls_low_power;
95 int32_t host_ls_low_power_phy_clk;
96 int32_t enable_dynamic_fifo;
97 int32_t data_fifo_size;
98 int32_t dev_rx_fifo_size;
99 int32_t dev_nperio_tx_fifo_size;
100 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
101 int32_t host_rx_fifo_size;
102 int32_t host_nperio_tx_fifo_size;
103 int32_t host_perio_tx_fifo_size;
104 int32_t max_transfer_size;
105 int32_t max_packet_count;
106 int32_t host_channels;
107 int32_t dev_endpoints;
109 int32_t phy_utmi_width;
110 int32_t phy_ulpi_ddr;
111 int32_t phy_ulpi_ext_vbus;
115 int32_t en_multiple_tx_fifo;
116 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
118 uint32_t tx_thr_length;
119 uint32_t rx_thr_length;
124 int32_t baseline_besl;
127 int32_t ahb_thr_ratio;
137 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
139 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
141 .dma_desc_enable = 0,
142 .dma_burst_size = -1,
144 .host_support_fs_ls_low_power = -1,
145 .host_ls_low_power_phy_clk = -1,
146 .enable_dynamic_fifo = 1,
147 .data_fifo_size = -1,
148 .dev_rx_fifo_size = 0x120,
149 .dev_nperio_tx_fifo_size = 0x10,
150 .dev_perio_tx_fifo_size = {
151 /* dev_perio_tx_fifo_size_1 */
169 .host_rx_fifo_size = -1,
170 .host_nperio_tx_fifo_size = -1,
171 .host_perio_tx_fifo_size = -1,
172 .max_transfer_size = -1,
173 .max_packet_count = -1,
177 .phy_utmi_width = -1,
179 .phy_ulpi_ext_vbus = -1,
183 .en_multiple_tx_fifo = -1,
184 .dev_tx_fifo_size = {
185 /* dev_tx_fifo_size */
223 #ifdef CONFIG_USB20_HOST
224 static struct dwc_otg_driver_module_params dwc_host_module_params = {
226 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
228 .dma_desc_enable = 0,
229 .dma_burst_size = -1,
231 .host_support_fs_ls_low_power = -1,
232 .host_ls_low_power_phy_clk = -1,
233 .enable_dynamic_fifo = -1,
234 .data_fifo_size = -1,
235 .dev_rx_fifo_size = -1,
236 .dev_nperio_tx_fifo_size = -1,
237 .dev_perio_tx_fifo_size = {
238 /* dev_perio_tx_fifo_size_1 */
256 .host_rx_fifo_size = -1,
257 .host_nperio_tx_fifo_size = -1,
258 .host_perio_tx_fifo_size = -1,
259 .max_transfer_size = -1,
260 .max_packet_count = -1,
264 .phy_utmi_width = -1,
266 .phy_ulpi_ext_vbus = -1,
270 .en_multiple_tx_fifo = -1,
271 .dev_tx_fifo_size = {
272 /* dev_tx_fifo_size */
312 * This function shows the Driver Version.
314 static ssize_t version_show(struct device_driver *dev, char *buf)
316 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
320 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
323 * Global Debug Level Mask.
325 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
328 * This function shows the driver Debug Level.
330 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
332 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
336 * This function stores the driver Debug Level.
338 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
341 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
345 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
348 extern void hcd_start(dwc_otg_core_if_t *core_if);
349 extern struct usb_hub *g_dwc_otg_root_hub20;
350 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
352 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
354 dwc_otg_device_t *otg_dev = core_if->otg_dev;
355 dctl_data_t dctl = {.d32 = 0 };
358 if (core_if->op_state == A_HOST) {
359 printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
362 core_if->op_state = A_HOST;
364 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
365 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
366 dctl.b.sftdiscon = 1;
367 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
369 local_irq_save(flags);
370 cil_pcd_stop(core_if);
372 * Initialize the Core for Host mode.
375 dwc_otg_core_init(core_if);
376 dwc_otg_enable_global_interrupts(core_if);
377 cil_hcd_start(core_if);
378 local_irq_restore(flags);
381 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
383 dwc_otg_device_t *otg_dev = core_if->otg_dev;
386 local_irq_save(flags);
388 if (core_if->op_state == B_PERIPHERAL) {
390 ("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
393 core_if->op_state = B_PERIPHERAL;
394 cil_hcd_stop(core_if);
395 /* dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20); */
396 otg_dev->pcd->phy_suspend = 1;
397 otg_dev->pcd->vbus_status = 0;
398 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
400 /* Reset the Controller */
401 dwc_otg_core_reset(core_if);
403 dwc_otg_core_init(core_if);
404 dwc_otg_disable_global_interrupts(core_if);
405 cil_pcd_start(core_if);
407 local_irq_restore(flags);
410 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
412 dwc_otg_device_t *otg_dev = g_otgdev;
413 dwc_otg_core_if_t *core_if = otg_dev->core_if;
415 return sprintf(buf, "%d\n", core_if->usb_mode);
418 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
421 int new_mode = simple_strtoul(buf, NULL, 16);
422 dwc_otg_device_t *otg_dev = g_otgdev;
423 dwc_otg_core_if_t *core_if;
424 struct dwc_otg_platform_data *pldata;
429 core_if = otg_dev->core_if;
430 pldata = otg_dev->pldata;
432 DWC_PRINTF("%s %d->%d\n", __func__, core_if->usb_mode, new_mode);
434 if (core_if->usb_mode == new_mode) {
438 if (pldata->phy_status == USB_PHY_SUSPEND) {
439 pldata->clock_enable(pldata, 1);
440 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
444 case USB_MODE_FORCE_HOST:
445 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
447 core_if->usb_mode = new_mode;
448 dwc_otg_force_host(core_if);
449 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
450 core_if->usb_mode = new_mode;
451 if (dwc_otg_is_host_mode(core_if))
452 dwc_otg_set_force_mode(core_if, new_mode);
454 dwc_otg_force_host(core_if);
458 case USB_MODE_FORCE_DEVICE:
459 if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
460 core_if->usb_mode = new_mode;
461 dwc_otg_force_device(core_if);
462 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
463 core_if->usb_mode = new_mode;
464 if (dwc_otg_is_device_mode(core_if))
465 dwc_otg_set_force_mode(core_if, new_mode);
467 dwc_otg_force_device(core_if);
471 case USB_MODE_NORMAL:
472 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
473 core_if->usb_mode = new_mode;
474 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
475 dwc_otg_set_force_mode(core_if, new_mode);
477 if (dwc_otg_is_host_mode(core_if)) {
478 dwc_otg_force_host(core_if);
480 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
482 } else if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
483 core_if->usb_mode = new_mode;
484 dwc_otg_set_force_mode(core_if, new_mode);
486 if (dwc_otg_is_device_mode(core_if)) {
487 dwc_otg_force_device(core_if);
498 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show,
499 force_usb_mode_store);
501 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
504 dwc_otg_device_t *otg_dev = g_otgdev;
505 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
506 return sprintf(_buf, "%d\n", _pcd->conn_en);
510 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv,
511 const char *_buf, size_t _count)
513 int enable = simple_strtoul(_buf, NULL, 10);
514 dwc_otg_device_t *otg_dev = g_otgdev;
515 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
516 DWC_PRINTF("%s %d->%d\n", __func__, _pcd->conn_en, enable);
518 _pcd->conn_en = enable;
522 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO | S_IWUSR, dwc_otg_conn_en_show,
523 dwc_otg_conn_en_store);
525 /* used for product vbus power control, SDK not need.
526 * If dwc_otg is host mode, enable vbus power.
527 * If dwc_otg is device mode, disable vbus power.
528 * return 1 - host mode, 0 - device mode.
530 int dwc_otg_usb_state(void)
532 dwc_otg_device_t *otg_dev = g_otgdev;
535 /* op_state is A_HOST */
536 if (1 == otg_dev->core_if->op_state)
538 /* op_state is B_PERIPHERAL */
539 else if (4 == otg_dev->core_if->op_state)
544 DWC_WARN("g_otgdev is NULL, maybe otg probe is failed!\n");
548 EXPORT_SYMBOL(dwc_otg_usb_state);
550 static ssize_t dwc_otg_op_state_show(struct device_driver *_drv, char *_buf)
552 dwc_otg_device_t *otg_dev = g_otgdev;
555 return sprintf(_buf, "%d\n", otg_dev->core_if->op_state);
557 return sprintf(_buf, "%d\n", 0);
560 static DRIVER_ATTR(op_state, S_IRUGO, dwc_otg_op_state_show, NULL);
562 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
564 dwc_otg_device_t *otg_dev = g_otgdev;
565 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
566 return sprintf(_buf, "%d\n", _pcd->vbus_status);
569 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
572 * This function is called during module intialization
573 * to pass module parameters to the DWC_OTG CORE.
575 static int set_parameters(dwc_otg_core_if_t *core_if,
576 struct dwc_otg_driver_module_params module_params)
581 if (module_params.otg_cap != -1) {
583 dwc_otg_set_param_otg_cap(core_if, module_params.otg_cap);
585 if (module_params.dma_enable != -1) {
587 dwc_otg_set_param_dma_enable(core_if,
588 module_params.dma_enable);
590 if (module_params.dma_desc_enable != -1) {
592 dwc_otg_set_param_dma_desc_enable(core_if,
593 module_params.dma_desc_enable);
595 if (module_params.opt != -1) {
596 retval += dwc_otg_set_param_opt(core_if, module_params.opt);
598 if (module_params.dma_burst_size != -1) {
600 dwc_otg_set_param_dma_burst_size(core_if,
601 module_params.dma_burst_size);
603 if (module_params.host_support_fs_ls_low_power != -1) {
605 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
606 module_params.host_support_fs_ls_low_power);
608 if (module_params.enable_dynamic_fifo != -1) {
610 dwc_otg_set_param_enable_dynamic_fifo(core_if,
611 module_params.enable_dynamic_fifo);
613 if (module_params.data_fifo_size != -1) {
615 dwc_otg_set_param_data_fifo_size(core_if,
616 module_params.data_fifo_size);
618 if (module_params.dev_rx_fifo_size != -1) {
620 dwc_otg_set_param_dev_rx_fifo_size(core_if,
621 module_params.dev_rx_fifo_size);
623 if (module_params.dev_nperio_tx_fifo_size != -1) {
625 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
626 module_params.dev_nperio_tx_fifo_size);
628 if (module_params.host_rx_fifo_size != -1) {
630 dwc_otg_set_param_host_rx_fifo_size(core_if,
634 if (module_params.host_nperio_tx_fifo_size != -1) {
636 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
637 module_params.host_nperio_tx_fifo_size);
639 if (module_params.host_perio_tx_fifo_size != -1) {
641 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
642 module_params.host_perio_tx_fifo_size);
644 if (module_params.max_transfer_size != -1) {
646 dwc_otg_set_param_max_transfer_size(core_if,
647 module_params.max_transfer_size);
649 if (module_params.max_packet_count != -1) {
651 dwc_otg_set_param_max_packet_count(core_if,
652 module_params.max_packet_count);
654 if (module_params.host_channels != -1) {
656 dwc_otg_set_param_host_channels(core_if,
657 module_params.host_channels);
659 if (module_params.dev_endpoints != -1) {
661 dwc_otg_set_param_dev_endpoints(core_if,
662 module_params.dev_endpoints);
664 if (module_params.phy_type != -1) {
666 dwc_otg_set_param_phy_type(core_if, module_params.phy_type);
668 if (module_params.speed != -1) {
669 retval += dwc_otg_set_param_speed(core_if, module_params.speed);
671 if (module_params.host_ls_low_power_phy_clk != -1) {
673 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
674 module_params.host_ls_low_power_phy_clk);
676 if (module_params.phy_ulpi_ddr != -1) {
678 dwc_otg_set_param_phy_ulpi_ddr(core_if,
679 module_params.phy_ulpi_ddr);
681 if (module_params.phy_ulpi_ext_vbus != -1) {
683 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
684 module_params.phy_ulpi_ext_vbus);
686 if (module_params.phy_utmi_width != -1) {
688 dwc_otg_set_param_phy_utmi_width(core_if,
689 module_params.phy_utmi_width);
691 if (module_params.ulpi_fs_ls != -1) {
693 dwc_otg_set_param_ulpi_fs_ls(core_if,
694 module_params.ulpi_fs_ls);
696 if (module_params.ts_dline != -1) {
698 dwc_otg_set_param_ts_dline(core_if, module_params.ts_dline);
700 if (module_params.i2c_enable != -1) {
702 dwc_otg_set_param_i2c_enable(core_if,
703 module_params.i2c_enable);
705 if (module_params.en_multiple_tx_fifo != -1) {
707 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
708 module_params.en_multiple_tx_fifo);
710 for (i = 0; i < 15; i++) {
711 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
713 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
714 module_params.dev_perio_tx_fifo_size
719 for (i = 0; i < 15; i++) {
720 if (module_params.dev_tx_fifo_size[i] != -1) {
721 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
722 module_params.dev_tx_fifo_size
726 if (module_params.thr_ctl != -1) {
728 dwc_otg_set_param_thr_ctl(core_if, module_params.thr_ctl);
730 if (module_params.mpi_enable != -1) {
732 dwc_otg_set_param_mpi_enable(core_if,
733 module_params.mpi_enable);
735 if (module_params.pti_enable != -1) {
737 dwc_otg_set_param_pti_enable(core_if,
738 module_params.pti_enable);
740 if (module_params.lpm_enable != -1) {
742 dwc_otg_set_param_lpm_enable(core_if,
743 module_params.lpm_enable);
745 if (module_params.besl_enable != -1) {
747 dwc_otg_set_param_besl_enable(core_if,
748 module_params.besl_enable);
750 if (module_params.baseline_besl != -1) {
752 dwc_otg_set_param_baseline_besl(core_if,
753 module_params.baseline_besl);
755 if (module_params.deep_besl != -1) {
757 dwc_otg_set_param_deep_besl(core_if,
758 module_params.deep_besl);
760 if (module_params.ic_usb_cap != -1) {
762 dwc_otg_set_param_ic_usb_cap(core_if,
763 module_params.ic_usb_cap);
765 if (module_params.tx_thr_length != -1) {
767 dwc_otg_set_param_tx_thr_length(core_if,
771 if (module_params.rx_thr_length != -1) {
773 dwc_otg_set_param_rx_thr_length(core_if,
774 module_params.rx_thr_length);
776 if (module_params.ahb_thr_ratio != -1) {
778 dwc_otg_set_param_ahb_thr_ratio(core_if,
782 if (module_params.power_down != -1) {
784 dwc_otg_set_param_power_down(core_if,
785 module_params.power_down);
787 if (module_params.reload_ctl != -1) {
789 dwc_otg_set_param_reload_ctl(core_if,
790 module_params.reload_ctl);
793 if (module_params.dev_out_nak != -1) {
795 dwc_otg_set_param_dev_out_nak(core_if,
796 module_params.dev_out_nak);
799 if (module_params.cont_on_bna != -1) {
801 dwc_otg_set_param_cont_on_bna(core_if,
802 module_params.cont_on_bna);
805 if (module_params.ahb_single != -1) {
807 dwc_otg_set_param_ahb_single(core_if,
808 module_params.ahb_single);
811 if (module_params.otg_ver != -1) {
813 dwc_otg_set_param_otg_ver(core_if, module_params.otg_ver);
815 if (module_params.adp_enable != -1) {
817 dwc_otg_set_param_adp_enable(core_if,
818 module_params.adp_enable);
824 * This function is the top level interrupt handler for the Common
825 * (Device and host modes) interrupts.
827 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
829 int32_t retval = IRQ_NONE;
831 retval = dwc_otg_handle_common_intr(dev);
833 /* S3C2410X_CLEAR_EINTPEND(); */
835 return IRQ_RETVAL(retval);
838 #ifdef CONFIG_USB20_HOST
840 * This function is called when a lm_device is unregistered with the
841 * dwc_otg_driver. This happens, for example, when the rmmod command is
842 * executed. The device may or may not be electrically present. If it is
843 * present, the driver stops device processing. Any resources used on behalf
844 * of this device are freed.
848 static int host20_driver_remove(struct platform_device *_dev)
851 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
852 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
855 /* Memory allocation for the dwc_otg_device failed. */
856 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
859 #ifndef DWC_DEVICE_ONLY
863 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
868 #ifndef DWC_HOST_ONLY
872 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
880 if (otg_dev->common_irq_installed) {
881 /* free_irq(_dev->irq, otg_dev); */
882 free_irq(platform_get_irq(_dev, 0), otg_dev);
884 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
889 if (otg_dev->core_if) {
890 dwc_otg_cil_remove(otg_dev->core_if);
892 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
897 * Remove the device attributes
899 dwc_otg_attr_remove(_dev);
904 if (otg_dev->os_dep.base) {
905 iounmap(otg_dev->os_dep.base);
910 * Clear the drvdata pointer.
913 dwc_set_device_platform_data(_dev, 0);
918 static const struct of_device_id usb20_host_of_match[] = {
921 .compatible = "rockchip,rk3188_usb20_host",
922 .data = &usb20host_pdata_rk3188,
925 .compatible = "rockchip,rk3288_usb20_host",
926 .data = &usb20host_pdata_rk3288,
929 .compatible = "rockchip,rk3036_usb20_host",
930 .data = &usb20host_pdata_rk3036,
933 .compatible = "rockchip,rk3126_usb20_host",
934 .data = &usb20host_pdata_rk3126,
940 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
943 * This function is called when an lm_device is bound to a
944 * dwc_otg_driver. It creates the driver components required to
945 * control the device (CIL, HCD, and PCD) and it initializes the
946 * device. The driver components are stored in a dwc_otg_device
947 * structure. A reference to the dwc_otg_device is saved in the
948 * lm_device. This allows the driver to access the dwc_otg_device
949 * structure on subsequent calls to driver methods for this device.
951 * @param _dev Bus device
953 static int host20_driver_probe(struct platform_device *_dev)
957 struct resource *res_base;
958 dwc_otg_device_t *dwc_otg_device;
959 struct device *dev = &_dev->dev;
960 struct device_node *node = _dev->dev.of_node;
961 struct dwc_otg_platform_data *pldata;
962 const struct of_device_id *match =
963 of_match_device(of_match_ptr(usb20_host_of_match), &_dev->dev);
965 if (match && match->data) {
966 pldata = (void *)match->data;
969 dev_err(dev, "usb20otg match failed\n");
974 dev_err(dev, "device node not found\n");
981 if (pldata->clock_init) {
982 pldata->clock_init(pldata);
983 pldata->clock_enable(pldata, 1);
986 if (pldata->phy_suspend)
987 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
989 if (pldata->soft_reset)
990 pldata->soft_reset(pldata, RST_POR);
992 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
994 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
996 if (!dwc_otg_device) {
997 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1002 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1003 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1006 * Map the DWC_otg Core memory into virtual address space.
1009 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1011 if (!dwc_otg_device->os_dep.base) {
1012 dev_err(&_dev->dev, "ioremap() failed\n");
1013 DWC_FREE(dwc_otg_device);
1017 dev_dbg(&_dev->dev, "base=0x%p\n", dwc_otg_device->os_dep.base);
1019 /* Set device flags indicating whether the HCD supports DMA. */
1020 if (!_dev->dev.dma_mask)
1021 _dev->dev.dma_mask = &_dev->dev.coherent_dma_mask;
1022 retval = dma_set_coherent_mask(&_dev->dev, DMA_BIT_MASK(32));
1027 * Initialize driver data to point to the global DWC_otg
1031 dwc_set_device_platform_data(_dev, dwc_otg_device);
1032 pldata->privdata = dwc_otg_device;
1033 dwc_otg_device->pldata = (void *)pldata;
1035 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1037 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1039 if (!dwc_otg_device->core_if) {
1040 dev_err(&_dev->dev, "CIL initialization failed!\n");
1045 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1048 * Attempt to ensure this device is really a DWC_otg Controller.
1049 * Read and verify the SNPSID register contents. The value should be
1050 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1051 * as in "OTG version 2.XX" or "OTG version 3.XX".
1054 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1056 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1058 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1059 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1065 * Validate parameter values.
1067 if (set_parameters(dwc_otg_device->core_if, dwc_host_module_params)) {
1073 * Create Device Attributes in sysfs
1075 dwc_otg_attr_create(_dev);
1078 * Disable the global interrupt until all the interrupt
1079 * handlers are installed.
1081 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1084 * Install the interrupt handler for the common interrupts before
1085 * enabling common interrupts in core_init below.
1087 irq = platform_get_irq(_dev, 0);
1088 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1089 retval = request_irq(irq, dwc_otg_common_irq,
1090 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1092 DWC_ERROR("request of irq%d failed\n", irq);
1096 dwc_otg_device->common_irq_installed = 1;
1100 * Initialize the DWC_otg core.
1101 * In order to reduce the time of initialization,
1102 * we do core soft reset after connection detected.
1104 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1107 * Initialize the HCD
1109 retval = host20_hcd_init(_dev);
1111 DWC_ERROR("hcd_init failed\n");
1112 dwc_otg_device->hcd = NULL;
1116 clk_set_rate(pldata->phyclk_480m, 480000000);
1118 * Enable the global interrupt after all the interrupt
1119 * handlers are installed if there is no ADP support else
1120 * perform initial actions required for Internal ADP logic.
1122 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1123 if (pldata->phy_status == USB_PHY_ENABLED) {
1124 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1126 pldata->clock_enable(pldata, 0);
1128 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1130 dwc_otg_adp_start(dwc_otg_device->core_if,
1131 dwc_otg_is_host_mode(dwc_otg_device->
1137 host20_driver_remove(_dev);
1139 if (pldata->clock_enable)
1140 pldata->clock_enable(pldata, 0);
1146 static int dwc_otg_driver_suspend(struct platform_device *_dev,
1152 static int dwc_otg_driver_resume(struct platform_device *_dev)
1157 static void dwc_otg_driver_shutdown(struct platform_device *_dev)
1159 struct device *dev = &_dev->dev;
1160 dwc_otg_device_t *otg_dev = dev->platform_data;
1161 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1162 struct dwc_otg_platform_data *pldata = otg_dev->pldata;
1163 dctl_data_t dctl = {.d32 = 0 };
1164 dwc_otg_pcd_t *pcd = core_if->otg_dev->pcd;
1166 DWC_PRINTF("%s: disconnect USB %s mode\n", __func__,
1167 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1169 if (dwc_otg_is_host_mode(core_if)) {
1170 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1171 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1173 cancel_delayed_work_sync(&pcd->check_vbus_work);
1174 /* soft disconnect */
1176 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
1177 dctl.b.sftdiscon = 1;
1178 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
1181 /* Clear any pending interrupts */
1182 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1184 if (pldata->dwc_otg_uart_mode != NULL)
1185 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1186 if (pldata->phy_suspend != NULL)
1187 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1192 * This structure defines the methods to be called by a bus driver
1193 * during the lifecycle of a device on that bus. Both drivers and
1194 * devices are registered with a bus driver. The bus driver matches
1195 * devices to drivers based on information in the device and driver
1198 * The probe function is called when the bus driver matches a device
1199 * to this driver. The remove function is called when a device is
1200 * unregistered with the bus driver.
1202 #ifdef CONFIG_USB20_HOST
1203 static struct platform_driver dwc_host_driver = {
1205 .name = (char *)dwc_host20_driver_name,
1206 .of_match_table = of_match_ptr(usb20_host_of_match),
1208 .probe = host20_driver_probe,
1209 .remove = host20_driver_remove,
1210 .suspend = dwc_otg_driver_suspend,
1211 .resume = dwc_otg_driver_resume,
1215 #ifdef CONFIG_USB20_OTG
1217 * This function is called when a lm_device is unregistered with the
1218 * dwc_otg_driver. This happens, for example, when the rmmod command is
1219 * executed. The device may or may not be electrically present. If it is
1220 * present, the driver stops device processing. Any resources used on behalf
1221 * of this device are freed.
1225 static int otg20_driver_remove(struct platform_device *_dev)
1228 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1229 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1232 /* Memory allocation for the dwc_otg_device failed. */
1233 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1236 #ifndef DWC_DEVICE_ONLY
1240 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1245 #ifndef DWC_HOST_ONLY
1249 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1256 if (otg_dev->common_irq_installed) {
1257 /* free_irq(_dev->irq, otg_dev); */
1258 free_irq(platform_get_irq(_dev, 0), otg_dev);
1260 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
1265 if (otg_dev->core_if) {
1266 dwc_otg_cil_remove(otg_dev->core_if);
1268 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1273 * Remove the device attributes
1275 dwc_otg_attr_remove(_dev);
1278 * Return the memory.
1280 if (otg_dev->os_dep.base)
1281 iounmap(otg_dev->os_dep.base);
1285 * Clear the drvdata pointer.
1288 dwc_set_device_platform_data(_dev, 0);
1293 static const struct of_device_id usb20_otg_of_match[] = {
1296 .compatible = "rockchip,rk3188_usb20_otg",
1297 .data = &usb20otg_pdata_rk3188,
1300 .compatible = "rockchip,rk3288_usb20_otg",
1301 .data = &usb20otg_pdata_rk3288,
1304 .compatible = "rockchip,rk3036_usb20_otg",
1305 .data = &usb20otg_pdata_rk3036,
1308 .compatible = "rockchip,rk3126_usb20_otg",
1309 .data = &usb20otg_pdata_rk3126,
1314 .compatible = "rockchip,rk3368-usb",
1315 .data = &usb20otg_pdata_rk3368,
1321 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1324 * This function is called when an lm_device is bound to a
1325 * dwc_otg_driver. It creates the driver components required to
1326 * control the device (CIL, HCD, and PCD) and it initializes the
1327 * device. The driver components are stored in a dwc_otg_device
1328 * structure. A reference to the dwc_otg_device is saved in the
1329 * lm_device. This allows the driver to access the dwc_otg_device
1330 * structure on subsequent calls to driver methods for this device.
1332 * @param _dev Bus device
1334 static int otg20_driver_probe(struct platform_device *_dev)
1339 struct resource *res_base;
1340 dwc_otg_device_t *dwc_otg_device;
1341 struct device *dev = &_dev->dev;
1342 struct device_node *node = _dev->dev.of_node;
1343 struct dwc_otg_platform_data *pldata;
1344 const struct of_device_id *match =
1345 of_match_device(of_match_ptr(usb20_otg_of_match), &_dev->dev);
1347 if (match && match->data) {
1348 pldata = (void *)match->data;
1351 dev_err(dev, "usb20otg match failed\n");
1356 dev_err(dev, "device node not found\n");
1360 if (pldata->hw_init)
1363 if (pldata->clock_init) {
1364 pldata->clock_init(pldata);
1365 pldata->clock_enable(pldata, 1);
1368 if (pldata->phy_suspend)
1369 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1371 if (pldata->dwc_otg_uart_mode)
1372 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1374 /* do reset later, because reset need about
1375 * 100ms to ensure otg id state change.
1378 if(pldata->soft_reset)
1379 pldata->soft_reset();
1383 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1385 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1387 if (!dwc_otg_device) {
1388 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1393 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1394 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1397 * Map the DWC_otg Core memory into virtual address space.
1400 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1402 if (!dwc_otg_device->os_dep.base) {
1403 dev_err(&_dev->dev, "ioremap() failed\n");
1404 DWC_FREE(dwc_otg_device);
1408 dev_dbg(&_dev->dev, "base=0x%p\n", dwc_otg_device->os_dep.base);
1410 /* Set device flags indicating whether the HCD supports DMA. */
1411 if (!_dev->dev.dma_mask)
1412 _dev->dev.dma_mask = &_dev->dev.coherent_dma_mask;
1413 retval = dma_set_coherent_mask(&_dev->dev, DMA_BIT_MASK(32));
1418 * Initialize driver data to point to the global DWC_otg
1422 g_otgdev = dwc_otg_device;
1423 dwc_otg_dev = (struct device *)&_dev->dev;
1424 pldata->privdata = dwc_otg_device;
1425 dwc_otg_device->pldata = pldata;
1427 dwc_set_device_platform_data(_dev, dwc_otg_device);
1429 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1431 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1432 if (!dwc_otg_device->core_if) {
1433 dev_err(&_dev->dev, "CIL initialization failed!\n");
1438 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1440 * Attempt to ensure this device is really a DWC_otg Controller.
1441 * Read and verify the SNPSID register contents. The value should be
1442 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1443 * as in "OTG version 2.XX" or "OTG version 3.XX".
1446 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1448 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1450 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1451 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1457 * Validate parameter values.
1459 if (set_parameters(dwc_otg_device->core_if, dwc_otg_module_params)) {
1465 * Create Device Attributes in sysfs
1467 dwc_otg_attr_create(_dev);
1470 * Disable the global interrupt until all the interrupt
1471 * handlers are installed.
1473 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1476 * Install the interrupt handler for the common interrupts before
1477 * enabling common interrupts in core_init below.
1479 irq = platform_get_irq(_dev, 0);
1480 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1481 retval = request_irq(irq, dwc_otg_common_irq,
1482 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1484 DWC_ERROR("request of irq%d failed\n", irq);
1488 dwc_otg_device->common_irq_installed = 1;
1492 * Initialize the DWC_otg core.
1493 * In order to reduce the time of initialization,
1494 * we do core soft reset after connection detected.
1496 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1499 * 0 - USB_MODE_NORMAL
1500 * 1 - USB_MODE_FORCE_HOST
1501 * 2 - USB_MODE_FORCE_DEVICE
1503 of_property_read_u32(node, "rockchip,usb-mode", &val);
1504 dwc_otg_device->core_if->usb_mode = val;
1506 #ifndef DWC_HOST_ONLY
1508 * Initialize the PCD
1510 retval = pcd_init(_dev);
1512 DWC_ERROR("pcd_init failed\n");
1513 dwc_otg_device->pcd = NULL;
1517 #ifndef DWC_DEVICE_ONLY
1519 * Initialize the HCD
1521 retval = otg20_hcd_init(_dev);
1523 DWC_ERROR("hcd_init failed\n");
1524 dwc_otg_device->hcd = NULL;
1529 * Enable the global interrupt after all the interrupt
1530 * handlers are installed if there is no ADP support else
1531 * perform initial actions required for Internal ADP logic.
1533 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1534 if (dwc_otg_device->core_if->usb_mode == USB_MODE_NORMAL &&
1535 pldata->phy_status == USB_PHY_ENABLED) {
1536 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1538 pldata->clock_enable(pldata, 0);
1540 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1542 dwc_otg_adp_start(dwc_otg_device->core_if,
1543 dwc_otg_is_host_mode(dwc_otg_device->
1549 otg20_driver_remove(_dev);
1552 if (pldata->clock_enable)
1553 pldata->clock_enable(pldata, 0);
1559 static int dwc_otg_pm_suspend(struct device *dev)
1561 dwc_otg_device_t *dwc_otg_device;
1562 struct dwc_otg_platform_data *pdata_otg;
1564 dwc_otg_device = dev_get_platdata(dev);
1566 dev_dbg(dev, "dwc_otg PM suspend\n");
1568 if (dwc_otg_device->core_if->op_state == B_PERIPHERAL)
1571 pdata_otg = dwc_otg_device->pldata;
1572 pdata_otg->phy_suspend(pdata_otg, USB_PHY_SUSPEND);
1577 static int dwc_otg_pm_resume(struct device *dev)
1579 dwc_otg_device_t *dwc_otg_device;
1580 struct dwc_otg_platform_data *pdata_otg;
1582 dwc_otg_device = dev_get_platdata(dev);
1584 dev_dbg(dev, "dwc_otg PM resume\n");
1586 if (dwc_otg_device->core_if->op_state == B_PERIPHERAL)
1589 pdata_otg = dwc_otg_device->pldata;
1590 pdata_otg->phy_suspend(pdata_otg, USB_PHY_ENABLED);
1595 #define dwc_otg_pm_suspend NULL
1596 #define dwc_otg_pm_resume NULL
1599 static const struct dev_pm_ops dwc_otg_dev_pm_ops = {
1600 .suspend = dwc_otg_pm_suspend,
1601 .resume = dwc_otg_pm_resume,
1604 static struct platform_driver dwc_otg_driver = {
1606 .name = (char *)dwc_otg20_driver_name,
1607 .of_match_table = of_match_ptr(usb20_otg_of_match),
1609 .pm = &dwc_otg_dev_pm_ops,
1612 .probe = otg20_driver_probe,
1613 .remove = otg20_driver_remove,
1614 .suspend = dwc_otg_driver_suspend,
1615 .resume = dwc_otg_driver_resume,
1616 .shutdown = dwc_otg_driver_shutdown,
1620 void rk_usb_power_up(void)
1622 struct dwc_otg_platform_data *pldata_otg;
1623 struct dwc_otg_platform_data *pldata_host;
1624 #ifdef CONFIG_USB_EHCI_RK
1625 struct rkehci_platform_data *pldata_ehci;
1628 if (cpu_is_rk3288()) {
1629 #ifdef CONFIG_RK_USB_UART
1630 /* enable USB bypass UART function */
1631 writel_relaxed(0x00c00000 | usb_to_uart_status,
1632 RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1635 /* unset siddq,the analog blocks are powered up */
1636 #ifdef CONFIG_USB20_OTG
1637 pldata_otg = &usb20otg_pdata_rk3288;
1639 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1640 writel_relaxed((0x01 << 13) << 16,
1642 RK3288_GRF_UOC0_CON0);
1645 #ifdef CONFIG_USB20_HOST
1646 pldata_host = &usb20host_pdata_rk3288;
1648 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1649 writel_relaxed((0x01 << 13) << 16,
1651 RK3288_GRF_UOC2_CON0);
1654 #ifdef CONFIG_USB_EHCI_RK
1655 pldata_ehci = &rkehci_pdata_rk3288;
1657 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1658 writel_relaxed((0x01 << 13) << 16,
1660 RK3288_GRF_UOC1_CON0);
1665 dwc_otg_device_t *otg_dev = g_otgdev;
1670 pldata_otg = otg_dev->pldata;
1671 if (pldata_otg && pldata_otg->phy_power_down)
1672 pldata_otg->phy_power_down(PHY_POWER_UP);
1676 void rk_usb_power_down(void)
1678 struct dwc_otg_platform_data *pldata_otg;
1679 struct dwc_otg_platform_data *pldata_host;
1680 #ifdef CONFIG_USB_EHCI_RK
1681 struct rkehci_platform_data *pldata_ehci;
1684 if (cpu_is_rk3288()) {
1685 #ifdef CONFIG_RK_USB_UART
1686 /* disable USB bypass UART function */
1687 usb_to_uart_status =
1688 readl_relaxed(RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1689 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1691 /* set siddq,the analog blocks are powered down
1693 * 1. Before asserting SIDDQ, ensure that VDATSRCENB0,
1694 * VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0,
1695 * and TESTBURNIN are set to 1'b0.
1696 * 2. Before asserting SIDDQ, ensure that phy enter suspend.*/
1697 #ifdef CONFIG_USB20_OTG
1698 pldata_otg = &usb20otg_pdata_rk3288;
1700 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1701 writel_relaxed((0x01 << 13) |
1702 ((0x01 << 13) << 16),
1704 RK3288_GRF_UOC0_CON0);
1707 #ifdef CONFIG_USB20_HOST
1708 pldata_host = &usb20host_pdata_rk3288;
1710 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1711 writel_relaxed((0x01 << 13) |
1712 ((0x01 << 13) << 16),
1714 RK3288_GRF_UOC2_CON0);
1717 #ifdef CONFIG_USB_EHCI_RK
1718 pldata_ehci = &rkehci_pdata_rk3288;
1720 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1721 writel_relaxed((0x01 << 13) |
1722 ((0x01 << 13) << 16),
1724 RK3288_GRF_UOC1_CON0);
1728 dwc_otg_device_t *otg_dev = g_otgdev;
1733 pldata_otg = otg_dev->pldata;
1734 if (pldata_otg && pldata_otg->phy_power_down)
1735 pldata_otg->phy_power_down(PHY_POWER_DOWN);
1739 EXPORT_SYMBOL(rk_usb_power_up);
1740 EXPORT_SYMBOL(rk_usb_power_down);
1742 * This function is called when the dwc_otg_driver is installed with the
1743 * insmod command. It registers the dwc_otg_driver structure with the
1744 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1745 * to be called. In addition, the bus driver will automatically expose
1746 * attributes defined for the device and driver in the special sysfs file
1751 static int __init dwc_otg_driver_init(void)
1756 #ifdef CONFIG_USB20_OTG
1757 /* register otg20 */
1758 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1759 DWC_DRIVER_VERSION);
1761 retval = platform_driver_register(&dwc_otg_driver);
1763 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1768 driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1770 driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1772 driver_create_file(&dwc_otg_driver.driver,
1773 &driver_attr_dwc_otg_conn_en);
1775 driver_create_file(&dwc_otg_driver.driver,
1776 &driver_attr_vbus_status);
1778 driver_create_file(&dwc_otg_driver.driver,
1779 &driver_attr_force_usb_mode);
1781 driver_create_file(&dwc_otg_driver.driver,
1782 &driver_attr_op_state);
1786 /* register host20 */
1787 #ifdef CONFIG_USB20_HOST
1788 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1789 DWC_DRIVER_VERSION);
1791 retval = platform_driver_register(&dwc_host_driver);
1793 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1798 driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1800 driver_create_file(&dwc_host_driver.driver,
1801 &driver_attr_debuglevel);
1806 module_init(dwc_otg_driver_init);
1809 * This function is called when the driver is removed from the kernel
1810 * with the rmmod command. The driver unregisters itself with its bus
1814 static void __exit dwc_otg_driver_cleanup(void)
1816 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1818 #ifdef CONFIG_USB20_HOST
1820 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1821 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1822 platform_driver_unregister(&dwc_host_driver);
1823 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1826 #ifdef CONFIG_USB20_OTG
1828 driver_remove_file(&dwc_otg_driver.driver,
1829 &driver_attr_dwc_otg_conn_en);
1830 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1831 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1832 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1833 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1834 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_op_state);
1835 platform_driver_unregister(&dwc_otg_driver);
1836 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1840 module_exit(dwc_otg_driver_cleanup);
1842 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1843 MODULE_AUTHOR("Synopsys Inc.");
1844 MODULE_LICENSE("GPL");
1846 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1847 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1848 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1849 MODULE_PARM_DESC(opt, "OPT Mode");
1850 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1851 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1853 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1855 MODULE_PARM_DESC(dma_desc_enable,
1856 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1858 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1860 MODULE_PARM_DESC(dma_burst_size,
1861 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1862 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1863 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1864 module_param_named(host_support_fs_ls_low_power,
1865 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1867 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1868 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1869 module_param_named(host_ls_low_power_phy_clk,
1870 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1871 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1872 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1873 module_param_named(enable_dynamic_fifo,
1874 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1875 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1876 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1878 MODULE_PARM_DESC(data_fifo_size,
1879 "Total number of words in the data FIFO memory 32-32768");
1880 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1882 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1883 module_param_named(dev_nperio_tx_fifo_size,
1884 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1885 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1886 "Number of words in the non-periodic Tx FIFO 16-32768");
1887 module_param_named(dev_perio_tx_fifo_size_1,
1888 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1889 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1890 "Number of words in the periodic Tx FIFO 4-768");
1891 module_param_named(dev_perio_tx_fifo_size_2,
1892 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1893 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1894 "Number of words in the periodic Tx FIFO 4-768");
1895 module_param_named(dev_perio_tx_fifo_size_3,
1896 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1897 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1898 "Number of words in the periodic Tx FIFO 4-768");
1899 module_param_named(dev_perio_tx_fifo_size_4,
1900 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1901 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1902 "Number of words in the periodic Tx FIFO 4-768");
1903 module_param_named(dev_perio_tx_fifo_size_5,
1904 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1905 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1906 "Number of words in the periodic Tx FIFO 4-768");
1907 module_param_named(dev_perio_tx_fifo_size_6,
1908 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1909 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1910 "Number of words in the periodic Tx FIFO 4-768");
1911 module_param_named(dev_perio_tx_fifo_size_7,
1912 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1913 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1914 "Number of words in the periodic Tx FIFO 4-768");
1915 module_param_named(dev_perio_tx_fifo_size_8,
1916 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1917 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1918 "Number of words in the periodic Tx FIFO 4-768");
1919 module_param_named(dev_perio_tx_fifo_size_9,
1920 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1921 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1922 "Number of words in the periodic Tx FIFO 4-768");
1923 module_param_named(dev_perio_tx_fifo_size_10,
1924 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1925 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1926 "Number of words in the periodic Tx FIFO 4-768");
1927 module_param_named(dev_perio_tx_fifo_size_11,
1928 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1929 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1930 "Number of words in the periodic Tx FIFO 4-768");
1931 module_param_named(dev_perio_tx_fifo_size_12,
1932 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1933 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1934 "Number of words in the periodic Tx FIFO 4-768");
1935 module_param_named(dev_perio_tx_fifo_size_13,
1936 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1937 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1938 "Number of words in the periodic Tx FIFO 4-768");
1939 module_param_named(dev_perio_tx_fifo_size_14,
1940 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1941 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1942 "Number of words in the periodic Tx FIFO 4-768");
1943 module_param_named(dev_perio_tx_fifo_size_15,
1944 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1945 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1946 "Number of words in the periodic Tx FIFO 4-768");
1947 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1949 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1950 module_param_named(host_nperio_tx_fifo_size,
1951 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1952 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1953 "Number of words in the non-periodic Tx FIFO 16-32768");
1954 module_param_named(host_perio_tx_fifo_size,
1955 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1956 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1957 "Number of words in the host periodic Tx FIFO 16-32768");
1958 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1960 /** @todo Set the max to 512K, modify checks */
1961 MODULE_PARM_DESC(max_transfer_size,
1962 "The maximum transfer size supported in bytes 2047-65535");
1963 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1965 MODULE_PARM_DESC(max_packet_count,
1966 "The maximum number of packets in a transfer 15-511");
1967 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1969 MODULE_PARM_DESC(host_channels,
1970 "The number of host channel registers to use 1-16");
1971 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1973 MODULE_PARM_DESC(dev_endpoints,
1974 "The number of endpoints in addition to EP0 available for device mode 1-15");
1975 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1976 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1977 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1979 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1980 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1981 MODULE_PARM_DESC(phy_ulpi_ddr,
1982 "ULPI at double or single data rate 0=Single 1=Double");
1983 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1985 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1986 "ULPI PHY using internal or external vbus 0=Internal");
1987 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1988 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1989 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1990 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1991 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1992 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1993 module_param_named(debug, g_dbg_lvl, int, 0444);
1994 MODULE_PARM_DESC(debug, "");
1996 module_param_named(en_multiple_tx_fifo,
1997 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1998 MODULE_PARM_DESC(en_multiple_tx_fifo,
1999 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
2000 module_param_named(dev_tx_fifo_size_1,
2001 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
2002 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
2003 module_param_named(dev_tx_fifo_size_2,
2004 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
2005 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
2006 module_param_named(dev_tx_fifo_size_3,
2007 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
2008 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
2009 module_param_named(dev_tx_fifo_size_4,
2010 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
2011 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
2012 module_param_named(dev_tx_fifo_size_5,
2013 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
2014 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
2015 module_param_named(dev_tx_fifo_size_6,
2016 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
2017 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
2018 module_param_named(dev_tx_fifo_size_7,
2019 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
2020 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
2021 module_param_named(dev_tx_fifo_size_8,
2022 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
2023 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
2024 module_param_named(dev_tx_fifo_size_9,
2025 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
2026 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
2027 module_param_named(dev_tx_fifo_size_10,
2028 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
2029 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
2030 module_param_named(dev_tx_fifo_size_11,
2031 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
2032 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
2033 module_param_named(dev_tx_fifo_size_12,
2034 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
2035 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
2036 module_param_named(dev_tx_fifo_size_13,
2037 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
2038 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
2039 module_param_named(dev_tx_fifo_size_14,
2040 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
2041 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
2042 module_param_named(dev_tx_fifo_size_15,
2043 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
2044 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
2046 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
2047 MODULE_PARM_DESC(thr_ctl,
2048 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
2049 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
2051 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
2052 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
2054 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
2056 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
2057 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
2058 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
2059 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
2061 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
2062 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
2063 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int,
2065 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
2066 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
2067 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
2069 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
2070 MODULE_PARM_DESC(ic_usb_cap,
2071 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
2072 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
2074 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
2075 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
2076 MODULE_PARM_DESC(power_down, "Power Down Mode");
2077 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
2078 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
2079 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
2080 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
2081 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
2082 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
2083 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
2084 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
2085 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
2086 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
2087 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
2088 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
2090 /** @page "Module Parameters"
2092 * The following parameters may be specified when starting the module.
2093 * These parameters define how the DWC_otg controller should be
2094 * configured. Parameter values are passed to the CIL initialization
2095 * function dwc_otg_cil_init
2097 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
2101 <tr><td>Parameter Name</td><td>Meaning</td></tr>
2105 <td>Specifies the OTG capabilities. The driver will automatically detect the
2106 value for this parameter if none is specified.
2107 - 0: HNP and SRP capable (default, if available)
2108 - 1: SRP Only capable
2109 - 2: No HNP/SRP capable
2114 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2115 The driver will automatically detect the value for this parameter if none is
2118 - 1: DMA (default, if available)
2122 <td>dma_burst_size</td>
2123 <td>The DMA Burst size (applicable only for External DMA Mode).
2124 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2129 <td>Specifies the maximum speed of operation in host and device mode. The
2130 actual speed depends on the speed of the attached device and the value of
2132 - 0: High Speed (default)
2137 <td>host_support_fs_ls_low_power</td>
2138 <td>Specifies whether low power mode is supported when attached to a Full
2139 Speed or Low Speed device in host mode.
2140 - 0: Don't support low power mode (default)
2141 - 1: Support low power mode
2145 <td>host_ls_low_power_phy_clk</td>
2146 <td>Specifies the PHY clock rate in low power mode when connected to a Low
2147 Speed device in host mode. This parameter is applicable only if
2148 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2149 - 0: 48 MHz (default)
2154 <td>enable_dynamic_fifo</td>
2155 <td> Specifies whether FIFOs may be resized by the driver software.
2156 - 0: Use cC FIFO size parameters
2157 - 1: Allow dynamic FIFO sizing (default)
2161 <td>data_fifo_size</td>
2162 <td>Total number of 4-byte words in the data FIFO memory. This memory
2163 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2164 - Values: 32 to 32768 (default 8192)
2166 Note: The total FIFO memory depth in the FPGA configuration is 8192.
2170 <td>dev_rx_fifo_size</td>
2171 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2172 FIFO sizing is enabled.
2173 - Values: 16 to 32768 (default 1064)
2177 <td>dev_nperio_tx_fifo_size</td>
2178 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2179 dynamic FIFO sizing is enabled.
2180 - Values: 16 to 32768 (default 1024)
2184 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2185 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2186 when dynamic FIFO sizing is enabled.
2187 - Values: 4 to 768 (default 256)
2191 <td>host_rx_fifo_size</td>
2192 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2194 - Values: 16 to 32768 (default 1024)
2198 <td>host_nperio_tx_fifo_size</td>
2199 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2200 dynamic FIFO sizing is enabled in the core.
2201 - Values: 16 to 32768 (default 1024)
2205 <td>host_perio_tx_fifo_size</td>
2206 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2208 - Values: 16 to 32768 (default 1024)
2212 <td>max_transfer_size</td>
2213 <td>The maximum transfer size supported in bytes.
2214 - Values: 2047 to 65,535 (default 65,535)
2218 <td>max_packet_count</td>
2219 <td>The maximum number of packets in a transfer.
2220 - Values: 15 to 511 (default 511)
2224 <td>host_channels</td>
2225 <td>The number of host channel registers to use.
2226 - Values: 1 to 16 (default 12)
2228 Note: The FPGA configuration supports a maximum of 12 host channels.
2232 <td>dev_endpoints</td>
2233 <td>The number of endpoints in addition to EP0 available for device mode
2235 - Values: 1 to 15 (default 6 IN and OUT)
2237 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2243 <td>Specifies the type of PHY interface to use. By default, the driver will
2244 automatically detect the phy_type.
2246 - 1: UTMI+ (default, if available)
2251 <td>phy_utmi_width</td>
2252 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2253 phy_type of UTMI+. Also, this parameter is applicable only if the
2254 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2255 core has been configured to work at either data path width.
2256 - Values: 8 or 16 bits (default 16)
2260 <td>phy_ulpi_ddr</td>
2261 <td>Specifies whether the ULPI operates at double or single data rate. This
2262 parameter is only applicable if phy_type is ULPI.
2263 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2264 - 1: double data rate ULPI interface with 4 bit wide data bus
2269 <td>Specifies whether to use the I2C interface for full speed PHY. This
2270 parameter is only applicable if PHY_TYPE is FS.
2271 - 0: Disabled (default)
2277 <td>Specifies whether to use ULPI FS/LS mode only.
2278 - 0: Disabled (default)
2284 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2285 - 0: Disabled (default)
2290 <td>en_multiple_tx_fifo</td>
2291 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2292 The driver will automatically detect the value for this parameter if none is
2295 - 1: Enabled (default, if available)
2299 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2300 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2301 when dynamic FIFO sizing is enabled.
2302 - Values: 4 to 768 (default 256)
2306 <td>tx_thr_length</td>
2307 <td>Transmit Threshold length in 32 bit double words
2308 - Values: 8 to 128 (default 64)
2312 <td>rx_thr_length</td>
2313 <td>Receive Threshold length in 32 bit double words
2314 - Values: 8 to 128 (default 64)
2319 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2320 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2321 Rx transfers accordingly.
2322 The driver will automatically detect the value for this parameter if none is
2324 - Values: 0 to 7 (default 0)
2325 Bit values indicate:
2326 - 0: Thresholding disabled
2327 - 1: Thresholding enabled
2331 <td>dma_desc_enable</td>
2332 <td>Specifies whether to enable Descriptor DMA mode.
2333 The driver will automatically detect the value for this parameter if none is
2335 - 0: Descriptor DMA disabled
2336 - 1: Descriptor DMA (default, if available)
2341 <td>Specifies whether to enable MPI enhancement mode.
2342 The driver will automatically detect the value for this parameter if none is
2344 - 0: MPI disabled (default)
2350 <td>Specifies whether to enable PTI enhancement support.
2351 The driver will automatically detect the value for this parameter if none is
2353 - 0: PTI disabled (default)
2359 <td>Specifies whether to enable LPM support.
2360 The driver will automatically detect the value for this parameter if none is
2363 - 1: LPM enable (default, if available)
2367 <td>besl_enable</td>
2368 <td>Specifies whether to enable LPM Errata support.
2369 The driver will automatically detect the value for this parameter if none is
2371 - 0: LPM Errata disabled (default)
2372 - 1: LPM Errata enable
2376 <td>baseline_besl</td>
2377 <td>Specifies the baseline besl value.
2378 - Values: 0 to 15 (default 0)
2383 <td>Specifies the deep besl value.
2384 - Values: 0 to 15 (default 15)
2389 <td>Specifies whether to enable IC_USB capability.
2390 The driver will automatically detect the value for this parameter if none is
2392 - 0: IC_USB disabled (default, if available)
2397 <td>ahb_thr_ratio</td>
2398 <td>Specifies AHB Threshold ratio.
2399 - Values: 0 to 3 (default 0)
2404 <td>Specifies Power Down(Hibernation) Mode.
2405 The driver will automatically detect the value for this parameter if none is
2407 - 0: Power Down disabled (default)
2408 - 2: Power Down enabled
2413 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2414 run time. The driver will automatically detect the value for this parameter if
2415 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2416 the core might misbehave.
2417 - 0: Reload Control disabled (default)
2418 - 1: Reload Control enabled
2422 <td>dev_out_nak</td>
2423 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2424 The driver will automatically detect the value for this parameter if
2425 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2426 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2427 - 1: The core sets NAK after Bulk OUT transfer complete
2431 <td>cont_on_bna</td>
2432 <td>Specifies whether Enable Continue on BNA enabled or no.
2433 After receiving BNA interrupt the core disables the endpoint,when the
2434 endpoint is re-enabled by the application the
2435 - 0: Core starts processing from the DOEPDMA descriptor (default)
2436 - 1: Core starts processing from the descriptor which received the BNA.
2437 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2442 <td>This bit when programmed supports SINGLE transfers for remainder data
2443 in a transfer for DMA mode of operation.
2444 - 0: The remainder data will be sent using INCR burst size (default)
2445 - 1: The remainder data will be sent using SINGLE burst size.
2450 <td>Specifies whether ADP feature is enabled.
2451 The driver will automatically detect the value for this parameter if none is
2453 - 0: ADP feature disabled (default)
2454 - 1: ADP feature enabled
2459 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2461 - 0: OTG 2.0 support disabled (default)
2462 - 1: OTG 2.0 support enabled