1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t *g_otgdev;
72 extern int pcd_init(struct platform_device *_dev);
73 extern int otg20_hcd_init(struct platform_device *_dev);
74 extern int host20_hcd_init(struct platform_device *_dev);
75 extern int pcd_remove(struct platform_device *_dev);
76 extern void hcd_remove(struct platform_device *_dev);
77 extern void dwc_otg_adp_start(dwc_otg_core_if_t *core_if, uint8_t is_host);
81 static u32 usb_to_uart_status;
82 /*-------------------------------------------------------------------------*/
83 /* Encapsulate the module parameter settings */
85 struct dwc_otg_driver_module_params {
89 int32_t dma_desc_enable;
90 int32_t dma_burst_size;
92 int32_t host_support_fs_ls_low_power;
93 int32_t host_ls_low_power_phy_clk;
94 int32_t enable_dynamic_fifo;
95 int32_t data_fifo_size;
96 int32_t dev_rx_fifo_size;
97 int32_t dev_nperio_tx_fifo_size;
98 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
99 int32_t host_rx_fifo_size;
100 int32_t host_nperio_tx_fifo_size;
101 int32_t host_perio_tx_fifo_size;
102 int32_t max_transfer_size;
103 int32_t max_packet_count;
104 int32_t host_channels;
105 int32_t dev_endpoints;
107 int32_t phy_utmi_width;
108 int32_t phy_ulpi_ddr;
109 int32_t phy_ulpi_ext_vbus;
113 int32_t en_multiple_tx_fifo;
114 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
116 uint32_t tx_thr_length;
117 uint32_t rx_thr_length;
122 int32_t baseline_besl;
125 int32_t ahb_thr_ratio;
135 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
137 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
139 .dma_desc_enable = 0,
140 .dma_burst_size = -1,
142 .host_support_fs_ls_low_power = -1,
143 .host_ls_low_power_phy_clk = -1,
144 .enable_dynamic_fifo = 1,
145 .data_fifo_size = -1,
146 .dev_rx_fifo_size = 0x120,
147 .dev_nperio_tx_fifo_size = 0x10,
148 .dev_perio_tx_fifo_size = {
149 /* dev_perio_tx_fifo_size_1 */
167 .host_rx_fifo_size = -1,
168 .host_nperio_tx_fifo_size = -1,
169 .host_perio_tx_fifo_size = -1,
170 .max_transfer_size = -1,
171 .max_packet_count = -1,
175 .phy_utmi_width = -1,
177 .phy_ulpi_ext_vbus = -1,
181 .en_multiple_tx_fifo = -1,
182 .dev_tx_fifo_size = {
183 /* dev_tx_fifo_size */
221 #ifdef CONFIG_USB20_HOST
222 static struct dwc_otg_driver_module_params dwc_host_module_params = {
224 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
226 .dma_desc_enable = 0,
227 .dma_burst_size = -1,
229 .host_support_fs_ls_low_power = -1,
230 .host_ls_low_power_phy_clk = -1,
231 .enable_dynamic_fifo = -1,
232 .data_fifo_size = -1,
233 .dev_rx_fifo_size = -1,
234 .dev_nperio_tx_fifo_size = -1,
235 .dev_perio_tx_fifo_size = {
236 /* dev_perio_tx_fifo_size_1 */
254 .host_rx_fifo_size = -1,
255 .host_nperio_tx_fifo_size = -1,
256 .host_perio_tx_fifo_size = -1,
257 .max_transfer_size = -1,
258 .max_packet_count = -1,
262 .phy_utmi_width = -1,
264 .phy_ulpi_ext_vbus = -1,
268 .en_multiple_tx_fifo = -1,
269 .dev_tx_fifo_size = {
270 /* dev_tx_fifo_size */
310 * This function shows the Driver Version.
312 static ssize_t version_show(struct device_driver *dev, char *buf)
314 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
318 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
321 * Global Debug Level Mask.
323 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
326 * This function shows the driver Debug Level.
328 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
330 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
334 * This function stores the driver Debug Level.
336 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
339 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
343 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
346 extern void hcd_start(dwc_otg_core_if_t *core_if);
347 extern struct usb_hub *g_dwc_otg_root_hub20;
348 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
350 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
352 dwc_otg_device_t *otg_dev = core_if->otg_dev;
353 dctl_data_t dctl = {.d32 = 0 };
356 if (core_if->op_state == A_HOST) {
357 printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
360 core_if->op_state = A_HOST;
362 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
363 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
364 dctl.b.sftdiscon = 1;
365 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
367 local_irq_save(flags);
368 cil_pcd_stop(core_if);
370 * Initialize the Core for Host mode.
373 dwc_otg_core_init(core_if);
374 dwc_otg_enable_global_interrupts(core_if);
375 cil_hcd_start(core_if);
376 local_irq_restore(flags);
379 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
381 dwc_otg_device_t *otg_dev = core_if->otg_dev;
384 local_irq_save(flags);
386 if (core_if->op_state == B_PERIPHERAL) {
388 ("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
391 core_if->op_state = B_PERIPHERAL;
392 cil_hcd_stop(core_if);
393 /* dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20); */
394 otg_dev->pcd->phy_suspend = 1;
395 otg_dev->pcd->vbus_status = 0;
396 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
398 /* Reset the Controller */
399 dwc_otg_core_reset(core_if);
401 dwc_otg_core_init(core_if);
402 dwc_otg_disable_global_interrupts(core_if);
403 cil_pcd_start(core_if);
405 local_irq_restore(flags);
408 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
410 dwc_otg_device_t *otg_dev = g_otgdev;
411 dwc_otg_core_if_t *core_if = otg_dev->core_if;
413 return sprintf(buf, "%d\n", core_if->usb_mode);
416 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
419 int new_mode = simple_strtoul(buf, NULL, 16);
420 dwc_otg_device_t *otg_dev = g_otgdev;
421 dwc_otg_core_if_t *core_if;
422 struct dwc_otg_platform_data *pldata;
427 core_if = otg_dev->core_if;
428 pldata = otg_dev->pldata;
430 DWC_PRINTF("%s %d->%d\n", __func__, core_if->usb_mode, new_mode);
432 if (core_if->usb_mode == new_mode) {
436 if (pldata->phy_status == USB_PHY_SUSPEND) {
437 pldata->clock_enable(pldata, 1);
438 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
442 case USB_MODE_FORCE_HOST:
443 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
445 core_if->usb_mode = new_mode;
446 dwc_otg_force_host(core_if);
447 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
448 core_if->usb_mode = new_mode;
449 if (dwc_otg_is_host_mode(core_if))
450 dwc_otg_set_force_mode(core_if, new_mode);
452 dwc_otg_force_host(core_if);
456 case USB_MODE_FORCE_DEVICE:
457 if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
458 core_if->usb_mode = new_mode;
459 dwc_otg_force_device(core_if);
460 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
461 core_if->usb_mode = new_mode;
462 if (dwc_otg_is_device_mode(core_if))
463 dwc_otg_set_force_mode(core_if, new_mode);
465 dwc_otg_force_device(core_if);
469 case USB_MODE_NORMAL:
470 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
471 core_if->usb_mode = new_mode;
472 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
473 dwc_otg_set_force_mode(core_if, new_mode);
475 if (dwc_otg_is_host_mode(core_if)) {
476 dwc_otg_force_host(core_if);
478 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
480 } else if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
481 core_if->usb_mode = new_mode;
482 dwc_otg_set_force_mode(core_if, new_mode);
484 if (dwc_otg_is_device_mode(core_if)) {
485 dwc_otg_force_device(core_if);
496 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show,
497 force_usb_mode_store);
499 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
502 dwc_otg_device_t *otg_dev = g_otgdev;
503 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
504 return sprintf(_buf, "%d\n", _pcd->conn_en);
508 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv,
509 const char *_buf, size_t _count)
511 int enable = simple_strtoul(_buf, NULL, 10);
512 dwc_otg_device_t *otg_dev = g_otgdev;
513 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
514 DWC_PRINTF("%s %d->%d\n", __func__, _pcd->conn_en, enable);
516 _pcd->conn_en = enable;
520 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO | S_IWUSR, dwc_otg_conn_en_show,
521 dwc_otg_conn_en_store);
523 /* used for product vbus power control, SDK not need.
524 * If dwc_otg is host mode, enable vbus power.
525 * If dwc_otg is device mode, disable vbus power.
526 * return 1 - host mode, 0 - device mode.
528 int dwc_otg_usb_state(void)
530 dwc_otg_device_t *otg_dev = g_otgdev;
533 /* op_state is A_HOST */
534 if (1 == otg_dev->core_if->op_state)
536 /* op_state is B_PERIPHERAL */
537 else if (4 == otg_dev->core_if->op_state)
542 DWC_WARN("g_otgdev is NULL, maybe otg probe is failed!\n");
546 EXPORT_SYMBOL(dwc_otg_usb_state);
548 static ssize_t dwc_otg_op_state_show(struct device_driver *_drv, char *_buf)
550 dwc_otg_device_t *otg_dev = g_otgdev;
553 return sprintf(_buf, "%d\n", otg_dev->core_if->op_state);
555 return sprintf(_buf, "%d\n", 0);
558 static DRIVER_ATTR(op_state, S_IRUGO, dwc_otg_op_state_show, NULL);
560 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
562 dwc_otg_device_t *otg_dev = g_otgdev;
563 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
564 return sprintf(_buf, "%d\n", _pcd->vbus_status);
567 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
570 * This function is called during module intialization
571 * to pass module parameters to the DWC_OTG CORE.
573 static int set_parameters(dwc_otg_core_if_t *core_if,
574 struct dwc_otg_driver_module_params module_params)
579 if (module_params.otg_cap != -1) {
581 dwc_otg_set_param_otg_cap(core_if, module_params.otg_cap);
583 if (module_params.dma_enable != -1) {
585 dwc_otg_set_param_dma_enable(core_if,
586 module_params.dma_enable);
588 if (module_params.dma_desc_enable != -1) {
590 dwc_otg_set_param_dma_desc_enable(core_if,
591 module_params.dma_desc_enable);
593 if (module_params.opt != -1) {
594 retval += dwc_otg_set_param_opt(core_if, module_params.opt);
596 if (module_params.dma_burst_size != -1) {
598 dwc_otg_set_param_dma_burst_size(core_if,
599 module_params.dma_burst_size);
601 if (module_params.host_support_fs_ls_low_power != -1) {
603 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
604 module_params.host_support_fs_ls_low_power);
606 if (module_params.enable_dynamic_fifo != -1) {
608 dwc_otg_set_param_enable_dynamic_fifo(core_if,
609 module_params.enable_dynamic_fifo);
611 if (module_params.data_fifo_size != -1) {
613 dwc_otg_set_param_data_fifo_size(core_if,
614 module_params.data_fifo_size);
616 if (module_params.dev_rx_fifo_size != -1) {
618 dwc_otg_set_param_dev_rx_fifo_size(core_if,
619 module_params.dev_rx_fifo_size);
621 if (module_params.dev_nperio_tx_fifo_size != -1) {
623 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
624 module_params.dev_nperio_tx_fifo_size);
626 if (module_params.host_rx_fifo_size != -1) {
628 dwc_otg_set_param_host_rx_fifo_size(core_if,
632 if (module_params.host_nperio_tx_fifo_size != -1) {
634 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
635 module_params.host_nperio_tx_fifo_size);
637 if (module_params.host_perio_tx_fifo_size != -1) {
639 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
640 module_params.host_perio_tx_fifo_size);
642 if (module_params.max_transfer_size != -1) {
644 dwc_otg_set_param_max_transfer_size(core_if,
645 module_params.max_transfer_size);
647 if (module_params.max_packet_count != -1) {
649 dwc_otg_set_param_max_packet_count(core_if,
650 module_params.max_packet_count);
652 if (module_params.host_channels != -1) {
654 dwc_otg_set_param_host_channels(core_if,
655 module_params.host_channels);
657 if (module_params.dev_endpoints != -1) {
659 dwc_otg_set_param_dev_endpoints(core_if,
660 module_params.dev_endpoints);
662 if (module_params.phy_type != -1) {
664 dwc_otg_set_param_phy_type(core_if, module_params.phy_type);
666 if (module_params.speed != -1) {
667 retval += dwc_otg_set_param_speed(core_if, module_params.speed);
669 if (module_params.host_ls_low_power_phy_clk != -1) {
671 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
672 module_params.host_ls_low_power_phy_clk);
674 if (module_params.phy_ulpi_ddr != -1) {
676 dwc_otg_set_param_phy_ulpi_ddr(core_if,
677 module_params.phy_ulpi_ddr);
679 if (module_params.phy_ulpi_ext_vbus != -1) {
681 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
682 module_params.phy_ulpi_ext_vbus);
684 if (module_params.phy_utmi_width != -1) {
686 dwc_otg_set_param_phy_utmi_width(core_if,
687 module_params.phy_utmi_width);
689 if (module_params.ulpi_fs_ls != -1) {
691 dwc_otg_set_param_ulpi_fs_ls(core_if,
692 module_params.ulpi_fs_ls);
694 if (module_params.ts_dline != -1) {
696 dwc_otg_set_param_ts_dline(core_if, module_params.ts_dline);
698 if (module_params.i2c_enable != -1) {
700 dwc_otg_set_param_i2c_enable(core_if,
701 module_params.i2c_enable);
703 if (module_params.en_multiple_tx_fifo != -1) {
705 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
706 module_params.en_multiple_tx_fifo);
708 for (i = 0; i < 15; i++) {
709 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
711 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
712 module_params.dev_perio_tx_fifo_size
717 for (i = 0; i < 15; i++) {
718 if (module_params.dev_tx_fifo_size[i] != -1) {
719 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
720 module_params.dev_tx_fifo_size
724 if (module_params.thr_ctl != -1) {
726 dwc_otg_set_param_thr_ctl(core_if, module_params.thr_ctl);
728 if (module_params.mpi_enable != -1) {
730 dwc_otg_set_param_mpi_enable(core_if,
731 module_params.mpi_enable);
733 if (module_params.pti_enable != -1) {
735 dwc_otg_set_param_pti_enable(core_if,
736 module_params.pti_enable);
738 if (module_params.lpm_enable != -1) {
740 dwc_otg_set_param_lpm_enable(core_if,
741 module_params.lpm_enable);
743 if (module_params.besl_enable != -1) {
745 dwc_otg_set_param_besl_enable(core_if,
746 module_params.besl_enable);
748 if (module_params.baseline_besl != -1) {
750 dwc_otg_set_param_baseline_besl(core_if,
751 module_params.baseline_besl);
753 if (module_params.deep_besl != -1) {
755 dwc_otg_set_param_deep_besl(core_if,
756 module_params.deep_besl);
758 if (module_params.ic_usb_cap != -1) {
760 dwc_otg_set_param_ic_usb_cap(core_if,
761 module_params.ic_usb_cap);
763 if (module_params.tx_thr_length != -1) {
765 dwc_otg_set_param_tx_thr_length(core_if,
769 if (module_params.rx_thr_length != -1) {
771 dwc_otg_set_param_rx_thr_length(core_if,
772 module_params.rx_thr_length);
774 if (module_params.ahb_thr_ratio != -1) {
776 dwc_otg_set_param_ahb_thr_ratio(core_if,
780 if (module_params.power_down != -1) {
782 dwc_otg_set_param_power_down(core_if,
783 module_params.power_down);
785 if (module_params.reload_ctl != -1) {
787 dwc_otg_set_param_reload_ctl(core_if,
788 module_params.reload_ctl);
791 if (module_params.dev_out_nak != -1) {
793 dwc_otg_set_param_dev_out_nak(core_if,
794 module_params.dev_out_nak);
797 if (module_params.cont_on_bna != -1) {
799 dwc_otg_set_param_cont_on_bna(core_if,
800 module_params.cont_on_bna);
803 if (module_params.ahb_single != -1) {
805 dwc_otg_set_param_ahb_single(core_if,
806 module_params.ahb_single);
809 if (module_params.otg_ver != -1) {
811 dwc_otg_set_param_otg_ver(core_if, module_params.otg_ver);
813 if (module_params.adp_enable != -1) {
815 dwc_otg_set_param_adp_enable(core_if,
816 module_params.adp_enable);
822 * This function is the top level interrupt handler for the Common
823 * (Device and host modes) interrupts.
825 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
827 int32_t retval = IRQ_NONE;
829 retval = dwc_otg_handle_common_intr(dev);
831 /* S3C2410X_CLEAR_EINTPEND(); */
833 return IRQ_RETVAL(retval);
836 #ifdef CONFIG_USB20_HOST
838 * This function is called when a lm_device is unregistered with the
839 * dwc_otg_driver. This happens, for example, when the rmmod command is
840 * executed. The device may or may not be electrically present. If it is
841 * present, the driver stops device processing. Any resources used on behalf
842 * of this device are freed.
846 static int host20_driver_remove(struct platform_device *_dev)
849 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
850 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
853 /* Memory allocation for the dwc_otg_device failed. */
854 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
857 #ifndef DWC_DEVICE_ONLY
861 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
866 #ifndef DWC_HOST_ONLY
870 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
878 if (otg_dev->common_irq_installed) {
879 /* free_irq(_dev->irq, otg_dev); */
880 free_irq(platform_get_irq(_dev, 0), otg_dev);
882 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
887 if (otg_dev->core_if) {
888 dwc_otg_cil_remove(otg_dev->core_if);
890 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
895 * Remove the device attributes
897 dwc_otg_attr_remove(_dev);
902 if (otg_dev->os_dep.base) {
903 iounmap(otg_dev->os_dep.base);
908 * Clear the drvdata pointer.
911 dwc_set_device_platform_data(_dev, 0);
916 static const struct of_device_id usb20_host_of_match[] = {
918 .compatible = "rockchip,rk3188_usb20_host",
919 .data = &usb20host_pdata_rk3188,
922 .compatible = "rockchip,rk3288_usb20_host",
923 .data = &usb20host_pdata_rk3288,
926 .compatible = "rockchip,rk3036_usb20_host",
927 .data = &usb20host_pdata_rk3036,
930 .compatible = "rockchip,rk3126_usb20_host",
931 .data = &usb20host_pdata_rk3126,
936 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
939 * This function is called when an lm_device is bound to a
940 * dwc_otg_driver. It creates the driver components required to
941 * control the device (CIL, HCD, and PCD) and it initializes the
942 * device. The driver components are stored in a dwc_otg_device
943 * structure. A reference to the dwc_otg_device is saved in the
944 * lm_device. This allows the driver to access the dwc_otg_device
945 * structure on subsequent calls to driver methods for this device.
947 * @param _dev Bus device
949 static int host20_driver_probe(struct platform_device *_dev)
953 struct resource *res_base;
954 dwc_otg_device_t *dwc_otg_device;
955 struct device *dev = &_dev->dev;
956 struct device_node *node = _dev->dev.of_node;
957 struct dwc_otg_platform_data *pldata;
958 const struct of_device_id *match =
959 of_match_device(of_match_ptr(usb20_host_of_match), &_dev->dev);
961 if (match && match->data) {
962 dev->platform_data = (void *)match->data;
964 dev_err(dev, "usb20host match failed\n");
968 pldata = dev->platform_data;
972 dev_err(dev, "device node not found\n");
979 if (pldata->clock_init) {
980 pldata->clock_init(pldata);
981 pldata->clock_enable(pldata, 1);
984 if (pldata->phy_suspend)
985 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
987 if (pldata->soft_reset)
988 pldata->soft_reset(pldata, RST_POR);
990 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
992 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
994 if (!dwc_otg_device) {
995 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1000 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1001 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1004 * Map the DWC_otg Core memory into virtual address space.
1007 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1009 if (!dwc_otg_device->os_dep.base) {
1010 dev_err(&_dev->dev, "ioremap() failed\n");
1011 DWC_FREE(dwc_otg_device);
1015 dev_dbg(&_dev->dev, "base=0x%08x\n",
1016 (unsigned)dwc_otg_device->os_dep.base);
1018 /* Set device flags indicating whether the HCD supports DMA. */
1019 if (!_dev->dev.dma_mask)
1020 _dev->dev.dma_mask = &_dev->dev.coherent_dma_mask;
1021 retval = dma_set_coherent_mask(&_dev->dev, DMA_BIT_MASK(32));
1026 * Initialize driver data to point to the global DWC_otg
1030 dwc_set_device_platform_data(_dev, dwc_otg_device);
1031 pldata->privdata = dwc_otg_device;
1032 dwc_otg_device->pldata = (void *)pldata;
1034 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1036 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1038 if (!dwc_otg_device->core_if) {
1039 dev_err(&_dev->dev, "CIL initialization failed!\n");
1044 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1047 * Attempt to ensure this device is really a DWC_otg Controller.
1048 * Read and verify the SNPSID register contents. The value should be
1049 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1050 * as in "OTG version 2.XX" or "OTG version 3.XX".
1053 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1055 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1057 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1058 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1064 * Validate parameter values.
1066 if (set_parameters(dwc_otg_device->core_if, dwc_host_module_params)) {
1072 * Create Device Attributes in sysfs
1074 dwc_otg_attr_create(_dev);
1077 * Disable the global interrupt until all the interrupt
1078 * handlers are installed.
1080 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1083 * Install the interrupt handler for the common interrupts before
1084 * enabling common interrupts in core_init below.
1086 irq = platform_get_irq(_dev, 0);
1087 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1088 retval = request_irq(irq, dwc_otg_common_irq,
1089 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1091 DWC_ERROR("request of irq%d failed\n", irq);
1095 dwc_otg_device->common_irq_installed = 1;
1099 * Initialize the DWC_otg core.
1100 * In order to reduce the time of initialization,
1101 * we do core soft reset after connection detected.
1103 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1106 * Initialize the HCD
1108 retval = host20_hcd_init(_dev);
1110 DWC_ERROR("hcd_init failed\n");
1111 dwc_otg_device->hcd = NULL;
1115 clk_set_rate(pldata->phyclk_480m, 480000000);
1117 * Enable the global interrupt after all the interrupt
1118 * handlers are installed if there is no ADP support else
1119 * perform initial actions required for Internal ADP logic.
1121 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1122 if (pldata->phy_status == USB_PHY_ENABLED) {
1123 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1125 pldata->clock_enable(pldata, 0);
1127 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1129 dwc_otg_adp_start(dwc_otg_device->core_if,
1130 dwc_otg_is_host_mode(dwc_otg_device->
1136 host20_driver_remove(_dev);
1138 if (pldata->clock_enable)
1139 pldata->clock_enable(pldata, 0);
1145 static int dwc_otg_driver_suspend(struct platform_device *_dev,
1151 static int dwc_otg_driver_resume(struct platform_device *_dev)
1156 static void dwc_otg_driver_shutdown(struct platform_device *_dev)
1158 struct device *dev = &_dev->dev;
1159 struct dwc_otg_platform_data *pldata = dev->platform_data;
1160 dwc_otg_device_t *otg_dev = dev->platform_data;
1161 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1162 dctl_data_t dctl = {.d32 = 0 };
1164 DWC_PRINTF("%s: disconnect USB %s mode\n", __func__,
1165 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1167 if( pldata->dwc_otg_uart_mode != NULL)
1168 pldata->dwc_otg_uart_mode( pldata, PHY_USB_MODE);
1169 if(pldata->phy_suspend != NULL)
1170 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1171 if (dwc_otg_is_host_mode(core_if)) {
1172 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1173 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1175 /* soft disconnect */
1177 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
1178 dctl.b.sftdiscon = 1;
1179 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
1182 /* Clear any pending interrupts */
1183 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1188 * This structure defines the methods to be called by a bus driver
1189 * during the lifecycle of a device on that bus. Both drivers and
1190 * devices are registered with a bus driver. The bus driver matches
1191 * devices to drivers based on information in the device and driver
1194 * The probe function is called when the bus driver matches a device
1195 * to this driver. The remove function is called when a device is
1196 * unregistered with the bus driver.
1198 #ifdef CONFIG_USB20_HOST
1199 static struct platform_driver dwc_host_driver = {
1201 .name = (char *)dwc_host20_driver_name,
1202 .of_match_table = of_match_ptr(usb20_host_of_match),
1204 .probe = host20_driver_probe,
1205 .remove = host20_driver_remove,
1206 .suspend = dwc_otg_driver_suspend,
1207 .resume = dwc_otg_driver_resume,
1211 #ifdef CONFIG_USB20_OTG
1213 * This function is called when a lm_device is unregistered with the
1214 * dwc_otg_driver. This happens, for example, when the rmmod command is
1215 * executed. The device may or may not be electrically present. If it is
1216 * present, the driver stops device processing. Any resources used on behalf
1217 * of this device are freed.
1221 static int otg20_driver_remove(struct platform_device *_dev)
1224 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1225 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1228 /* Memory allocation for the dwc_otg_device failed. */
1229 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1232 #ifndef DWC_DEVICE_ONLY
1236 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1241 #ifndef DWC_HOST_ONLY
1245 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1252 if (otg_dev->common_irq_installed) {
1253 /* free_irq(_dev->irq, otg_dev); */
1254 free_irq(platform_get_irq(_dev, 0), otg_dev);
1256 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
1261 if (otg_dev->core_if) {
1262 dwc_otg_cil_remove(otg_dev->core_if);
1264 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1269 * Remove the device attributes
1271 dwc_otg_attr_remove(_dev);
1274 * Return the memory.
1276 if (otg_dev->os_dep.base)
1277 iounmap(otg_dev->os_dep.base);
1281 * Clear the drvdata pointer.
1284 dwc_set_device_platform_data(_dev, 0);
1289 static const struct of_device_id usb20_otg_of_match[] = {
1291 .compatible = "rockchip,rk3188_usb20_otg",
1292 .data = &usb20otg_pdata_rk3188,
1295 .compatible = "rockchip,rk3288_usb20_otg",
1296 .data = &usb20otg_pdata_rk3288,
1299 .compatible = "rockchip,rk3036_usb20_otg",
1300 .data = &usb20otg_pdata_rk3036,
1303 .compatible = "rockchip,rk3126_usb20_otg",
1304 .data = &usb20otg_pdata_rk3126,
1309 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1312 * This function is called when an lm_device is bound to a
1313 * dwc_otg_driver. It creates the driver components required to
1314 * control the device (CIL, HCD, and PCD) and it initializes the
1315 * device. The driver components are stored in a dwc_otg_device
1316 * structure. A reference to the dwc_otg_device is saved in the
1317 * lm_device. This allows the driver to access the dwc_otg_device
1318 * structure on subsequent calls to driver methods for this device.
1320 * @param _dev Bus device
1322 static int otg20_driver_probe(struct platform_device *_dev)
1327 struct resource *res_base;
1328 dwc_otg_device_t *dwc_otg_device;
1329 struct device *dev = &_dev->dev;
1330 struct device_node *node = _dev->dev.of_node;
1331 struct dwc_otg_platform_data *pldata;
1332 const struct of_device_id *match =
1333 of_match_device(of_match_ptr(usb20_otg_of_match), &_dev->dev);
1336 dev->platform_data = (void *)match->data;
1338 dev_err(dev, "usb20otg match failed\n");
1342 pldata = dev->platform_data;
1346 dev_err(dev, "device node not found\n");
1349 /*todo : move to usbdev_rk-XX.c */
1350 if (pldata->hw_init)
1353 if (pldata->clock_init) {
1354 pldata->clock_init(pldata);
1355 pldata->clock_enable(pldata, 1);
1358 if (pldata->phy_suspend)
1359 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1361 if (pldata->dwc_otg_uart_mode)
1362 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1364 /* do reset later, because reset need about
1365 * 100ms to ensure otg id state change.
1368 if(pldata->soft_reset)
1369 pldata->soft_reset();
1373 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1375 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1377 if (!dwc_otg_device) {
1378 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1383 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1384 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1387 * Map the DWC_otg Core memory into virtual address space.
1390 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1392 if (!dwc_otg_device->os_dep.base) {
1393 dev_err(&_dev->dev, "ioremap() failed\n");
1394 DWC_FREE(dwc_otg_device);
1398 dev_dbg(&_dev->dev, "base=0x%08x\n",
1399 (unsigned)dwc_otg_device->os_dep.base);
1401 /* Set device flags indicating whether the HCD supports DMA. */
1402 if (!_dev->dev.dma_mask)
1403 _dev->dev.dma_mask = &_dev->dev.coherent_dma_mask;
1404 retval = dma_set_coherent_mask(&_dev->dev, DMA_BIT_MASK(32));
1409 * Initialize driver data to point to the global DWC_otg
1413 g_otgdev = dwc_otg_device;
1414 pldata->privdata = dwc_otg_device;
1415 dwc_otg_device->pldata = pldata;
1417 dwc_set_device_platform_data(_dev, dwc_otg_device);
1419 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1421 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1422 if (!dwc_otg_device->core_if) {
1423 dev_err(&_dev->dev, "CIL initialization failed!\n");
1428 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1430 * Attempt to ensure this device is really a DWC_otg Controller.
1431 * Read and verify the SNPSID register contents. The value should be
1432 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1433 * as in "OTG version 2.XX" or "OTG version 3.XX".
1436 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1438 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1440 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1441 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1447 * Validate parameter values.
1449 if (set_parameters(dwc_otg_device->core_if, dwc_otg_module_params)) {
1455 * Create Device Attributes in sysfs
1457 dwc_otg_attr_create(_dev);
1460 * Disable the global interrupt until all the interrupt
1461 * handlers are installed.
1463 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1466 * Install the interrupt handler for the common interrupts before
1467 * enabling common interrupts in core_init below.
1469 irq = platform_get_irq(_dev, 0);
1470 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1471 retval = request_irq(irq, dwc_otg_common_irq,
1472 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1474 DWC_ERROR("request of irq%d failed\n", irq);
1478 dwc_otg_device->common_irq_installed = 1;
1482 * Initialize the DWC_otg core.
1483 * In order to reduce the time of initialization,
1484 * we do core soft reset after connection detected.
1486 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1489 * 0 - USB_MODE_NORMAL
1490 * 1 - USB_MODE_FORCE_HOST
1491 * 2 - USB_MODE_FORCE_DEVICE
1493 of_property_read_u32(node, "rockchip,usb-mode", &val);
1494 dwc_otg_device->core_if->usb_mode = val;
1496 #ifndef DWC_HOST_ONLY
1498 * Initialize the PCD
1500 retval = pcd_init(_dev);
1502 DWC_ERROR("pcd_init failed\n");
1503 dwc_otg_device->pcd = NULL;
1507 #ifndef DWC_DEVICE_ONLY
1509 * Initialize the HCD
1511 retval = otg20_hcd_init(_dev);
1513 DWC_ERROR("hcd_init failed\n");
1514 dwc_otg_device->hcd = NULL;
1519 * Enable the global interrupt after all the interrupt
1520 * handlers are installed if there is no ADP support else
1521 * perform initial actions required for Internal ADP logic.
1523 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1524 if (pldata->phy_status == USB_PHY_ENABLED) {
1525 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1527 pldata->clock_enable(pldata, 0);
1529 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1531 dwc_otg_adp_start(dwc_otg_device->core_if,
1532 dwc_otg_is_host_mode(dwc_otg_device->
1538 otg20_driver_remove(_dev);
1541 if (pldata->clock_enable)
1542 pldata->clock_enable(pldata, 0);
1547 static struct platform_driver dwc_otg_driver = {
1549 .name = (char *)dwc_otg20_driver_name,
1550 .of_match_table = of_match_ptr(usb20_otg_of_match),
1552 .probe = otg20_driver_probe,
1553 .remove = otg20_driver_remove,
1554 .suspend = dwc_otg_driver_suspend,
1555 .resume = dwc_otg_driver_resume,
1556 .shutdown = dwc_otg_driver_shutdown,
1560 void rk_usb_power_up(void)
1562 struct dwc_otg_platform_data *pldata_otg;
1563 struct dwc_otg_platform_data *pldata_host;
1564 struct rkehci_platform_data *pldata_ehci;
1565 if (cpu_is_rk312x()) {
1566 pldata_otg = &usb20otg_pdata_rk3126;
1567 if (usb_to_uart_status)
1568 pldata_otg->dwc_otg_uart_mode(pldata_otg, PHY_UART_MODE);
1570 if (cpu_is_rk3288()) {
1571 #ifdef CONFIG_RK_USB_UART
1572 /* enable USB bypass UART function */
1573 writel_relaxed(0x00c00000 | usb_to_uart_status,
1574 RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1577 /* unset siddq,the analog blocks are powered up */
1578 #ifdef CONFIG_USB20_OTG
1579 pldata_otg = &usb20otg_pdata_rk3288;
1581 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1582 writel_relaxed((0x01 << 13) << 16,
1584 RK3288_GRF_UOC0_CON0);
1587 #ifdef CONFIG_USB20_HOST
1588 pldata_host = &usb20host_pdata_rk3288;
1590 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1591 writel_relaxed((0x01 << 13) << 16,
1593 RK3288_GRF_UOC2_CON0);
1596 #ifdef CONFIG_USB_EHCI_RK
1597 pldata_ehci = &rkehci_pdata_rk3288;
1599 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1600 writel_relaxed((0x01 << 13) << 16,
1602 RK3288_GRF_UOC1_CON0);
1609 void rk_usb_power_down(void)
1611 struct dwc_otg_platform_data *pldata_otg;
1612 struct dwc_otg_platform_data *pldata_host;
1613 struct rkehci_platform_data *pldata_ehci;
1615 if (cpu_is_rk312x()) {
1616 pldata_otg = &usb20otg_pdata_rk3126;
1617 usb_to_uart_status = pldata_otg->get_status(USB_STATUS_UARTMODE);
1618 pldata_otg->dwc_otg_uart_mode(pldata_otg, PHY_USB_MODE);
1620 if (cpu_is_rk3288()) {
1621 #ifdef CONFIG_RK_USB_UART
1622 /* disable USB bypass UART function */
1623 usb_to_uart_status =
1624 readl_relaxed(RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1625 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1627 /* set siddq,the analog blocks are powered down
1629 * 1. Before asserting SIDDQ, ensure that VDATSRCENB0,
1630 * VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0,
1631 * and TESTBURNIN are set to 1'b0.
1632 * 2. Before asserting SIDDQ, ensure that phy enter suspend.*/
1633 #ifdef CONFIG_USB20_OTG
1634 pldata_otg = &usb20otg_pdata_rk3288;
1636 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1637 writel_relaxed((0x01 << 13) |
1638 ((0x01 << 13) << 16),
1640 RK3288_GRF_UOC0_CON0);
1643 #ifdef CONFIG_USB20_HOST
1644 pldata_host = &usb20host_pdata_rk3288;
1646 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1647 writel_relaxed((0x01 << 13) |
1648 ((0x01 << 13) << 16),
1650 RK3288_GRF_UOC2_CON0);
1653 #ifdef CONFIG_USB_EHCI_RK
1654 pldata_ehci = &rkehci_pdata_rk3288;
1656 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1657 writel_relaxed((0x01 << 13) |
1658 ((0x01 << 13) << 16),
1660 RK3288_GRF_UOC1_CON0);
1666 EXPORT_SYMBOL(rk_usb_power_up);
1667 EXPORT_SYMBOL(rk_usb_power_down);
1669 * This function is called when the dwc_otg_driver is installed with the
1670 * insmod command. It registers the dwc_otg_driver structure with the
1671 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1672 * to be called. In addition, the bus driver will automatically expose
1673 * attributes defined for the device and driver in the special sysfs file
1678 static int __init dwc_otg_driver_init(void)
1683 #ifdef CONFIG_USB20_OTG
1684 /* register otg20 */
1685 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1686 DWC_DRIVER_VERSION);
1688 retval = platform_driver_register(&dwc_otg_driver);
1690 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1695 driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1697 driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1699 driver_create_file(&dwc_otg_driver.driver,
1700 &driver_attr_dwc_otg_conn_en);
1702 driver_create_file(&dwc_otg_driver.driver,
1703 &driver_attr_vbus_status);
1705 driver_create_file(&dwc_otg_driver.driver,
1706 &driver_attr_force_usb_mode);
1708 driver_create_file(&dwc_otg_driver.driver,
1709 &driver_attr_op_state);
1713 /* register host20 */
1714 #ifdef CONFIG_USB20_HOST
1715 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1716 DWC_DRIVER_VERSION);
1718 retval = platform_driver_register(&dwc_host_driver);
1720 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1725 driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1727 driver_create_file(&dwc_host_driver.driver,
1728 &driver_attr_debuglevel);
1733 module_init(dwc_otg_driver_init);
1736 * This function is called when the driver is removed from the kernel
1737 * with the rmmod command. The driver unregisters itself with its bus
1741 static void __exit dwc_otg_driver_cleanup(void)
1743 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1745 #ifdef CONFIG_USB20_HOST
1747 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1748 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1749 platform_driver_unregister(&dwc_host_driver);
1750 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1753 #ifdef CONFIG_USB20_OTG
1755 driver_remove_file(&dwc_otg_driver.driver,
1756 &driver_attr_dwc_otg_conn_en);
1757 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1758 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1759 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1760 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1761 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_op_state);
1762 platform_driver_unregister(&dwc_otg_driver);
1763 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1767 module_exit(dwc_otg_driver_cleanup);
1769 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1770 MODULE_AUTHOR("Synopsys Inc.");
1771 MODULE_LICENSE("GPL");
1773 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1774 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1775 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1776 MODULE_PARM_DESC(opt, "OPT Mode");
1777 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1778 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1780 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1782 MODULE_PARM_DESC(dma_desc_enable,
1783 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1785 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1787 MODULE_PARM_DESC(dma_burst_size,
1788 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1789 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1790 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1791 module_param_named(host_support_fs_ls_low_power,
1792 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1794 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1795 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1796 module_param_named(host_ls_low_power_phy_clk,
1797 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1798 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1799 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1800 module_param_named(enable_dynamic_fifo,
1801 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1802 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1803 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1805 MODULE_PARM_DESC(data_fifo_size,
1806 "Total number of words in the data FIFO memory 32-32768");
1807 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1809 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1810 module_param_named(dev_nperio_tx_fifo_size,
1811 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1812 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1813 "Number of words in the non-periodic Tx FIFO 16-32768");
1814 module_param_named(dev_perio_tx_fifo_size_1,
1815 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1816 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1817 "Number of words in the periodic Tx FIFO 4-768");
1818 module_param_named(dev_perio_tx_fifo_size_2,
1819 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1820 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1821 "Number of words in the periodic Tx FIFO 4-768");
1822 module_param_named(dev_perio_tx_fifo_size_3,
1823 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1824 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1825 "Number of words in the periodic Tx FIFO 4-768");
1826 module_param_named(dev_perio_tx_fifo_size_4,
1827 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1828 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1829 "Number of words in the periodic Tx FIFO 4-768");
1830 module_param_named(dev_perio_tx_fifo_size_5,
1831 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1832 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1833 "Number of words in the periodic Tx FIFO 4-768");
1834 module_param_named(dev_perio_tx_fifo_size_6,
1835 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1836 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1837 "Number of words in the periodic Tx FIFO 4-768");
1838 module_param_named(dev_perio_tx_fifo_size_7,
1839 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1840 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1841 "Number of words in the periodic Tx FIFO 4-768");
1842 module_param_named(dev_perio_tx_fifo_size_8,
1843 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1844 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1845 "Number of words in the periodic Tx FIFO 4-768");
1846 module_param_named(dev_perio_tx_fifo_size_9,
1847 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1848 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1849 "Number of words in the periodic Tx FIFO 4-768");
1850 module_param_named(dev_perio_tx_fifo_size_10,
1851 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1852 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1853 "Number of words in the periodic Tx FIFO 4-768");
1854 module_param_named(dev_perio_tx_fifo_size_11,
1855 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1856 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1857 "Number of words in the periodic Tx FIFO 4-768");
1858 module_param_named(dev_perio_tx_fifo_size_12,
1859 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1860 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1861 "Number of words in the periodic Tx FIFO 4-768");
1862 module_param_named(dev_perio_tx_fifo_size_13,
1863 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1864 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1865 "Number of words in the periodic Tx FIFO 4-768");
1866 module_param_named(dev_perio_tx_fifo_size_14,
1867 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1868 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1869 "Number of words in the periodic Tx FIFO 4-768");
1870 module_param_named(dev_perio_tx_fifo_size_15,
1871 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1872 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1873 "Number of words in the periodic Tx FIFO 4-768");
1874 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1876 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1877 module_param_named(host_nperio_tx_fifo_size,
1878 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1879 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1880 "Number of words in the non-periodic Tx FIFO 16-32768");
1881 module_param_named(host_perio_tx_fifo_size,
1882 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1883 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1884 "Number of words in the host periodic Tx FIFO 16-32768");
1885 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1887 /** @todo Set the max to 512K, modify checks */
1888 MODULE_PARM_DESC(max_transfer_size,
1889 "The maximum transfer size supported in bytes 2047-65535");
1890 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1892 MODULE_PARM_DESC(max_packet_count,
1893 "The maximum number of packets in a transfer 15-511");
1894 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1896 MODULE_PARM_DESC(host_channels,
1897 "The number of host channel registers to use 1-16");
1898 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1900 MODULE_PARM_DESC(dev_endpoints,
1901 "The number of endpoints in addition to EP0 available for device mode 1-15");
1902 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1903 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1904 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1906 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1907 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1908 MODULE_PARM_DESC(phy_ulpi_ddr,
1909 "ULPI at double or single data rate 0=Single 1=Double");
1910 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1912 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1913 "ULPI PHY using internal or external vbus 0=Internal");
1914 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1915 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1916 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1917 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1918 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1919 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1920 module_param_named(debug, g_dbg_lvl, int, 0444);
1921 MODULE_PARM_DESC(debug, "");
1923 module_param_named(en_multiple_tx_fifo,
1924 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1925 MODULE_PARM_DESC(en_multiple_tx_fifo,
1926 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1927 module_param_named(dev_tx_fifo_size_1,
1928 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1929 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1930 module_param_named(dev_tx_fifo_size_2,
1931 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1932 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1933 module_param_named(dev_tx_fifo_size_3,
1934 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1935 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1936 module_param_named(dev_tx_fifo_size_4,
1937 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1938 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1939 module_param_named(dev_tx_fifo_size_5,
1940 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1941 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1942 module_param_named(dev_tx_fifo_size_6,
1943 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1944 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1945 module_param_named(dev_tx_fifo_size_7,
1946 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1947 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1948 module_param_named(dev_tx_fifo_size_8,
1949 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1950 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1951 module_param_named(dev_tx_fifo_size_9,
1952 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1953 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1954 module_param_named(dev_tx_fifo_size_10,
1955 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1956 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
1957 module_param_named(dev_tx_fifo_size_11,
1958 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1959 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
1960 module_param_named(dev_tx_fifo_size_12,
1961 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1962 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
1963 module_param_named(dev_tx_fifo_size_13,
1964 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1965 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
1966 module_param_named(dev_tx_fifo_size_14,
1967 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
1968 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
1969 module_param_named(dev_tx_fifo_size_15,
1970 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
1971 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
1973 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
1974 MODULE_PARM_DESC(thr_ctl,
1975 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
1976 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
1978 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
1979 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
1981 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
1983 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
1984 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
1985 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
1986 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
1988 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
1989 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
1990 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int,
1992 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
1993 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
1994 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
1996 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
1997 MODULE_PARM_DESC(ic_usb_cap,
1998 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
1999 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
2001 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
2002 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
2003 MODULE_PARM_DESC(power_down, "Power Down Mode");
2004 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
2005 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
2006 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
2007 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
2008 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
2009 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
2010 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
2011 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
2012 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
2013 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
2014 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
2015 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
2017 /** @page "Module Parameters"
2019 * The following parameters may be specified when starting the module.
2020 * These parameters define how the DWC_otg controller should be
2021 * configured. Parameter values are passed to the CIL initialization
2022 * function dwc_otg_cil_init
2024 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
2028 <tr><td>Parameter Name</td><td>Meaning</td></tr>
2032 <td>Specifies the OTG capabilities. The driver will automatically detect the
2033 value for this parameter if none is specified.
2034 - 0: HNP and SRP capable (default, if available)
2035 - 1: SRP Only capable
2036 - 2: No HNP/SRP capable
2041 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2042 The driver will automatically detect the value for this parameter if none is
2045 - 1: DMA (default, if available)
2049 <td>dma_burst_size</td>
2050 <td>The DMA Burst size (applicable only for External DMA Mode).
2051 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2056 <td>Specifies the maximum speed of operation in host and device mode. The
2057 actual speed depends on the speed of the attached device and the value of
2059 - 0: High Speed (default)
2064 <td>host_support_fs_ls_low_power</td>
2065 <td>Specifies whether low power mode is supported when attached to a Full
2066 Speed or Low Speed device in host mode.
2067 - 0: Don't support low power mode (default)
2068 - 1: Support low power mode
2072 <td>host_ls_low_power_phy_clk</td>
2073 <td>Specifies the PHY clock rate in low power mode when connected to a Low
2074 Speed device in host mode. This parameter is applicable only if
2075 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2076 - 0: 48 MHz (default)
2081 <td>enable_dynamic_fifo</td>
2082 <td> Specifies whether FIFOs may be resized by the driver software.
2083 - 0: Use cC FIFO size parameters
2084 - 1: Allow dynamic FIFO sizing (default)
2088 <td>data_fifo_size</td>
2089 <td>Total number of 4-byte words in the data FIFO memory. This memory
2090 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2091 - Values: 32 to 32768 (default 8192)
2093 Note: The total FIFO memory depth in the FPGA configuration is 8192.
2097 <td>dev_rx_fifo_size</td>
2098 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2099 FIFO sizing is enabled.
2100 - Values: 16 to 32768 (default 1064)
2104 <td>dev_nperio_tx_fifo_size</td>
2105 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2106 dynamic FIFO sizing is enabled.
2107 - Values: 16 to 32768 (default 1024)
2111 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2112 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2113 when dynamic FIFO sizing is enabled.
2114 - Values: 4 to 768 (default 256)
2118 <td>host_rx_fifo_size</td>
2119 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2121 - Values: 16 to 32768 (default 1024)
2125 <td>host_nperio_tx_fifo_size</td>
2126 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2127 dynamic FIFO sizing is enabled in the core.
2128 - Values: 16 to 32768 (default 1024)
2132 <td>host_perio_tx_fifo_size</td>
2133 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2135 - Values: 16 to 32768 (default 1024)
2139 <td>max_transfer_size</td>
2140 <td>The maximum transfer size supported in bytes.
2141 - Values: 2047 to 65,535 (default 65,535)
2145 <td>max_packet_count</td>
2146 <td>The maximum number of packets in a transfer.
2147 - Values: 15 to 511 (default 511)
2151 <td>host_channels</td>
2152 <td>The number of host channel registers to use.
2153 - Values: 1 to 16 (default 12)
2155 Note: The FPGA configuration supports a maximum of 12 host channels.
2159 <td>dev_endpoints</td>
2160 <td>The number of endpoints in addition to EP0 available for device mode
2162 - Values: 1 to 15 (default 6 IN and OUT)
2164 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2170 <td>Specifies the type of PHY interface to use. By default, the driver will
2171 automatically detect the phy_type.
2173 - 1: UTMI+ (default, if available)
2178 <td>phy_utmi_width</td>
2179 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2180 phy_type of UTMI+. Also, this parameter is applicable only if the
2181 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2182 core has been configured to work at either data path width.
2183 - Values: 8 or 16 bits (default 16)
2187 <td>phy_ulpi_ddr</td>
2188 <td>Specifies whether the ULPI operates at double or single data rate. This
2189 parameter is only applicable if phy_type is ULPI.
2190 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2191 - 1: double data rate ULPI interface with 4 bit wide data bus
2196 <td>Specifies whether to use the I2C interface for full speed PHY. This
2197 parameter is only applicable if PHY_TYPE is FS.
2198 - 0: Disabled (default)
2204 <td>Specifies whether to use ULPI FS/LS mode only.
2205 - 0: Disabled (default)
2211 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2212 - 0: Disabled (default)
2217 <td>en_multiple_tx_fifo</td>
2218 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2219 The driver will automatically detect the value for this parameter if none is
2222 - 1: Enabled (default, if available)
2226 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2227 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2228 when dynamic FIFO sizing is enabled.
2229 - Values: 4 to 768 (default 256)
2233 <td>tx_thr_length</td>
2234 <td>Transmit Threshold length in 32 bit double words
2235 - Values: 8 to 128 (default 64)
2239 <td>rx_thr_length</td>
2240 <td>Receive Threshold length in 32 bit double words
2241 - Values: 8 to 128 (default 64)
2246 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2247 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2248 Rx transfers accordingly.
2249 The driver will automatically detect the value for this parameter if none is
2251 - Values: 0 to 7 (default 0)
2252 Bit values indicate:
2253 - 0: Thresholding disabled
2254 - 1: Thresholding enabled
2258 <td>dma_desc_enable</td>
2259 <td>Specifies whether to enable Descriptor DMA mode.
2260 The driver will automatically detect the value for this parameter if none is
2262 - 0: Descriptor DMA disabled
2263 - 1: Descriptor DMA (default, if available)
2268 <td>Specifies whether to enable MPI enhancement mode.
2269 The driver will automatically detect the value for this parameter if none is
2271 - 0: MPI disabled (default)
2277 <td>Specifies whether to enable PTI enhancement support.
2278 The driver will automatically detect the value for this parameter if none is
2280 - 0: PTI disabled (default)
2286 <td>Specifies whether to enable LPM support.
2287 The driver will automatically detect the value for this parameter if none is
2290 - 1: LPM enable (default, if available)
2294 <td>besl_enable</td>
2295 <td>Specifies whether to enable LPM Errata support.
2296 The driver will automatically detect the value for this parameter if none is
2298 - 0: LPM Errata disabled (default)
2299 - 1: LPM Errata enable
2303 <td>baseline_besl</td>
2304 <td>Specifies the baseline besl value.
2305 - Values: 0 to 15 (default 0)
2310 <td>Specifies the deep besl value.
2311 - Values: 0 to 15 (default 15)
2316 <td>Specifies whether to enable IC_USB capability.
2317 The driver will automatically detect the value for this parameter if none is
2319 - 0: IC_USB disabled (default, if available)
2324 <td>ahb_thr_ratio</td>
2325 <td>Specifies AHB Threshold ratio.
2326 - Values: 0 to 3 (default 0)
2331 <td>Specifies Power Down(Hibernation) Mode.
2332 The driver will automatically detect the value for this parameter if none is
2334 - 0: Power Down disabled (default)
2335 - 2: Power Down enabled
2340 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2341 run time. The driver will automatically detect the value for this parameter if
2342 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2343 the core might misbehave.
2344 - 0: Reload Control disabled (default)
2345 - 1: Reload Control enabled
2349 <td>dev_out_nak</td>
2350 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2351 The driver will automatically detect the value for this parameter if
2352 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2353 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2354 - 1: The core sets NAK after Bulk OUT transfer complete
2358 <td>cont_on_bna</td>
2359 <td>Specifies whether Enable Continue on BNA enabled or no.
2360 After receiving BNA interrupt the core disables the endpoint,when the
2361 endpoint is re-enabled by the application the
2362 - 0: Core starts processing from the DOEPDMA descriptor (default)
2363 - 1: Core starts processing from the descriptor which received the BNA.
2364 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2369 <td>This bit when programmed supports SINGLE transfers for remainder data
2370 in a transfer for DMA mode of operation.
2371 - 0: The remainder data will be sent using INCR burst size (default)
2372 - 1: The remainder data will be sent using SINGLE burst size.
2377 <td>Specifies whether ADP feature is enabled.
2378 The driver will automatically detect the value for this parameter if none is
2380 - 0: ADP feature disabled (default)
2381 - 1: ADP feature enabled
2386 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2388 - 0: OTG 2.0 support disabled (default)
2389 - 1: OTG 2.0 support enabled