drivers/usb/dwc_otg_310/dwc_otg_hcd.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
   3  * $Revision: #106 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 /** @file
  36  * This file implements HCD Core. All code in this file is portable and doesn't
  37  * use any OS specific functions.
  38  * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
  39  * header file.
  40  */
  41
  42 #include "dwc_otg_hcd.h"
  43 #include "dwc_otg_regs.h"
  44 #include "usbdev_rk.h"
  45 #include "dwc_otg_driver.h"
  46 #include <linux/usb.h>
  47 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
  48 #include <../drivers/usb/core/hcd.h>
  49 #else
  50 #include <linux/usb/hcd.h>
  51 #endif
  52
  53 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
  54 {
  55         return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
  56 }
  57
  58 /**
  59  * Connection timeout function.  An OTG host is required to display a
  60  * message if the device does not connect within 10 seconds.
  61  */
  62 void dwc_otg_hcd_connect_timeout(void *ptr)
  63 {
  64         dwc_otg_hcd_t *hcd;
  65         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
  66         DWC_PRINTF("Connect Timeout\n");
  67         __DWC_ERROR("Device Not Connected/Responding\n");
  68         /** Remove buspower after 10s */
  69         hcd = ptr;
  70         if (hcd->core_if->otg_ver)
  71                 dwc_otg_set_prtpower(hcd->core_if, 0);
  72 }
  73
  74 #ifdef DEBUG
  75 static void dump_channel_info(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
  76 {
  77         if (qh->channel != NULL) {
  78                 dwc_hc_t *hc = qh->channel;
  79                 dwc_list_link_t *item;
  80                 dwc_otg_qh_t *qh_item;
  81                 int num_channels = hcd->core_if->core_params->host_channels;
  82                 int i;
  83
  84                 dwc_otg_hc_regs_t *hc_regs;
  85                 hcchar_data_t hcchar;
  86                 hcsplt_data_t hcsplt;
  87                 hctsiz_data_t hctsiz;
  88                 uint32_t hcdma;
  89
  90                 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
  91                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
  92                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
  93                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
  94                 hcdma = DWC_READ_REG32(&hc_regs->hcdma);
  95
  96                 DWC_PRINTF("  Assigned to channel %p:\n", hc);
  97                 DWC_PRINTF("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
  98                            hcsplt.d32);
  99                 DWC_PRINTF("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
 100                            hcdma);
 101                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
 102                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
 103                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
 104                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
 105                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
 106                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
 107                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
 108                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
 109                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
 110                 DWC_PRINTF("    qh: %p\n", hc->qh);
 111                 DWC_PRINTF("  NP inactive sched:\n");
 112                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
 113                         qh_item =
 114                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 115                         DWC_PRINTF("    %p\n", qh_item);
 116                 }
 117                 DWC_PRINTF("  NP active sched:\n");
 118                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
 119                         qh_item =
 120                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 121                         DWC_PRINTF("    %p\n", qh_item);
 122                 }
 123                 DWC_PRINTF("  Channels: \n");
 124                 for (i = 0; i < num_channels; i++) {
 125                         dwc_hc_t *hc = hcd->hc_ptr_array[i];
 126                         DWC_PRINTF("    %2d: %p\n", i, hc);
 127                 }
 128         }
 129 }
 130 #endif /* DEBUG */
 131
 132 /**
 133  * Work queue function for starting the HCD when A-Cable is connected.
 134  * The hcd_start() must be called in a process context.
 135  */
 136 static void hcd_start_func(void *_vp)
 137 {
 138         dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
 139
 140         DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
 141         if (hcd) {
 142                 hcd->fops->start(hcd);
 143         }
 144 }
 145
 146 static void del_xfer_timers(dwc_otg_hcd_t *hcd)
 147 {
 148 #ifdef DEBUG
 149         int i;
 150         int num_channels = hcd->core_if->core_params->host_channels;
 151         for (i = 0; i < num_channels; i++) {
 152                 DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
 153         }
 154 #endif
 155 }
 156
 157 static void del_timers(dwc_otg_hcd_t *hcd)
 158 {
 159         del_xfer_timers(hcd);
 160         DWC_TIMER_CANCEL(hcd->conn_timer);
 161 }
 162
 163 /**
 164  * Processes all the URBs in a single list of QHs. Completes them with
 165  * -ETIMEDOUT and frees the QTD.
 166  */
 167 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
 168 {
 169         dwc_list_link_t *qh_item;
 170         dwc_otg_qh_t *qh;
 171         dwc_otg_qtd_t *qtd, *qtd_tmp;
 172
 173         DWC_LIST_FOREACH(qh_item, qh_list) {
 174                 qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
 175                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
 176                                          &qh->qtd_list, qtd_list_entry) {
 177                         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
 178                         if (qtd->urb != NULL) {
 179                                 hcd->fops->complete(hcd, qtd->urb->priv,
 180                                                     qtd->urb, -DWC_E_SHUTDOWN);
 181                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
 182                         }
 183
 184                 }
 185         }
 186 }
 187
 188 /**
 189  * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
 190  * and periodic schedules. The QTD associated with each URB is removed from
 191  * the schedule and freed. This function may be called when a disconnect is
 192  * detected or when the HCD is being stopped.
 193  */
 194 static void kill_all_urbs(dwc_otg_hcd_t *hcd)
 195 {
 196         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
 197         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
 198         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
 199         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
 200         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
 201         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
 202 }
 203
 204 /**
 205  * Start the connection timer.  An OTG host is required to display a
 206  * message if the device does not connect within 10 seconds.  The
 207  * timer is deleted if a port connect interrupt occurs before the
 208  * timer expires.
 209  */
 210 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd)
 211 {
 212         DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */);
 213 }
 214
 215 /**
 216  * HCD Callback function for disconnect of the HCD.
 217  *
 218  * @param p void pointer to the <code>struct usb_hcd</code>
 219  */
 220 static int32_t dwc_otg_hcd_session_start_cb(void *p)
 221 {
 222         dwc_otg_hcd_t *dwc_otg_hcd;
 223         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
 224         dwc_otg_hcd = p;
 225         dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
 226         return 1;
 227 }
 228
 229 /**
 230  * HCD Callback function for starting the HCD when A-Cable is
 231  * connected.
 232  *
 233  * @param p void pointer to the <code>struct usb_hcd</code>
 234  */
 235 static int32_t dwc_otg_hcd_start_cb(void *p)
 236 {
 237         dwc_otg_hcd_t *dwc_otg_hcd = p;
 238         dwc_otg_core_if_t *core_if;
 239         hprt0_data_t hprt0;
 240         uint32_t timeout = 50;
 241
 242         core_if = dwc_otg_hcd->core_if;
 243
 244         if (core_if->op_state == B_HOST) {
 245                 /*
 246                  * Reset the port.  During a HNP mode switch the reset
 247                  * needs to occur within 1ms and have a duration of at
 248                  * least 50ms.
 249                  */
 250                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
 251                 hprt0.b.prtrst = 1;
 252                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 253                 if (core_if->otg_ver) {
 254                         dwc_mdelay(60);
 255                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 256                         hprt0.b.prtrst = 0;
 257                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 258                 }
 259         }
 260         /**@todo vahrama: Check the timeout value for OTG 2.0 */
 261         if (core_if->otg_ver)
 262                 timeout = 25;
 263         DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
 264                                    hcd_start_func, dwc_otg_hcd, timeout,
 265                                    "start hcd");
 266
 267         return 1;
 268 }
 269
 270 /**
 271  * HCD Callback function for disconnect of the HCD.
 272  *
 273  * @param p void pointer to the <code>struct usb_hcd</code>
 274  */
 275 static int32_t dwc_otg_hcd_disconnect_cb(void *p)
 276 {
 277         gintsts_data_t intr;
 278         dwc_otg_hcd_t *dwc_otg_hcd = p;
 279         hprt0_data_t hprt0;
 280
 281         dwc_otg_hcd->non_periodic_qh_ptr = &dwc_otg_hcd->non_periodic_sched_active;
 282         dwc_otg_hcd->non_periodic_channels = 0;
 283         dwc_otg_hcd->periodic_channels = 0;
 284         dwc_otg_hcd->frame_number =0;
 285
 286         hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 287         /* In some case, we don't disconnect a usb device, but
 288          * disconnect intr was triggered, so check hprt0 here. */
 289         if ((!hprt0.b.prtenchng)
 290             && (!hprt0.b.prtconndet)
 291             && hprt0.b.prtconnsts) {
 292                 DWC_PRINTF("%s: hprt0 = 0x%08x\n", __func__, hprt0.d32);
 293                 return 1;
 294         }
 295         /*
 296          * Set status flags for the hub driver.
 297          */
 298         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 299         dwc_otg_hcd->flags.b.port_connect_status = 0;
 300
 301         /*
 302          * Shutdown any transfers in process by clearing the Tx FIFO Empty
 303          * interrupt mask and status bits and disabling subsequent host
 304          * channel interrupts.
 305          */
 306         intr.d32 = 0;
 307         intr.b.nptxfempty = 1;
 308         intr.b.ptxfempty = 1;
 309         intr.b.hcintr = 1;
 310         DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
 311                          intr.d32, 0);
 312         DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
 313                          intr.d32, 0);
 314
 315         /*
 316          * Turn off the vbus power only if the core has transitioned to device
 317          * mode. If still in host mode, need to keep power on to detect a
 318          * reconnection.
 319          */
 320         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
 321                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
 322                         hprt0_data_t hprt0 = {.d32 = 0 };
 323                         DWC_PRINTF("Disconnect: PortPower off\n");
 324                         hprt0.b.prtpwr = 0;
 325                         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
 326                                         hprt0.d32);
 327                 }
 328                 /** Delete timers if become device */
 329                 del_timers(dwc_otg_hcd);
 330                 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
 331                 goto out;
 332         }
 333
 334         /* Respond with an error status to all URBs in the schedule. */
 335         kill_all_urbs(dwc_otg_hcd);
 336
 337         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
 338                 /* Clean up any host channels that were in use. */
 339                 int num_channels;
 340                 int i;
 341                 dwc_hc_t *channel;
 342                 dwc_otg_hc_regs_t *hc_regs;
 343                 hcchar_data_t hcchar;
 344
 345                 DWC_PRINTF("Disconnect cb-Host\n");
 346                 if (dwc_otg_hcd->core_if->otg_ver == 1)
 347                         del_xfer_timers(dwc_otg_hcd);
 348                 else
 349                         del_timers(dwc_otg_hcd);
 350
 351                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 352
 353                 if (!dwc_otg_hcd->core_if->dma_enable) {
 354                         /* Flush out any channel requests in slave mode. */
 355                         for (i = 0; i < num_channels; i++) {
 356                                 channel = dwc_otg_hcd->hc_ptr_array[i];
 357                                 if (DWC_CIRCLEQ_EMPTY_ENTRY
 358                                     (channel, hc_list_entry)) {
 359                                         hc_regs =
 360                                             dwc_otg_hcd->core_if->host_if->
 361                                             hc_regs[i];
 362                                         hcchar.d32 =
 363                                             DWC_READ_REG32(&hc_regs->hcchar);
 364                                         if (hcchar.b.chen) {
 365                                                 hcchar.b.chen = 0;
 366                                                 hcchar.b.chdis = 1;
 367                                                 hcchar.b.epdir = 0;
 368                                                 DWC_WRITE_REG32
 369                                                     (&hc_regs->hcchar,
 370                                                      hcchar.d32);
 371                                         }
 372                                 }
 373                         }
 374                 }
 375
 376                 for (i = 0; i < num_channels; i++) {
 377                         channel = dwc_otg_hcd->hc_ptr_array[i];
 378                         if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
 379                                 hc_regs =
 380                                     dwc_otg_hcd->core_if->host_if->hc_regs[i];
 381                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
 382                                 if (hcchar.b.chen) {
 383                                         /* Halt the channel. */
 384                                         hcchar.b.chdis = 1;
 385                                         DWC_WRITE_REG32(&hc_regs->hcchar,
 386                                                         hcchar.d32);
 387                                 }
 388
 389                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
 390                                                    channel);
 391                                 DWC_CIRCLEQ_INSERT_TAIL
 392                                     (&dwc_otg_hcd->free_hc_list, channel,
 393                                      hc_list_entry);
 394                                 /*
 395                                  * Added for Descriptor DMA to prevent channel double cleanup
 396                                  * in release_channel_ddma(). Which called from ep_disable
 397                                  * when device disconnect.
 398                                  */
 399                                 channel->qh = NULL;
 400                         }
 401                 }
 402         }
 403
 404 out:
 405         if (dwc_otg_hcd->fops->disconnect) {
 406                 dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
 407         }
 408
 409         return 1;
 410 }
 411
 412 /**
 413  * HCD Callback function for stopping the HCD.
 414  *
 415  * @param p void pointer to the <code>struct usb_hcd</code>
 416  */
 417 static int32_t dwc_otg_hcd_stop_cb(void *p)
 418 {
 419         dwc_otg_hcd_t *dwc_otg_hcd = p;
 420
 421         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
 422         dwc_otg_hcd_stop(dwc_otg_hcd);
 423         return 1;
 424 }
 425
 426 #ifdef CONFIG_USB_DWC_OTG_LPM
 427 /**
 428  * HCD Callback function for sleep of HCD.
 429  *
 430  * @param p void pointer to the <code>struct usb_hcd</code>
 431  */
 432 static int dwc_otg_hcd_sleep_cb(void *p)
 433 {
 434         dwc_otg_hcd_t *hcd = p;
 435
 436         dwc_otg_hcd_free_hc_from_lpm(hcd);
 437
 438         return 0;
 439 }
 440 #endif
 441
 442 /**
 443  * HCD Callback function for Remote Wakeup.
 444  *
 445  * @param p void pointer to the <code>struct usb_hcd</code>
 446  */
 447 static int dwc_otg_hcd_rem_wakeup_cb(void *p)
 448 {
 449         dwc_otg_hcd_t *dwc_otg_hcd = p;
 450         struct usb_hcd *hcd = dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
 451
 452         if (dwc_otg_hcd->core_if->lx_state == DWC_OTG_L2) {
 453                 dwc_otg_hcd->flags.b.port_suspend_change = 1;
 454                 usb_hcd_resume_root_hub(hcd);
 455         }
 456 #ifdef CONFIG_USB_DWC_OTG_LPM
 457         else {
 458                 dwc_otg_hcd->flags.b.port_l1_change = 1;
 459         }
 460 #endif
 461         return 0;
 462 }
 463
 464 /**
 465  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
 466  * stopped.
 467  */
 468 void dwc_otg_hcd_stop(dwc_otg_hcd_t *hcd)
 469 {
 470         hprt0_data_t hprt0 = {.d32 = 0 };
 471         struct dwc_otg_platform_data *pldata;
 472         pldata = hcd->core_if->otg_dev->pldata;
 473
 474         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
 475
 476         /*
 477          * The root hub should be disconnected before this function is called.
 478          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
 479          * and the QH lists (via ..._hcd_endpoint_disable).
 480          */
 481
 482         /* Turn off all host-specific interrupts. */
 483         dwc_otg_disable_host_interrupts(hcd->core_if);
 484
 485         /* Turn off the vbus power */
 486         DWC_PRINTF("PortPower off\n");
 487         hprt0.b.prtpwr = 0;
 488         DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
 489
 490         if (pldata->power_enable)
 491                 pldata->power_enable(0);
 492
 493         dwc_mdelay(1);
 494 }
 495
 496 int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t *hcd,
 497                             dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle,
 498                             int atomic_alloc)
 499 {
 500         dwc_irqflags_t flags;
 501         int retval = 0;
 502         dwc_otg_qtd_t *qtd;
 503         gintmsk_data_t intr_mask = {.d32 = 0 };
 504
 505         if (!hcd->flags.b.port_connect_status) {
 506                 /* No longer connected. */
 507                 DWC_DEBUG("Not connected\n");
 508                 return -DWC_E_NO_DEVICE;
 509         }
 510
 511         qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
 512         if (qtd == NULL) {
 513                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
 514                 return -DWC_E_NO_MEMORY;
 515         }
 516         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 517         retval =
 518             dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, 1);
 519
 520         if (retval < 0) {
 521                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
 522                           "Error status %d\n", retval);
 523                 dwc_otg_hcd_qtd_free(qtd);
 524         }
 525         intr_mask.d32 =
 526             DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
 527         if (!intr_mask.b.sofintr && retval == 0) {
 528                 dwc_otg_transaction_type_e tr_type;
 529                 if ((qtd->qh->ep_type == UE_BULK)
 530                     && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
 531                         /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
 532                         retval = 0;
 533                         goto out;
 534                 }
 535                 tr_type = dwc_otg_hcd_select_transactions(hcd);
 536                 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 537                         dwc_otg_hcd_queue_transactions(hcd, tr_type);
 538                 }
 539         }
 540 out:
 541         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 542         return retval;
 543 }
 544
 545 int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t *hcd,
 546                             dwc_otg_hcd_urb_t *dwc_otg_urb)
 547 {
 548         dwc_otg_qh_t *qh;
 549         dwc_otg_qtd_t *urb_qtd;
 550
 551         urb_qtd = dwc_otg_urb->qtd;
 552         if (((uint32_t) urb_qtd & 0xf0000000) == 0) {
 553                 DWC_PRINTF("%s error: urb_qtd is %p dwc_otg_urb %p!!!\n",
 554                            __func__, urb_qtd, dwc_otg_urb);
 555                 return 0;
 556         }
 557         qh = urb_qtd->qh;
 558 #ifdef DEBUG
 559         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
 560                 if (urb_qtd->in_process) {
 561                         dump_channel_info(hcd, qh);
 562                 }
 563         }
 564 #endif
 565         if (urb_qtd->in_process && qh->channel) {
 566                 /* The QTD is in process (it has been assigned to a channel). */
 567                 if (hcd->flags.b.port_connect_status) {
 568                         /*
 569                          * If still connected (i.e. in host mode), halt the
 570                          * channel so it can be used for other transfers. If
 571                          * no longer connected, the host registers can't be
 572                          * written to halt the channel since the core is in
 573                          * device mode.
 574                          */
 575                         dwc_otg_hc_halt(hcd->core_if, qh->channel,
 576                                         DWC_OTG_HC_XFER_URB_DEQUEUE);
 577                 }
 578         }
 579
 580         /*
 581          * Free the QTD and clean up the associated QH. Leave the QH in the
 582          * schedule if it has any remaining QTDs.
 583          */
 584
 585         if (!hcd->core_if->dma_desc_enable) {
 586                 uint8_t b = urb_qtd->in_process;
 587                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
 588                 if (b) {
 589                         dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
 590                         qh->channel = NULL;
 591                 } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
 592                         dwc_otg_hcd_qh_remove(hcd, qh);
 593                 }
 594         } else {
 595                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
 596         }
 597         return 0;
 598 }
 599
 600 int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t *hcd, void *ep_handle,
 601                                  int retry)
 602 {
 603         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
 604         int retval = 0;
 605         dwc_irqflags_t flags;
 606
 607         if (retry < 0) {
 608                 retval = -DWC_E_INVALID;
 609                 goto done;
 610         }
 611
 612         if (!qh) {
 613                 retval = -DWC_E_INVALID;
 614                 goto done;
 615         }
 616
 617         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 618
 619         while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
 620                 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 621                 retry--;
 622                 dwc_msleep(5);
 623                 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 624         }
 625
 626         dwc_otg_hcd_qh_remove(hcd, qh);
 627
 628         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 629         /*
 630          * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
 631          * and qh_free to prevent stack dump on DWC_DMA_FREE() with
 632          * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
 633          * and dwc_otg_hcd_frame_list_alloc().
 634          */
 635         dwc_otg_hcd_qh_free(hcd, qh);
 636
 637 done:
 638         return retval;
 639 }
 640
 641 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)
 642 int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t *hcd, void *ep_handle)
 643 {
 644         int retval = 0;
 645         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
 646         if (!qh)
 647                 return -DWC_E_INVALID;
 648
 649         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
 650         return retval;
 651 }
 652 #endif
 653
 654 /**
 655  * HCD Callback structure for handling mode switching.
 656  */
 657 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
 658         .start = dwc_otg_hcd_start_cb,
 659         .stop = dwc_otg_hcd_stop_cb,
 660         .disconnect = dwc_otg_hcd_disconnect_cb,
 661         .session_start = dwc_otg_hcd_session_start_cb,
 662         .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
 663 #ifdef CONFIG_USB_DWC_OTG_LPM
 664         .sleep = dwc_otg_hcd_sleep_cb,
 665 #endif
 666         .p = 0,
 667 };
 668
 669 /**
 670  * Reset tasklet function
 671  */
 672 static void reset_tasklet_func(void *data)
 673 {
 674         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
 675         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 676         hprt0_data_t hprt0;
 677
 678         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
 679
 680         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 681         hprt0.b.prtrst = 1;
 682         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 683         dwc_mdelay(60);
 684
 685         hprt0.b.prtrst = 0;
 686         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 687         dwc_otg_hcd->flags.b.port_reset_change = 1;
 688 }
 689
 690 static void qh_list_free(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
 691 {
 692         dwc_list_link_t *item;
 693         dwc_otg_qh_t *qh;
 694         dwc_irqflags_t flags;
 695
 696         if (!qh_list->next) {
 697                 /* The list hasn't been initialized yet. */
 698                 return;
 699         }
 700         /*
 701          * Hold spinlock here. Not needed in that case if bellow
 702          * function is being called from ISR
 703          */
 704         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 705         /* Ensure there are no QTDs or URBs left. */
 706         kill_urbs_in_qh_list(hcd, qh_list);
 707         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 708
 709         DWC_LIST_FOREACH(item, qh_list) {
 710                 qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 711                 dwc_otg_hcd_qh_remove_and_free(hcd, qh);
 712         }
 713 }
 714
 715 /**
 716  * Exit from Hibernation if Host did not detect SRP from connected SRP capable
 717  * Device during SRP time by host power up.
 718  */
 719 void dwc_otg_hcd_power_up(void *ptr)
 720 {
 721         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 722         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
 723
 724         DWC_PRINTF("%s called\n", __FUNCTION__);
 725
 726         if (!core_if->hibernation_suspend) {
 727                 DWC_PRINTF("Already exited from Hibernation\n");
 728                 return;
 729         }
 730
 731         /* Switch on the voltage to the core */
 732         gpwrdn.b.pwrdnswtch = 1;
 733         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 734         dwc_udelay(10);
 735
 736         /* Reset the core */
 737         gpwrdn.d32 = 0;
 738         gpwrdn.b.pwrdnrstn = 1;
 739         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 740         dwc_udelay(10);
 741
 742         /* Disable power clamps */
 743         gpwrdn.d32 = 0;
 744         gpwrdn.b.pwrdnclmp = 1;
 745         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 746
 747         /* Remove reset the core signal */
 748         gpwrdn.d32 = 0;
 749         gpwrdn.b.pwrdnrstn = 1;
 750         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 751         dwc_udelay(10);
 752
 753         /* Disable PMU interrupt */
 754         gpwrdn.d32 = 0;
 755         gpwrdn.b.pmuintsel = 1;
 756         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 757
 758         core_if->hibernation_suspend = 0;
 759
 760         /* Disable PMU */
 761         gpwrdn.d32 = 0;
 762         gpwrdn.b.pmuactv = 1;
 763         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 764         dwc_udelay(10);
 765
 766         /* Enable VBUS */
 767         gpwrdn.d32 = 0;
 768         gpwrdn.b.dis_vbus = 1;
 769         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 770
 771         core_if->op_state = A_HOST;
 772         dwc_otg_core_init(core_if);
 773         dwc_otg_enable_global_interrupts(core_if);
 774         cil_hcd_start(core_if);
 775 }
 776
 777 /**
 778  * Frees secondary storage associated with the dwc_otg_hcd structure contained
 779  * in the struct usb_hcd field.
 780  */
 781 static void dwc_otg_hcd_free(dwc_otg_hcd_t *dwc_otg_hcd)
 782 {
 783         int i;
 784
 785         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
 786
 787         del_timers(dwc_otg_hcd);
 788
 789         /* Free memory for QH/QTD lists */
 790         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
 791         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
 792         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
 793         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
 794         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
 795         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
 796
 797         /* Free memory for the host channels. */
 798         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 799                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
 800
 801 #ifdef DEBUG
 802                 if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
 803                         DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 804                 }
 805 #endif
 806                 if (hc != NULL) {
 807                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
 808                                     i, hc);
 809                         DWC_FREE(hc);
 810                 }
 811         }
 812
 813         if (dwc_otg_hcd->core_if->dma_enable) {
 814                 if (dwc_otg_hcd->status_buf_dma) {
 815                         DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
 816                                      dwc_otg_hcd->status_buf,
 817                                      dwc_otg_hcd->status_buf_dma);
 818                 }
 819         } else if (dwc_otg_hcd->status_buf != NULL) {
 820                 DWC_FREE(dwc_otg_hcd->status_buf);
 821         }
 822         DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
 823         /* Set core_if's lock pointer to NULL */
 824         dwc_otg_hcd->core_if->lock = NULL;
 825
 826         DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
 827         DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
 828
 829 #ifdef DWC_DEV_SRPCAP
 830         if (dwc_otg_hcd->core_if->power_down == 2 &&
 831             dwc_otg_hcd->core_if->pwron_timer) {
 832                 DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
 833         }
 834 #endif
 835         DWC_FREE(dwc_otg_hcd);
 836 }
 837
 838 int dwc_otg_hcd_init(dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
 839 {
 840         int retval = 0;
 841         int num_channels;
 842         int i;
 843         dwc_hc_t *channel;
 844
 845         hcd->lock = DWC_SPINLOCK_ALLOC();
 846         if (!hcd->lock) {
 847                 DWC_ERROR("Could not allocate lock for pcd");
 848                 DWC_FREE(hcd);
 849                 retval = -DWC_E_NO_MEMORY;
 850                 goto out;
 851         }
 852         hcd->core_if = core_if;
 853
 854         /* Register the HCD CIL Callbacks */
 855         dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
 856                                            &hcd_cil_callbacks, hcd);
 857
 858         /* Initialize the non-periodic schedule. */
 859         DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
 860         DWC_LIST_INIT(&hcd->non_periodic_sched_active);
 861
 862         /* Initialize the periodic schedule. */
 863         DWC_LIST_INIT(&hcd->periodic_sched_inactive);
 864         DWC_LIST_INIT(&hcd->periodic_sched_ready);
 865         DWC_LIST_INIT(&hcd->periodic_sched_assigned);
 866         DWC_LIST_INIT(&hcd->periodic_sched_queued);
 867
 868         /*
 869          * Create a host channel descriptor for each host channel implemented
 870          * in the controller. Initialize the channel descriptor array.
 871          */
 872         DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
 873         num_channels = hcd->core_if->core_params->host_channels;
 874         DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
 875         for (i = 0; i < num_channels; i++) {
 876                 channel = DWC_ALLOC(sizeof(dwc_hc_t));
 877                 if (channel == NULL) {
 878                         retval = -DWC_E_NO_MEMORY;
 879                         DWC_ERROR("%s: host channel allocation failed\n",
 880                                   __func__);
 881                         dwc_otg_hcd_free(hcd);
 882                         goto out;
 883                 }
 884                 channel->hc_num = i;
 885                 hcd->hc_ptr_array[i] = channel;
 886 #ifdef DEBUG
 887                 hcd->core_if->hc_xfer_timer[i] =
 888                     DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
 889                                     &hcd->core_if->hc_xfer_info[i]);
 890 #endif
 891                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
 892                             channel);
 893         }
 894
 895         /* Initialize the Connection timeout timer. */
 896         hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
 897                                           dwc_otg_hcd_connect_timeout, hcd);
 898
 899         /* Initialize reset tasklet. */
 900         hcd->reset_tasklet =
 901             DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
 902 #ifdef DWC_DEV_SRPCAP
 903         if (hcd->core_if->power_down == 2) {
 904                 /* Initialize Power on timer for Host power up in case hibernation */
 905                 hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
 906                                                             dwc_otg_hcd_power_up,
 907                                                             core_if);
 908         }
 909 #endif
 910
 911         /*
 912          * Allocate space for storing data on status transactions. Normally no
 913          * data is sent, but this space acts as a bit bucket. This must be
 914          * done after usb_add_hcd since that function allocates the DMA buffer
 915          * pool.
 916          */
 917         if (hcd->core_if->dma_enable) {
 918                 hcd->status_buf =
 919                     DWC_DMA_ALLOC_ATOMIC(DWC_OTG_HCD_STATUS_BUF_SIZE,
 920                                          &hcd->status_buf_dma);
 921         } else {
 922                 hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
 923         }
 924         if (!hcd->status_buf) {
 925                 retval = -DWC_E_NO_MEMORY;
 926                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 927                 dwc_otg_hcd_free(hcd);
 928                 goto out;
 929         }
 930
 931         hcd->otg_port = 1;
 932         hcd->frame_list = NULL;
 933         hcd->frame_list_dma = 0;
 934         hcd->periodic_qh_count = 0;
 935 out:
 936         return retval;
 937 }
 938
 939 void dwc_otg_hcd_remove(dwc_otg_hcd_t *hcd)
 940 {
 941         /* Turn off all host-specific interrupts. */
 942         dwc_otg_disable_host_interrupts(hcd->core_if);
 943
 944         dwc_otg_hcd_free(hcd);
 945 }
 946
 947 /**
 948  * Initializes dynamic portions of the DWC_otg HCD state.
 949  */
 950 static void dwc_otg_hcd_reinit(dwc_otg_hcd_t *hcd)
 951 {
 952         int num_channels;
 953         int i;
 954         dwc_hc_t *channel;
 955         dwc_hc_t *channel_tmp;
 956
 957         hcd->flags.d32 = 0;
 958
 959         hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
 960         hcd->non_periodic_channels = 0;
 961         hcd->periodic_channels = 0;
 962
 963         /*
 964          * Put all channels in the free channel list and clean up channel
 965          * states.
 966          */
 967         DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
 968                                  &hcd->free_hc_list, hc_list_entry) {
 969                 DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
 970         }
 971
 972         num_channels = hcd->core_if->core_params->host_channels;
 973         for (i = 0; i < num_channels; i++) {
 974                 channel = hcd->hc_ptr_array[i];
 975                 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
 976                                         hc_list_entry);
 977                 dwc_otg_hc_cleanup(hcd->core_if, channel);
 978         }
 979
 980         /* Initialize the DWC core for host mode operation. */
 981         dwc_otg_core_host_init(hcd->core_if);
 982
 983         /* Set core_if's lock pointer to the hcd->lock */
 984         hcd->core_if->lock = hcd->lock;
 985 }
 986
 987 /**
 988  * Assigns transactions from a QTD to a free host channel and initializes the
 989  * host channel to perform the transactions. The host channel is removed from
 990  * the free list.
 991  *
 992  * @param hcd The HCD state structure.
 993  * @param qh Transactions from the first QTD for this QH are selected and
 994  * assigned to a free host channel.
 995  */
 996 static int assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 997 {
 998         dwc_hc_t *hc;
 999         dwc_otg_qtd_t *qtd;
1000         dwc_otg_hcd_urb_t *urb;
1001         void *ptr = NULL;
1002         int retval = 0;
1003
1004         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
1005
1006         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
1007
1008         /* Remove the host channel from the free list. */
1009         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
1010
1011         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
1012
1013         urb = qtd->urb;
1014         if (urb == NULL) {
1015                 printk("%s : urb is NULL\n", __func__);
1016                 retval = -EINVAL;
1017                 return retval;
1018         }
1019
1020         qh->channel = hc;
1021
1022         qtd->in_process = 1;
1023
1024         /*
1025          * Use usb_pipedevice to determine device address. This address is
1026          * 0 before the SET_ADDRESS command and the correct address afterward.
1027          */
1028         hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
1029         hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
1030         hc->speed = qh->dev_speed;
1031         hc->max_packet = dwc_max_packet(qh->maxp);
1032
1033         hc->xfer_started = 0;
1034         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
1035         hc->error_state = (qtd->error_count > 0);
1036         hc->halt_on_queue = 0;
1037         hc->halt_pending = 0;
1038         hc->requests = 0;
1039
1040         /*
1041          * The following values may be modified in the transfer type section
1042          * below. The xfer_len value may be reduced when the transfer is
1043          * started to accommodate the max widths of the XferSize and PktCnt
1044          * fields in the HCTSIZn register.
1045          */
1046
1047         hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
1048         if (hc->ep_is_in)
1049                 hc->do_ping = 0;
1050         else
1051                 hc->do_ping = qh->ping_state;
1052
1053         hc->data_pid_start = qh->data_toggle;
1054         hc->multi_count = 1;
1055
1056         if (hcd->core_if->dma_enable) {
1057                 hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
1058
1059                 /* For non-dword aligned case */
1060                 if (((unsigned long)hc->xfer_buff & 0x3)
1061                     && !hcd->core_if->dma_desc_enable) {
1062                         ptr = (uint8_t *) urb->buf + urb->actual_length;
1063                 }
1064         } else {
1065                 hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
1066         }
1067         hc->xfer_len = urb->length - urb->actual_length;
1068         hc->xfer_count = 0;
1069
1070         /*
1071          * Set the split attributes
1072          */
1073         hc->do_split = 0;
1074         hc->csplit_nak = 0;
1075         if (qh->do_split) {
1076                 uint32_t hub_addr, port_addr;
1077                 hc->do_split = 1;
1078                 hc->xact_pos = qtd->isoc_split_pos;
1079                 hc->complete_split = qtd->complete_split;
1080                 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
1081                 hc->hub_addr = (uint8_t) hub_addr;
1082                 hc->port_addr = (uint8_t) port_addr;
1083         }
1084
1085         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1086         case UE_CONTROL:
1087                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
1088                 switch (qtd->control_phase) {
1089                 case DWC_OTG_CONTROL_SETUP:
1090                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
1091                         hc->do_ping = 0;
1092                         hc->ep_is_in = 0;
1093                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
1094                         if (hcd->core_if->dma_enable)
1095                                 hc->xfer_buff = (uint8_t *) urb->setup_dma;
1096                         else
1097                                 hc->xfer_buff = (uint8_t *) urb->setup_packet;
1098
1099                         hc->xfer_len = 8;
1100                         ptr = NULL;
1101                         break;
1102                 case DWC_OTG_CONTROL_DATA:
1103                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
1104                         hc->data_pid_start = qtd->data_toggle;
1105                         break;
1106                 case DWC_OTG_CONTROL_STATUS:
1107                         /*
1108                          * Direction is opposite of data direction or IN if no
1109                          * data.
1110                          */
1111                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
1112                         if (urb->length == 0) {
1113                                 hc->ep_is_in = 1;
1114                         } else {
1115                                 hc->ep_is_in =
1116                                     dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
1117                         }
1118                         if (hc->ep_is_in)
1119                                 hc->do_ping = 0;
1120
1121                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
1122
1123                         hc->xfer_len = 0;
1124                         if (hcd->core_if->dma_enable)
1125                                 hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
1126                         else
1127                                 hc->xfer_buff = (uint8_t *) hcd->status_buf;
1128
1129                         ptr = NULL;
1130                         break;
1131                 }
1132                 break;
1133         case UE_BULK:
1134                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
1135                 break;
1136         case UE_INTERRUPT:
1137                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
1138                 break;
1139         case UE_ISOCHRONOUS:
1140                 {
1141                         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1142
1143                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
1144
1145                         if (hcd->core_if->dma_desc_enable)
1146                                 break;
1147
1148                         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
1149
1150                         frame_desc->status = 0;
1151
1152                         if (hcd->core_if->dma_enable) {
1153                                 hc->xfer_buff = (uint8_t *) urb->dma;
1154                         } else {
1155                                 hc->xfer_buff = (uint8_t *) urb->buf;
1156                         }
1157                         hc->xfer_buff +=
1158                             frame_desc->offset + qtd->isoc_split_offset;
1159                         hc->xfer_len =
1160                             frame_desc->length - qtd->isoc_split_offset;
1161
1162                         /* For non-dword aligned buffers */
1163                         if (((unsigned long)hc->xfer_buff & 0x3)
1164                             && hcd->core_if->dma_enable) {
1165                                 ptr =
1166                                     (uint8_t *) urb->buf + frame_desc->offset +
1167                                     qtd->isoc_split_offset;
1168                         } else
1169                                 ptr = NULL;
1170
1171                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1172                                 if (hc->xfer_len <= 188) {
1173                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
1174                                 } else {
1175                                         hc->xact_pos =
1176                                             DWC_HCSPLIT_XACTPOS_BEGIN;
1177                                 }
1178                         }
1179                 }
1180                 break;
1181         }
1182         /* non DWORD-aligned buffer case */
1183         if (ptr) {
1184                 uint32_t buf_size;
1185                 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1186                         buf_size = hcd->core_if->core_params->max_transfer_size;
1187                 } else {
1188                         buf_size = 4096;
1189                 }
1190                 if (!qh->dw_align_buf) {
1191                         qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
1192                                                                 &qh->
1193                                                                 dw_align_buf_dma);
1194                         if (!qh->dw_align_buf) {
1195                                 DWC_ERROR
1196                                     ("%s: Failed to allocate memory to handle "
1197                                      "non-dword aligned buffer case\n",
1198                                      __func__);
1199                                 return retval;
1200                         }
1201                 }
1202                 if (!hc->ep_is_in) {
1203                         dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
1204                 }
1205                 hc->align_buff = qh->dw_align_buf_dma;
1206         } else {
1207                 hc->align_buff = 0;
1208         }
1209
1210         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1211             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1212                 /*
1213                  * This value may be modified when the transfer is started to
1214                  * reflect the actual transfer length.
1215                  */
1216                 hc->multi_count = dwc_hb_mult(qh->maxp);
1217         }
1218
1219         if (hcd->core_if->dma_desc_enable)
1220                 hc->desc_list_addr = qh->desc_list_dma;
1221
1222         dwc_otg_hc_init(hcd->core_if, hc);
1223         hc->qh = qh;
1224         return retval;
1225 }
1226
1227 /**
1228  * This function selects transactions from the HCD transfer schedule and
1229  * assigns them to available host channels. It is called from HCD interrupt
1230  * handler functions.
1231  *
1232  * @param hcd The HCD state structure.
1233  *
1234  * @return The types of new transactions that were assigned to host channels.
1235  */
1236 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
1237 {
1238         dwc_list_link_t *qh_ptr;
1239         dwc_otg_qh_t *qh;
1240         int num_channels;
1241         dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
1242         int err;
1243
1244 #ifdef DEBUG_SOF
1245         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
1246 #endif
1247
1248         /* Process entries in the periodic ready list. */
1249         qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
1250
1251         while (qh_ptr != &hcd->periodic_sched_ready &&
1252                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1253
1254                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1255                 assign_and_init_hc(hcd, qh);
1256
1257                 /*
1258                  * Move the QH from the periodic ready schedule to the
1259                  * periodic assigned schedule.
1260                  */
1261                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1262                 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
1263                                    &qh->qh_list_entry);
1264
1265                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
1266         }
1267
1268         /*
1269          * Process entries in the inactive portion of the non-periodic
1270          * schedule. Some free host channels may not be used if they are
1271          * reserved for periodic transfers.
1272          */
1273         qh_ptr = hcd->non_periodic_sched_inactive.next;
1274         num_channels = hcd->core_if->core_params->host_channels;
1275         while (qh_ptr != &hcd->non_periodic_sched_inactive &&
1276                (hcd->non_periodic_channels <
1277                 num_channels - hcd->periodic_channels) &&
1278                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1279
1280                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1281
1282                 err = assign_and_init_hc(hcd, qh);
1283
1284                 /*
1285                  * Move the QH from the non-periodic inactive schedule to the
1286                  * non-periodic active schedule.
1287                  */
1288                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1289                 if (err != 0)
1290                         continue;
1291                 DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
1292                                    &qh->qh_list_entry);
1293
1294                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
1295                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
1296                 } else {
1297                         ret_val = DWC_OTG_TRANSACTION_ALL;
1298                 }
1299
1300                 hcd->non_periodic_channels++;
1301         }
1302
1303         return ret_val;
1304 }
1305
1306 /**
1307  * Attempts to queue a single transaction request for a host channel
1308  * associated with either a periodic or non-periodic transfer. This function
1309  * assumes that there is space available in the appropriate request queue. For
1310  * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
1311  * is available in the appropriate Tx FIFO.
1312  *
1313  * @param hcd The HCD state structure.
1314  * @param hc Host channel descriptor associated with either a periodic or
1315  * non-periodic transfer.
1316  * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
1317  * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
1318  * transfers.
1319  *
1320  * @return 1 if a request is queued and more requests may be needed to
1321  * complete the transfer, 0 if no more requests are required for this
1322  * transfer, -1 if there is insufficient space in the Tx FIFO.
1323  */
1324 static int queue_transaction(dwc_otg_hcd_t *hcd,
1325                              dwc_hc_t *hc, uint16_t fifo_dwords_avail)
1326 {
1327         int retval;
1328
1329         if (hcd->core_if->dma_enable) {
1330                 if (hcd->core_if->dma_desc_enable) {
1331                         if (!hc->xfer_started
1332                             || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
1333                                 dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
1334                                 hc->qh->ping_state = 0;
1335                         }
1336                 } else if (!hc->xfer_started) {
1337                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1338                         hc->qh->ping_state = 0;
1339                 }
1340                 retval = 0;
1341         } else if (hc->halt_pending) {
1342                 /* Don't queue a request if the channel has been halted. */
1343                 retval = 0;
1344         } else if (hc->halt_on_queue) {
1345                 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
1346                 retval = 0;
1347         } else if (hc->do_ping) {
1348                 if (!hc->xfer_started) {
1349                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1350                 }
1351                 retval = 0;
1352         } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
1353                 if ((fifo_dwords_avail * 4) >= hc->max_packet) {
1354                         if (!hc->xfer_started) {
1355                                 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1356                                 retval = 1;
1357                         } else {
1358                                 retval =
1359                                     dwc_otg_hc_continue_transfer(hcd->core_if,
1360                                                                  hc);
1361                         }
1362                 } else {
1363                         retval = -1;
1364                 }
1365         } else {
1366                 if (!hc->xfer_started) {
1367                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1368                         retval = 1;
1369                 } else {
1370                         retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
1371                 }
1372         }
1373
1374         return retval;
1375 }
1376
1377 /**
1378  * Processes periodic channels for the next frame and queues transactions for
1379  * these channels to the DWC_otg controller. After queueing transactions, the
1380  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1381  * to queue as Periodic Tx FIFO or request queue space becomes available.
1382  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1383  */
1384 static void process_periodic_channels(dwc_otg_hcd_t *hcd)
1385 {
1386         hptxsts_data_t tx_status;
1387         dwc_list_link_t *qh_ptr;
1388         dwc_otg_qh_t *qh;
1389         int status;
1390         int no_queue_space = 0;
1391         int no_fifo_space = 0;
1392
1393         dwc_otg_host_global_regs_t *host_regs;
1394         host_regs = hcd->core_if->host_if->host_global_regs;
1395
1396         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
1397 #ifdef DEBUG
1398         tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1399         DWC_DEBUGPL(DBG_HCDV,
1400                     "  P Tx Req Queue Space Avail (before queue): %d\n",
1401                     tx_status.b.ptxqspcavail);
1402         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
1403                     tx_status.b.ptxfspcavail);
1404 #endif
1405
1406         qh_ptr = hcd->periodic_sched_assigned.next;
1407         while (qh_ptr != &hcd->periodic_sched_assigned) {
1408                 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1409                 if (tx_status.b.ptxqspcavail == 0) {
1410                         no_queue_space = 1;
1411                         break;
1412                 }
1413
1414                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1415
1416                 /*
1417                  * Set a flag if we're queuing high-bandwidth in slave mode.
1418                  * The flag prevents any halts to get into the request queue in
1419                  * the middle of multiple high-bandwidth packets getting queued.
1420                  */
1421                 if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
1422                         hcd->core_if->queuing_high_bandwidth = 1;
1423                 }
1424                 status =
1425                     queue_transaction(hcd, qh->channel,
1426                                       tx_status.b.ptxfspcavail);
1427                 if (status < 0) {
1428                         no_fifo_space = 1;
1429                         break;
1430                 }
1431
1432                 /*
1433                  * In Slave mode, stay on the current transfer until there is
1434                  * nothing more to do or the high-bandwidth request count is
1435                  * reached. In DMA mode, only need to queue one request. The
1436                  * controller automatically handles multiple packets for
1437                  * high-bandwidth transfers.
1438                  */
1439                 if (hcd->core_if->dma_enable || status == 0 ||
1440                     qh->channel->requests == qh->channel->multi_count) {
1441                         qh_ptr = qh_ptr->next;
1442                         /*
1443                          * Move the QH from the periodic assigned schedule to
1444                          * the periodic queued schedule.
1445                          */
1446                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
1447                                            &qh->qh_list_entry);
1448
1449                         /* done queuing high bandwidth */
1450                         hcd->core_if->queuing_high_bandwidth = 0;
1451                 }
1452         }
1453
1454         if (!hcd->core_if->dma_enable) {
1455                 dwc_otg_core_global_regs_t *global_regs;
1456                 gintmsk_data_t intr_mask = {.d32 = 0 };
1457
1458                 global_regs = hcd->core_if->core_global_regs;
1459                 intr_mask.b.ptxfempty = 1;
1460 #ifdef DEBUG
1461                 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1462                 DWC_DEBUGPL(DBG_HCDV,
1463                             "  P Tx Req Queue Space Avail (after queue): %d\n",
1464                             tx_status.b.ptxqspcavail);
1465                 DWC_DEBUGPL(DBG_HCDV,
1466                             "  P Tx FIFO Space Avail (after queue): %d\n",
1467                             tx_status.b.ptxfspcavail);
1468 #endif
1469                 if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
1470                     no_queue_space || no_fifo_space) {
1471                         /*
1472                          * May need to queue more transactions as the request
1473                          * queue or Tx FIFO empties. Enable the periodic Tx
1474                          * FIFO empty interrupt. (Always use the half-empty
1475                          * level to ensure that new requests are loaded as
1476                          * soon as possible.)
1477                          */
1478                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1479                                          intr_mask.d32);
1480                 } else {
1481                         /*
1482                          * Disable the Tx FIFO empty interrupt since there are
1483                          * no more transactions that need to be queued right
1484                          * now. This function is called from interrupt
1485                          * handlers to queue more transactions as transfer
1486                          * states change.
1487                          */
1488                         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1489                                          0);
1490                 }
1491         }
1492 }
1493
1494 /**
1495  * Processes active non-periodic channels and queues transactions for these
1496  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1497  * FIFO Empty interrupt is enabled if there are more transactions to queue as
1498  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1499  * FIFO Empty interrupt is disabled.
1500  */
1501 static void process_non_periodic_channels(dwc_otg_hcd_t *hcd)
1502 {
1503         gnptxsts_data_t tx_status;
1504         dwc_list_link_t *orig_qh_ptr;
1505         dwc_otg_qh_t *qh;
1506         int status;
1507         int no_queue_space = 0;
1508         int no_fifo_space = 0;
1509         int more_to_do = 0;
1510
1511         dwc_otg_core_global_regs_t *global_regs =
1512             hcd->core_if->core_global_regs;
1513
1514         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
1515 #ifdef DEBUG
1516         tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1517         DWC_DEBUGPL(DBG_HCDV,
1518                     "  NP Tx Req Queue Space Avail (before queue): %d\n",
1519                     tx_status.b.nptxqspcavail);
1520         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
1521                     tx_status.b.nptxfspcavail);
1522 #endif
1523         /*
1524          * Keep track of the starting point. Skip over the start-of-list
1525          * entry.
1526          */
1527         if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1528                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1529         }
1530         orig_qh_ptr = hcd->non_periodic_qh_ptr;
1531
1532         /*
1533          * Process once through the active list or until no more space is
1534          * available in the request queue or the Tx FIFO.
1535          */
1536         do {
1537                 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1538                 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
1539                         no_queue_space = 1;
1540                         break;
1541                 }
1542
1543                 qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
1544                                     qh_list_entry);
1545                 status =
1546                     queue_transaction(hcd, qh->channel,
1547                                       tx_status.b.nptxfspcavail);
1548
1549                 if (status > 0) {
1550                         more_to_do = 1;
1551                 } else if (status < 0) {
1552                         no_fifo_space = 1;
1553                         break;
1554                 }
1555
1556                 /* Advance to next QH, skipping start-of-list entry. */
1557                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1558                 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1559                         hcd->non_periodic_qh_ptr =
1560                             hcd->non_periodic_qh_ptr->next;
1561                 }
1562
1563         } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
1564
1565         if (!hcd->core_if->dma_enable) {
1566                 gintmsk_data_t intr_mask = {.d32 = 0 };
1567                 intr_mask.b.nptxfempty = 1;
1568
1569 #ifdef DEBUG
1570                 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1571                 DWC_DEBUGPL(DBG_HCDV,
1572                             "  NP Tx Req Queue Space Avail (after queue): %d\n",
1573                             tx_status.b.nptxqspcavail);
1574                 DWC_DEBUGPL(DBG_HCDV,
1575                             "  NP Tx FIFO Space Avail (after queue): %d\n",
1576                             tx_status.b.nptxfspcavail);
1577 #endif
1578                 if (more_to_do || no_queue_space || no_fifo_space) {
1579                         /*
1580                          * May need to queue more transactions as the request
1581                          * queue or Tx FIFO empties. Enable the non-periodic
1582                          * Tx FIFO empty interrupt. (Always use the half-empty
1583                          * level to ensure that new requests are loaded as
1584                          * soon as possible.)
1585                          */
1586                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1587                                          intr_mask.d32);
1588                 } else {
1589                         /*
1590                          * Disable the Tx FIFO empty interrupt since there are
1591                          * no more transactions that need to be queued right
1592                          * now. This function is called from interrupt
1593                          * handlers to queue more transactions as transfer
1594                          * states change.
1595                          */
1596                         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1597                                          0);
1598                 }
1599         }
1600 }
1601
1602 /**
1603  * This function processes the currently active host channels and queues
1604  * transactions for these channels to the DWC_otg controller. It is called
1605  * from HCD interrupt handler functions.
1606  *
1607  * @param hcd The HCD state structure.
1608  * @param tr_type The type(s) of transactions to queue (non-periodic,
1609  * periodic, or both).
1610  */
1611 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
1612                                     dwc_otg_transaction_type_e tr_type)
1613 {
1614 #ifdef DEBUG_SOF
1615         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
1616 #endif
1617         /* Process host channels associated with periodic transfers. */
1618         if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
1619              tr_type == DWC_OTG_TRANSACTION_ALL) &&
1620             !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
1621
1622                 process_periodic_channels(hcd);
1623         }
1624
1625         /* Process host channels associated with non-periodic transfers. */
1626         if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
1627             tr_type == DWC_OTG_TRANSACTION_ALL) {
1628                 if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
1629                         process_non_periodic_channels(hcd);
1630                 } else {
1631                         /*
1632                          * Ensure NP Tx FIFO empty interrupt is disabled when
1633                          * there are no non-periodic transfers to process.
1634                          */
1635                         gintmsk_data_t gintmsk = {.d32 = 0 };
1636                         gintmsk.b.nptxfempty = 1;
1637                         DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->
1638                                          gintmsk, gintmsk.d32, 0);
1639                 }
1640         }
1641 }
1642
1643 #ifdef DWC_HS_ELECT_TST
1644 /*
1645  * Quick and dirty hack to implement the HS Electrical Test
1646  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1647  *
1648  * This code was copied from our userspace app "hset". It sends a
1649  * Get Device Descriptor control sequence in two parts, first the
1650  * Setup packet by itself, followed some time later by the In and
1651  * Ack packets. Rather than trying to figure out how to add this
1652  * functionality to the normal driver code, we just hijack the
1653  * hardware, using these two function to drive the hardware
1654  * directly.
1655  */
1656
1657 static dwc_otg_core_global_regs_t *global_regs;
1658 static dwc_otg_host_global_regs_t *hc_global_regs;
1659 static dwc_otg_hc_regs_t *hc_regs;
1660 static uint32_t *data_fifo;
1661
1662 static void do_setup(void)
1663 {
1664         gintsts_data_t gintsts;
1665         hctsiz_data_t hctsiz;
1666         hcchar_data_t hcchar;
1667         haint_data_t haint;
1668         hcint_data_t hcint;
1669
1670         /* Enable HAINTs */
1671         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1672
1673         /* Enable HCINTs */
1674         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1675
1676         /* Read GINTSTS */
1677         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1678
1679         /* Read HAINT */
1680         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1681
1682         /* Read HCINT */
1683         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1684
1685         /* Read HCCHAR */
1686         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1687
1688         /* Clear HCINT */
1689         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1690
1691         /* Clear HAINT */
1692         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1693
1694         /* Clear GINTSTS */
1695         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1696
1697         /* Read GINTSTS */
1698         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1699
1700         /*
1701          * Send Setup packet (Get Device Descriptor)
1702          */
1703
1704         /* Make sure channel is disabled */
1705         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1706         if (hcchar.b.chen) {
1707                 hcchar.b.chdis = 1;
1708                 /* hcchar.b.chen = 1; */
1709                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1710                 /* sleep(1); */
1711                 dwc_mdelay(1000);
1712
1713                 /* Read GINTSTS */
1714                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1715
1716                 /* Read HAINT */
1717                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1718
1719                 /* Read HCINT */
1720                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1721
1722                 /* Read HCCHAR */
1723                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1724
1725                 /* Clear HCINT */
1726                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1727
1728                 /* Clear HAINT */
1729                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1730
1731                 /* Clear GINTSTS */
1732                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1733
1734                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1735         }
1736
1737         /* Set HCTSIZ */
1738         hctsiz.d32 = 0;
1739         hctsiz.b.xfersize = 8;
1740         hctsiz.b.pktcnt = 1;
1741         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1742         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1743
1744         /* Set HCCHAR */
1745         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1746         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1747         hcchar.b.epdir = 0;
1748         hcchar.b.epnum = 0;
1749         hcchar.b.mps = 8;
1750         hcchar.b.chen = 1;
1751         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1752
1753         /* Fill FIFO with Setup data for Get Device Descriptor */
1754         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1755         DWC_WRITE_REG32(data_fifo++, 0x01000680);
1756         DWC_WRITE_REG32(data_fifo++, 0x00080000);
1757
1758         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1759
1760         /* Wait for host channel interrupt */
1761         do {
1762                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1763         } while (gintsts.b.hcintr == 0);
1764
1765         /* Disable HCINTs */
1766         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
1767
1768         /* Disable HAINTs */
1769         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
1770
1771         /* Read HAINT */
1772         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1773
1774         /* Read HCINT */
1775         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1776
1777         /* Read HCCHAR */
1778         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1779
1780         /* Clear HCINT */
1781         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1782
1783         /* Clear HAINT */
1784         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1785
1786         /* Clear GINTSTS */
1787         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1788
1789         /* Read GINTSTS */
1790         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1791 }
1792
1793 static void do_in_ack(void)
1794 {
1795         gintsts_data_t gintsts;
1796         hctsiz_data_t hctsiz;
1797         hcchar_data_t hcchar;
1798         haint_data_t haint;
1799         hcint_data_t hcint;
1800         host_grxsts_data_t grxsts;
1801
1802         /* Enable HAINTs */
1803         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1804
1805         /* Enable HCINTs */
1806         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1807
1808         /* Read GINTSTS */
1809         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1810
1811         /* Read HAINT */
1812         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1813
1814         /* Read HCINT */
1815         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1816
1817         /* Read HCCHAR */
1818         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1819
1820         /* Clear HCINT */
1821         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1822
1823         /* Clear HAINT */
1824         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1825
1826         /* Clear GINTSTS */
1827         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1828
1829         /* Read GINTSTS */
1830         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1831
1832         /*
1833          * Receive Control In packet
1834          */
1835
1836         /* Make sure channel is disabled */
1837         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1838         if (hcchar.b.chen) {
1839                 hcchar.b.chdis = 1;
1840                 hcchar.b.chen = 1;
1841                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1842                 /* sleep(1); */
1843                 dwc_mdelay(1000);
1844
1845                 /* Read GINTSTS */
1846                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1847
1848                 /* Read HAINT */
1849                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1850
1851                 /* Read HCINT */
1852                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1853
1854                 /* Read HCCHAR */
1855                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1856
1857                 /* Clear HCINT */
1858                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1859
1860                 /* Clear HAINT */
1861                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1862
1863                 /* Clear GINTSTS */
1864                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1865
1866                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1867         }
1868
1869         /* Set HCTSIZ */
1870         hctsiz.d32 = 0;
1871         hctsiz.b.xfersize = 8;
1872         hctsiz.b.pktcnt = 1;
1873         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1874         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1875
1876         /* Set HCCHAR */
1877         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1878         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1879         hcchar.b.epdir = 1;
1880         hcchar.b.epnum = 0;
1881         hcchar.b.mps = 8;
1882         hcchar.b.chen = 1;
1883         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1884
1885         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1886
1887         /* Wait for receive status queue interrupt */
1888         do {
1889                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1890         } while (gintsts.b.rxstsqlvl == 0);
1891
1892         /* Read RXSTS */
1893         grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1894
1895         /* Clear RXSTSQLVL in GINTSTS */
1896         gintsts.d32 = 0;
1897         gintsts.b.rxstsqlvl = 1;
1898         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1899
1900         switch (grxsts.b.pktsts) {
1901         case DWC_GRXSTS_PKTSTS_IN:
1902                 /* Read the data into the host buffer */
1903                 if (grxsts.b.bcnt > 0) {
1904                         int i;
1905                         int word_count = (grxsts.b.bcnt + 3) / 4;
1906
1907                         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1908
1909                         for (i = 0; i < word_count; i++) {
1910                                 (void)DWC_READ_REG32(data_fifo++);
1911                         }
1912                 }
1913                 break;
1914
1915         default:
1916                 break;
1917         }
1918
1919         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1920
1921         /* Wait for receive status queue interrupt */
1922         do {
1923                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1924         } while (gintsts.b.rxstsqlvl == 0);
1925
1926         /* Read RXSTS */
1927         grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1928
1929         /* Clear RXSTSQLVL in GINTSTS */
1930         gintsts.d32 = 0;
1931         gintsts.b.rxstsqlvl = 1;
1932         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1933
1934         switch (grxsts.b.pktsts) {
1935         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
1936                 break;
1937
1938         default:
1939                 break;
1940         }
1941
1942         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1943
1944         /* Wait for host channel interrupt */
1945         do {
1946                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1947         } while (gintsts.b.hcintr == 0);
1948
1949         /* Read HAINT */
1950         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1951
1952         /* Read HCINT */
1953         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1954
1955         /* Read HCCHAR */
1956         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1957
1958         /* Clear HCINT */
1959         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1960
1961         /* Clear HAINT */
1962         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1963
1964         /* Clear GINTSTS */
1965         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1966
1967         /* Read GINTSTS */
1968         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1969
1970         /* usleep(100000); */
1971         /* mdelay(100); */
1972         dwc_mdelay(1);
1973
1974         /*
1975          * Send handshake packet
1976          */
1977
1978         /* Read HAINT */
1979         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1980
1981         /* Read HCINT */
1982         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1983
1984         /* Read HCCHAR */
1985         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1986
1987         /* Clear HCINT */
1988         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1989
1990         /* Clear HAINT */
1991         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1992
1993         /* Clear GINTSTS */
1994         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1995
1996         /* Read GINTSTS */
1997         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1998
1999         /* Make sure channel is disabled */
2000         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2001         if (hcchar.b.chen) {
2002                 hcchar.b.chdis = 1;
2003                 hcchar.b.chen = 1;
2004                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2005                 /* sleep(1); */
2006                 dwc_mdelay(1000);
2007
2008                 /* Read GINTSTS */
2009                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2010
2011                 /* Read HAINT */
2012                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2013
2014                 /* Read HCINT */
2015                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2016
2017                 /* Read HCCHAR */
2018                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2019
2020                 /* Clear HCINT */
2021                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2022
2023                 /* Clear HAINT */
2024                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2025
2026                 /* Clear GINTSTS */
2027                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2028
2029                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2030         }
2031
2032         /* Set HCTSIZ */
2033         hctsiz.d32 = 0;
2034         hctsiz.b.xfersize = 0;
2035         hctsiz.b.pktcnt = 1;
2036         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2037         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
2038
2039         /* Set HCCHAR */
2040         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2041         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2042         hcchar.b.epdir = 0;
2043         hcchar.b.epnum = 0;
2044         hcchar.b.mps = 8;
2045         hcchar.b.chen = 1;
2046         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2047
2048         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2049
2050         /* Wait for host channel interrupt */
2051         do {
2052                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2053         } while (gintsts.b.hcintr == 0);
2054
2055         /* Disable HCINTs */
2056         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
2057
2058         /* Disable HAINTs */
2059         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
2060
2061         /* Read HAINT */
2062         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2063
2064         /* Read HCINT */
2065         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2066
2067         /* Read HCCHAR */
2068         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2069
2070         /* Clear HCINT */
2071         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2072
2073         /* Clear HAINT */
2074         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2075
2076         /* Clear GINTSTS */
2077         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2078
2079         /* Read GINTSTS */
2080         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2081 }
2082 #endif
2083
2084 /** Handles hub class-specific requests. */
2085 int dwc_otg_hcd_hub_control(dwc_otg_hcd_t *dwc_otg_hcd,
2086                             uint16_t typeReq,
2087                             uint16_t wValue,
2088                             uint16_t wIndex, uint8_t *buf, uint16_t wLength)
2089 {
2090         int retval = 0;
2091
2092         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
2093         usb_hub_descriptor_t *hub_desc;
2094         hprt0_data_t hprt0 = {.d32 = 0 };
2095
2096         uint32_t port_status;
2097
2098         switch (typeReq) {
2099         case UCR_CLEAR_HUB_FEATURE:
2100                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2101                             "ClearHubFeature 0x%x\n", wValue);
2102                 switch (wValue) {
2103                 case UHF_C_HUB_LOCAL_POWER:
2104                 case UHF_C_HUB_OVER_CURRENT:
2105                         /* Nothing required here */
2106                         break;
2107                 default:
2108                         retval = -DWC_E_INVALID;
2109                         DWC_ERROR("DWC OTG HCD - "
2110                                   "ClearHubFeature request %xh unknown\n",
2111                                   wValue);
2112                 }
2113                 break;
2114         case UCR_CLEAR_PORT_FEATURE:
2115 #ifdef CONFIG_USB_DWC_OTG_LPM
2116                 if (wValue != UHF_PORT_L1)
2117 #endif
2118                         if (!wIndex || wIndex > 1)
2119                                 goto error;
2120
2121                 switch (wValue) {
2122                 case UHF_PORT_ENABLE:
2123                         DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2124                                     "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2125                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2126                         hprt0.b.prtena = 1;
2127                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2128                         break;
2129                 case UHF_PORT_SUSPEND:
2130                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2131                                     "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2132
2133                         if (core_if->power_down == 2) {
2134                                 dwc_otg_host_hibernation_restore(core_if, 0, 0);
2135                         } else {
2136                                 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2137                                 dwc_mdelay(5);
2138
2139                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2140                                 hprt0.b.prtres = 1;
2141                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2142                                                 hprt0.d32);
2143                                 hprt0.b.prtsusp = 0;
2144                                 /* Clear Resume bit */
2145                                 dwc_mdelay(100);
2146                                 hprt0.b.prtres = 0;
2147                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2148                                                 hprt0.d32);
2149                         }
2150                         break;
2151 #ifdef CONFIG_USB_DWC_OTG_LPM
2152                 case UHF_PORT_L1:
2153                         {
2154                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2155                                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
2156
2157                                 lpmcfg.d32 =
2158                                     DWC_READ_REG32(&core_if->core_global_regs->
2159                                                    glpmcfg);
2160                                 lpmcfg.b.en_utmi_sleep = 0;
2161                                 lpmcfg.b.hird_thres &= (~(1 << 4));
2162                                 lpmcfg.b.prt_sleep_sts = 1;
2163                                 DWC_WRITE_REG32(&core_if->core_global_regs->
2164                                                 glpmcfg, lpmcfg.d32);
2165
2166                                 /* Clear Enbl_L1Gating bit. */
2167                                 pcgcctl.b.enbl_sleep_gating = 1;
2168                                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2169                                                  0);
2170
2171                                 dwc_mdelay(5);
2172
2173                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2174                                 hprt0.b.prtres = 1;
2175                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2176                                                 hprt0.d32);
2177                                 /* This bit will be cleared in wakeup interrupt handle */
2178                                 break;
2179                         }
2180 #endif
2181                 case UHF_PORT_POWER:
2182                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2183                                     "ClearPortFeature USB_PORT_FEAT_POWER\n");
2184                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2185                         hprt0.b.prtpwr = 0;
2186                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2187                         break;
2188                 case UHF_PORT_INDICATOR:
2189                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2190                                     "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2191                         /* Port inidicator not supported */
2192                         break;
2193                 case UHF_C_PORT_CONNECTION:
2194                         /* Clears drivers internal connect status change
2195                          * flag */
2196                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2197                                     "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2198                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2199                         break;
2200                 case UHF_C_PORT_RESET:
2201                         /* Clears the driver's internal Port Reset Change
2202                          * flag */
2203                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2204                                     "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2205                         dwc_otg_hcd->flags.b.port_reset_change = 0;
2206                         break;
2207                 case UHF_C_PORT_ENABLE:
2208                         /* Clears the driver's internal Port
2209                          * Enable/Disable Change flag */
2210                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2211                                     "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2212                         dwc_otg_hcd->flags.b.port_enable_change = 0;
2213                         break;
2214                 case UHF_C_PORT_SUSPEND:
2215                         /* Clears the driver's internal Port Suspend
2216                          * Change flag, which is set when resume signaling on
2217                          * the host port is complete */
2218                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2219                                     "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2220                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
2221                         break;
2222 #ifdef CONFIG_USB_DWC_OTG_LPM
2223                 case UHF_C_PORT_L1:
2224                         dwc_otg_hcd->flags.b.port_l1_change = 0;
2225                         break;
2226 #endif
2227                 case UHF_C_PORT_OVER_CURRENT:
2228                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2229                                     "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2230                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
2231                         break;
2232                 default:
2233                         retval = -DWC_E_INVALID;
2234                         DWC_ERROR("DWC OTG HCD - "
2235                                   "ClearPortFeature request %xh "
2236                                   "unknown or unsupported\n", wValue);
2237                 }
2238                 break;
2239         case UCR_GET_HUB_DESCRIPTOR:
2240                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2241                             "GetHubDescriptor\n");
2242                 hub_desc = (usb_hub_descriptor_t *) buf;
2243                 hub_desc->bDescLength = 9;
2244                 hub_desc->bDescriptorType = 0x29;
2245                 hub_desc->bNbrPorts = 1;
2246                 USETW(hub_desc->wHubCharacteristics, 0x08);
2247                 hub_desc->bPwrOn2PwrGood = 1;
2248                 hub_desc->bHubContrCurrent = 0;
2249                 hub_desc->DeviceRemovable[0] = 0;
2250                 hub_desc->DeviceRemovable[1] = 0xff;
2251                 break;
2252         case UCR_GET_HUB_STATUS:
2253                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2254                             "GetHubStatus\n");
2255                 DWC_MEMSET(buf, 0, 4);
2256                 break;
2257         case UCR_GET_PORT_STATUS:
2258                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2259                             "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
2260                             wIndex, dwc_otg_hcd->flags.d32);
2261                 if (!wIndex || wIndex > 1)
2262                         goto error;
2263
2264                 port_status = 0;
2265
2266                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2267                         port_status |= (1 << UHF_C_PORT_CONNECTION);
2268
2269                 if (dwc_otg_hcd->flags.b.port_enable_change)
2270                         port_status |= (1 << UHF_C_PORT_ENABLE);
2271
2272                 if (dwc_otg_hcd->flags.b.port_suspend_change)
2273                         port_status |= (1 << UHF_C_PORT_SUSPEND);
2274
2275                 if (dwc_otg_hcd->flags.b.port_l1_change)
2276                         port_status |= (1 << UHF_C_PORT_L1);
2277
2278                 if (dwc_otg_hcd->flags.b.port_reset_change) {
2279                         port_status |= (1 << UHF_C_PORT_RESET);
2280                 }
2281
2282                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2283                         DWC_WARN("Overcurrent change detected\n");
2284                         port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
2285                 }
2286
2287                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2288                         /*
2289                          * The port is disconnected, which means the core is
2290                          * either in device mode or it soon will be. Just
2291                          * return 0's for the remainder of the port status
2292                          * since the port register can't be read if the core
2293                          * is in device mode.
2294                          */
2295                         *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2296                         break;
2297                 }
2298
2299                 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
2300                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
2301
2302                 if (hprt0.b.prtconnsts)
2303                         port_status |= (1 << UHF_PORT_CONNECTION);
2304
2305                 if (hprt0.b.prtena)
2306                         port_status |= (1 << UHF_PORT_ENABLE);
2307
2308                 if (hprt0.b.prtsusp)
2309                         port_status |= (1 << UHF_PORT_SUSPEND);
2310
2311                 if (hprt0.b.prtovrcurract)
2312                         port_status |= (1 << UHF_PORT_OVER_CURRENT);
2313
2314                 if (hprt0.b.prtrst)
2315                         port_status |= (1 << UHF_PORT_RESET);
2316
2317                 if (hprt0.b.prtpwr)
2318                         port_status |= (1 << UHF_PORT_POWER);
2319
2320                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2321                         port_status |= (1 << UHF_PORT_HIGH_SPEED);
2322                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2323                         port_status |= (1 << UHF_PORT_LOW_SPEED);
2324
2325                 if (hprt0.b.prttstctl)
2326                         port_status |= (1 << UHF_PORT_TEST);
2327                 if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
2328                         port_status |= (1 << UHF_PORT_L1);
2329                 }
2330                 /*
2331                    For Synopsys HW emulation of Power down wkup_control asserts the
2332                    hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
2333                    We intentionally tell the software that port is in L2Suspend state.
2334                    Only for STE.
2335                  */
2336                 if ((core_if->power_down == 2)
2337                     && (core_if->hibernation_suspend == 1)) {
2338                         port_status |= (1 << UHF_PORT_SUSPEND);
2339                 }
2340                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2341
2342                 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2343
2344                 break;
2345         case UCR_SET_HUB_FEATURE:
2346                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2347                             "SetHubFeature\n");
2348                 /* No HUB features supported */
2349                 break;
2350         case UCR_SET_PORT_FEATURE:
2351                 if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
2352                         goto error;
2353
2354                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2355                         /*
2356                          * The port is disconnected, which means the core is
2357                          * either in device mode or it soon will be. Just
2358                          * return without doing anything since the port
2359                          * register can't be written if the core is in device
2360                          * mode.
2361                          */
2362                         break;
2363                 }
2364
2365                 switch (wValue) {
2366                 case UHF_PORT_SUSPEND:
2367                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2368                                     "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2369                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
2370                                 goto error;
2371                         }
2372                         if (core_if->power_down == 2) {
2373                                 int timeout = 300;
2374                                 dwc_irqflags_t flags;
2375                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2376                                 gpwrdn_data_t gpwrdn = {.d32 = 0 };
2377                                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
2378 #ifdef DWC_DEV_SRPCAP
2379                                 int32_t otg_cap_param =
2380                                     core_if->core_params->otg_cap;
2381 #endif
2382                                 DWC_PRINTF
2383                                     ("Preparing for complete power-off\n");
2384
2385                                 /* Save registers before hibernation */
2386                                 dwc_otg_save_global_regs(core_if);
2387                                 dwc_otg_save_host_regs(core_if);
2388
2389                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2390                                 hprt0.b.prtsusp = 1;
2391                                 hprt0.b.prtena = 0;
2392                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2393                                                 hprt0.d32);
2394                                 /* Spin hprt0.b.prtsusp to became 1 */
2395                                 do {
2396                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2397                                         if (hprt0.b.prtsusp) {
2398                                                 break;
2399                                         }
2400                                         dwc_mdelay(1);
2401                                 } while (--timeout);
2402                                 if (!timeout) {
2403                                         DWC_WARN("Suspend wasn't genereted\n");
2404                                 }
2405                                 dwc_udelay(10);
2406
2407                                 /*
2408                                  * We need to disable interrupts to prevent servicing of any IRQ
2409                                  * during going to hibernation
2410                                  */
2411                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2412                                 core_if->lx_state = DWC_OTG_L2;
2413 #ifdef DWC_DEV_SRPCAP
2414                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2415                                 hprt0.b.prtpwr = 0;
2416                                 hprt0.b.prtena = 0;
2417                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2418                                                 hprt0.d32);
2419 #endif
2420                                 gusbcfg.d32 =
2421                                     DWC_READ_REG32(&core_if->
2422                                                    core_global_regs->gusbcfg);
2423                                 if (gusbcfg.b.ulpi_utmi_sel == 1) {
2424                                         /* ULPI interface */
2425                                         /* Suspend the Phy Clock */
2426                                         pcgcctl.d32 = 0;
2427                                         pcgcctl.b.stoppclk = 1;
2428                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2429                                                          pcgcctl.d32);
2430                                         dwc_udelay(10);
2431                                         gpwrdn.b.pmuactv = 1;
2432                                         DWC_MODIFY_REG32
2433                                             (&core_if->core_global_regs->gpwrdn,
2434                                              0, gpwrdn.d32);
2435                                 } else {
2436                                         /* UTMI+ Interface */
2437                                         gpwrdn.b.pmuactv = 1;
2438                                         DWC_MODIFY_REG32
2439                                             (&core_if->core_global_regs->gpwrdn,
2440                                              0, gpwrdn.d32);
2441                                         dwc_udelay(10);
2442                                         pcgcctl.b.stoppclk = 1;
2443                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2444                                                          pcgcctl.d32);
2445                                         dwc_udelay(10);
2446                                 }
2447 #ifdef DWC_DEV_SRPCAP
2448                                 gpwrdn.d32 = 0;
2449                                 gpwrdn.b.dis_vbus = 1;
2450                                 DWC_MODIFY_REG32(&core_if->
2451                                                  core_global_regs->gpwrdn, 0,
2452                                                  gpwrdn.d32);
2453 #endif
2454                                 gpwrdn.d32 = 0;
2455                                 gpwrdn.b.pmuintsel = 1;
2456                                 DWC_MODIFY_REG32(&core_if->
2457                                                  core_global_regs->gpwrdn, 0,
2458                                                  gpwrdn.d32);
2459                                 dwc_udelay(10);
2460
2461                                 gpwrdn.d32 = 0;
2462 #ifdef DWC_DEV_SRPCAP
2463                                 gpwrdn.b.srp_det_msk = 1;
2464 #endif
2465                                 gpwrdn.b.disconn_det_msk = 1;
2466                                 gpwrdn.b.lnstchng_msk = 1;
2467                                 gpwrdn.b.sts_chngint_msk = 1;
2468                                 DWC_MODIFY_REG32(&core_if->
2469                                                  core_global_regs->gpwrdn, 0,
2470                                                  gpwrdn.d32);
2471                                 dwc_udelay(10);
2472
2473                                 /* Enable Power Down Clamp and all interrupts in GPWRDN */
2474                                 gpwrdn.d32 = 0;
2475                                 gpwrdn.b.pwrdnclmp = 1;
2476                                 DWC_MODIFY_REG32(&core_if->
2477                                                  core_global_regs->gpwrdn, 0,
2478                                                  gpwrdn.d32);
2479                                 dwc_udelay(10);
2480
2481                                 /* Switch off VDD */
2482                                 gpwrdn.d32 = 0;
2483                                 gpwrdn.b.pwrdnswtch = 1;
2484                                 DWC_MODIFY_REG32(&core_if->
2485                                                  core_global_regs->gpwrdn, 0,
2486                                                  gpwrdn.d32);
2487
2488 #ifdef DWC_DEV_SRPCAP
2489                                 if (otg_cap_param ==
2490                                     DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
2491                                         core_if->pwron_timer_started = 1;
2492                                         DWC_TIMER_SCHEDULE(core_if->pwron_timer,
2493                                                            6000 /* 6 secs */);
2494                                 }
2495 #endif
2496                                 /* Save gpwrdn register for further usage if stschng interrupt */
2497                                 core_if->gr_backup->gpwrdn_local =
2498                                     DWC_READ_REG32(&core_if->core_global_regs->
2499                                                    gpwrdn);
2500
2501                                 /* Set flag to indicate that we are in hibernation */
2502                                 core_if->hibernation_suspend = 1;
2503                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2504                                                           flags);
2505
2506                                 DWC_PRINTF("Host hibernation completed\n");
2507                                 /* Exit from case statement */
2508                                 break;
2509
2510                         }
2511                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
2512                             dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2513                                 gotgctl_data_t gotgctl = {.d32 = 0 };
2514                                 gotgctl.b.hstsethnpen = 1;
2515                                 DWC_MODIFY_REG32(&core_if->
2516                                                  core_global_regs->gotgctl, 0,
2517                                                  gotgctl.d32);
2518                                 core_if->op_state = A_SUSPEND;
2519                         }
2520                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2521                         hprt0.b.prtsusp = 1;
2522                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2523                         {
2524                                 dwc_irqflags_t flags;
2525                                 /* Update lx_state */
2526                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2527                                 core_if->lx_state = DWC_OTG_L2;
2528                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2529                                                           flags);
2530                         }
2531                         /* Suspend the Phy Clock */
2532                         if (core_if->otg_ver == 0) {
2533                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2534                                 pcgcctl.b.stoppclk = 1;
2535                                 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2536                                                  pcgcctl.d32);
2537                                 dwc_udelay(10);
2538                         }
2539
2540                         /* For HNP the bus must be suspended for at least 200ms. */
2541                         if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2542                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2543                                 pcgcctl.b.stoppclk = 1;
2544                                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2545                                                  0);
2546                                 dwc_mdelay(200);
2547                         }
2548
2549                         /** @todo - check how sw can wait for 1 sec to check asesvld??? */
2550 #if 0
2551                         if (core_if->adp_enable) {
2552                                 gotgctl_data_t gotgctl = {.d32 = 0 };
2553                                 gpwrdn_data_t gpwrdn;
2554
2555                                 while (gotgctl.b.asesvld == 1) {
2556                                         gotgctl.d32 =
2557                                             DWC_READ_REG32
2558                                             (&core_if->core_global_regs->gotgctl);
2559                                         dwc_mdelay(100);
2560                                 }
2561
2562                                 /* Enable Power Down Logic */
2563                                 gpwrdn.d32 = 0;
2564                                 gpwrdn.b.pmuactv = 1;
2565                                 DWC_MODIFY_REG32(&core_if->
2566                                                  core_global_regs->gpwrdn, 0,
2567                                                  gpwrdn.d32);
2568
2569                                 /* Unmask SRP detected interrupt from Power Down Logic */
2570                                 gpwrdn.d32 = 0;
2571                                 gpwrdn.b.srp_det_msk = 1;
2572                                 DWC_MODIFY_REG32(&core_if->
2573                                                  core_global_regs->gpwrdn, 0,
2574                                                  gpwrdn.d32);
2575
2576                                 dwc_otg_adp_probe_start(core_if);
2577                         }
2578 #endif
2579                         break;
2580                 case UHF_PORT_POWER:
2581                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2582                                     "SetPortFeature - USB_PORT_FEAT_POWER\n");
2583                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2584                         hprt0.b.prtpwr = 1;
2585                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2586                         break;
2587                 case UHF_PORT_RESET:
2588                         if ((core_if->power_down == 2)
2589                             && (core_if->hibernation_suspend == 1)) {
2590                                 /* If we are going to exit from Hibernated
2591                                  * state via USB RESET.
2592                                  */
2593                                 dwc_otg_host_hibernation_restore(core_if, 0, 1);
2594                         } else {
2595                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2596
2597                                 DWC_DEBUGPL(DBG_HCD,
2598                                             "DWC OTG HCD HUB CONTROL - "
2599                                             "SetPortFeature - USB_PORT_FEAT_RESET\n");
2600                                 {
2601                                         pcgcctl_data_t pcgcctl = {.d32 = 0 };
2602                                         pcgcctl.b.enbl_sleep_gating = 1;
2603                                         pcgcctl.b.stoppclk = 1;
2604                                         DWC_MODIFY_REG32(core_if->pcgcctl,
2605                                                          pcgcctl.d32, 0);
2606                                         DWC_WRITE_REG32(core_if->pcgcctl, 0);
2607                                 }
2608 #ifdef CONFIG_USB_DWC_OTG_LPM
2609                                 {
2610                                         glpmcfg_data_t lpmcfg;
2611                                         lpmcfg.d32 =
2612                                             DWC_READ_REG32(&core_if->
2613                                                            core_global_regs->
2614                                                            glpmcfg);
2615                                         if (lpmcfg.b.prt_sleep_sts) {
2616                                                 lpmcfg.b.en_utmi_sleep = 0;
2617                                                 lpmcfg.b.hird_thres &=
2618                                                     (~(1 << 4));
2619                                                 DWC_WRITE_REG32(&core_if->
2620                                                                 core_global_regs->
2621                                                                 glpmcfg,
2622                                                                 lpmcfg.d32);
2623                                                 dwc_mdelay(1);
2624                                         }
2625                                 }
2626 #endif
2627                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2628                                 /* Clear suspend bit if resetting from suspended state. */
2629                                 hprt0.b.prtsusp = 0;
2630                                 /* When B-Host the Port reset bit is set in
2631                                  * the Start HCD Callback function, so that
2632                                  * the reset is started within 1ms of the HNP
2633                                  * success interrupt. */
2634                                 if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
2635                                         hprt0.b.prtpwr = 1;
2636                                         hprt0.b.prtrst = 1;
2637                                         DWC_PRINTF
2638                                             ("Indeed it is in host mode hprt0 = %08x\n",
2639                                              hprt0.d32);
2640                                         DWC_WRITE_REG32(core_if->host_if->hprt0,
2641                                                         hprt0.d32);
2642                                 }
2643                                 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2644                                 dwc_mdelay(60);
2645                                 hprt0.b.prtrst = 0;
2646                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2647                                                 hprt0.d32);
2648                                 core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
2649                         }
2650                         break;
2651 #ifdef DWC_HS_ELECT_TST
2652                 case UHF_PORT_TEST:
2653                         {
2654                                 uint32_t t;
2655                                 gintmsk_data_t gintmsk;
2656
2657                                 t = (wIndex >> 8);      /* MSB wIndex USB */
2658                                 DWC_DEBUGPL(DBG_HCD,
2659                                             "DWC OTG HCD HUB CONTROL - "
2660                                             "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
2661                                             t);
2662                                 DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
2663                                 if (t < 6) {
2664                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2665                                         hprt0.b.prttstctl = t;
2666                                         DWC_WRITE_REG32(core_if->host_if->hprt0,
2667                                                         hprt0.d32);
2668                                 } else {
2669                                         /* Setup global vars with reg addresses (quick and
2670                                          * dirty hack, should be cleaned up)
2671                                          */
2672                                         global_regs = core_if->core_global_regs;
2673                                         hc_global_regs =
2674                                             core_if->host_if->host_global_regs;
2675                                         hc_regs =
2676                                             (dwc_otg_hc_regs_t *) ((char *)
2677                                                                    global_regs +
2678                                                                    0x500);
2679                                         data_fifo =
2680                                             (uint32_t *) ((char *)global_regs +
2681                                                           0x1000);
2682
2683                                         if (t == 6) {   /* HS_HOST_PORT_SUSPEND_RESUME */
2684                                                 /* Save current interrupt mask */
2685                                                 gintmsk.d32 =
2686                                                     DWC_READ_REG32
2687                                                     (&global_regs->gintmsk);
2688
2689                                                 /* Disable all interrupts while we muck with
2690                                                  * the hardware directly
2691                                                  */
2692                                                 DWC_WRITE_REG32(&global_regs->
2693                                                                 gintmsk, 0);
2694
2695                                                 /* 15 second delay per the test spec */
2696                                                 dwc_mdelay(15000);
2697
2698                                                 /* Drive suspend on the root port */
2699                                                 hprt0.d32 =
2700                                                     dwc_otg_read_hprt0(core_if);
2701                                                 hprt0.b.prtsusp = 1;
2702                                                 hprt0.b.prtres = 0;
2703                                                 DWC_WRITE_REG32(core_if->
2704                                                                 host_if->hprt0,
2705                                                                 hprt0.d32);
2706
2707                                                 /* 15 second delay per the test spec */
2708                                                 dwc_mdelay(15000);
2709
2710                                                 /* Drive resume on the root port */
2711                                                 hprt0.d32 =
2712                                                     dwc_otg_read_hprt0(core_if);
2713                                                 hprt0.b.prtsusp = 0;
2714                                                 hprt0.b.prtres = 1;
2715                                                 DWC_WRITE_REG32(core_if->
2716                                                                 host_if->hprt0,
2717                                                                 hprt0.d32);
2718                                                 dwc_mdelay(100);
2719
2720                                                 /* Clear the resume bit */
2721                                                 hprt0.b.prtres = 0;
2722                                                 DWC_WRITE_REG32(core_if->
2723                                                                 host_if->hprt0,
2724                                                                 hprt0.d32);
2725
2726                                                 /* Restore interrupts */
2727                                                 DWC_WRITE_REG32(&global_regs->
2728                                                                 gintmsk,
2729                                                                 gintmsk.d32);
2730                                         } else if (t == 7) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2731                                                 /* Save current interrupt mask */
2732                                                 gintmsk.d32 =
2733                                                     DWC_READ_REG32
2734                                                     (&global_regs->gintmsk);
2735
2736                                                 /* Disable all interrupts while we muck with
2737                                                  * the hardware directly
2738                                                  */
2739                                                 DWC_WRITE_REG32(&global_regs->
2740                                                                 gintmsk, 0);
2741
2742                                                 /* 15 second delay per the test spec */
2743                                                 dwc_mdelay(15000);
2744
2745                                                 /* Send the Setup packet */
2746                                                 do_setup();
2747
2748                                                 /* 15 second delay so nothing else happens for awhile */
2749                                                 dwc_mdelay(15000);
2750
2751                                                 /* Restore interrupts */
2752                                                 DWC_WRITE_REG32(&global_regs->
2753                                                                 gintmsk,
2754                                                                 gintmsk.d32);
2755                                         } else if (t == 8) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2756                                                 /* Save current interrupt mask */
2757                                                 gintmsk.d32 =
2758                                                     DWC_READ_REG32
2759                                                     (&global_regs->gintmsk);
2760
2761                                                 /* Disable all interrupts while we muck with
2762                                                  * the hardware directly
2763                                                  */
2764                                                 DWC_WRITE_REG32(&global_regs->
2765                                                                 gintmsk, 0);
2766
2767                                                 /* Send the Setup packet */
2768                                                 do_setup();
2769
2770                                                 /* 15 second delay so nothing else happens for awhile */
2771                                                 dwc_mdelay(15000);
2772
2773                                                 /* Send the In and Ack packets */
2774                                                 do_in_ack();
2775
2776                                                 /* 15 second delay so nothing else happens for awhile */
2777                                                 dwc_mdelay(15000);
2778
2779                                                 /* Restore interrupts */
2780                                                 DWC_WRITE_REG32(&global_regs->
2781                                                                 gintmsk,
2782                                                                 gintmsk.d32);
2783                                         }
2784                                 }
2785                                 break;
2786                         }
2787 #endif /* DWC_HS_ELECT_TST */
2788
2789                 case UHF_PORT_INDICATOR:
2790                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2791                                     "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2792                         /* Not supported */
2793                         break;
2794                 default:
2795                         retval = -DWC_E_INVALID;
2796                         DWC_ERROR("DWC OTG HCD - "
2797                                   "SetPortFeature request %xh "
2798                                   "unknown or unsupported\n", wValue);
2799                         break;
2800                 }
2801                 break;
2802 #ifdef CONFIG_USB_DWC_OTG_LPM
2803         case UCR_SET_AND_TEST_PORT_FEATURE:
2804                 if (wValue != UHF_PORT_L1) {
2805                         goto error;
2806                 }
2807                 {
2808                         int portnum, hird, devaddr, remwake;
2809                         glpmcfg_data_t lpmcfg;
2810                         uint32_t time_usecs;
2811                         gintsts_data_t gintsts;
2812                         gintmsk_data_t gintmsk;
2813
2814                         if (!dwc_otg_get_param_lpm_enable(core_if)) {
2815                                 goto error;
2816                         }
2817                         if (wValue != UHF_PORT_L1 || wLength != 1) {
2818                                 goto error;
2819                         }
2820                         /* Check if the port currently is in SLEEP state */
2821                         lpmcfg.d32 =
2822                             DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
2823                         if (lpmcfg.b.prt_sleep_sts) {
2824                                 DWC_INFO("Port is already in sleep mode\n");
2825                                 buf[0] = 0;     /* Return success */
2826                                 break;
2827                         }
2828
2829                         portnum = wIndex & 0xf;
2830                         hird = (wIndex >> 4) & 0xf;
2831                         devaddr = (wIndex >> 8) & 0x7f;
2832                         remwake = (wIndex >> 15);
2833
2834                         if (portnum != 1) {
2835                                 retval = -DWC_E_INVALID;
2836                                 DWC_WARN
2837                                     ("Wrong port number(%d) in SetandTestPortFeature request\n",
2838                                      portnum);
2839                                 break;
2840                         }
2841
2842                         DWC_PRINTF
2843                             ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
2844                              portnum, hird, devaddr, remwake);
2845                         /* Disable LPM interrupt */
2846                         gintmsk.d32 = 0;
2847                         gintmsk.b.lpmtranrcvd = 1;
2848                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
2849                                          gintmsk.d32, 0);
2850
2851                         if (dwc_otg_hcd_send_lpm
2852                             (dwc_otg_hcd, devaddr, hird, remwake)) {
2853                                 retval = -DWC_E_INVALID;
2854                                 break;
2855                         }
2856
2857                         time_usecs = 10 * (lpmcfg.b.retry_count + 1);
2858                         /* We will consider timeout if time_usecs microseconds pass,
2859                          * and we don't receive LPM transaction status.
2860                          * After receiving non-error responce(ACK/NYET/STALL) from device,
2861                          *  core will set lpmtranrcvd bit.
2862                          */
2863                         do {
2864                                 gintsts.d32 =
2865                                     DWC_READ_REG32(&core_if->core_global_regs->
2866                                                    gintsts);
2867                                 if (gintsts.b.lpmtranrcvd) {
2868                                         break;
2869                                 }
2870                                 dwc_udelay(1);
2871                         } while (--time_usecs);
2872                         /* lpm_int bit will be cleared in LPM interrupt handler */
2873
2874                         /* Now fill status
2875                          * 0x00 - Success
2876                          * 0x10 - NYET
2877                          * 0x11 - Timeout
2878                          */
2879                         if (!gintsts.b.lpmtranrcvd) {
2880                                 buf[0] = 0x3;   /* Completion code is Timeout */
2881                                 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
2882                         } else {
2883                                 lpmcfg.d32 =
2884                                     DWC_READ_REG32(&core_if->core_global_regs->
2885                                                    glpmcfg);
2886                                 if (lpmcfg.b.lpm_resp == 0x3) {
2887                                         /* ACK responce from the device */
2888                                         buf[0] = 0x00;  /* Success */
2889                                 } else if (lpmcfg.b.lpm_resp == 0x2) {
2890                                         /* NYET responce from the device */
2891                                         buf[0] = 0x2;
2892                                 } else {
2893                                         /* Otherwise responce with Timeout */
2894                                         buf[0] = 0x3;
2895                                 }
2896                         }
2897                         DWC_PRINTF("Device responce to LPM trans is %x\n",
2898                                    lpmcfg.b.lpm_resp);
2899                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
2900                                          gintmsk.d32);
2901
2902                         break;
2903                 }
2904 #endif /* CONFIG_USB_DWC_OTG_LPM */
2905         default:
2906 error:
2907                 retval = -DWC_E_INVALID;
2908                 DWC_WARN("DWC OTG HCD - "
2909                          "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2910                          typeReq, wIndex, wValue);
2911                 break;
2912         }
2913
2914         return retval;
2915 }
2916
2917 #ifdef CONFIG_USB_DWC_OTG_LPM
2918 /** Returns index of host channel to perform LPM transaction. */
2919 int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t *hcd, uint8_t devaddr)
2920 {
2921         dwc_otg_core_if_t *core_if = hcd->core_if;
2922         dwc_hc_t *hc;
2923         hcchar_data_t hcchar;
2924         gintmsk_data_t gintmsk = {.d32 = 0 };
2925
2926         if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
2927                 DWC_PRINTF("No free channel to select for LPM transaction\n");
2928                 return -1;
2929         }
2930
2931         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
2932
2933         /* Mask host channel interrupts. */
2934         gintmsk.b.hcintr = 1;
2935         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
2936
2937         /* Fill fields that core needs for LPM transaction */
2938         hcchar.b.devaddr = devaddr;
2939         hcchar.b.epnum = 0;
2940         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2941         hcchar.b.mps = 64;
2942         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2943         hcchar.b.epdir = 0;     /* OUT */
2944         DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
2945                         hcchar.d32);
2946
2947         /* Remove the host channel from the free list. */
2948         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
2949
2950         DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
2951
2952         return hc->hc_num;
2953 }
2954
2955 /** Release hc after performing LPM transaction */
2956 void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t *hcd)
2957 {
2958         dwc_hc_t *hc;
2959         glpmcfg_data_t lpmcfg;
2960         uint8_t hc_num;
2961
2962         lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2963         hc_num = lpmcfg.b.lpm_chan_index;
2964
2965         hc = hcd->hc_ptr_array[hc_num];
2966
2967         DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
2968         /* Return host channel to free list */
2969         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
2970 }
2971
2972 int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t *hcd, uint8_t devaddr, uint8_t hird,
2973                          uint8_t bRemoteWake)
2974 {
2975         glpmcfg_data_t lpmcfg;
2976         pcgcctl_data_t pcgcctl = {.d32 = 0 };
2977         int channel;
2978
2979         channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
2980         if (channel < 0) {
2981                 return channel;
2982         }
2983
2984         pcgcctl.b.enbl_sleep_gating = 1;
2985         DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
2986
2987         /* Read LPM config register */
2988         lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2989
2990         /* Program LPM transaction fields */
2991         lpmcfg.b.rem_wkup_en = bRemoteWake;
2992         lpmcfg.b.hird = hird;
2993
2994         if (dwc_otg_get_param_besl_enable(hcd->core_if)) {
2995                 lpmcfg.b.hird_thres = 0x16;
2996                 lpmcfg.b.en_besl = 1;
2997         } else {
2998                 lpmcfg.b.hird_thres = 0x1c;
2999         }
3000
3001         lpmcfg.b.lpm_chan_index = channel;
3002         lpmcfg.b.en_utmi_sleep = 1;
3003         /* Program LPM config register */
3004         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3005
3006         /* Send LPM transaction */
3007         lpmcfg.b.send_lpm = 1;
3008         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3009
3010         return 0;
3011 }
3012
3013 #endif /* CONFIG_USB_DWC_OTG_LPM */
3014
3015 int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t *hcd, int port)
3016 {
3017         int retval;
3018
3019         if (port != 1) {
3020                 return -DWC_E_INVALID;
3021         }
3022
3023         retval = (hcd->flags.b.port_connect_status_change ||
3024                   hcd->flags.b.port_reset_change ||
3025                   hcd->flags.b.port_enable_change ||
3026                   hcd->flags.b.port_suspend_change ||
3027                   hcd->flags.b.port_over_current_change);
3028 #ifdef DEBUG
3029         if (retval) {
3030                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
3031                             " Root port status changed\n");
3032                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
3033                             hcd->flags.b.port_connect_status_change);
3034                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
3035                             hcd->flags.b.port_reset_change);
3036                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
3037                             hcd->flags.b.port_enable_change);
3038                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
3039                             hcd->flags.b.port_suspend_change);
3040                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
3041                             hcd->flags.b.port_over_current_change);
3042         }
3043 #endif
3044         return retval;
3045 }
3046
3047 int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t *dwc_otg_hcd)
3048 {
3049         hfnum_data_t hfnum;
3050         hfnum.d32 =
3051             DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->
3052                            host_global_regs->hfnum);
3053
3054 #ifdef DEBUG_SOF
3055         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
3056                     hfnum.b.frnum);
3057 #endif
3058         return hfnum.b.frnum;
3059 }
3060
3061 int dwc_otg_hcd_start(dwc_otg_hcd_t *hcd,
3062                       struct dwc_otg_hcd_function_ops *fops)
3063 {
3064         int retval = 0;
3065
3066         hcd->fops = fops;
3067         if (!dwc_otg_is_device_mode(hcd->core_if) &&
3068             (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
3069                 dwc_otg_hcd_reinit(hcd);
3070         } else {
3071                 retval = -DWC_E_NO_DEVICE;
3072         }
3073
3074         return retval;
3075 }
3076
3077 void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t *hcd)
3078 {
3079         return hcd->priv;
3080 }
3081
3082 void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t *hcd, void *priv_data)
3083 {
3084         hcd->priv = priv_data;
3085 }
3086
3087 uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t *hcd)
3088 {
3089         return hcd->otg_port;
3090 }
3091
3092 uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t *hcd)
3093 {
3094         uint32_t is_b_host;
3095         if (hcd->core_if->op_state == B_HOST) {
3096                 is_b_host = 1;
3097         } else {
3098                 is_b_host = 0;
3099         }
3100
3101         return is_b_host;
3102 }
3103
3104 dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t *hcd,
3105                                          int iso_desc_count, int atomic_alloc)
3106 {
3107         dwc_otg_hcd_urb_t *dwc_otg_urb;
3108         uint32_t size;
3109
3110         size =
3111             sizeof(*dwc_otg_urb) +
3112             iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
3113         if (atomic_alloc)
3114                 dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
3115         else
3116                 dwc_otg_urb = DWC_ALLOC(size);
3117
3118         dwc_otg_urb->packet_count = iso_desc_count;
3119
3120         return dwc_otg_urb;
3121 }
3122
3123 void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t *dwc_otg_urb,
3124                                   uint8_t dev_addr, uint8_t ep_num,
3125                                   uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
3126 {
3127         dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
3128                               ep_type, ep_dir, mps);
3129 #if 0
3130         DWC_PRINTF
3131             ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
3132              dev_addr, ep_num, ep_dir, ep_type, mps);
3133 #endif
3134 }
3135
3136 void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3137                                 void *urb_handle, void *buf, dwc_dma_t dma,
3138                                 uint32_t buflen, void *setup_packet,
3139                                 dwc_dma_t setup_dma, uint32_t flags,
3140                                 uint16_t interval)
3141 {
3142         dwc_otg_urb->priv = urb_handle;
3143         dwc_otg_urb->buf = buf;
3144         dwc_otg_urb->dma = dma;
3145         dwc_otg_urb->length = buflen;
3146         dwc_otg_urb->setup_packet = setup_packet;
3147         dwc_otg_urb->setup_dma = setup_dma;
3148         dwc_otg_urb->flags = flags;
3149         dwc_otg_urb->interval = interval;
3150         dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
3151 }
3152
3153 uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t *dwc_otg_urb)
3154 {
3155         return dwc_otg_urb->status;
3156 }
3157
3158 uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *dwc_otg_urb)
3159 {
3160         return dwc_otg_urb->actual_length;
3161 }
3162
3163 uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *dwc_otg_urb)
3164 {
3165         return dwc_otg_urb->error_count;
3166 }
3167
3168 void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3169                                          int desc_num, uint32_t offset,
3170                                          uint32_t length)
3171 {
3172         dwc_otg_urb->iso_descs[desc_num].offset = offset;
3173         dwc_otg_urb->iso_descs[desc_num].length = length;
3174 }
3175
3176 uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *dwc_otg_urb,
3177                                              int desc_num)
3178 {
3179         return dwc_otg_urb->iso_descs[desc_num].status;
3180 }
3181
3182 uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
3183                                                     dwc_otg_urb, int desc_num)
3184 {
3185         return dwc_otg_urb->iso_descs[desc_num].actual_length;
3186 }
3187
3188 int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t *hcd, void *ep_handle)
3189 {
3190         int allocated = 0;
3191         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3192
3193         if (qh) {
3194                 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3195                         allocated = 1;
3196                 }
3197         }
3198         return allocated;
3199 }
3200
3201 int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t *hcd, void *ep_handle)
3202 {
3203         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3204         int freed = 0;
3205         DWC_ASSERT(qh, "qh is not allocated\n");
3206
3207         if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3208                 freed = 1;
3209         }
3210
3211         return freed;
3212 }
3213
3214 uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t *hcd, void *ep_handle)
3215 {
3216         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3217         DWC_ASSERT(qh, "qh is not allocated\n");
3218         return qh->usecs;
3219 }
3220
3221 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
3222 {
3223 #ifdef DEBUG
3224         int num_channels;
3225         int i;
3226         gnptxsts_data_t np_tx_status;
3227         hptxsts_data_t p_tx_status;
3228
3229         num_channels = hcd->core_if->core_params->host_channels;
3230         DWC_PRINTF("\n");
3231         DWC_PRINTF
3232             ("************************************************************\n");
3233         DWC_PRINTF("HCD State:\n");
3234         DWC_PRINTF("  Num channels: %d\n", num_channels);
3235         for (i = 0; i < num_channels; i++) {
3236                 dwc_hc_t *hc = hcd->hc_ptr_array[i];
3237                 DWC_PRINTF("  Channel %d:\n", i);
3238                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3239                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
3240                 DWC_PRINTF("    speed: %d\n", hc->speed);
3241                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
3242                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
3243                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
3244                 DWC_PRINTF("    multi_count: %d\n", hc->multi_count);
3245                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
3246                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
3247                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
3248                 DWC_PRINTF("    xfer_count: %d\n", hc->xfer_count);
3249                 DWC_PRINTF("    halt_on_queue: %d\n", hc->halt_on_queue);
3250                 DWC_PRINTF("    halt_pending: %d\n", hc->halt_pending);
3251                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
3252                 DWC_PRINTF("    do_split: %d\n", hc->do_split);
3253                 DWC_PRINTF("    complete_split: %d\n", hc->complete_split);
3254                 DWC_PRINTF("    hub_addr: %d\n", hc->hub_addr);
3255                 DWC_PRINTF("    port_addr: %d\n", hc->port_addr);
3256                 DWC_PRINTF("    xact_pos: %d\n", hc->xact_pos);
3257                 DWC_PRINTF("    requests: %d\n", hc->requests);
3258                 DWC_PRINTF("    qh: %p\n", hc->qh);
3259                 if (hc->xfer_started) {
3260                         hfnum_data_t hfnum;
3261                         hcchar_data_t hcchar;
3262                         hctsiz_data_t hctsiz;
3263                         hcint_data_t hcint;
3264                         hcintmsk_data_t hcintmsk;
3265                         hfnum.d32 =
3266                             DWC_READ_REG32(&hcd->core_if->host_if->
3267                                            host_global_regs->hfnum);
3268                         hcchar.d32 =
3269                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3270                                            hcchar);
3271                         hctsiz.d32 =
3272                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3273                                            hctsiz);
3274                         hcint.d32 =
3275                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3276                                            hcint);
3277                         hcintmsk.d32 =
3278                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3279                                            hcintmsk);
3280                         DWC_PRINTF("    hfnum: 0x%08x\n", hfnum.d32);
3281                         DWC_PRINTF("    hcchar: 0x%08x\n", hcchar.d32);
3282                         DWC_PRINTF("    hctsiz: 0x%08x\n", hctsiz.d32);
3283                         DWC_PRINTF("    hcint: 0x%08x\n", hcint.d32);
3284                         DWC_PRINTF("    hcintmsk: 0x%08x\n", hcintmsk.d32);
3285                 }
3286                 if (hc->xfer_started && hc->qh) {
3287                         dwc_otg_qtd_t *qtd;
3288                         dwc_otg_hcd_urb_t *urb;
3289
3290                         DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list,
3291                                             qtd_list_entry) {
3292                                 if (!qtd->in_process)
3293                                         break;
3294
3295                                 urb = qtd->urb;
3296                                 DWC_PRINTF("    URB Info:\n");
3297                                 DWC_PRINTF("      qtd: %p, urb: %p\n", qtd,
3298                                            urb);
3299                                 if (urb) {
3300                                         DWC_PRINTF("      Dev: %d, EP: %d %s\n",
3301                                                    dwc_otg_hcd_get_dev_addr
3302                                                    (&urb->pipe_info),
3303                                                    dwc_otg_hcd_get_ep_num
3304                                                    (&urb->pipe_info),
3305                                                    dwc_otg_hcd_is_pipe_in
3306                                                    (&urb->pipe_info) ? "IN" :
3307                                                    "OUT");
3308                                         DWC_PRINTF
3309                                             ("      Max packet size: %d\n",
3310                                              dwc_otg_hcd_get_mps
3311                                              (&urb->pipe_info));
3312                                         DWC_PRINTF
3313                                             ("      transfer_buffer: %p\n",
3314                                              urb->buf);
3315                                         DWC_PRINTF("      transfer_dma: %p\n",
3316                                                    (void *)urb->dma);
3317                                         DWC_PRINTF
3318                                             ("      transfer_buffer_length: %d\n",
3319                                              urb->length);
3320                                         DWC_PRINTF("      actual_length: %d\n",
3321                                                    urb->actual_length);
3322                                 }
3323                         }
3324                 }
3325         }
3326         DWC_PRINTF("  non_periodic_channels: %d\n", hcd->non_periodic_channels);
3327         DWC_PRINTF("  periodic_channels: %d\n", hcd->periodic_channels);
3328         DWC_PRINTF("  periodic_usecs: %d\n", hcd->periodic_usecs);
3329         np_tx_status.d32 =
3330             DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
3331         DWC_PRINTF("  NP Tx Req Queue Space Avail: %d\n",
3332                    np_tx_status.b.nptxqspcavail);
3333         DWC_PRINTF("  NP Tx FIFO Space Avail: %d\n",
3334                    np_tx_status.b.nptxfspcavail);
3335         p_tx_status.d32 =
3336             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
3337         DWC_PRINTF("  P Tx Req Queue Space Avail: %d\n",
3338                    p_tx_status.b.ptxqspcavail);
3339         DWC_PRINTF("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3340         dwc_otg_hcd_dump_frrem(hcd);
3341         dwc_otg_dump_global_registers(hcd->core_if);
3342         dwc_otg_dump_host_registers(hcd->core_if);
3343         DWC_PRINTF
3344             ("************************************************************\n");
3345         DWC_PRINTF("\n");
3346 #endif
3347 }
3348
3349 #ifdef DEBUG
3350 void dwc_print_setup_data(uint8_t *setup)
3351 {
3352         int i;
3353         if (CHK_DEBUG_LEVEL(DBG_HCD)) {
3354                 DWC_PRINTF("Setup Data = MSB ");
3355                 for (i = 7; i >= 0; i--)
3356                         DWC_PRINTF("%02x ", setup[i]);
3357                 DWC_PRINTF("\n");
3358                 DWC_PRINTF("  bmRequestType Tranfer = %s\n",
3359                            (setup[0] & 0x80) ? "Device-to-Host" :
3360                            "Host-to-Device");
3361                 DWC_PRINTF("  bmRequestType Type = ");
3362                 switch ((setup[0] & 0x60) >> 5) {
3363                 case 0:
3364                         DWC_PRINTF("Standard\n");
3365                         break;
3366                 case 1:
3367                         DWC_PRINTF("Class\n");
3368                         break;
3369                 case 2:
3370                         DWC_PRINTF("Vendor\n");
3371                         break;
3372                 case 3:
3373                         DWC_PRINTF("Reserved\n");
3374                         break;
3375                 }
3376                 DWC_PRINTF("  bmRequestType Recipient = ");
3377                 switch (setup[0] & 0x1f) {
3378                 case 0:
3379                         DWC_PRINTF("Device\n");
3380                         break;
3381                 case 1:
3382                         DWC_PRINTF("Interface\n");
3383                         break;
3384                 case 2:
3385                         DWC_PRINTF("Endpoint\n");
3386                         break;
3387                 case 3:
3388                         DWC_PRINTF("Other\n");
3389                         break;
3390                 default:
3391                         DWC_PRINTF("Reserved\n");
3392                         break;
3393                 }
3394                 DWC_PRINTF("  bRequest = 0x%0x\n", setup[1]);
3395                 DWC_PRINTF("  wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3396                 DWC_PRINTF("  wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3397                 DWC_PRINTF("  wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3398         }
3399 }
3400 #endif
3401
3402 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd)
3403 {
3404 #if 0
3405         DWC_PRINTF("Frame remaining at SOF:\n");
3406         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3407                    hcd->frrem_samples, hcd->frrem_accum,
3408                    (hcd->frrem_samples > 0) ?
3409                    hcd->frrem_accum / hcd->frrem_samples : 0);
3410
3411         DWC_PRINTF("\n");
3412         DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
3413         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3414                    hcd->core_if->hfnum_7_samples,
3415                    hcd->core_if->hfnum_7_frrem_accum,
3416                    (hcd->core_if->hfnum_7_samples >
3417                     0) ? hcd->core_if->hfnum_7_frrem_accum /
3418                    hcd->core_if->hfnum_7_samples : 0);
3419         DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
3420         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3421                    hcd->core_if->hfnum_0_samples,
3422                    hcd->core_if->hfnum_0_frrem_accum,
3423                    (hcd->core_if->hfnum_0_samples >
3424                     0) ? hcd->core_if->hfnum_0_frrem_accum /
3425                    hcd->core_if->hfnum_0_samples : 0);
3426         DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
3427         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3428                    hcd->core_if->hfnum_other_samples,
3429                    hcd->core_if->hfnum_other_frrem_accum,
3430                    (hcd->core_if->hfnum_other_samples >
3431                     0) ? hcd->core_if->hfnum_other_frrem_accum /
3432                    hcd->core_if->hfnum_other_samples : 0);
3433
3434         DWC_PRINTF("\n");
3435         DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
3436         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3437                    hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
3438                    (hcd->hfnum_7_samples_a > 0) ?
3439                    hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
3440         DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
3441         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3442                    hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
3443                    (hcd->hfnum_0_samples_a > 0) ?
3444                    hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
3445         DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
3446         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3447                    hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
3448                    (hcd->hfnum_other_samples_a > 0) ?
3449                    hcd->hfnum_other_frrem_accum_a /
3450                    hcd->hfnum_other_samples_a : 0);
3451
3452         DWC_PRINTF("\n");
3453         DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
3454         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3455                    hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
3456                    (hcd->hfnum_7_samples_b > 0) ?
3457                    hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
3458         DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
3459         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3460                    hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
3461                    (hcd->hfnum_0_samples_b > 0) ?
3462                    hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
3463         DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
3464         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3465                    hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
3466                    (hcd->hfnum_other_samples_b > 0) ?
3467                    hcd->hfnum_other_frrem_accum_b /
3468                    hcd->hfnum_other_samples_b : 0);
3469 #endif
3470 }
3471
3472 #endif /* DWC_DEVICE_ONLY */