drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
   3  * $Revision: #92 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 #include "dwc_otg_hcd.h"
  36 #include "dwc_otg_regs.h"
  37 #include <linux/usb.h>
  38 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
  39 #include <../drivers/usb/core/hcd.h>
  40 #else
  41 #include <linux/usb/hcd.h>
  42 #endif
  43 /** @file
  44  * This file contains the implementation of the HCD Interrupt handlers.
  45  */
  46
  47 /** This function handles interrupts for the HCD. */
  48 int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd)
  49 {
  50         int retval = 0;
  51
  52         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
  53         gintsts_data_t gintsts;
  54 #ifdef DEBUG
  55         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
  56 #endif
  57
  58         if (dwc_otg_check_haps_status(core_if) == -1) {
  59                 DWC_WARN("HAPS is disconnected");
  60                 return retval;
  61         }
  62
  63         /* Exit from ISR if core is hibernated */
  64         if (core_if->hibernation_suspend == 1) {
  65                 return retval;
  66         }
  67         DWC_SPINLOCK(dwc_otg_hcd->lock);
  68         /* Check if HOST Mode */
  69         if (dwc_otg_is_host_mode(core_if)) {
  70                 gintsts.d32 = dwc_otg_read_core_intr(core_if);
  71                 if (!gintsts.d32) {
  72                         DWC_SPINUNLOCK(dwc_otg_hcd->lock);
  73                         return 0;
  74                 }
  75 #ifdef DEBUG
  76                 /* Don't print debug message in the interrupt handler on SOF */
  77 #ifndef DEBUG_SOF
  78                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
  79 #endif
  80                         DWC_DEBUGPL(DBG_HCD, "\n");
  81 #endif
  82
  83 #ifdef DEBUG
  84 #ifndef DEBUG_SOF
  85                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
  86 #endif
  87                         DWC_DEBUGPL(DBG_HCD,
  88                                     "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
  89                                     gintsts.d32);
  90 #endif
  91
  92                 if (gintsts.b.sofintr) {
  93                         retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
  94                 }
  95                 if (gintsts.b.rxstsqlvl) {
  96                         retval |=
  97                             dwc_otg_hcd_handle_rx_status_q_level_intr
  98                             (dwc_otg_hcd);
  99                 }
 100                 if (gintsts.b.nptxfempty) {
 101                         retval |=
 102                             dwc_otg_hcd_handle_np_tx_fifo_empty_intr
 103                             (dwc_otg_hcd);
 104                 }
 105                 if (gintsts.b.i2cintr) {
 106                         /** @todo Implement i2cintr handler. */
 107                 }
 108                 if (gintsts.b.portintr) {
 109                         retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
 110                 }
 111                 if (gintsts.b.hcintr) {
 112                         retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
 113                 }
 114                 if (gintsts.b.ptxfempty) {
 115                         retval |=
 116                             dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
 117                             (dwc_otg_hcd);
 118                 }
 119 #ifdef DEBUG
 120 #ifndef DEBUG_SOF
 121                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
 122 #endif
 123                 {
 124                         DWC_DEBUGPL(DBG_HCD,
 125                                     "DWC OTG HCD Finished Servicing Interrupts\n");
 126                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
 127                                     DWC_READ_REG32(&global_regs->gintsts));
 128                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
 129                                     DWC_READ_REG32(&global_regs->gintmsk));
 130                 }
 131 #endif
 132
 133 #ifdef DEBUG
 134 #ifndef DEBUG_SOF
 135                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
 136 #endif
 137                         DWC_DEBUGPL(DBG_HCD, "\n");
 138 #endif
 139
 140         }
 141         DWC_SPINUNLOCK(dwc_otg_hcd->lock);
 142         return retval;
 143 }
 144
 145 #ifdef DWC_TRACK_MISSED_SOFS
 146 #warning Compiling code to track missed SOFs
 147 #define FRAME_NUM_ARRAY_SIZE 1000
 148 /**
 149  * This function is for debug only.
 150  */
 151 static inline void track_missed_sofs(uint16_t curr_frame_number)
 152 {
 153         static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
 154         static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
 155         static int frame_num_idx;
 156         static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
 157         static int dumped_frame_num_array;
 158
 159         if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
 160                 if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
 161                     curr_frame_number) {
 162                         frame_num_array[frame_num_idx] = curr_frame_number;
 163                         last_frame_num_array[frame_num_idx++] = last_frame_num;
 164                 }
 165         } else if (!dumped_frame_num_array) {
 166                 int i;
 167                 DWC_PRINTF("Frame     Last Frame\n");
 168                 DWC_PRINTF("-----     ----------\n");
 169                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
 170                         DWC_PRINTF("0x%04x    0x%04x\n",
 171                                    frame_num_array[i], last_frame_num_array[i]);
 172                 }
 173                 dumped_frame_num_array = 1;
 174         }
 175         last_frame_num = curr_frame_number;
 176 }
 177 #endif
 178
 179 /**
 180  * Handles the start-of-frame interrupt in host mode. Non-periodic
 181  * transactions may be queued to the DWC_otg controller for the current
 182  * (micro)frame. Periodic transactions may be queued to the controller for the
 183  * next (micro)frame.
 184  */
 185 int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *hcd)
 186 {
 187         hfnum_data_t hfnum;
 188         dwc_list_link_t *qh_entry;
 189         dwc_otg_qh_t *qh;
 190         dwc_otg_transaction_type_e tr_type;
 191         gintsts_data_t gintsts = {.d32 = 0 };
 192
 193         hfnum.d32 =
 194             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
 195
 196 #ifdef DEBUG_SOF
 197         DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
 198 #endif
 199         hcd->frame_number = hfnum.b.frnum;
 200
 201 #ifdef DEBUG
 202         hcd->frrem_accum += hfnum.b.frrem;
 203         hcd->frrem_samples++;
 204 #endif
 205
 206 #ifdef DWC_TRACK_MISSED_SOFS
 207         track_missed_sofs(hcd->frame_number);
 208 #endif
 209         /* Determine whether any periodic QHs should be executed. */
 210         qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
 211         while (qh_entry != &hcd->periodic_sched_inactive) {
 212                 qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
 213                 qh_entry = qh_entry->next;
 214                 if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
 215                         /*
 216                          * Move QH to the ready list to be executed next
 217                          * (micro)frame.
 218                          */
 219                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
 220                                            &qh->qh_list_entry);
 221                 }
 222         }
 223         tr_type = dwc_otg_hcd_select_transactions(hcd);
 224         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 225                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
 226         }
 227
 228         /* Clear interrupt */
 229         gintsts.b.sofintr = 1;
 230         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
 231
 232         return 1;
 233 }
 234
 235 /** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
 236  * least one packet in the Rx FIFO.  The packets are moved from the FIFO to
 237  * memory if the DWC_otg controller is operating in Slave mode. */
 238 int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 239 {
 240         host_grxsts_data_t grxsts;
 241         dwc_hc_t *hc = NULL;
 242
 243         DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
 244
 245         grxsts.d32 =
 246             DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
 247
 248         hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
 249         if (!hc) {
 250                 DWC_ERROR("Unable to get corresponding channel\n");
 251                 return 0;
 252         }
 253
 254         /* Packet Status */
 255         DWC_DEBUGPL(DBG_HCDV, "    Ch num = %d\n", grxsts.b.chnum);
 256         DWC_DEBUGPL(DBG_HCDV, "    Count = %d\n", grxsts.b.bcnt);
 257         DWC_DEBUGPL(DBG_HCDV, "    DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
 258                     hc->data_pid_start);
 259         DWC_DEBUGPL(DBG_HCDV, "    PStatus = %d\n", grxsts.b.pktsts);
 260
 261         switch (grxsts.b.pktsts) {
 262         case DWC_GRXSTS_PKTSTS_IN:
 263                 /* Read the data into the host buffer. */
 264                 if (grxsts.b.bcnt > 0) {
 265                         dwc_otg_read_packet(dwc_otg_hcd->core_if,
 266                                             hc->xfer_buff, grxsts.b.bcnt);
 267
 268                         /* Update the HC fields for the next packet received. */
 269                         hc->xfer_count += grxsts.b.bcnt;
 270                         hc->xfer_buff += grxsts.b.bcnt;
 271                 }
 272
 273         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
 274         case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
 275         case DWC_GRXSTS_PKTSTS_CH_HALTED:
 276                 /* Handled in interrupt, just ignore data */
 277                 break;
 278         default:
 279                 DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
 280                           grxsts.b.pktsts);
 281                 break;
 282         }
 283
 284         return 1;
 285 }
 286
 287 /** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 288  * data packets may be written to the FIFO for OUT transfers. More requests
 289  * may be written to the non-periodic request queue for IN transfers. This
 290  * interrupt is enabled only in Slave mode. */
 291 int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 292 {
 293         DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 294         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
 295                                        DWC_OTG_TRANSACTION_NON_PERIODIC);
 296         return 1;
 297 }
 298
 299 /** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 300  * packets may be written to the FIFO for OUT transfers. More requests may be
 301  * written to the periodic request queue for IN transfers. This interrupt is
 302  * enabled only in Slave mode. */
 303 int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 304 {
 305         DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
 306         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
 307                                        DWC_OTG_TRANSACTION_PERIODIC);
 308         return 1;
 309 }
 310
 311 /** There are multiple conditions that can cause a port interrupt. This function
 312  * determines which interrupt conditions have occurred and handles them
 313  * appropriately. */
 314 int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 315 {
 316         int retval = 0;
 317         hprt0_data_t hprt0;
 318         hprt0_data_t hprt0_modify;
 319         struct usb_hcd *hcd = dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
 320         struct usb_bus *bus = hcd_to_bus(hcd);
 321
 322         hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 323         hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 324
 325         /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
 326          * GINTSTS */
 327
 328         hprt0_modify.b.prtena = 0;
 329         hprt0_modify.b.prtconndet = 0;
 330         hprt0_modify.b.prtenchng = 0;
 331         hprt0_modify.b.prtovrcurrchng = 0;
 332
 333         /* Port Connect Detected
 334          * Set flag and clear if detected */
 335         if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
 336                 /* Dont modify port status if we are in hibernation state */
 337                 hprt0_modify.b.prtconndet = 1;
 338                 hprt0_modify.b.prtenchng = 1;
 339                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
 340                                 hprt0_modify.d32);
 341                 hprt0.d32 =
 342                     DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 343                 return retval;
 344         }
 345
 346         if (hprt0.b.prtconndet) {
 347                 /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
 348                 if (dwc_otg_hcd->core_if->adp_enable &&
 349                     dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
 350                         DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
 351                         DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.
 352                                          vbuson_timer);
 353                         dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
 354                         /* TODO - check if this is required, as
 355                          * host initialization was already performed
 356                          * after initial ADP probing
 357                          */
 358                         /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
 359                            dwc_otg_core_init(dwc_otg_hcd->core_if);
 360                            dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
 361                            cil_hcd_start(dwc_otg_hcd->core_if); */
 362                 } else {
 363                         hprt0_data_t hprt0_local;
 364                         /* check if root hub is in suspend state
 365                          * if root hub in suspend, resume it.
 366                          */
 367                         if ((bus->root_hub)
 368                             && (hcd->state == HC_STATE_SUSPENDED)) {
 369                                 DWC_PRINTF
 370                                     ("%s: hcd->state = %d, hcd->flags = %ld\n",
 371                                      __func__, hcd->state, hcd->flags);
 372                                 usb_hcd_resume_root_hub(hcd);
 373                         }
 374                         DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
 375                                     "Port Connect Detected--\n", hprt0.d32);
 376                         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 377                         dwc_otg_hcd->flags.b.port_connect_status = 1;
 378                         hprt0_modify.b.prtconndet = 1;
 379                         /* PET testing */
 380                         if (dwc_otg_hcd->core_if->otg_ver
 381                             && (dwc_otg_hcd->core_if->test_mode == 7)) {
 382                                 hprt0_local.d32 =
 383                                     dwc_otg_read_hprt0(dwc_otg_hcd->core_if);
 384                                 hprt0_local.b.prtrst = 1;
 385                                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->
 386                                                 hprt0, hprt0_local.d32);
 387                                 dwc_mdelay(60);
 388                                 hprt0.d32 =
 389                                     dwc_otg_read_hprt0(dwc_otg_hcd->core_if);
 390                                 hprt0.b.prtrst = 0;
 391                                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->
 392                                                 hprt0, hprt0.d32);
 393                         }
 394
 395                         /* B-Device has connected, Delete the connection timer. */
 396                         DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
 397                 }
 398                 /* The Hub driver asserts a reset when it sees port connect
 399                  * status change flag */
 400                 retval |= 1;
 401         }
 402
 403         /* Port Enable Changed
 404          * Clear if detected - Set internal flag if disabled */
 405         if (hprt0.b.prtenchng) {
 406                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
 407                             "Port Enable Changed--\n", hprt0.d32);
 408                 hprt0_modify.b.prtenchng = 1;
 409                 if (hprt0.b.prtena == 1) {
 410                         hfir_data_t hfir;
 411                         int do_reset = 0;
 412                         dwc_otg_core_params_t *params =
 413                             dwc_otg_hcd->core_if->core_params;
 414                         dwc_otg_core_global_regs_t *global_regs =
 415                             dwc_otg_hcd->core_if->core_global_regs;
 416                         dwc_otg_host_if_t *host_if =
 417                             dwc_otg_hcd->core_if->host_if;
 418
 419                         /* Every time when port enables calculate
 420                          * HFIR.FrInterval
 421                          */
 422                         hfir.d32 =
 423                             DWC_READ_REG32(&host_if->host_global_regs->hfir);
 424                         hfir.b.frint =
 425                             calc_frame_interval(dwc_otg_hcd->core_if);
 426                         DWC_WRITE_REG32(&host_if->host_global_regs->hfir,
 427                                         hfir.d32);
 428
 429                         /* Check if we need to adjust the PHY clock speed for
 430                          * low power and adjust it */
 431                         if (params->host_support_fs_ls_low_power) {
 432                                 gusbcfg_data_t usbcfg;
 433
 434                                 usbcfg.d32 =
 435                                     DWC_READ_REG32(&global_regs->gusbcfg);
 436
 437                                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
 438                                     || hprt0.b.prtspd ==
 439                                     DWC_HPRT0_PRTSPD_FULL_SPEED) {
 440                                         /*
 441                                          * Low power
 442                                          */
 443                                         hcfg_data_t hcfg;
 444                                         if (usbcfg.b.phylpwrclksel == 0) {
 445                                                 /* Set PHY low power clock select for FS/LS devices */
 446                                                 usbcfg.b.phylpwrclksel = 1;
 447                                                 DWC_WRITE_REG32
 448                                                     (&global_regs->gusbcfg,
 449                                                      usbcfg.d32);
 450                                                 do_reset = 1;
 451                                         }
 452
 453                                         hcfg.d32 =
 454                                             DWC_READ_REG32
 455                                             (&host_if->host_global_regs->hcfg);
 456
 457                                         if (hprt0.b.prtspd ==
 458                                             DWC_HPRT0_PRTSPD_LOW_SPEED
 459                                             && params->host_ls_low_power_phy_clk
 460                                             ==
 461                                             DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
 462                                                 /* 6 MHZ */
 463                                                 DWC_DEBUGPL(DBG_CIL,
 464                                                             "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
 465                                                 if (hcfg.b.fslspclksel !=
 466                                                     DWC_HCFG_6_MHZ) {
 467                                                         hcfg.b.fslspclksel =
 468                                                             DWC_HCFG_6_MHZ;
 469                                                         DWC_WRITE_REG32
 470                                                             (&host_if->
 471                                                              host_global_regs->
 472                                                              hcfg, hcfg.d32);
 473                                                         do_reset = 1;
 474                                                 }
 475                                         } else {
 476                                                 /* 48 MHZ */
 477                                                 DWC_DEBUGPL(DBG_CIL,
 478                                                             "FS_PHY programming HCFG to 48 MHz ()\n");
 479                                                 if (hcfg.b.fslspclksel !=
 480                                                     DWC_HCFG_48_MHZ) {
 481                                                         hcfg.b.fslspclksel =
 482                                                             DWC_HCFG_48_MHZ;
 483                                                         DWC_WRITE_REG32
 484                                                             (&host_if->
 485                                                              host_global_regs->
 486                                                              hcfg, hcfg.d32);
 487                                                         do_reset = 1;
 488                                                 }
 489                                         }
 490                                 } else {
 491                                         /*
 492                                          * Not low power
 493                                          */
 494                                         if (usbcfg.b.phylpwrclksel == 1) {
 495                                                 usbcfg.b.phylpwrclksel = 0;
 496                                                 DWC_WRITE_REG32
 497                                                     (&global_regs->gusbcfg,
 498                                                      usbcfg.d32);
 499                                                 do_reset = 1;
 500                                         }
 501                                 }
 502
 503                                 if (do_reset) {
 504                                         DWC_TASK_SCHEDULE(dwc_otg_hcd->
 505                                                           reset_tasklet);
 506                                 }
 507                         }
 508
 509                         if (!do_reset) {
 510                                 /* Port has been enabled set the reset change flag */
 511                                 dwc_otg_hcd->flags.b.port_reset_change = 1;
 512                         }
 513                 } else {
 514                         dwc_otg_hcd->flags.b.port_enable_change = 1;
 515                 }
 516                 retval |= 1;
 517         }
 518
 519         /** Overcurrent Change Interrupt */
 520         if (hprt0.b.prtovrcurrchng) {
 521                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
 522                             "Port Overcurrent Changed--\n", hprt0.d32);
 523                 dwc_otg_hcd->flags.b.port_over_current_change = 1;
 524                 hprt0_modify.b.prtovrcurrchng = 1;
 525                 retval |= 1;
 526         }
 527
 528         /* Clear Port Interrupts */
 529         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
 530
 531         return retval;
 532 }
 533
 534 /** This interrupt indicates that one or more host channels has a pending
 535  * interrupt. There are multiple conditions that can cause each host channel
 536  * interrupt. This function determines which conditions have occurred for each
 537  * host channel interrupt and handles them appropriately. */
 538 int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 539 {
 540         int i;
 541         int retval = 0;
 542         haint_data_t haint;
 543
 544         /* Clear appropriate bits in HCINTn to clear the interrupt bit in
 545          * GINTSTS */
 546
 547         haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
 548
 549         for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
 550                 if (haint.b2.chint & (1 << i)) {
 551                         retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
 552                 }
 553         }
 554
 555         return retval;
 556 }
 557
 558 /**
 559  * Gets the actual length of a transfer after the transfer halts. _halt_status
 560  * holds the reason for the halt.
 561  *
 562  * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
 563  * *short_read is set to 1 upon return if less than the requested
 564  * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
 565  * return. short_read may also be NULL on entry, in which case it remains
 566  * unchanged.
 567  */
 568 static uint32_t get_actual_xfer_length(dwc_hc_t *hc,
 569                                        dwc_otg_hc_regs_t *hc_regs,
 570                                        dwc_otg_qtd_t *qtd,
 571                                        dwc_otg_halt_status_e halt_status,
 572                                        int *short_read)
 573 {
 574         hctsiz_data_t hctsiz;
 575         uint32_t length;
 576
 577         if (short_read != NULL) {
 578                 *short_read = 0;
 579         }
 580         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 581
 582         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
 583                 if (hc->ep_is_in) {
 584                         length = hc->xfer_len - hctsiz.b.xfersize;
 585                         if (short_read != NULL) {
 586                                 *short_read = (hctsiz.b.xfersize != 0);
 587                         }
 588                 } else if (hc->qh->do_split) {
 589                         length = qtd->ssplit_out_xfer_count;
 590                 } else {
 591                         length = hc->xfer_len;
 592                 }
 593         } else {
 594                 /*
 595                  * Must use the hctsiz.pktcnt field to determine how much data
 596                  * has been transferred. This field reflects the number of
 597                  * packets that have been transferred via the USB. This is
 598                  * always an integral number of packets if the transfer was
 599                  * halted before its normal completion. (Can't use the
 600                  * hctsiz.xfersize field because that reflects the number of
 601                  * bytes transferred via the AHB, not the USB).
 602                  */
 603                 length =
 604                     (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
 605         }
 606
 607         return length;
 608 }
 609
 610 /**
 611  * Updates the state of the URB after a Transfer Complete interrupt on the
 612  * host channel. Updates the actual_length field of the URB based on the
 613  * number of bytes transferred via the host channel. Sets the URB status
 614  * if the data transfer is finished.
 615  *
 616  * @return 1 if the data transfer specified by the URB is completely finished,
 617  * 0 otherwise.
 618  */
 619 static int update_urb_state_xfer_comp(dwc_hc_t *hc,
 620                                       dwc_otg_hc_regs_t *hc_regs,
 621                                       dwc_otg_hcd_urb_t *urb,
 622                                       dwc_otg_qtd_t *qtd)
 623 {
 624         int xfer_done = 0;
 625         int short_read = 0;
 626
 627         int xfer_length;
 628
 629         xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
 630                                              DWC_OTG_HC_XFER_COMPLETE,
 631                                              &short_read);
 632
 633         /* non DWORD-aligned buffer case handling. */
 634         if (hc->align_buff && xfer_length && hc->ep_is_in) {
 635                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
 636                            xfer_length);
 637         }
 638
 639         urb->actual_length += xfer_length;
 640
 641         if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
 642             (urb->flags & URB_SEND_ZERO_PACKET)
 643             && (urb->actual_length == urb->length)
 644             && !(urb->length % hc->max_packet)) {
 645                 xfer_done = 0;
 646         } else if (short_read || urb->actual_length >= urb->length) {
 647                 xfer_done = 1;
 648                 urb->status = 0;
 649         }
 650 #ifdef DEBUG
 651         {
 652                 hctsiz_data_t hctsiz;
 653                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 654                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
 655                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
 656                             hc->hc_num);
 657                 DWC_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", hc->xfer_len);
 658                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n",
 659                             hctsiz.b.xfersize);
 660                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
 661                             urb->length);
 662                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
 663                             urb->actual_length);
 664                 DWC_DEBUGPL(DBG_HCDV, "  short_read %d, xfer_done %d\n",
 665                             short_read, xfer_done);
 666         }
 667 #endif
 668
 669         return xfer_done;
 670 }
 671
 672 /*
 673  * Save the starting data toggle for the next transfer. The data toggle is
 674  * saved in the QH for non-control transfers and it's saved in the QTD for
 675  * control transfers.
 676  */
 677 void dwc_otg_hcd_save_data_toggle(dwc_hc_t *hc,
 678                                   dwc_otg_hc_regs_t *hc_regs,
 679                                   dwc_otg_qtd_t *qtd)
 680 {
 681         hctsiz_data_t hctsiz;
 682         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 683
 684         if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
 685                 dwc_otg_qh_t *qh = hc->qh;
 686                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
 687                         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
 688                 } else {
 689                         qh->data_toggle = DWC_OTG_HC_PID_DATA1;
 690                 }
 691         } else {
 692                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
 693                         qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
 694                 } else {
 695                         qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
 696                 }
 697         }
 698 }
 699
 700 /**
 701  * Updates the state of an Isochronous URB when the transfer is stopped for
 702  * any reason. The fields of the current entry in the frame descriptor array
 703  * are set based on the transfer state and the input _halt_status. Completes
 704  * the Isochronous URB if all the URB frames have been completed.
 705  *
 706  * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
 707  * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
 708  */
 709 static dwc_otg_halt_status_e
 710 update_isoc_urb_state(dwc_otg_hcd_t *hcd,
 711                       dwc_hc_t *hc,
 712                       dwc_otg_hc_regs_t *hc_regs,
 713                       dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
 714 {
 715         dwc_otg_hcd_urb_t *urb = qtd->urb;
 716         dwc_otg_halt_status_e ret_val = halt_status;
 717         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
 718
 719         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 720         switch (halt_status) {
 721         case DWC_OTG_HC_XFER_COMPLETE:
 722                 frame_desc->status = 0;
 723                 frame_desc->actual_length =
 724                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
 725
 726                 /* non DWORD-aligned buffer case handling. */
 727                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
 728                         dwc_memcpy(urb->buf + frame_desc->offset +
 729                                    qtd->isoc_split_offset, hc->qh->dw_align_buf,
 730                                    frame_desc->actual_length);
 731                 }
 732
 733                 break;
 734         case DWC_OTG_HC_XFER_FRAME_OVERRUN:
 735                 urb->error_count++;
 736                 if (hc->ep_is_in) {
 737                         frame_desc->status = -DWC_E_NO_STREAM_RES;
 738                 } else {
 739                         frame_desc->status = -DWC_E_COMMUNICATION;
 740                 }
 741                 frame_desc->actual_length = 0;
 742                 break;
 743         case DWC_OTG_HC_XFER_BABBLE_ERR:
 744                 urb->error_count++;
 745                 frame_desc->status = -DWC_E_OVERFLOW;
 746                 /* Don't need to update actual_length in this case. */
 747                 break;
 748         case DWC_OTG_HC_XFER_XACT_ERR:
 749                 urb->error_count++;
 750                 frame_desc->status = -DWC_E_PROTOCOL;
 751                 frame_desc->actual_length =
 752                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
 753
 754                 /* non DWORD-aligned buffer case handling. */
 755                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
 756                         dwc_memcpy(urb->buf + frame_desc->offset +
 757                                    qtd->isoc_split_offset, hc->qh->dw_align_buf,
 758                                    frame_desc->actual_length);
 759                 }
 760                 /* Skip whole frame */
 761                 if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
 762                     hc->ep_is_in && hcd->core_if->dma_enable) {
 763                         qtd->complete_split = 0;
 764                         qtd->isoc_split_offset = 0;
 765                 }
 766
 767                 break;
 768         default:
 769                 DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
 770                 break;
 771         }
 772         if (++qtd->isoc_frame_index == urb->packet_count) {
 773                 /*
 774                  * urb->status is not used for isoc transfers.
 775                  * The individual frame_desc statuses are used instead.
 776                  */
 777                 hcd->fops->complete(hcd, urb->priv, urb, 0);
 778                 ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
 779         } else {
 780                 ret_val = DWC_OTG_HC_XFER_COMPLETE;
 781         }
 782         return ret_val;
 783 }
 784
 785 /**
 786  * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 787  * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 788  * still linked to the QH, the QH is added to the end of the inactive
 789  * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 790  * schedule if no more QTDs are linked to the QH.
 791  */
 792 static void deactivate_qh(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int free_qtd)
 793 {
 794         int continue_split = 0;
 795         dwc_otg_qtd_t *qtd;
 796
 797         DWC_DEBUGPL(DBG_HCDV, "  %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
 798
 799         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
 800
 801         if (qtd->complete_split) {
 802                 continue_split = 1;
 803         } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
 804                    qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
 805                 continue_split = 1;
 806         }
 807
 808         if (free_qtd) {
 809                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
 810                 continue_split = 0;
 811         }
 812
 813         qh->channel = NULL;
 814         dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
 815 }
 816
 817 /**
 818  * Releases a host channel for use by other transfers. Attempts to select and
 819  * queue more transactions since at least one host channel is available.
 820  *
 821  * @param hcd The HCD state structure.
 822  * @param hc The host channel to release.
 823  * @param qtd The QTD associated with the host channel. This QTD may be freed
 824  * if the transfer is complete or an error has occurred.
 825  * @param halt_status Reason the channel is being released. This status
 826  * determines the actions taken by this function.
 827  */
 828 static void release_channel(dwc_otg_hcd_t *hcd,
 829                             dwc_hc_t *hc,
 830                             dwc_otg_qtd_t *qtd,
 831                             dwc_otg_halt_status_e halt_status)
 832 {
 833         dwc_otg_transaction_type_e tr_type;
 834         int free_qtd;
 835         int continue_trans = 1;
 836
 837         DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d\n",
 838                     __func__, hc->hc_num, halt_status);
 839
 840         if (halt_status != DWC_OTG_HC_XFER_URB_DEQUEUE) {
 841                 if (((uint32_t) qtd & 0xf0000000) == 0) {
 842                         DWC_PRINTF("%s error: qtd %p, status %d 0!!!\n",
 843                                    __func__, qtd, halt_status);
 844                         goto cleanup;
 845                 }
 846
 847                 if (((uint32_t) qtd & 0x80000000) == 0) {
 848                         DWC_PRINTF("%s error: qtd %p, status %d 1!!!\n",
 849                                    __func__, qtd, halt_status);
 850                         goto cleanup;
 851                 }
 852
 853                 if (((uint32_t) qtd->urb & 0xf0000000) == 0) {
 854                         DWC_PRINTF("%s qtd %p urb %p, status %d\n", __func__,
 855                                    qtd, qtd->urb, halt_status);
 856                         goto cleanup;
 857                 }
 858         }
 859
 860         switch (halt_status) {
 861         case DWC_OTG_HC_XFER_URB_COMPLETE:
 862                 free_qtd = 1;
 863                 break;
 864         case DWC_OTG_HC_XFER_AHB_ERR:
 865         case DWC_OTG_HC_XFER_STALL:
 866         case DWC_OTG_HC_XFER_BABBLE_ERR:
 867                 free_qtd = 1;
 868                 break;
 869         case DWC_OTG_HC_XFER_XACT_ERR:
 870                 if (qtd->error_count >= 3) {
 871                         DWC_DEBUGPL(DBG_HCDV,
 872                                     "  Complete URB with transaction error\n");
 873                         free_qtd = 1;
 874                         qtd->urb->status = -DWC_E_PROTOCOL;
 875                         hcd->fops->complete(hcd, qtd->urb->priv,
 876                                             qtd->urb, -DWC_E_PROTOCOL);
 877                 } else {
 878                         free_qtd = 0;
 879                 }
 880                 break;
 881         case DWC_OTG_HC_XFER_URB_DEQUEUE:
 882                 /*
 883                  * The QTD has already been removed and the QH has been
 884                  * deactivated. Don't want to do anything except release the
 885                  * host channel and try to queue more transfers.
 886                  */
 887                 continue_trans = 0;
 888                 goto cleanup;
 889         case DWC_OTG_HC_XFER_NO_HALT_STATUS:
 890                 free_qtd = 0;
 891                 break;
 892         case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
 893                 DWC_DEBUGPL(DBG_HCDV, "  Complete URB with I/O error\n");
 894                 free_qtd = 1;
 895                 qtd->urb->status = -DWC_E_IO;
 896                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, -DWC_E_IO);
 897                 break;
 898         default:
 899                 free_qtd = 0;
 900                 break;
 901         }
 902
 903         if (hc->csplit_nak) {
 904                 continue_trans = 0;
 905                 hc->csplit_nak = 0;
 906         }
 907         deactivate_qh(hcd, hc->qh, free_qtd);
 908
 909 cleanup:
 910         /*
 911          * Release the host channel for use by other transfers. The cleanup
 912          * function clears the channel interrupt enables and conditions, so
 913          * there's no need to clear the Channel Halted interrupt separately.
 914          */
 915         dwc_otg_hc_cleanup(hcd->core_if, hc);
 916         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
 917
 918         switch (hc->ep_type) {
 919         case DWC_OTG_EP_TYPE_CONTROL:
 920         case DWC_OTG_EP_TYPE_BULK:
 921                 hcd->non_periodic_channels--;
 922                 break;
 923
 924         default:
 925                 /*
 926                  * Don't release reservations for periodic channels here.
 927                  * That's done when a periodic transfer is descheduled (i.e.
 928                  * when the QH is removed from the periodic schedule).
 929                  */
 930                 break;
 931         }
 932
 933         /* Try to queue more transfers now that there's a free channel. */
 934         if (continue_trans) {
 935                 tr_type = dwc_otg_hcd_select_transactions(hcd);
 936                 if (tr_type != DWC_OTG_TRANSACTION_NONE)
 937                         dwc_otg_hcd_queue_transactions(hcd, tr_type);
 938         }
 939 }
 940
 941 /**
 942  * Halts a host channel. If the channel cannot be halted immediately because
 943  * the request queue is full, this function ensures that the FIFO empty
 944  * interrupt for the appropriate queue is enabled so that the halt request can
 945  * be queued when there is space in the request queue.
 946  *
 947  * This function may also be called in DMA mode. In that case, the channel is
 948  * simply released since the core always halts the channel automatically in
 949  * DMA mode.
 950  */
 951 static void halt_channel(dwc_otg_hcd_t *hcd,
 952                          dwc_hc_t *hc,
 953                          dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
 954 {
 955         if (hcd->core_if->dma_enable) {
 956                 release_channel(hcd, hc, qtd, halt_status);
 957                 return;
 958         }
 959
 960         /* Slave mode processing... */
 961         dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
 962
 963         if (hc->halt_on_queue) {
 964                 gintmsk_data_t gintmsk = {.d32 = 0 };
 965                 dwc_otg_core_global_regs_t *global_regs;
 966                 global_regs = hcd->core_if->core_global_regs;
 967
 968                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
 969                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
 970                         /*
 971                          * Make sure the Non-periodic Tx FIFO empty interrupt
 972                          * is enabled so that the non-periodic schedule will
 973                          * be processed.
 974                          */
 975                         gintmsk.b.nptxfempty = 1;
 976                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
 977                 } else {
 978                         /*
 979                          * Move the QH from the periodic queued schedule to
 980                          * the periodic assigned schedule. This allows the
 981                          * halt to be queued when the periodic schedule is
 982                          * processed.
 983                          */
 984                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
 985                                            &hc->qh->qh_list_entry);
 986
 987                         /*
 988                          * Make sure the Periodic Tx FIFO Empty interrupt is
 989                          * enabled so that the periodic schedule will be
 990                          * processed.
 991                          */
 992                         gintmsk.b.ptxfempty = 1;
 993                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
 994                 }
 995         }
 996 }
 997
 998 /**
 999  * Performs common cleanup for non-periodic transfers after a Transfer
1000  * Complete interrupt. This function should be called after any endpoint type
1001  * specific handling is finished to release the host channel.
1002  */
1003 static void complete_non_periodic_xfer(dwc_otg_hcd_t *hcd,
1004                                        dwc_hc_t *hc,
1005                                        dwc_otg_hc_regs_t *hc_regs,
1006                                        dwc_otg_qtd_t *qtd,
1007                                        dwc_otg_halt_status_e halt_status)
1008 {
1009         hcint_data_t hcint;
1010
1011         qtd->error_count = 0;
1012
1013         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1014         if (hcint.b.nyet) {
1015                 /*
1016                  * Got a NYET on the last transaction of the transfer. This
1017                  * means that the endpoint should be in the PING state at the
1018                  * beginning of the next transfer.
1019                  */
1020                 hc->qh->ping_state = 1;
1021                 clear_hc_int(hc_regs, nyet);
1022         }
1023
1024         /*
1025          * Always halt and release the host channel to make it available for
1026          * more transfers. There may still be more phases for a control
1027          * transfer or more data packets for a bulk transfer at this point,
1028          * but the host channel is still halted. A channel will be reassigned
1029          * to the transfer when the non-periodic schedule is processed after
1030          * the channel is released. This allows transactions to be queued
1031          * properly via dwc_otg_hcd_queue_transactions, which also enables the
1032          * Tx FIFO Empty interrupt if necessary.
1033          */
1034         if (hc->ep_is_in) {
1035                 /*
1036                  * IN transfers in Slave mode require an explicit disable to
1037                  * halt the channel. (In DMA mode, this call simply releases
1038                  * the channel.)
1039                  */
1040                 halt_channel(hcd, hc, qtd, halt_status);
1041         } else {
1042                 /*
1043                  * The channel is automatically disabled by the core for OUT
1044                  * transfers in Slave mode.
1045                  */
1046                 release_channel(hcd, hc, qtd, halt_status);
1047         }
1048 }
1049
1050 /**
1051  * Performs common cleanup for periodic transfers after a Transfer Complete
1052  * interrupt. This function should be called after any endpoint type specific
1053  * handling is finished to release the host channel.
1054  */
1055 static void complete_periodic_xfer(dwc_otg_hcd_t *hcd,
1056                                    dwc_hc_t *hc,
1057                                    dwc_otg_hc_regs_t *hc_regs,
1058                                    dwc_otg_qtd_t *qtd,
1059                                    dwc_otg_halt_status_e halt_status)
1060 {
1061         hctsiz_data_t hctsiz;
1062         qtd->error_count = 0;
1063
1064         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1065         if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
1066                 /* Core halts channel in these cases. */
1067                 release_channel(hcd, hc, qtd, halt_status);
1068         } else {
1069                 /* Flush any outstanding requests from the Tx queue. */
1070                 halt_channel(hcd, hc, qtd, halt_status);
1071         }
1072 }
1073
1074 static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t *hcd,
1075                                              dwc_hc_t *hc,
1076                                              dwc_otg_hc_regs_t *hc_regs,
1077                                              dwc_otg_qtd_t *qtd)
1078 {
1079         uint32_t len;
1080         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1081         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
1082
1083         len = get_actual_xfer_length(hc, hc_regs, qtd,
1084                                      DWC_OTG_HC_XFER_COMPLETE, NULL);
1085
1086         if (!len) {
1087                 qtd->complete_split = 0;
1088                 qtd->isoc_split_offset = 0;
1089                 return 0;
1090         }
1091         frame_desc->actual_length += len;
1092
1093         if (hc->align_buff && len)
1094                 dwc_memcpy(qtd->urb->buf + frame_desc->offset +
1095                            qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
1096         qtd->isoc_split_offset += len;
1097
1098         if (frame_desc->length == frame_desc->actual_length) {
1099                 frame_desc->status = 0;
1100                 qtd->isoc_frame_index++;
1101                 qtd->complete_split = 0;
1102                 qtd->isoc_split_offset = 0;
1103         }
1104
1105         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
1106                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
1107                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
1108         } else {
1109                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
1110         }
1111
1112         return 1;               /* Indicates that channel released */
1113 }
1114
1115 /**
1116  * Handles a host channel Transfer Complete interrupt. This handler may be
1117  * called in either DMA mode or Slave mode.
1118  */
1119 static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *hcd,
1120                                        dwc_hc_t *hc,
1121                                        dwc_otg_hc_regs_t *hc_regs,
1122                                        dwc_otg_qtd_t *qtd)
1123 {
1124         int urb_xfer_done;
1125         dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
1126         dwc_otg_hcd_urb_t *urb;
1127         int pipe_type;
1128
1129         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1130                     "Transfer Complete--\n", hc->hc_num);
1131
1132         if (((uint32_t) qtd & 0xf0000000) == 0) {
1133                 DWC_PRINTF("%s qtd %p\n", __func__, qtd);
1134                 release_channel(hcd, hc, qtd, hc->halt_status);
1135                 return 1;
1136         }
1137
1138         urb = qtd->urb;
1139         if (((uint32_t) urb & 0xf0000000) == 0) {
1140                 DWC_PRINTF("%s qtd %p, urb %p\n", __func__, qtd, urb);
1141                 release_channel(hcd, hc, qtd, hc->halt_status);
1142                 return 1;
1143         }
1144
1145         pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
1146
1147         if (hcd->core_if->dma_desc_enable) {
1148                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
1149                 if (pipe_type == UE_ISOCHRONOUS) {
1150                         /* Do not disable the interrupt, just clear it */
1151                         clear_hc_int(hc_regs, xfercomp);
1152                         return 1;
1153                 }
1154                 goto handle_xfercomp_done;
1155         }
1156
1157         /*
1158          * Handle xfer complete on CSPLIT.
1159          */
1160
1161         if (hc->qh->do_split) {
1162                 if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
1163                     && hcd->core_if->dma_enable) {
1164                         if (qtd->complete_split
1165                             && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
1166                                                              qtd))
1167                                 goto handle_xfercomp_done;
1168                 } else {
1169                         qtd->complete_split = 0;
1170                 }
1171         }
1172
1173         /* Update the QTD and URB states. */
1174         switch (pipe_type) {
1175         case UE_CONTROL:
1176                 switch (qtd->control_phase) {
1177                 case DWC_OTG_CONTROL_SETUP:
1178                         if (urb->length > 0) {
1179                                 qtd->control_phase = DWC_OTG_CONTROL_DATA;
1180                         } else {
1181                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
1182                         }
1183                         DWC_DEBUGPL(DBG_HCDV,
1184                                     "  Control setup transaction done\n");
1185                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1186                         break;
1187                 case DWC_OTG_CONTROL_DATA:{
1188                                 urb_xfer_done =
1189                                     update_urb_state_xfer_comp(hc, hc_regs, urb,
1190                                                                qtd);
1191                                 if (urb_xfer_done) {
1192                                         qtd->control_phase =
1193                                             DWC_OTG_CONTROL_STATUS;
1194                                         DWC_DEBUGPL(DBG_HCDV,
1195                                                     "  Control data transfer done\n");
1196                                 } else {
1197                                         dwc_otg_hcd_save_data_toggle(hc,
1198                                                                      hc_regs,
1199                                                                      qtd);
1200                                 }
1201                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1202                                 break;
1203                         }
1204                 case DWC_OTG_CONTROL_STATUS:
1205                         DWC_DEBUGPL(DBG_HCDV, "  Control transfer complete\n");
1206                         if (urb->status == -DWC_E_IN_PROGRESS) {
1207                                 urb->status = 0;
1208                         }
1209                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1210                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1211                         break;
1212                 }
1213
1214                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1215                 break;
1216         case UE_BULK:
1217                 DWC_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
1218                 urb_xfer_done =
1219                     update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1220                 if (urb_xfer_done) {
1221                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1222                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1223                 } else {
1224                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1225                 }
1226
1227                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1228                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1229                 break;
1230         case UE_INTERRUPT:
1231                 DWC_DEBUGPL(DBG_HCDV, "  Interrupt transfer complete\n");
1232                 urb_xfer_done =
1233                     update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1234
1235                 /*
1236                  * Interrupt URB is done on the first transfer complete
1237                  * interrupt.
1238                  */
1239                 if (urb_xfer_done) {
1240                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1241                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1242                 } else {
1243                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1244                 }
1245
1246                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1247                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1248                 break;
1249         case UE_ISOCHRONOUS:
1250                 DWC_DEBUGPL(DBG_HCDV, "  Isochronous transfer complete\n");
1251                 if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1252                         halt_status =
1253                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1254                                                   DWC_OTG_HC_XFER_COMPLETE);
1255                 }
1256                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1257                 break;
1258         }
1259
1260 handle_xfercomp_done:
1261         disable_hc_int(hc_regs, xfercompl);
1262
1263         return 1;
1264 }
1265
1266 /**
1267  * Handles a host channel STALL interrupt. This handler may be called in
1268  * either DMA mode or Slave mode.
1269  */
1270 static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *hcd,
1271                                     dwc_hc_t *hc,
1272                                     dwc_otg_hc_regs_t *hc_regs,
1273                                     dwc_otg_qtd_t *qtd)
1274 {
1275         dwc_otg_hcd_urb_t *urb = qtd->urb;
1276         int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
1277
1278         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1279                     "STALL Received--\n", hc->hc_num);
1280
1281         if (hcd->core_if->dma_desc_enable) {
1282                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1283                                                DWC_OTG_HC_XFER_STALL);
1284                 goto handle_stall_done;
1285         }
1286
1287         if (pipe_type == UE_CONTROL) {
1288                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
1289         }
1290
1291         if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
1292                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
1293                 /*
1294                  * USB protocol requires resetting the data toggle for bulk
1295                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1296                  * setup command is issued to the endpoint. Anticipate the
1297                  * CLEAR_FEATURE command since a STALL has occurred and reset
1298                  * the data toggle now.
1299                  */
1300                 hc->qh->data_toggle = 0;
1301         }
1302
1303         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
1304
1305 handle_stall_done:
1306         disable_hc_int(hc_regs, stall);
1307
1308         return 1;
1309 }
1310
1311 /*
1312  * Updates the state of the URB when a transfer has been stopped due to an
1313  * abnormal condition before the transfer completes. Modifies the
1314  * actual_length field of the URB to reflect the number of bytes that have
1315  * actually been transferred via the host channel.
1316  */
1317 static void update_urb_state_xfer_intr(dwc_hc_t *hc,
1318                                        dwc_otg_hc_regs_t *hc_regs,
1319                                        dwc_otg_hcd_urb_t *urb,
1320                                        dwc_otg_qtd_t *qtd,
1321                                        dwc_otg_halt_status_e halt_status)
1322 {
1323         uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
1324                                                             halt_status, NULL);
1325         /* non DWORD-aligned buffer case handling. */
1326         if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
1327                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
1328                            bytes_transferred);
1329         }
1330
1331         urb->actual_length += bytes_transferred;
1332
1333 #ifdef DEBUG
1334         {
1335                 hctsiz_data_t hctsiz;
1336                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1337                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
1338                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
1339                             hc->hc_num);
1340                 DWC_DEBUGPL(DBG_HCDV, "  hc->start_pkt_count %d\n",
1341                             hc->start_pkt_count);
1342                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
1343                 DWC_DEBUGPL(DBG_HCDV, "  hc->max_packet %d\n", hc->max_packet);
1344                 DWC_DEBUGPL(DBG_HCDV, "  bytes_transferred %d\n",
1345                             bytes_transferred);
1346                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
1347                             urb->actual_length);
1348                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
1349                             urb->length);
1350         }
1351 #endif
1352 }
1353
1354 /**
1355  * Handles a host channel NAK interrupt. This handler may be called in either
1356  * DMA mode or Slave mode.
1357  */
1358 static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *hcd,
1359                                   dwc_hc_t *hc,
1360                                   dwc_otg_hc_regs_t *hc_regs,
1361                                   dwc_otg_qtd_t *qtd)
1362 {
1363         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1364                     "NAK Received--\n", hc->hc_num);
1365
1366         /*
1367          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1368          * interrupt.  Re-start the SSPLIT transfer.
1369          */
1370         if (hc->do_split) {
1371                 if (hc->complete_split) {
1372                         qtd->error_count = 0;
1373                 }
1374                 hc->csplit_nak = 1;
1375                 qtd->complete_split = 0;
1376                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1377                 goto handle_nak_done;
1378         }
1379
1380         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1381         case UE_CONTROL:
1382         case UE_BULK:
1383                 if (hcd->core_if->dma_enable && hc->ep_is_in) {
1384                         /*
1385                          * NAK interrupts are enabled on bulk/control IN
1386                          * transfers in DMA mode for the sole purpose of
1387                          * resetting the error count after a transaction error
1388                          * occurs. The core will continue transferring data.
1389                          */
1390                         qtd->error_count = 0;
1391                         goto handle_nak_done;
1392                 }
1393
1394                 /*
1395                  * NAK interrupts normally occur during OUT transfers in DMA
1396                  * or Slave mode. For IN transfers, more requests will be
1397                  * queued as request queue space is available.
1398                  */
1399                 qtd->error_count = 0;
1400
1401                 if (!hc->qh->ping_state) {
1402                         update_urb_state_xfer_intr(hc, hc_regs,
1403                                                    qtd->urb, qtd,
1404                                                    DWC_OTG_HC_XFER_NAK);
1405                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1406
1407                         if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
1408                                 hc->qh->ping_state = 1;
1409                 }
1410
1411                 /*
1412                  * Halt the channel so the transfer can be re-started from
1413                  * the appropriate point or the PING protocol will
1414                  * start/continue.
1415                  */
1416                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1417                 break;
1418         case UE_INTERRUPT:
1419                 qtd->error_count = 0;
1420                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1421                 break;
1422         case UE_ISOCHRONOUS:
1423                 /* Should never get called for isochronous transfers. */
1424                 DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
1425                 break;
1426         }
1427
1428 handle_nak_done:
1429         disable_hc_int(hc_regs, nak);
1430
1431         return 1;
1432 }
1433
1434 /**
1435  * Handles a host channel ACK interrupt. This interrupt is enabled when
1436  * performing the PING protocol in Slave mode, when errors occur during
1437  * either Slave mode or DMA mode, and during Start Split transactions.
1438  */
1439 static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *hcd,
1440                                   dwc_hc_t *hc,
1441                                   dwc_otg_hc_regs_t *hc_regs,
1442                                   dwc_otg_qtd_t *qtd)
1443 {
1444         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1445                     "ACK Received--\n", hc->hc_num);
1446
1447         if (hc->do_split) {
1448                 /*
1449                  * Handle ACK on SSPLIT.
1450                  * ACK should not occur in CSPLIT.
1451                  */
1452                 if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
1453                         qtd->ssplit_out_xfer_count = hc->xfer_len;
1454                 }
1455                 if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
1456                         /* Don't need complete for isochronous out transfers. */
1457                         qtd->complete_split = 1;
1458                 }
1459
1460                 /* ISOC OUT */
1461                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1462                         switch (hc->xact_pos) {
1463                         case DWC_HCSPLIT_XACTPOS_ALL:
1464                                 break;
1465                         case DWC_HCSPLIT_XACTPOS_END:
1466                                 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
1467                                 qtd->isoc_split_offset = 0;
1468                                 break;
1469                         case DWC_HCSPLIT_XACTPOS_BEGIN:
1470                         case DWC_HCSPLIT_XACTPOS_MID:
1471                                 /*
1472                                  * For BEGIN or MID, calculate the length for
1473                                  * the next microframe to determine the correct
1474                                  * SSPLIT token, either MID or END.
1475                                  */
1476                                 {
1477                                         struct dwc_otg_hcd_iso_packet_desc
1478                                         *frame_desc;
1479
1480                                         frame_desc =
1481                                             &qtd->urb->iso_descs[qtd->
1482                                                                  isoc_frame_index];
1483                                         qtd->isoc_split_offset += 188;
1484
1485                                         if ((frame_desc->length -
1486                                              qtd->isoc_split_offset) <= 188) {
1487                                                 qtd->isoc_split_pos =
1488                                                     DWC_HCSPLIT_XACTPOS_END;
1489                                         } else {
1490                                                 qtd->isoc_split_pos =
1491                                                     DWC_HCSPLIT_XACTPOS_MID;
1492                                         }
1493
1494                                 }
1495                                 break;
1496                         }
1497                 } else {
1498                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1499                 }
1500         } else {
1501                 qtd->error_count = 0;
1502
1503                 if (hc->qh->ping_state) {
1504                         hc->qh->ping_state = 0;
1505                         /*
1506                          * Halt the channel so the transfer can be re-started
1507                          * from the appropriate point. This only happens in
1508                          * Slave mode. In DMA mode, the ping_state is cleared
1509                          * when the transfer is started because the core
1510                          * automatically executes the PING, then the transfer.
1511                          */
1512                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1513                 }
1514         }
1515
1516         /*
1517          * If the ACK occurred when _not_ in the PING state, let the channel
1518          * continue transferring data after clearing the error count.
1519          */
1520
1521         disable_hc_int(hc_regs, ack);
1522
1523         return 1;
1524 }
1525
1526 /**
1527  * Handles a host channel NYET interrupt. This interrupt should only occur on
1528  * Bulk and Control OUT endpoints and for complete split transactions. If a
1529  * NYET occurs at the same time as a Transfer Complete interrupt, it is
1530  * handled in the xfercomp interrupt handler, not here. This handler may be
1531  * called in either DMA mode or Slave mode.
1532  */
1533 static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *hcd,
1534                                    dwc_hc_t *hc,
1535                                    dwc_otg_hc_regs_t *hc_regs,
1536                                    dwc_otg_qtd_t *qtd)
1537 {
1538         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1539                     "NYET Received--\n", hc->hc_num);
1540
1541         /*
1542          * NYET on CSPLIT
1543          * re-do the CSPLIT immediately on non-periodic
1544          */
1545         if (hc->do_split && hc->complete_split) {
1546                 if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
1547                     && hcd->core_if->dma_enable) {
1548                         qtd->complete_split = 0;
1549                         qtd->isoc_split_offset = 0;
1550                         if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
1551                                 hcd->fops->complete(hcd, qtd->urb->priv,
1552                                                     qtd->urb, 0);
1553                                 release_channel(hcd, hc, qtd,
1554                                                 DWC_OTG_HC_XFER_URB_COMPLETE);
1555                         } else
1556                                 release_channel(hcd, hc, qtd,
1557                                                 DWC_OTG_HC_XFER_NO_HALT_STATUS);
1558                         goto handle_nyet_done;
1559                 }
1560
1561                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1562                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1563                         int frnum = dwc_otg_hcd_get_frame_number(hcd);
1564
1565                         if (dwc_full_frame_num(frnum) !=
1566                             dwc_full_frame_num(hc->qh->sched_frame)) {
1567                                 /*
1568                                  * No longer in the same full speed frame.
1569                                  * Treat this as a transaction error.
1570                                  */
1571 #if 0
1572                                 /** @todo Fix system performance so this can
1573                                  * be treated as an error. Right now complete
1574                                  * splits cannot be scheduled precisely enough
1575                                  * due to other system activity, so this error
1576                                  * occurs regularly in Slave mode.
1577                                  */
1578                                 qtd->error_count++;
1579 #endif
1580                                 qtd->complete_split = 0;
1581                                 halt_channel(hcd, hc, qtd,
1582                                              DWC_OTG_HC_XFER_XACT_ERR);
1583                                 /** @todo add support for isoc release */
1584                                 goto handle_nyet_done;
1585                         }
1586                 }
1587
1588                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1589                 goto handle_nyet_done;
1590         }
1591
1592         hc->qh->ping_state = 1;
1593         qtd->error_count = 0;
1594
1595         update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
1596                                    DWC_OTG_HC_XFER_NYET);
1597         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1598
1599         /*
1600          * Halt the channel and re-start the transfer so the PING
1601          * protocol will start.
1602          */
1603         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1604
1605 handle_nyet_done:
1606         disable_hc_int(hc_regs, nyet);
1607         return 1;
1608 }
1609
1610 /**
1611  * Handles a host channel babble interrupt. This handler may be called in
1612  * either DMA mode or Slave mode.
1613  */
1614 static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *hcd,
1615                                      dwc_hc_t *hc,
1616                                      dwc_otg_hc_regs_t *hc_regs,
1617                                      dwc_otg_qtd_t *qtd)
1618 {
1619         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1620                     "Babble Error--\n", hc->hc_num);
1621
1622         if (hcd->core_if->dma_desc_enable) {
1623                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1624                                                DWC_OTG_HC_XFER_BABBLE_ERR);
1625                 goto handle_babble_done;
1626         }
1627
1628         if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1629                 hcd->fops->complete(hcd, qtd->urb->priv,
1630                                     qtd->urb, -DWC_E_OVERFLOW);
1631                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
1632         } else {
1633                 dwc_otg_halt_status_e halt_status;
1634                 halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1635                                                     DWC_OTG_HC_XFER_BABBLE_ERR);
1636                 halt_channel(hcd, hc, qtd, halt_status);
1637         }
1638
1639 handle_babble_done:
1640         disable_hc_int(hc_regs, bblerr);
1641         return 1;
1642 }
1643
1644 /**
1645  * Handles a host channel AHB error interrupt. This handler is only called in
1646  * DMA mode.
1647  */
1648 static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *hcd,
1649                                      dwc_hc_t *hc,
1650                                      dwc_otg_hc_regs_t *hc_regs,
1651                                      dwc_otg_qtd_t *qtd)
1652 {
1653         hcchar_data_t hcchar;
1654         hcsplt_data_t hcsplt;
1655         hctsiz_data_t hctsiz;
1656         uint32_t hcdma;
1657         char *pipetype, *speed;
1658
1659         dwc_otg_hcd_urb_t *urb = qtd->urb;
1660
1661         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1662                     "AHB Error--\n", hc->hc_num);
1663
1664         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1665         hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
1666         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1667         hcdma = DWC_READ_REG32(&hc_regs->hcdma);
1668
1669         DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
1670         DWC_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1671         DWC_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1672         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
1673         DWC_ERROR("  Device address: %d\n",
1674                   dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
1675         DWC_ERROR("  Endpoint: %d, %s\n",
1676                   dwc_otg_hcd_get_ep_num(&urb->pipe_info),
1677                   (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
1678
1679         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1680         case UE_CONTROL:
1681                 pipetype = "CONTROL";
1682                 break;
1683         case UE_BULK:
1684                 pipetype = "BULK";
1685                 break;
1686         case UE_INTERRUPT:
1687                 pipetype = "INTERRUPT";
1688                 break;
1689         case UE_ISOCHRONOUS:
1690                 pipetype = "ISOCHRONOUS";
1691                 break;
1692         default:
1693                 pipetype = "UNKNOWN";
1694                 break;
1695         }
1696
1697         DWC_ERROR("  Endpoint type: %s\n", pipetype);
1698
1699         switch (hc->speed) {
1700         case DWC_OTG_EP_SPEED_HIGH:
1701                 speed = "HIGH";
1702                 break;
1703         case DWC_OTG_EP_SPEED_FULL:
1704                 speed = "FULL";
1705                 break;
1706         case DWC_OTG_EP_SPEED_LOW:
1707                 speed = "LOW";
1708                 break;
1709         default:
1710                 speed = "UNKNOWN";
1711                 break;
1712         };
1713
1714         DWC_ERROR("  Speed: %s\n", speed);
1715
1716         DWC_ERROR("  Max packet size: %d\n",
1717                   dwc_otg_hcd_get_mps(&urb->pipe_info));
1718         DWC_ERROR("  Data buffer length: %d\n", urb->length);
1719         DWC_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
1720                   urb->buf, (void *)urb->dma);
1721         DWC_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
1722                   urb->setup_packet, (void *)urb->setup_dma);
1723         DWC_ERROR("  Interval: %d\n", urb->interval);
1724
1725         /* Core haltes the channel for Descriptor DMA mode */
1726         if (hcd->core_if->dma_desc_enable) {
1727                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1728                                                DWC_OTG_HC_XFER_AHB_ERR);
1729                 goto handle_ahberr_done;
1730         }
1731
1732         hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
1733
1734         /*
1735          * Force a channel halt. Don't call halt_channel because that won't
1736          * write to the HCCHARn register in DMA mode to force the halt.
1737          */
1738         dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
1739 handle_ahberr_done:
1740         disable_hc_int(hc_regs, ahberr);
1741         return 1;
1742 }
1743
1744 /**
1745  * Handles a host channel transaction error interrupt. This handler may be
1746  * called in either DMA mode or Slave mode.
1747  */
1748 static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *hcd,
1749                                       dwc_hc_t *hc,
1750                                       dwc_otg_hc_regs_t *hc_regs,
1751                                       dwc_otg_qtd_t *qtd)
1752 {
1753         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1754                     "Transaction Error--\n", hc->hc_num);
1755
1756         if (hcd->core_if->dma_desc_enable) {
1757                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1758                                                DWC_OTG_HC_XFER_XACT_ERR);
1759                 goto handle_xacterr_done;
1760         }
1761
1762         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1763         case UE_CONTROL:
1764         case UE_BULK:
1765                 qtd->error_count++;
1766                 if (!hc->qh->ping_state) {
1767
1768                         update_urb_state_xfer_intr(hc, hc_regs,
1769                                                    qtd->urb, qtd,
1770                                                    DWC_OTG_HC_XFER_XACT_ERR);
1771                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1772                         if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
1773                                 hc->qh->ping_state = 1;
1774                         }
1775                 }
1776
1777                 /*
1778                  * Halt the channel so the transfer can be re-started from
1779                  * the appropriate point or the PING protocol will start.
1780                  */
1781                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1782                 break;
1783         case UE_INTERRUPT:
1784                 qtd->error_count++;
1785                 if (hc->do_split && hc->complete_split) {
1786                         qtd->complete_split = 0;
1787                 }
1788                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1789                 break;
1790         case UE_ISOCHRONOUS:
1791                 {
1792                         dwc_otg_halt_status_e halt_status;
1793                         halt_status =
1794                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1795                                                   DWC_OTG_HC_XFER_XACT_ERR);
1796
1797                         halt_channel(hcd, hc, qtd, halt_status);
1798                 }
1799                 break;
1800         }
1801 handle_xacterr_done:
1802         disable_hc_int(hc_regs, xacterr);
1803
1804         return 1;
1805 }
1806
1807 /**
1808  * Handles a host channel frame overrun interrupt. This handler may be called
1809  * in either DMA mode or Slave mode.
1810  */
1811 static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *hcd,
1812                                        dwc_hc_t *hc,
1813                                        dwc_otg_hc_regs_t *hc_regs,
1814                                        dwc_otg_qtd_t *qtd)
1815 {
1816         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1817                     "Frame Overrun--\n", hc->hc_num);
1818
1819         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1820         case UE_CONTROL:
1821         case UE_BULK:
1822                 break;
1823         case UE_INTERRUPT:
1824                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
1825                 break;
1826         case UE_ISOCHRONOUS:
1827                 {
1828                         dwc_otg_halt_status_e halt_status;
1829                         halt_status =
1830                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1831                                                   DWC_OTG_HC_XFER_FRAME_OVERRUN);
1832
1833                         halt_channel(hcd, hc, qtd, halt_status);
1834                 }
1835                 break;
1836         }
1837
1838         disable_hc_int(hc_regs, frmovrun);
1839
1840         return 1;
1841 }
1842
1843 /**
1844  * Handles a host channel data toggle error interrupt. This handler may be
1845  * called in either DMA mode or Slave mode.
1846  */
1847 static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *hcd,
1848                                          dwc_hc_t *hc,
1849                                          dwc_otg_hc_regs_t *hc_regs,
1850                                          dwc_otg_qtd_t *qtd)
1851 {
1852         DWC_ERROR("--Host Channel %d Interrupt: "
1853                   "Data Toggle Error--\n", hc->hc_num);
1854         if (!hcd->flags.b.port_connect_status) {
1855                 /* No longer connected. */
1856                 DWC_ERROR("Not connected\n");
1857                 return 1;
1858         }
1859         if (hc->ep_is_in) {
1860                 qtd->error_count += 3;  /* Complete the error URB immediately */
1861         } else {
1862                 DWC_ERROR("Data Toggle Error on OUT transfer,"
1863                           "channel %d\n", hc->hc_num);
1864         }
1865         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1866         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1867         clear_hc_int(hc_regs, chhltd);
1868
1869         return 1;
1870 }
1871
1872 #ifdef DEBUG
1873 /**
1874  * This function is for debug only. It checks that a valid halt status is set
1875  * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
1876  * taken and a warning is issued.
1877  * @return 1 if halt status is ok, 0 otherwise.
1878  */
1879 static inline int halt_status_ok(dwc_otg_hcd_t *hcd,
1880                                  dwc_hc_t *hc,
1881                                  dwc_otg_hc_regs_t *hc_regs,
1882                                  dwc_otg_qtd_t *qtd)
1883 {
1884         hcchar_data_t hcchar;
1885         hctsiz_data_t hctsiz;
1886         hcint_data_t hcint;
1887         hcintmsk_data_t hcintmsk;
1888         hcsplt_data_t hcsplt;
1889
1890         if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
1891                 /*
1892                  * This code is here only as a check. This condition should
1893                  * never happen. Ignore the halt if it does occur.
1894                  */
1895                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1896                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1897                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1898                 hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
1899                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
1900                 DWC_WARN
1901                     ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
1902                      "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
1903                      "hcint 0x%08x, hcintmsk 0x%08x, "
1904                      "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
1905                      hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
1906                      hcintmsk.d32, hcsplt.d32, qtd->complete_split);
1907
1908                 DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
1909                          __func__, hc->hc_num);
1910                 DWC_WARN("\n");
1911                 clear_hc_int(hc_regs, chhltd);
1912                 return 0;
1913         }
1914
1915         /*
1916          * This code is here only as a check. hcchar.chdis should
1917          * never be set when the halt interrupt occurs. Halt the
1918          * channel again if it does occur.
1919          */
1920         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1921         if (hcchar.b.chdis) {
1922                 DWC_WARN("%s: hcchar.chdis set unexpectedly, "
1923                          "hcchar 0x%08x, trying to halt again\n",
1924                          __func__, hcchar.d32);
1925                 clear_hc_int(hc_regs, chhltd);
1926                 hc->halt_pending = 0;
1927                 halt_channel(hcd, hc, qtd, hc->halt_status);
1928                 return 0;
1929         }
1930
1931         return 1;
1932 }
1933 #endif
1934
1935 /**
1936  * Handles a host Channel Halted interrupt in DMA mode. This handler
1937  * determines the reason the channel halted and proceeds accordingly.
1938  */
1939 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd,
1940                                       dwc_hc_t *hc,
1941                                       dwc_otg_hc_regs_t *hc_regs,
1942                                       dwc_otg_qtd_t *qtd)
1943 {
1944         hcint_data_t hcint;
1945         hcintmsk_data_t hcintmsk;
1946         int out_nak_enh = 0;
1947
1948         /* For core with OUT NAK enhancement, the flow for high-
1949          * speed CONTROL/BULK OUT is handled a little differently.
1950          */
1951         if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
1952                 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
1953                     (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
1954                      hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
1955                         out_nak_enh = 1;
1956                 }
1957         }
1958
1959         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
1960             (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
1961              && !hcd->core_if->dma_desc_enable)) {
1962                 /*
1963                  * Just release the channel. A dequeue can happen on a
1964                  * transfer timeout. In the case of an AHB Error, the channel
1965                  * was forced to halt because there's no way to gracefully
1966                  * recover.
1967                  */
1968                 if (hcd->core_if->dma_desc_enable)
1969                         dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1970                                                        hc->halt_status);
1971                 else
1972                         release_channel(hcd, hc, qtd, hc->halt_status);
1973                 return;
1974         }
1975
1976         /* Read the HCINTn register to determine the cause for the halt. */
1977         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1978         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
1979
1980         if (hcint.b.xfercomp) {
1981                 /** @todo This is here because of a possible hardware bug.  Spec
1982                  * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1983                  * interrupt w/ACK bit set should occur, but I only see the
1984                  * XFERCOMP bit, even with it masked out.  This is a workaround
1985                  * for that behavior.  Should fix this when hardware is fixed.
1986                  */
1987                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1988                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1989                 }
1990                 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
1991         } else if (hcint.b.stall) {
1992                 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
1993         } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
1994                 if (out_nak_enh) {
1995                         if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
1996                                 DWC_DEBUG("XactErr with NYET/NAK/ACK\n");
1997                                 qtd->error_count = 0;
1998                         } else {
1999                                 DWC_DEBUG("XactErr without NYET/NAK/ACK\n");
2000                         }
2001                 }
2002
2003                 /*
2004                  * Must handle xacterr before nak or ack. Could get a xacterr
2005                  * at the same time as either of these on a BULK/CONTROL OUT
2006                  * that started with a PING. The xacterr takes precedence.
2007                  */
2008                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
2009         } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
2010                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
2011         } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
2012                 handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
2013         } else if (hcint.b.bblerr) {
2014                 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
2015         } else if (hcint.b.frmovrun) {
2016                 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
2017         } else if (hcint.b.datatglerr) {
2018                 handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
2019         } else if (!out_nak_enh) {
2020                 if (hcint.b.nyet) {
2021                         /*
2022                          * Must handle nyet before nak or ack. Could get a nyet at the
2023                          * same time as either of those on a BULK/CONTROL OUT that
2024                          * started with a PING. The nyet takes precedence.
2025                          */
2026                         handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
2027                 } else if (hcint.b.nak && !hcintmsk.b.nak) {
2028                         /*
2029                          * If nak is not masked, it's because a non-split IN transfer
2030                          * is in an error state. In that case, the nak is handled by
2031                          * the nak interrupt handler, not here. Handle nak here for
2032                          * BULK/CONTROL OUT transfers, which halt on a NAK to allow
2033                          * rewinding the buffer pointer.
2034                          */
2035                         handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
2036                 } else if (hcint.b.ack && !hcintmsk.b.ack) {
2037                         /*
2038                          * If ack is not masked, it's because a non-split IN transfer
2039                          * is in an error state. In that case, the ack is handled by
2040                          * the ack interrupt handler, not here. Handle ack here for
2041                          * split transfers. Start splits halt on ACK.
2042                          */
2043                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
2044                 } else {
2045                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2046                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2047                                 /*
2048                                  * A periodic transfer halted with no other channel
2049                                  * interrupts set. Assume it was halted by the core
2050                                  * because it could not be completed in its scheduled
2051                                  * (micro)frame.
2052                                  */
2053 #ifdef DEBUG
2054                                 DWC_PRINTF
2055                                     ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
2056                                      __func__, hc->hc_num);
2057 #endif
2058                                 halt_channel(hcd, hc, qtd,
2059                                              DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
2060                         } else {
2061                                 DWC_ERROR
2062                                     ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
2063                                      "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
2064                                      __func__, hc->hc_num, hcint.d32,
2065                                      DWC_READ_REG32(&hcd->core_if->
2066                                                     core_global_regs->gintsts));
2067                                 clear_hc_int(hc_regs, chhltd);
2068                         }
2069
2070                 }
2071         } else {
2072                 DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
2073                            hcint.d32);
2074                 if (!hcint.b.nyet && !hcint.b.nak && !hcint.b.ack)
2075                         clear_hc_int(hc_regs, chhltd);
2076         }
2077 }
2078
2079 /**
2080  * Handles a host channel Channel Halted interrupt.
2081  *
2082  * In slave mode, this handler is called only when the driver specifically
2083  * requests a halt. This occurs during handling other host channel interrupts
2084  * (e.g. nak, xacterr, stall, nyet, etc.).
2085  *
2086  * In DMA mode, this is the interrupt that occurs when the core has finished
2087  * processing a transfer on a channel. Other host channel interrupts (except
2088  * ahberr) are disabled in DMA mode.
2089  */
2090 static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *hcd,
2091                                      dwc_hc_t *hc,
2092                                      dwc_otg_hc_regs_t *hc_regs,
2093                                      dwc_otg_qtd_t *qtd)
2094 {
2095         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
2096                     "Channel Halted--\n", hc->hc_num);
2097
2098         if (hcd->core_if->dma_enable) {
2099                 handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
2100         } else {
2101 #ifdef DEBUG
2102                 if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
2103                         return 1;
2104                 }
2105 #endif
2106                 release_channel(hcd, hc, qtd, hc->halt_status);
2107         }
2108
2109         return 1;
2110 }
2111
2112 /** Handles interrupt for a specific Host Channel */
2113 int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
2114 {
2115         int retval = 0;
2116         hcint_data_t hcint;
2117         hcintmsk_data_t hcintmsk;
2118         dwc_hc_t *hc;
2119         dwc_otg_hc_regs_t *hc_regs;
2120         dwc_otg_qtd_t *qtd;
2121
2122         DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
2123
2124         hc = dwc_otg_hcd->hc_ptr_array[num];
2125         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
2126         qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
2127
2128         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2129         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
2130         DWC_DEBUGPL(DBG_HCDV,
2131                     "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2132                     hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
2133         hcint.d32 = hcint.d32 & hcintmsk.d32;
2134
2135         if (!dwc_otg_hcd->core_if->dma_enable) {
2136                 if (hcint.b.chhltd && hcint.d32 != 0x2) {
2137                         hcint.b.chhltd = 0;
2138                 }
2139         }
2140
2141         if (hcint.b.chhltd) {
2142                 retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2143         }
2144         if (hcint.b.xfercomp) {
2145                 retval |=
2146                     handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2147                 /*
2148                  * If NYET occurred at same time as Xfer Complete, the NYET is
2149                  * handled by the Xfer Complete interrupt handler. Don't want
2150                  * to call the NYET interrupt handler in this case.
2151                  */
2152                 hcint.b.nyet = 0;
2153         }
2154         if (hcint.b.ahberr) {
2155                 retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2156         }
2157         if (hcint.b.stall) {
2158                 retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2159         }
2160         if (hcint.b.nak) {
2161                 retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2162         }
2163         if (hcint.b.ack) {
2164                 if (!hcint.b.chhltd)
2165                         retval |=
2166                             handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2167         }
2168         if (hcint.b.nyet) {
2169                 retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2170         }
2171         if (hcint.b.xacterr) {
2172                 retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2173         }
2174         if (hcint.b.bblerr) {
2175                 retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2176         }
2177         if (hcint.b.frmovrun) {
2178                 retval |=
2179                     handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2180         }
2181         if (hcint.b.datatglerr) {
2182                 retval |=
2183                     handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2184         }
2185
2186         return retval;
2187 }
2188
2189 #endif /* DWC_DEVICE_ONLY */