drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
   3  * $Revision: #92 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 #include "dwc_otg_hcd.h"
  36 #include "dwc_otg_regs.h"
  37 #include <linux/usb.h>
  38 #include "dwc_otg_driver.h"
  39 #include "usbdev_rk.h"
  40 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
  41 #include <../drivers/usb/core/hcd.h>
  42 #else
  43 #include <linux/usb/hcd.h>
  44 #endif
  45 /** @file
  46  * This file contains the implementation of the HCD Interrupt handlers.
  47  */
  48
  49 /** This function handles interrupts for the HCD. */
  50 int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd)
  51 {
  52         int retval = 0;
  53
  54         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
  55         gintsts_data_t gintsts;
  56 #ifdef DEBUG
  57         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
  58 #endif
  59
  60         if (dwc_otg_check_haps_status(core_if) == -1) {
  61                 DWC_WARN("HAPS is disconnected");
  62                 return retval;
  63         }
  64
  65         /* Exit from ISR if core is hibernated */
  66         if (core_if->hibernation_suspend == 1) {
  67                 return retval;
  68         }
  69         DWC_SPINLOCK(dwc_otg_hcd->lock);
  70         /* Check if HOST Mode */
  71         if (dwc_otg_is_host_mode(core_if)) {
  72                 gintsts.d32 = dwc_otg_read_core_intr(core_if);
  73                 if (!gintsts.d32) {
  74                         DWC_SPINUNLOCK(dwc_otg_hcd->lock);
  75                         return 0;
  76                 }
  77 #ifdef DEBUG
  78                 /* Don't print debug message in the interrupt handler on SOF */
  79 #ifndef DEBUG_SOF
  80                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
  81 #endif
  82                         DWC_DEBUGPL(DBG_HCD, "\n");
  83 #endif
  84
  85 #ifdef DEBUG
  86 #ifndef DEBUG_SOF
  87                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
  88 #endif
  89                         DWC_DEBUGPL(DBG_HCD,
  90                                     "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
  91                                     gintsts.d32);
  92 #endif
  93
  94                 if (gintsts.b.sofintr) {
  95                         retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
  96                 }
  97                 if (gintsts.b.rxstsqlvl) {
  98                         retval |=
  99                             dwc_otg_hcd_handle_rx_status_q_level_intr
 100                             (dwc_otg_hcd);
 101                 }
 102                 if (gintsts.b.nptxfempty) {
 103                         retval |=
 104                             dwc_otg_hcd_handle_np_tx_fifo_empty_intr
 105                             (dwc_otg_hcd);
 106                 }
 107                 if (gintsts.b.i2cintr) {
 108                         /** @todo Implement i2cintr handler. */
 109                 }
 110                 if (gintsts.b.portintr) {
 111                         retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
 112                 }
 113                 if (gintsts.b.hcintr) {
 114                         retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
 115                 }
 116                 if (gintsts.b.ptxfempty) {
 117                         retval |=
 118                             dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
 119                             (dwc_otg_hcd);
 120                 }
 121 #ifdef DEBUG
 122 #ifndef DEBUG_SOF
 123                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
 124 #endif
 125                 {
 126                         DWC_DEBUGPL(DBG_HCD,
 127                                     "DWC OTG HCD Finished Servicing Interrupts\n");
 128                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
 129                                     DWC_READ_REG32(&global_regs->gintsts));
 130                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
 131                                     DWC_READ_REG32(&global_regs->gintmsk));
 132                 }
 133 #endif
 134
 135 #ifdef DEBUG
 136 #ifndef DEBUG_SOF
 137                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
 138 #endif
 139                         DWC_DEBUGPL(DBG_HCD, "\n");
 140 #endif
 141
 142         }
 143         DWC_SPINUNLOCK(dwc_otg_hcd->lock);
 144         return retval;
 145 }
 146
 147 #ifdef DWC_TRACK_MISSED_SOFS
 148 #warning Compiling code to track missed SOFs
 149 #define FRAME_NUM_ARRAY_SIZE 1000
 150 /**
 151  * This function is for debug only.
 152  */
 153 static inline void track_missed_sofs(uint16_t curr_frame_number)
 154 {
 155         static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
 156         static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
 157         static int frame_num_idx;
 158         static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
 159         static int dumped_frame_num_array;
 160
 161         if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
 162                 if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
 163                     curr_frame_number) {
 164                         frame_num_array[frame_num_idx] = curr_frame_number;
 165                         last_frame_num_array[frame_num_idx++] = last_frame_num;
 166                 }
 167         } else if (!dumped_frame_num_array) {
 168                 int i;
 169                 DWC_PRINTF("Frame     Last Frame\n");
 170                 DWC_PRINTF("-----     ----------\n");
 171                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
 172                         DWC_PRINTF("0x%04x    0x%04x\n",
 173                                    frame_num_array[i], last_frame_num_array[i]);
 174                 }
 175                 dumped_frame_num_array = 1;
 176         }
 177         last_frame_num = curr_frame_number;
 178 }
 179 #endif
 180
 181 /**
 182  * Handles the start-of-frame interrupt in host mode. Non-periodic
 183  * transactions may be queued to the DWC_otg controller for the current
 184  * (micro)frame. Periodic transactions may be queued to the controller for the
 185  * next (micro)frame.
 186  */
 187 int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *hcd)
 188 {
 189         hfnum_data_t hfnum;
 190         dwc_list_link_t *qh_entry;
 191         dwc_otg_qh_t *qh;
 192         dwc_otg_transaction_type_e tr_type;
 193         gintsts_data_t gintsts = {.d32 = 0 };
 194
 195         hfnum.d32 =
 196             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
 197
 198 #ifdef DEBUG_SOF
 199         DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
 200 #endif
 201         hcd->frame_number = hfnum.b.frnum;
 202
 203 #ifdef DEBUG
 204         hcd->frrem_accum += hfnum.b.frrem;
 205         hcd->frrem_samples++;
 206 #endif
 207
 208 #ifdef DWC_TRACK_MISSED_SOFS
 209         track_missed_sofs(hcd->frame_number);
 210 #endif
 211         /* Determine whether any periodic QHs should be executed. */
 212         qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
 213         while (qh_entry != &hcd->periodic_sched_inactive) {
 214                 qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
 215                 qh_entry = qh_entry->next;
 216                 if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
 217                         /*
 218                          * Move QH to the ready list to be executed next
 219                          * (micro)frame.
 220                          */
 221                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
 222                                            &qh->qh_list_entry);
 223                 }
 224         }
 225         tr_type = dwc_otg_hcd_select_transactions(hcd);
 226         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 227                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
 228         }
 229
 230         /* Clear interrupt */
 231         gintsts.b.sofintr = 1;
 232         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
 233
 234         return 1;
 235 }
 236
 237 /** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
 238  * least one packet in the Rx FIFO.  The packets are moved from the FIFO to
 239  * memory if the DWC_otg controller is operating in Slave mode. */
 240 int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 241 {
 242         host_grxsts_data_t grxsts;
 243         dwc_hc_t *hc = NULL;
 244
 245         DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
 246
 247         grxsts.d32 =
 248             DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
 249
 250         hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
 251         if (!hc) {
 252                 DWC_ERROR("Unable to get corresponding channel\n");
 253                 return 0;
 254         }
 255
 256         /* Packet Status */
 257         DWC_DEBUGPL(DBG_HCDV, "    Ch num = %d\n", grxsts.b.chnum);
 258         DWC_DEBUGPL(DBG_HCDV, "    Count = %d\n", grxsts.b.bcnt);
 259         DWC_DEBUGPL(DBG_HCDV, "    DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
 260                     hc->data_pid_start);
 261         DWC_DEBUGPL(DBG_HCDV, "    PStatus = %d\n", grxsts.b.pktsts);
 262
 263         switch (grxsts.b.pktsts) {
 264         case DWC_GRXSTS_PKTSTS_IN:
 265                 /* Read the data into the host buffer. */
 266                 if (grxsts.b.bcnt > 0) {
 267                         dwc_otg_read_packet(dwc_otg_hcd->core_if,
 268                                             hc->xfer_buff, grxsts.b.bcnt);
 269
 270                         /* Update the HC fields for the next packet received. */
 271                         hc->xfer_count += grxsts.b.bcnt;
 272                         hc->xfer_buff += grxsts.b.bcnt;
 273                 }
 274
 275         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
 276         case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
 277         case DWC_GRXSTS_PKTSTS_CH_HALTED:
 278                 /* Handled in interrupt, just ignore data */
 279                 break;
 280         default:
 281                 DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
 282                           grxsts.b.pktsts);
 283                 break;
 284         }
 285
 286         return 1;
 287 }
 288
 289 /** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 290  * data packets may be written to the FIFO for OUT transfers. More requests
 291  * may be written to the non-periodic request queue for IN transfers. This
 292  * interrupt is enabled only in Slave mode. */
 293 int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 294 {
 295         DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 296         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
 297                                        DWC_OTG_TRANSACTION_NON_PERIODIC);
 298         return 1;
 299 }
 300
 301 /** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 302  * packets may be written to the FIFO for OUT transfers. More requests may be
 303  * written to the periodic request queue for IN transfers. This interrupt is
 304  * enabled only in Slave mode. */
 305 int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 306 {
 307         DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
 308         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
 309                                        DWC_OTG_TRANSACTION_PERIODIC);
 310         return 1;
 311 }
 312
 313 /** There are multiple conditions that can cause a port interrupt. This function
 314  * determines which interrupt conditions have occurred and handles them
 315  * appropriately. */
 316 int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 317 {
 318         int retval = 0;
 319         hprt0_data_t hprt0;
 320         hprt0_data_t hprt0_modify;
 321         struct usb_hcd *hcd = dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
 322         struct usb_bus *bus = hcd_to_bus(hcd);
 323
 324         hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 325         hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 326
 327         /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
 328          * GINTSTS */
 329
 330         hprt0_modify.b.prtena = 0;
 331         hprt0_modify.b.prtconndet = 0;
 332         hprt0_modify.b.prtenchng = 0;
 333         hprt0_modify.b.prtovrcurrchng = 0;
 334
 335         /* Port Connect Detected
 336          * Set flag and clear if detected */
 337         if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
 338                 /* Dont modify port status if we are in hibernation state */
 339                 hprt0_modify.b.prtconndet = 1;
 340                 hprt0_modify.b.prtenchng = 1;
 341                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
 342                                 hprt0_modify.d32);
 343                 hprt0.d32 =
 344                     DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 345                 return retval;
 346         }
 347
 348         if (hprt0.b.prtconndet) {
 349                 /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
 350                 if (dwc_otg_hcd->core_if->adp_enable &&
 351                     dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
 352                         DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
 353                         DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.
 354                                          vbuson_timer);
 355                         dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
 356                         /* TODO - check if this is required, as
 357                          * host initialization was already performed
 358                          * after initial ADP probing
 359                          */
 360                         /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
 361                            dwc_otg_core_init(dwc_otg_hcd->core_if);
 362                            dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
 363                            cil_hcd_start(dwc_otg_hcd->core_if); */
 364                 } else {
 365                         hprt0_data_t hprt0_local;
 366                         /* check if root hub is in suspend state
 367                          * if root hub in suspend, resume it.
 368                          */
 369                         if ((bus->root_hub)
 370                             && (hcd->state == HC_STATE_SUSPENDED)) {
 371                                 DWC_PRINTF
 372                                     ("%s: hcd->state = %d, hcd->flags = %ld\n",
 373                                      __func__, hcd->state, hcd->flags);
 374                                 usb_hcd_resume_root_hub(hcd);
 375                         }
 376                         DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
 377                                     "Port Connect Detected--\n", hprt0.d32);
 378                         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 379                         dwc_otg_hcd->flags.b.port_connect_status = 1;
 380                         hprt0_modify.b.prtconndet = 1;
 381                         /* PET testing */
 382                         if (dwc_otg_hcd->core_if->otg_ver
 383                             && (dwc_otg_hcd->core_if->test_mode == 7)) {
 384                                 hprt0_local.d32 =
 385                                     dwc_otg_read_hprt0(dwc_otg_hcd->core_if);
 386                                 hprt0_local.b.prtrst = 1;
 387                                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->
 388                                                 hprt0, hprt0_local.d32);
 389                                 dwc_mdelay(60);
 390                                 hprt0.d32 =
 391                                     dwc_otg_read_hprt0(dwc_otg_hcd->core_if);
 392                                 hprt0.b.prtrst = 0;
 393                                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->
 394                                                 hprt0, hprt0.d32);
 395                         }
 396
 397                         /* B-Device has connected, Delete the connection timer. */
 398                         DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
 399                 }
 400                 /* The Hub driver asserts a reset when it sees port connect
 401                  * status change flag */
 402                 retval |= 1;
 403         }
 404
 405         /* Port Enable Changed
 406          * Clear if detected - Set internal flag if disabled */
 407         if (hprt0.b.prtenchng) {
 408                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
 409                             "Port Enable Changed--\n", hprt0.d32);
 410                 hprt0_modify.b.prtenchng = 1;
 411                 if (hprt0.b.prtena == 1) {
 412                         hfir_data_t hfir;
 413                         int do_reset = 0;
 414                         dwc_otg_core_params_t *params =
 415                             dwc_otg_hcd->core_if->core_params;
 416                         dwc_otg_core_global_regs_t *global_regs =
 417                             dwc_otg_hcd->core_if->core_global_regs;
 418                         dwc_otg_host_if_t *host_if =
 419                             dwc_otg_hcd->core_if->host_if;
 420
 421                         /* Every time when port enables calculate
 422                          * HFIR.FrInterval
 423                          */
 424                         hfir.d32 =
 425                             DWC_READ_REG32(&host_if->host_global_regs->hfir);
 426                         hfir.b.frint =
 427                             calc_frame_interval(dwc_otg_hcd->core_if);
 428                         DWC_WRITE_REG32(&host_if->host_global_regs->hfir,
 429                                         hfir.d32);
 430
 431                         /* Check if we need to adjust the PHY clock speed for
 432                          * low power and adjust it */
 433                         if (params->host_support_fs_ls_low_power) {
 434                                 gusbcfg_data_t usbcfg;
 435
 436                                 usbcfg.d32 =
 437                                     DWC_READ_REG32(&global_regs->gusbcfg);
 438
 439                                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
 440                                     || hprt0.b.prtspd ==
 441                                     DWC_HPRT0_PRTSPD_FULL_SPEED) {
 442                                         /*
 443                                          * Low power
 444                                          */
 445                                         hcfg_data_t hcfg;
 446                                         if (usbcfg.b.phylpwrclksel == 0) {
 447                                                 /* Set PHY low power clock select for FS/LS devices */
 448                                                 usbcfg.b.phylpwrclksel = 1;
 449                                                 DWC_WRITE_REG32
 450                                                     (&global_regs->gusbcfg,
 451                                                      usbcfg.d32);
 452                                                 do_reset = 1;
 453                                         }
 454
 455                                         hcfg.d32 =
 456                                             DWC_READ_REG32
 457                                             (&host_if->host_global_regs->hcfg);
 458
 459                                         if (hprt0.b.prtspd ==
 460                                             DWC_HPRT0_PRTSPD_LOW_SPEED
 461                                             && params->host_ls_low_power_phy_clk
 462                                             ==
 463                                             DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
 464                                                 /* 6 MHZ */
 465                                                 DWC_DEBUGPL(DBG_CIL,
 466                                                             "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
 467                                                 if (hcfg.b.fslspclksel !=
 468                                                     DWC_HCFG_6_MHZ) {
 469                                                         hcfg.b.fslspclksel =
 470                                                             DWC_HCFG_6_MHZ;
 471                                                         DWC_WRITE_REG32
 472                                                             (&host_if->
 473                                                              host_global_regs->
 474                                                              hcfg, hcfg.d32);
 475                                                         do_reset = 1;
 476                                                 }
 477                                         } else {
 478                                                 /* 48 MHZ */
 479                                                 DWC_DEBUGPL(DBG_CIL,
 480                                                             "FS_PHY programming HCFG to 48 MHz ()\n");
 481                                                 if (hcfg.b.fslspclksel !=
 482                                                     DWC_HCFG_48_MHZ) {
 483                                                         hcfg.b.fslspclksel =
 484                                                             DWC_HCFG_48_MHZ;
 485                                                         DWC_WRITE_REG32
 486                                                             (&host_if->
 487                                                              host_global_regs->
 488                                                              hcfg, hcfg.d32);
 489                                                         do_reset = 1;
 490                                                 }
 491                                         }
 492                                 } else {
 493                                         /*
 494                                          * Not low power
 495                                          */
 496                                         if (usbcfg.b.phylpwrclksel == 1) {
 497                                                 usbcfg.b.phylpwrclksel = 0;
 498                                                 DWC_WRITE_REG32
 499                                                     (&global_regs->gusbcfg,
 500                                                      usbcfg.d32);
 501                                                 do_reset = 1;
 502                                         }
 503                                 }
 504
 505                                 if (do_reset) {
 506                                         DWC_TASK_SCHEDULE(dwc_otg_hcd->
 507                                                           reset_tasklet);
 508                                 }
 509                         }
 510
 511                         if (!do_reset) {
 512                                 /* Port has been enabled set the reset change flag */
 513                                 dwc_otg_hcd->flags.b.port_reset_change = 1;
 514                         }
 515                 } else {
 516                         dwc_otg_hcd->flags.b.port_enable_change = 1;
 517                 }
 518                 retval |= 1;
 519         }
 520
 521         /** Overcurrent Change Interrupt */
 522         if (hprt0.b.prtovrcurrchng) {
 523                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
 524                             "Port Overcurrent Changed--\n", hprt0.d32);
 525                 dwc_otg_hcd->flags.b.port_over_current_change = 1;
 526                 hprt0_modify.b.prtovrcurrchng = 1;
 527                 retval |= 1;
 528         }
 529
 530         /* Clear Port Interrupts */
 531         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
 532
 533         return retval;
 534 }
 535
 536 /** This interrupt indicates that one or more host channels has a pending
 537  * interrupt. There are multiple conditions that can cause each host channel
 538  * interrupt. This function determines which conditions have occurred for each
 539  * host channel interrupt and handles them appropriately. */
 540 int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 541 {
 542         int i;
 543         int retval = 0;
 544         haint_data_t haint;
 545
 546         /* Clear appropriate bits in HCINTn to clear the interrupt bit in
 547          * GINTSTS */
 548
 549         haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
 550
 551         for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
 552                 if (haint.b2.chint & (1 << i)) {
 553                         retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
 554                 }
 555         }
 556
 557         return retval;
 558 }
 559
 560 /**
 561  * Gets the actual length of a transfer after the transfer halts. _halt_status
 562  * holds the reason for the halt.
 563  *
 564  * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
 565  * *short_read is set to 1 upon return if less than the requested
 566  * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
 567  * return. short_read may also be NULL on entry, in which case it remains
 568  * unchanged.
 569  */
 570 static uint32_t get_actual_xfer_length(dwc_hc_t *hc,
 571                                        dwc_otg_hc_regs_t *hc_regs,
 572                                        dwc_otg_qtd_t *qtd,
 573                                        dwc_otg_halt_status_e halt_status,
 574                                        int *short_read)
 575 {
 576         hctsiz_data_t hctsiz;
 577         uint32_t length;
 578
 579         if (short_read != NULL) {
 580                 *short_read = 0;
 581         }
 582         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 583
 584         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
 585                 if (hc->ep_is_in) {
 586                         length = hc->xfer_len - hctsiz.b.xfersize;
 587                         if (short_read != NULL) {
 588                                 *short_read = (hctsiz.b.xfersize != 0);
 589                         }
 590                 } else if (hc->qh->do_split) {
 591                         length = qtd->ssplit_out_xfer_count;
 592                 } else {
 593                         length = hc->xfer_len;
 594                 }
 595         } else {
 596                 /*
 597                  * Must use the hctsiz.pktcnt field to determine how much data
 598                  * has been transferred. This field reflects the number of
 599                  * packets that have been transferred via the USB. This is
 600                  * always an integral number of packets if the transfer was
 601                  * halted before its normal completion. (Can't use the
 602                  * hctsiz.xfersize field because that reflects the number of
 603                  * bytes transferred via the AHB, not the USB).
 604                  */
 605                 length =
 606                     (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
 607         }
 608
 609         return length;
 610 }
 611
 612 /**
 613  * Updates the state of the URB after a Transfer Complete interrupt on the
 614  * host channel. Updates the actual_length field of the URB based on the
 615  * number of bytes transferred via the host channel. Sets the URB status
 616  * if the data transfer is finished.
 617  *
 618  * @return 1 if the data transfer specified by the URB is completely finished,
 619  * 0 otherwise.
 620  */
 621 static int update_urb_state_xfer_comp(dwc_hc_t *hc,
 622                                       dwc_otg_hc_regs_t *hc_regs,
 623                                       dwc_otg_hcd_urb_t *urb,
 624                                       dwc_otg_qtd_t *qtd)
 625 {
 626         int xfer_done = 0;
 627         int short_read = 0;
 628
 629         int xfer_length;
 630
 631         xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
 632                                              DWC_OTG_HC_XFER_COMPLETE,
 633                                              &short_read);
 634
 635         /* non DWORD-aligned buffer case handling. */
 636         if (hc->align_buff && xfer_length && hc->ep_is_in) {
 637                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
 638                            xfer_length);
 639         }
 640
 641         urb->actual_length += xfer_length;
 642
 643         if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
 644             (urb->flags & URB_SEND_ZERO_PACKET)
 645             && (urb->actual_length == urb->length)
 646             && !(urb->length % hc->max_packet)) {
 647                 xfer_done = 0;
 648         } else if (short_read || urb->actual_length >= urb->length) {
 649                 xfer_done = 1;
 650                 urb->status = 0;
 651         }
 652 #ifdef DEBUG
 653         {
 654                 hctsiz_data_t hctsiz;
 655                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 656                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
 657                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
 658                             hc->hc_num);
 659                 DWC_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", hc->xfer_len);
 660                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n",
 661                             hctsiz.b.xfersize);
 662                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
 663                             urb->length);
 664                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
 665                             urb->actual_length);
 666                 DWC_DEBUGPL(DBG_HCDV, "  short_read %d, xfer_done %d\n",
 667                             short_read, xfer_done);
 668         }
 669 #endif
 670
 671         return xfer_done;
 672 }
 673
 674 /*
 675  * Save the starting data toggle for the next transfer. The data toggle is
 676  * saved in the QH for non-control transfers and it's saved in the QTD for
 677  * control transfers.
 678  */
 679 void dwc_otg_hcd_save_data_toggle(dwc_hc_t *hc,
 680                                   dwc_otg_hc_regs_t *hc_regs,
 681                                   dwc_otg_qtd_t *qtd)
 682 {
 683         hctsiz_data_t hctsiz;
 684         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 685
 686         if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
 687                 dwc_otg_qh_t *qh = hc->qh;
 688                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
 689                         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
 690                 } else {
 691                         qh->data_toggle = DWC_OTG_HC_PID_DATA1;
 692                 }
 693         } else {
 694                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
 695                         qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
 696                 } else {
 697                         qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
 698                 }
 699         }
 700 }
 701
 702 /**
 703  * Updates the state of an Isochronous URB when the transfer is stopped for
 704  * any reason. The fields of the current entry in the frame descriptor array
 705  * are set based on the transfer state and the input _halt_status. Completes
 706  * the Isochronous URB if all the URB frames have been completed.
 707  *
 708  * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
 709  * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
 710  */
 711 static dwc_otg_halt_status_e
 712 update_isoc_urb_state(dwc_otg_hcd_t *hcd,
 713                       dwc_hc_t *hc,
 714                       dwc_otg_hc_regs_t *hc_regs,
 715                       dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
 716 {
 717         dwc_otg_hcd_urb_t *urb = qtd->urb;
 718         dwc_otg_halt_status_e ret_val = halt_status;
 719         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
 720
 721         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 722         switch (halt_status) {
 723         case DWC_OTG_HC_XFER_COMPLETE:
 724                 frame_desc->status = 0;
 725                 frame_desc->actual_length =
 726                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
 727
 728                 /* non DWORD-aligned buffer case handling. */
 729                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
 730                         dwc_memcpy(urb->buf + frame_desc->offset +
 731                                    qtd->isoc_split_offset, hc->qh->dw_align_buf,
 732                                    frame_desc->actual_length);
 733                 }
 734
 735                 break;
 736         case DWC_OTG_HC_XFER_FRAME_OVERRUN:
 737                 urb->error_count++;
 738                 if (hc->ep_is_in) {
 739                         frame_desc->status = -DWC_E_NO_STREAM_RES;
 740                 } else {
 741                         frame_desc->status = -DWC_E_COMMUNICATION;
 742                 }
 743                 frame_desc->actual_length = 0;
 744                 break;
 745         case DWC_OTG_HC_XFER_BABBLE_ERR:
 746                 urb->error_count++;
 747                 frame_desc->status = -DWC_E_OVERFLOW;
 748                 /* Don't need to update actual_length in this case. */
 749                 break;
 750         case DWC_OTG_HC_XFER_XACT_ERR:
 751                 urb->error_count++;
 752                 frame_desc->status = -DWC_E_PROTOCOL;
 753                 frame_desc->actual_length =
 754                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
 755
 756                 /* non DWORD-aligned buffer case handling. */
 757                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
 758                         dwc_memcpy(urb->buf + frame_desc->offset +
 759                                    qtd->isoc_split_offset, hc->qh->dw_align_buf,
 760                                    frame_desc->actual_length);
 761                 }
 762                 /* Skip whole frame */
 763                 if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
 764                     hc->ep_is_in && hcd->core_if->dma_enable) {
 765                         qtd->complete_split = 0;
 766                         qtd->isoc_split_offset = 0;
 767                 }
 768
 769                 break;
 770         default:
 771                 DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
 772                 break;
 773         }
 774         if (++qtd->isoc_frame_index == urb->packet_count) {
 775                 /*
 776                  * urb->status is not used for isoc transfers.
 777                  * The individual frame_desc statuses are used instead.
 778                  */
 779                 hcd->fops->complete(hcd, urb->priv, urb, 0);
 780                 ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
 781         } else {
 782                 ret_val = DWC_OTG_HC_XFER_COMPLETE;
 783         }
 784         return ret_val;
 785 }
 786
 787 /**
 788  * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 789  * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 790  * still linked to the QH, the QH is added to the end of the inactive
 791  * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 792  * schedule if no more QTDs are linked to the QH.
 793  */
 794 static void deactivate_qh(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int free_qtd)
 795 {
 796         int continue_split = 0;
 797         dwc_otg_qtd_t *qtd;
 798
 799         DWC_DEBUGPL(DBG_HCDV, "  %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
 800
 801         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
 802
 803         if (qtd->complete_split) {
 804                 continue_split = 1;
 805         } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
 806                    qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
 807                 continue_split = 1;
 808         }
 809
 810         if (free_qtd) {
 811                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
 812                 continue_split = 0;
 813         }
 814
 815         qh->channel = NULL;
 816         dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
 817 }
 818
 819 /**
 820  * Releases a host channel for use by other transfers. Attempts to select and
 821  * queue more transactions since at least one host channel is available.
 822  *
 823  * @param hcd The HCD state structure.
 824  * @param hc The host channel to release.
 825  * @param qtd The QTD associated with the host channel. This QTD may be freed
 826  * if the transfer is complete or an error has occurred.
 827  * @param halt_status Reason the channel is being released. This status
 828  * determines the actions taken by this function.
 829  */
 830 static void release_channel(dwc_otg_hcd_t *hcd,
 831                             dwc_hc_t *hc,
 832                             dwc_otg_qtd_t *qtd,
 833                             dwc_otg_halt_status_e halt_status)
 834 {
 835         dwc_otg_transaction_type_e tr_type;
 836         int free_qtd;
 837         int continue_trans = 1;
 838
 839         DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d\n",
 840                     __func__, hc->hc_num, halt_status);
 841
 842         switch (halt_status) {
 843         case DWC_OTG_HC_XFER_URB_COMPLETE:
 844                 free_qtd = 1;
 845                 break;
 846         case DWC_OTG_HC_XFER_AHB_ERR:
 847         case DWC_OTG_HC_XFER_STALL:
 848         case DWC_OTG_HC_XFER_BABBLE_ERR:
 849                 free_qtd = 1;
 850                 break;
 851         case DWC_OTG_HC_XFER_XACT_ERR:
 852                 if (qtd->error_count >= 3) {
 853                         DWC_DEBUGPL(DBG_HCDV,
 854                                     "  Complete URB with transaction error\n");
 855                         free_qtd = 1;
 856                         qtd->urb->status = -DWC_E_PROTOCOL;
 857                         hcd->fops->complete(hcd, qtd->urb->priv,
 858                                             qtd->urb, -DWC_E_PROTOCOL);
 859                 } else {
 860                         free_qtd = 0;
 861                 }
 862                 break;
 863         case DWC_OTG_HC_XFER_URB_DEQUEUE:
 864                 /*
 865                  * The QTD has already been removed and the QH has been
 866                  * deactivated. Don't want to do anything except release the
 867                  * host channel and try to queue more transfers.
 868                  */
 869                 continue_trans = 0;
 870                 goto cleanup;
 871         case DWC_OTG_HC_XFER_NO_HALT_STATUS:
 872                 free_qtd = 0;
 873                 break;
 874         case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
 875                 DWC_DEBUGPL(DBG_HCDV, "  Complete URB with I/O error\n");
 876                 free_qtd = 1;
 877                 qtd->urb->status = -DWC_E_IO;
 878                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, -DWC_E_IO);
 879                 break;
 880         default:
 881                 free_qtd = 0;
 882                 break;
 883         }
 884
 885         if (hc->csplit_nak) {
 886                 continue_trans = 0;
 887                 hc->csplit_nak = 0;
 888         }
 889         deactivate_qh(hcd, hc->qh, free_qtd);
 890
 891 cleanup:
 892         /*
 893          * Release the host channel for use by other transfers. The cleanup
 894          * function clears the channel interrupt enables and conditions, so
 895          * there's no need to clear the Channel Halted interrupt separately.
 896          */
 897         dwc_otg_hc_cleanup(hcd->core_if, hc);
 898         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
 899
 900         switch (hc->ep_type) {
 901         case DWC_OTG_EP_TYPE_CONTROL:
 902         case DWC_OTG_EP_TYPE_BULK:
 903                 hcd->non_periodic_channels--;
 904                 break;
 905
 906         default:
 907                 /*
 908                  * Don't release reservations for periodic channels here.
 909                  * That's done when a periodic transfer is descheduled (i.e.
 910                  * when the QH is removed from the periodic schedule).
 911                  */
 912                 break;
 913         }
 914
 915         /* Try to queue more transfers now that there's a free channel. */
 916         if (continue_trans) {
 917                 tr_type = dwc_otg_hcd_select_transactions(hcd);
 918                 if (tr_type != DWC_OTG_TRANSACTION_NONE)
 919                         dwc_otg_hcd_queue_transactions(hcd, tr_type);
 920         }
 921 }
 922
 923 /**
 924  * Halts a host channel. If the channel cannot be halted immediately because
 925  * the request queue is full, this function ensures that the FIFO empty
 926  * interrupt for the appropriate queue is enabled so that the halt request can
 927  * be queued when there is space in the request queue.
 928  *
 929  * This function may also be called in DMA mode. In that case, the channel is
 930  * simply released since the core always halts the channel automatically in
 931  * DMA mode.
 932  */
 933 static void halt_channel(dwc_otg_hcd_t *hcd,
 934                          dwc_hc_t *hc,
 935                          dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
 936 {
 937         if (hcd->core_if->dma_enable) {
 938                 release_channel(hcd, hc, qtd, halt_status);
 939                 return;
 940         }
 941
 942         /* Slave mode processing... */
 943         dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
 944
 945         if (hc->halt_on_queue) {
 946                 gintmsk_data_t gintmsk = {.d32 = 0 };
 947                 dwc_otg_core_global_regs_t *global_regs;
 948                 global_regs = hcd->core_if->core_global_regs;
 949
 950                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
 951                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
 952                         /*
 953                          * Make sure the Non-periodic Tx FIFO empty interrupt
 954                          * is enabled so that the non-periodic schedule will
 955                          * be processed.
 956                          */
 957                         gintmsk.b.nptxfempty = 1;
 958                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
 959                 } else {
 960                         /*
 961                          * Move the QH from the periodic queued schedule to
 962                          * the periodic assigned schedule. This allows the
 963                          * halt to be queued when the periodic schedule is
 964                          * processed.
 965                          */
 966                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
 967                                            &hc->qh->qh_list_entry);
 968
 969                         /*
 970                          * Make sure the Periodic Tx FIFO Empty interrupt is
 971                          * enabled so that the periodic schedule will be
 972                          * processed.
 973                          */
 974                         gintmsk.b.ptxfempty = 1;
 975                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
 976                 }
 977         }
 978 }
 979
 980 /**
 981  * Performs common cleanup for non-periodic transfers after a Transfer
 982  * Complete interrupt. This function should be called after any endpoint type
 983  * specific handling is finished to release the host channel.
 984  */
 985 static void complete_non_periodic_xfer(dwc_otg_hcd_t *hcd,
 986                                        dwc_hc_t *hc,
 987                                        dwc_otg_hc_regs_t *hc_regs,
 988                                        dwc_otg_qtd_t *qtd,
 989                                        dwc_otg_halt_status_e halt_status)
 990 {
 991         hcint_data_t hcint;
 992
 993         qtd->error_count = 0;
 994
 995         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
 996         if (hcint.b.nyet) {
 997                 /*
 998                  * Got a NYET on the last transaction of the transfer. This
 999                  * means that the endpoint should be in the PING state at the
1000                  * beginning of the next transfer.
1001                  */
1002                 hc->qh->ping_state = 1;
1003                 clear_hc_int(hc_regs, nyet);
1004         }
1005
1006         /*
1007          * Always halt and release the host channel to make it available for
1008          * more transfers. There may still be more phases for a control
1009          * transfer or more data packets for a bulk transfer at this point,
1010          * but the host channel is still halted. A channel will be reassigned
1011          * to the transfer when the non-periodic schedule is processed after
1012          * the channel is released. This allows transactions to be queued
1013          * properly via dwc_otg_hcd_queue_transactions, which also enables the
1014          * Tx FIFO Empty interrupt if necessary.
1015          */
1016         if (hc->ep_is_in) {
1017                 /*
1018                  * IN transfers in Slave mode require an explicit disable to
1019                  * halt the channel. (In DMA mode, this call simply releases
1020                  * the channel.)
1021                  */
1022                 halt_channel(hcd, hc, qtd, halt_status);
1023         } else {
1024                 /*
1025                  * The channel is automatically disabled by the core for OUT
1026                  * transfers in Slave mode.
1027                  */
1028                 release_channel(hcd, hc, qtd, halt_status);
1029         }
1030 }
1031
1032 /**
1033  * Performs common cleanup for periodic transfers after a Transfer Complete
1034  * interrupt. This function should be called after any endpoint type specific
1035  * handling is finished to release the host channel.
1036  */
1037 static void complete_periodic_xfer(dwc_otg_hcd_t *hcd,
1038                                    dwc_hc_t *hc,
1039                                    dwc_otg_hc_regs_t *hc_regs,
1040                                    dwc_otg_qtd_t *qtd,
1041                                    dwc_otg_halt_status_e halt_status)
1042 {
1043         hctsiz_data_t hctsiz;
1044         qtd->error_count = 0;
1045
1046         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1047         if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
1048                 /* Core halts channel in these cases. */
1049                 release_channel(hcd, hc, qtd, halt_status);
1050         } else {
1051                 /* Flush any outstanding requests from the Tx queue. */
1052                 halt_channel(hcd, hc, qtd, halt_status);
1053         }
1054 }
1055
1056 static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t *hcd,
1057                                              dwc_hc_t *hc,
1058                                              dwc_otg_hc_regs_t *hc_regs,
1059                                              dwc_otg_qtd_t *qtd)
1060 {
1061         uint32_t len;
1062         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1063         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
1064
1065         len = get_actual_xfer_length(hc, hc_regs, qtd,
1066                                      DWC_OTG_HC_XFER_COMPLETE, NULL);
1067
1068         if (!len) {
1069                 qtd->complete_split = 0;
1070                 qtd->isoc_split_offset = 0;
1071                 return 0;
1072         }
1073         frame_desc->actual_length += len;
1074
1075         if (hc->align_buff && len)
1076                 dwc_memcpy(qtd->urb->buf + frame_desc->offset +
1077                            qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
1078         qtd->isoc_split_offset += len;
1079
1080         if (frame_desc->length == frame_desc->actual_length) {
1081                 frame_desc->status = 0;
1082                 qtd->isoc_frame_index++;
1083                 qtd->complete_split = 0;
1084                 qtd->isoc_split_offset = 0;
1085         }
1086
1087         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
1088                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
1089                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
1090         } else {
1091                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
1092         }
1093
1094         return 1;               /* Indicates that channel released */
1095 }
1096
1097 /**
1098  * Handles a host channel Transfer Complete interrupt. This handler may be
1099  * called in either DMA mode or Slave mode.
1100  */
1101 static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *hcd,
1102                                        dwc_hc_t *hc,
1103                                        dwc_otg_hc_regs_t *hc_regs,
1104                                        dwc_otg_qtd_t *qtd)
1105 {
1106         int urb_xfer_done;
1107         dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
1108         dwc_otg_hcd_urb_t *urb;
1109         int pipe_type;
1110
1111         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1112                     "Transfer Complete--\n", hc->hc_num);
1113
1114         if (!qtd) {
1115                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_DEQUEUE);
1116                 goto handle_xfercomp_done;
1117         }
1118
1119         urb = qtd->urb;
1120         if (!urb) {
1121                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_DEQUEUE);
1122                 goto handle_xfercomp_done;
1123         }
1124
1125         pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
1126
1127         if (hcd->core_if->dma_desc_enable) {
1128                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
1129                 if (pipe_type == UE_ISOCHRONOUS) {
1130                         /* Do not disable the interrupt, just clear it */
1131                         clear_hc_int(hc_regs, xfercomp);
1132                         return 1;
1133                 }
1134                 goto handle_xfercomp_done;
1135         }
1136
1137         /*
1138          * Handle xfer complete on CSPLIT.
1139          */
1140
1141         if (hc->qh->do_split) {
1142                 if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
1143                     && hcd->core_if->dma_enable) {
1144                         if (qtd->complete_split
1145                             && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
1146                                                              qtd))
1147                                 goto handle_xfercomp_done;
1148                 } else {
1149                         qtd->complete_split = 0;
1150                 }
1151         }
1152
1153         /* Update the QTD and URB states. */
1154         switch (pipe_type) {
1155         case UE_CONTROL:
1156                 switch (qtd->control_phase) {
1157                 case DWC_OTG_CONTROL_SETUP:
1158                         if (urb->length > 0) {
1159                                 qtd->control_phase = DWC_OTG_CONTROL_DATA;
1160                         } else {
1161                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
1162                         }
1163                         DWC_DEBUGPL(DBG_HCDV,
1164                                     "  Control setup transaction done\n");
1165                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1166                         break;
1167                 case DWC_OTG_CONTROL_DATA:{
1168                                 urb_xfer_done =
1169                                     update_urb_state_xfer_comp(hc, hc_regs, urb,
1170                                                                qtd);
1171                                 if (urb_xfer_done) {
1172                                         qtd->control_phase =
1173                                             DWC_OTG_CONTROL_STATUS;
1174                                         DWC_DEBUGPL(DBG_HCDV,
1175                                                     "  Control data transfer done\n");
1176                                 } else {
1177                                         dwc_otg_hcd_save_data_toggle(hc,
1178                                                                      hc_regs,
1179                                                                      qtd);
1180                                 }
1181                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1182                                 break;
1183                         }
1184                 case DWC_OTG_CONTROL_STATUS:
1185                         DWC_DEBUGPL(DBG_HCDV, "  Control transfer complete\n");
1186                         if (urb->status == -DWC_E_IN_PROGRESS) {
1187                                 urb->status = 0;
1188                         }
1189                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1190                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1191                         break;
1192                 }
1193
1194                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1195                 break;
1196         case UE_BULK:
1197                 DWC_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
1198                 urb_xfer_done =
1199                     update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1200                 if (urb_xfer_done) {
1201                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1202                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1203                 } else {
1204                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1205                 }
1206
1207                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1208                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1209                 break;
1210         case UE_INTERRUPT:
1211                 DWC_DEBUGPL(DBG_HCDV, "  Interrupt transfer complete\n");
1212                 urb_xfer_done =
1213                     update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1214
1215                 /*
1216                  * Interrupt URB is done on the first transfer complete
1217                  * interrupt.
1218                  */
1219                 if (urb_xfer_done) {
1220                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1221                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1222                 } else {
1223                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1224                 }
1225
1226                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1227                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1228                 break;
1229         case UE_ISOCHRONOUS:
1230                 DWC_DEBUGPL(DBG_HCDV, "  Isochronous transfer complete\n");
1231                 if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1232                         halt_status =
1233                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1234                                                   DWC_OTG_HC_XFER_COMPLETE);
1235                 }
1236                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1237                 break;
1238         }
1239
1240 handle_xfercomp_done:
1241         disable_hc_int(hc_regs, xfercompl);
1242
1243         return 1;
1244 }
1245
1246 /**
1247  * Handles a host channel STALL interrupt. This handler may be called in
1248  * either DMA mode or Slave mode.
1249  */
1250 static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *hcd,
1251                                     dwc_hc_t *hc,
1252                                     dwc_otg_hc_regs_t *hc_regs,
1253                                     dwc_otg_qtd_t *qtd)
1254 {
1255         dwc_otg_hcd_urb_t *urb = qtd->urb;
1256         int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
1257
1258         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1259                     "STALL Received--\n", hc->hc_num);
1260
1261         if (hcd->core_if->dma_desc_enable) {
1262                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1263                                                DWC_OTG_HC_XFER_STALL);
1264                 goto handle_stall_done;
1265         }
1266
1267         if (pipe_type == UE_CONTROL) {
1268                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
1269         }
1270
1271         if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
1272                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
1273                 /*
1274                  * USB protocol requires resetting the data toggle for bulk
1275                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1276                  * setup command is issued to the endpoint. Anticipate the
1277                  * CLEAR_FEATURE command since a STALL has occurred and reset
1278                  * the data toggle now.
1279                  */
1280                 hc->qh->data_toggle = 0;
1281         }
1282
1283         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
1284
1285 handle_stall_done:
1286         disable_hc_int(hc_regs, stall);
1287
1288         return 1;
1289 }
1290
1291 /*
1292  * Updates the state of the URB when a transfer has been stopped due to an
1293  * abnormal condition before the transfer completes. Modifies the
1294  * actual_length field of the URB to reflect the number of bytes that have
1295  * actually been transferred via the host channel.
1296  */
1297 static void update_urb_state_xfer_intr(dwc_hc_t *hc,
1298                                        dwc_otg_hc_regs_t *hc_regs,
1299                                        dwc_otg_hcd_urb_t *urb,
1300                                        dwc_otg_qtd_t *qtd,
1301                                        dwc_otg_halt_status_e halt_status)
1302 {
1303         uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
1304                                                             halt_status, NULL);
1305         /* non DWORD-aligned buffer case handling. */
1306         if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
1307                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
1308                            bytes_transferred);
1309         }
1310
1311         urb->actual_length += bytes_transferred;
1312
1313 #ifdef DEBUG
1314         {
1315                 hctsiz_data_t hctsiz;
1316                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1317                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
1318                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
1319                             hc->hc_num);
1320                 DWC_DEBUGPL(DBG_HCDV, "  hc->start_pkt_count %d\n",
1321                             hc->start_pkt_count);
1322                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
1323                 DWC_DEBUGPL(DBG_HCDV, "  hc->max_packet %d\n", hc->max_packet);
1324                 DWC_DEBUGPL(DBG_HCDV, "  bytes_transferred %d\n",
1325                             bytes_transferred);
1326                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
1327                             urb->actual_length);
1328                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
1329                             urb->length);
1330         }
1331 #endif
1332 }
1333
1334 /**
1335  * Handles a host channel NAK interrupt. This handler may be called in either
1336  * DMA mode or Slave mode.
1337  */
1338 static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *hcd,
1339                                   dwc_hc_t *hc,
1340                                   dwc_otg_hc_regs_t *hc_regs,
1341                                   dwc_otg_qtd_t *qtd)
1342 {
1343         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1344                     "NAK Received--\n", hc->hc_num);
1345
1346         /*
1347          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1348          * interrupt.  Re-start the SSPLIT transfer.
1349          */
1350         if (hc->do_split) {
1351                 if (hc->complete_split) {
1352                         qtd->error_count = 0;
1353                 }
1354                 hc->csplit_nak = 1;
1355                 qtd->complete_split = 0;
1356                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1357                 goto handle_nak_done;
1358         }
1359
1360         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1361         case UE_CONTROL:
1362         case UE_BULK:
1363                 if (hcd->core_if->dma_enable && hc->ep_is_in) {
1364                         /*
1365                          * NAK interrupts are enabled on bulk/control IN
1366                          * transfers in DMA mode for the sole purpose of
1367                          * resetting the error count after a transaction error
1368                          * occurs. The core will continue transferring data.
1369                          */
1370                         qtd->error_count = 0;
1371                         goto handle_nak_done;
1372                 }
1373
1374                 /*
1375                  * NAK interrupts normally occur during OUT transfers in DMA
1376                  * or Slave mode. For IN transfers, more requests will be
1377                  * queued as request queue space is available.
1378                  */
1379                 qtd->error_count = 0;
1380
1381                 if (!hc->qh->ping_state) {
1382                         update_urb_state_xfer_intr(hc, hc_regs,
1383                                                    qtd->urb, qtd,
1384                                                    DWC_OTG_HC_XFER_NAK);
1385                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1386
1387                         if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
1388                                 hc->qh->ping_state = 1;
1389                 }
1390
1391                 /*
1392                  * Halt the channel so the transfer can be re-started from
1393                  * the appropriate point or the PING protocol will
1394                  * start/continue.
1395                  */
1396                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1397                 break;
1398         case UE_INTERRUPT:
1399                 qtd->error_count = 0;
1400                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1401                 break;
1402         case UE_ISOCHRONOUS:
1403                 /* Should never get called for isochronous transfers. */
1404                 DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
1405                 break;
1406         }
1407
1408 handle_nak_done:
1409         disable_hc_int(hc_regs, nak);
1410
1411         return 1;
1412 }
1413
1414 /**
1415  * Handles a host channel ACK interrupt. This interrupt is enabled when
1416  * performing the PING protocol in Slave mode, when errors occur during
1417  * either Slave mode or DMA mode, and during Start Split transactions.
1418  */
1419 static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *hcd,
1420                                   dwc_hc_t *hc,
1421                                   dwc_otg_hc_regs_t *hc_regs,
1422                                   dwc_otg_qtd_t *qtd)
1423 {
1424         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1425                     "ACK Received--\n", hc->hc_num);
1426
1427         if (hc->do_split) {
1428                 /*
1429                  * Handle ACK on SSPLIT.
1430                  * ACK should not occur in CSPLIT.
1431                  */
1432                 if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
1433                         qtd->ssplit_out_xfer_count = hc->xfer_len;
1434                 }
1435                 if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
1436                         /* Don't need complete for isochronous out transfers. */
1437                         qtd->complete_split = 1;
1438                 }
1439
1440                 /* ISOC OUT */
1441                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1442                         switch (hc->xact_pos) {
1443                         case DWC_HCSPLIT_XACTPOS_ALL:
1444                                 break;
1445                         case DWC_HCSPLIT_XACTPOS_END:
1446                                 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
1447                                 qtd->isoc_split_offset = 0;
1448                                 break;
1449                         case DWC_HCSPLIT_XACTPOS_BEGIN:
1450                         case DWC_HCSPLIT_XACTPOS_MID:
1451                                 /*
1452                                  * For BEGIN or MID, calculate the length for
1453                                  * the next microframe to determine the correct
1454                                  * SSPLIT token, either MID or END.
1455                                  */
1456                                 {
1457                                         struct dwc_otg_hcd_iso_packet_desc
1458                                         *frame_desc;
1459
1460                                         frame_desc =
1461                                             &qtd->urb->iso_descs[qtd->
1462                                                                  isoc_frame_index];
1463                                         qtd->isoc_split_offset += 188;
1464
1465                                         if ((frame_desc->length -
1466                                              qtd->isoc_split_offset) <= 188) {
1467                                                 qtd->isoc_split_pos =
1468                                                     DWC_HCSPLIT_XACTPOS_END;
1469                                         } else {
1470                                                 qtd->isoc_split_pos =
1471                                                     DWC_HCSPLIT_XACTPOS_MID;
1472                                         }
1473
1474                                 }
1475                                 break;
1476                         }
1477                 } else {
1478                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1479                 }
1480         } else {
1481                 qtd->error_count = 0;
1482
1483                 if (hc->qh->ping_state) {
1484                         hc->qh->ping_state = 0;
1485                         /*
1486                          * Halt the channel so the transfer can be re-started
1487                          * from the appropriate point. This only happens in
1488                          * Slave mode. In DMA mode, the ping_state is cleared
1489                          * when the transfer is started because the core
1490                          * automatically executes the PING, then the transfer.
1491                          */
1492                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1493                 }
1494         }
1495
1496         /*
1497          * If the ACK occurred when _not_ in the PING state, let the channel
1498          * continue transferring data after clearing the error count.
1499          */
1500
1501         disable_hc_int(hc_regs, ack);
1502
1503         return 1;
1504 }
1505
1506 /**
1507  * Handles a host channel NYET interrupt. This interrupt should only occur on
1508  * Bulk and Control OUT endpoints and for complete split transactions. If a
1509  * NYET occurs at the same time as a Transfer Complete interrupt, it is
1510  * handled in the xfercomp interrupt handler, not here. This handler may be
1511  * called in either DMA mode or Slave mode.
1512  */
1513 static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *hcd,
1514                                    dwc_hc_t *hc,
1515                                    dwc_otg_hc_regs_t *hc_regs,
1516                                    dwc_otg_qtd_t *qtd)
1517 {
1518         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1519                     "NYET Received--\n", hc->hc_num);
1520
1521         /*
1522          * NYET on CSPLIT
1523          * re-do the CSPLIT immediately on non-periodic
1524          */
1525         if (hc->do_split && hc->complete_split) {
1526                 if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
1527                     && hcd->core_if->dma_enable) {
1528                         qtd->complete_split = 0;
1529                         qtd->isoc_split_offset = 0;
1530                         if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
1531                                 hcd->fops->complete(hcd, qtd->urb->priv,
1532                                                     qtd->urb, 0);
1533                                 release_channel(hcd, hc, qtd,
1534                                                 DWC_OTG_HC_XFER_URB_COMPLETE);
1535                         } else
1536                                 release_channel(hcd, hc, qtd,
1537                                                 DWC_OTG_HC_XFER_NO_HALT_STATUS);
1538                         goto handle_nyet_done;
1539                 }
1540
1541                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1542                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1543                         int frnum = dwc_otg_hcd_get_frame_number(hcd);
1544
1545                         if (dwc_full_frame_num(frnum) !=
1546                             dwc_full_frame_num(hc->qh->sched_frame)) {
1547                                 /*
1548                                  * No longer in the same full speed frame.
1549                                  * Treat this as a transaction error.
1550                                  */
1551 #if 0
1552                                 /** @todo Fix system performance so this can
1553                                  * be treated as an error. Right now complete
1554                                  * splits cannot be scheduled precisely enough
1555                                  * due to other system activity, so this error
1556                                  * occurs regularly in Slave mode.
1557                                  */
1558                                 qtd->error_count++;
1559 #endif
1560                                 qtd->complete_split = 0;
1561                                 halt_channel(hcd, hc, qtd,
1562                                              DWC_OTG_HC_XFER_XACT_ERR);
1563                                 /** @todo add support for isoc release */
1564                                 goto handle_nyet_done;
1565                         }
1566                 }
1567
1568                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1569                 goto handle_nyet_done;
1570         }
1571
1572         hc->qh->ping_state = 1;
1573         qtd->error_count = 0;
1574
1575         update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
1576                                    DWC_OTG_HC_XFER_NYET);
1577         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1578
1579         /*
1580          * Halt the channel and re-start the transfer so the PING
1581          * protocol will start.
1582          */
1583         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1584
1585 handle_nyet_done:
1586         disable_hc_int(hc_regs, nyet);
1587         return 1;
1588 }
1589
1590 /**
1591  * Handles a host channel babble interrupt. This handler may be called in
1592  * either DMA mode or Slave mode.
1593  */
1594 static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *hcd,
1595                                      dwc_hc_t *hc,
1596                                      dwc_otg_hc_regs_t *hc_regs,
1597                                      dwc_otg_qtd_t *qtd)
1598 {
1599         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1600                     "Babble Error--\n", hc->hc_num);
1601
1602         if (hcd->core_if->dma_desc_enable) {
1603                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1604                                                DWC_OTG_HC_XFER_BABBLE_ERR);
1605                 goto handle_babble_done;
1606         }
1607
1608         if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1609                 hcd->fops->complete(hcd, qtd->urb->priv,
1610                                     qtd->urb, -DWC_E_OVERFLOW);
1611                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
1612         } else {
1613                 dwc_otg_halt_status_e halt_status;
1614                 halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1615                                                     DWC_OTG_HC_XFER_BABBLE_ERR);
1616                 halt_channel(hcd, hc, qtd, halt_status);
1617         }
1618
1619 handle_babble_done:
1620         disable_hc_int(hc_regs, bblerr);
1621         return 1;
1622 }
1623
1624 /**
1625  * Handles a host channel AHB error interrupt. This handler is only called in
1626  * DMA mode.
1627  */
1628 static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *hcd,
1629                                      dwc_hc_t *hc,
1630                                      dwc_otg_hc_regs_t *hc_regs,
1631                                      dwc_otg_qtd_t *qtd)
1632 {
1633         hcchar_data_t hcchar;
1634         hcsplt_data_t hcsplt;
1635         hctsiz_data_t hctsiz;
1636         uint32_t hcdma;
1637         char *pipetype, *speed;
1638
1639         dwc_otg_hcd_urb_t *urb = qtd->urb;
1640
1641         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1642                     "AHB Error--\n", hc->hc_num);
1643
1644         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1645         hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
1646         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1647         hcdma = DWC_READ_REG32(&hc_regs->hcdma);
1648
1649         DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
1650         DWC_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1651         DWC_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1652         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
1653         DWC_ERROR("  Device address: %d\n",
1654                   dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
1655         DWC_ERROR("  Endpoint: %d, %s\n",
1656                   dwc_otg_hcd_get_ep_num(&urb->pipe_info),
1657                   (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
1658
1659         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1660         case UE_CONTROL:
1661                 pipetype = "CONTROL";
1662                 break;
1663         case UE_BULK:
1664                 pipetype = "BULK";
1665                 break;
1666         case UE_INTERRUPT:
1667                 pipetype = "INTERRUPT";
1668                 break;
1669         case UE_ISOCHRONOUS:
1670                 pipetype = "ISOCHRONOUS";
1671                 break;
1672         default:
1673                 pipetype = "UNKNOWN";
1674                 break;
1675         }
1676
1677         DWC_ERROR("  Endpoint type: %s\n", pipetype);
1678
1679         switch (hc->speed) {
1680         case DWC_OTG_EP_SPEED_HIGH:
1681                 speed = "HIGH";
1682                 break;
1683         case DWC_OTG_EP_SPEED_FULL:
1684                 speed = "FULL";
1685                 break;
1686         case DWC_OTG_EP_SPEED_LOW:
1687                 speed = "LOW";
1688                 break;
1689         default:
1690                 speed = "UNKNOWN";
1691                 break;
1692         };
1693
1694         DWC_ERROR("  Speed: %s\n", speed);
1695
1696         DWC_ERROR("  Max packet size: %d\n",
1697                   dwc_otg_hcd_get_mps(&urb->pipe_info));
1698         DWC_ERROR("  Data buffer length: %d\n", urb->length);
1699         DWC_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
1700                   urb->buf, (void *)urb->dma);
1701         DWC_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
1702                   urb->setup_packet, (void *)urb->setup_dma);
1703         DWC_ERROR("  Interval: %d\n", urb->interval);
1704
1705         /* Core haltes the channel for Descriptor DMA mode */
1706         if (hcd->core_if->dma_desc_enable) {
1707                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1708                                                DWC_OTG_HC_XFER_AHB_ERR);
1709                 goto handle_ahberr_done;
1710         }
1711
1712         hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
1713
1714         /*
1715          * Force a channel halt. Don't call halt_channel because that won't
1716          * write to the HCCHARn register in DMA mode to force the halt.
1717          */
1718         dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
1719 handle_ahberr_done:
1720         disable_hc_int(hc_regs, ahberr);
1721         return 1;
1722 }
1723
1724 /**
1725  * Handles a host channel transaction error interrupt. This handler may be
1726  * called in either DMA mode or Slave mode.
1727  */
1728 static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *hcd,
1729                                       dwc_hc_t *hc,
1730                                       dwc_otg_hc_regs_t *hc_regs,
1731                                       dwc_otg_qtd_t *qtd)
1732 {
1733         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1734                     "Transaction Error--\n", hc->hc_num);
1735
1736         if (hcd->core_if->dma_desc_enable) {
1737                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1738                                                DWC_OTG_HC_XFER_XACT_ERR);
1739                 goto handle_xacterr_done;
1740         }
1741
1742         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1743         case UE_CONTROL:
1744         case UE_BULK:
1745                 qtd->error_count++;
1746                 if (!hc->qh->ping_state) {
1747
1748                         update_urb_state_xfer_intr(hc, hc_regs,
1749                                                    qtd->urb, qtd,
1750                                                    DWC_OTG_HC_XFER_XACT_ERR);
1751                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1752                         if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
1753                                 hc->qh->ping_state = 1;
1754                         }
1755                 }
1756
1757                 /*
1758                  * Halt the channel so the transfer can be re-started from
1759                  * the appropriate point or the PING protocol will start.
1760                  */
1761                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1762                 break;
1763         case UE_INTERRUPT:
1764                 qtd->error_count++;
1765                 if (hc->do_split && hc->complete_split) {
1766                         qtd->complete_split = 0;
1767                 }
1768                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1769                 break;
1770         case UE_ISOCHRONOUS:
1771                 {
1772                         dwc_otg_halt_status_e halt_status;
1773                         halt_status =
1774                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1775                                                   DWC_OTG_HC_XFER_XACT_ERR);
1776
1777                         halt_channel(hcd, hc, qtd, halt_status);
1778                 }
1779                 break;
1780         }
1781 handle_xacterr_done:
1782         disable_hc_int(hc_regs, xacterr);
1783
1784         return 1;
1785 }
1786
1787 /**
1788  * Handles a host channel frame overrun interrupt. This handler may be called
1789  * in either DMA mode or Slave mode.
1790  */
1791 static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *hcd,
1792                                        dwc_hc_t *hc,
1793                                        dwc_otg_hc_regs_t *hc_regs,
1794                                        dwc_otg_qtd_t *qtd)
1795 {
1796         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1797                     "Frame Overrun--\n", hc->hc_num);
1798
1799         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1800         case UE_CONTROL:
1801         case UE_BULK:
1802                 break;
1803         case UE_INTERRUPT:
1804                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
1805                 break;
1806         case UE_ISOCHRONOUS:
1807                 {
1808                         dwc_otg_halt_status_e halt_status;
1809                         halt_status =
1810                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1811                                                   DWC_OTG_HC_XFER_FRAME_OVERRUN);
1812
1813                         halt_channel(hcd, hc, qtd, halt_status);
1814                 }
1815                 break;
1816         }
1817
1818         disable_hc_int(hc_regs, frmovrun);
1819
1820         return 1;
1821 }
1822
1823 /**
1824  * Handles a host channel data toggle error interrupt. This handler may be
1825  * called in either DMA mode or Slave mode.
1826  */
1827 static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *hcd,
1828                                          dwc_hc_t *hc,
1829                                          dwc_otg_hc_regs_t *hc_regs,
1830                                          dwc_otg_qtd_t *qtd)
1831 {
1832         DWC_ERROR("--Host Channel %d Interrupt: "
1833                   "Data Toggle Error--\n", hc->hc_num);
1834         if (!hcd->flags.b.port_connect_status) {
1835                 /* No longer connected. */
1836                 DWC_ERROR("Not connected\n");
1837                 return 1;
1838         }
1839         if (hc->ep_is_in) {
1840                 qtd->error_count += 3;  /* Complete the error URB immediately */
1841         } else {
1842                 DWC_ERROR("Data Toggle Error on OUT transfer,"
1843                           "channel %d\n", hc->hc_num);
1844         }
1845         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1846         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1847         clear_hc_int(hc_regs, chhltd);
1848
1849         return 1;
1850 }
1851
1852 #ifdef DEBUG
1853 /**
1854  * This function is for debug only. It checks that a valid halt status is set
1855  * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
1856  * taken and a warning is issued.
1857  * @return 1 if halt status is ok, 0 otherwise.
1858  */
1859 static inline int halt_status_ok(dwc_otg_hcd_t *hcd,
1860                                  dwc_hc_t *hc,
1861                                  dwc_otg_hc_regs_t *hc_regs,
1862                                  dwc_otg_qtd_t *qtd)
1863 {
1864         hcchar_data_t hcchar;
1865         hctsiz_data_t hctsiz;
1866         hcint_data_t hcint;
1867         hcintmsk_data_t hcintmsk;
1868         hcsplt_data_t hcsplt;
1869
1870         if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
1871                 /*
1872                  * This code is here only as a check. This condition should
1873                  * never happen. Ignore the halt if it does occur.
1874                  */
1875                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1876                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1877                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1878                 hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
1879                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
1880                 DWC_WARN
1881                     ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
1882                      "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
1883                      "hcint 0x%08x, hcintmsk 0x%08x, "
1884                      "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
1885                      hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
1886                      hcintmsk.d32, hcsplt.d32, qtd->complete_split);
1887
1888                 DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
1889                          __func__, hc->hc_num);
1890                 DWC_WARN("\n");
1891                 clear_hc_int(hc_regs, chhltd);
1892                 return 0;
1893         }
1894
1895         /*
1896          * This code is here only as a check. hcchar.chdis should
1897          * never be set when the halt interrupt occurs. Halt the
1898          * channel again if it does occur.
1899          */
1900         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1901         if (hcchar.b.chdis) {
1902                 DWC_WARN("%s: hcchar.chdis set unexpectedly, "
1903                          "hcchar 0x%08x, trying to halt again\n",
1904                          __func__, hcchar.d32);
1905                 clear_hc_int(hc_regs, chhltd);
1906                 hc->halt_pending = 0;
1907                 halt_channel(hcd, hc, qtd, hc->halt_status);
1908                 return 0;
1909         }
1910
1911         return 1;
1912 }
1913 #endif
1914
1915 /**
1916  * Handles a host Channel Halted interrupt in DMA mode. This handler
1917  * determines the reason the channel halted and proceeds accordingly.
1918  */
1919 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd,
1920                                       dwc_hc_t *hc,
1921                                       dwc_otg_hc_regs_t *hc_regs,
1922                                       dwc_otg_qtd_t *qtd)
1923 {
1924         hcint_data_t hcint;
1925         hcintmsk_data_t hcintmsk;
1926         int out_nak_enh = 0;
1927         struct dwc_otg_platform_data *pldata = hcd->core_if->otg_dev->pldata;
1928
1929         /* For core with OUT NAK enhancement, the flow for high-
1930          * speed CONTROL/BULK OUT is handled a little differently.
1931          */
1932         if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
1933                 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
1934                     (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
1935                      hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
1936                         out_nak_enh = 1;
1937                 }
1938         }
1939
1940         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
1941             (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
1942              && !hcd->core_if->dma_desc_enable)) {
1943                 /*
1944                  * Just release the channel. A dequeue can happen on a
1945                  * transfer timeout. In the case of an AHB Error, the channel
1946                  * was forced to halt because there's no way to gracefully
1947                  * recover.
1948                  */
1949                 if (hcd->core_if->dma_desc_enable)
1950                         dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1951                                                        hc->halt_status);
1952                 else
1953                         release_channel(hcd, hc, qtd, hc->halt_status);
1954                 return;
1955         }
1956
1957         /* Read the HCINTn register to determine the cause for the halt. */
1958         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1959         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
1960
1961         if (hcint.b.xfercomp) {
1962                 /** @todo This is here because of a possible hardware bug.  Spec
1963                  * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1964                  * interrupt w/ACK bit set should occur, but I only see the
1965                  * XFERCOMP bit, even with it masked out.  This is a workaround
1966                  * for that behavior.  Should fix this when hardware is fixed.
1967                  */
1968                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1969                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1970                 }
1971                 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
1972         } else if (hcint.b.stall) {
1973                 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
1974         } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
1975                 if (out_nak_enh) {
1976                         if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
1977                                 DWC_DEBUG("XactErr with NYET/NAK/ACK\n");
1978                                 qtd->error_count = 0;
1979                         } else {
1980                                 DWC_DEBUG("XactErr without NYET/NAK/ACK\n");
1981                         }
1982                 }
1983
1984                 /*
1985                  * Must handle xacterr before nak or ack. Could get a xacterr
1986                  * at the same time as either of these on a BULK/CONTROL OUT
1987                  * that started with a PING. The xacterr takes precedence.
1988                  */
1989                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1990         } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
1991                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1992         } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
1993                 handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
1994         } else if (hcint.b.bblerr) {
1995                 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
1996         } else if (hcint.b.frmovrun) {
1997                 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
1998         } else if (hcint.b.datatglerr) {
1999                 handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
2000         } else if (!out_nak_enh) {
2001                 if (hcint.b.nyet) {
2002                         /*
2003                          * Must handle nyet before nak or ack. Could get a nyet at the
2004                          * same time as either of those on a BULK/CONTROL OUT that
2005                          * started with a PING. The nyet takes precedence.
2006                          */
2007                         handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
2008                 } else if (hcint.b.nak && !hcintmsk.b.nak) {
2009                         /*
2010                          * If nak is not masked, it's because a non-split IN transfer
2011                          * is in an error state. In that case, the nak is handled by
2012                          * the nak interrupt handler, not here. Handle nak here for
2013                          * BULK/CONTROL OUT transfers, which halt on a NAK to allow
2014                          * rewinding the buffer pointer.
2015                          */
2016                         handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
2017                 } else if (hcint.b.ack && !hcintmsk.b.ack) {
2018                         /*
2019                          * If ack is not masked, it's because a non-split IN transfer
2020                          * is in an error state. In that case, the ack is handled by
2021                          * the ack interrupt handler, not here. Handle ack here for
2022                          * split transfers. Start splits halt on ACK.
2023                          */
2024                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
2025                 } else {
2026                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2027                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2028                                 /*
2029                                  * A periodic transfer halted with no other channel
2030                                  * interrupts set. Assume it was halted by the core
2031                                  * because it could not be completed in its scheduled
2032                                  * (micro)frame.
2033                                  */
2034 #ifdef DEBUG
2035                                 DWC_PRINTF
2036                                     ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
2037                                      __func__, hc->hc_num);
2038 #endif
2039                                 halt_channel(hcd, hc, qtd,
2040                                              DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
2041                         } else {
2042                                 DWC_ERROR
2043                                     ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
2044                                      "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
2045                                      __func__, hc->hc_num, hcint.d32,
2046                                      DWC_READ_REG32(&hcd->core_if->
2047                                                     core_global_regs->gintsts));
2048                                 clear_hc_int(hc_regs, chhltd);
2049                         }
2050
2051                 }
2052         } else {
2053                 DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
2054                            hcint.d32);
2055                 pldata->soft_reset(pldata, RST_CHN_HALT);
2056                 mdelay(5);
2057                 if (!hcint.b.nyet && !hcint.b.nak && !hcint.b.ack)
2058                         clear_hc_int(hc_regs, chhltd);
2059         }
2060 }
2061
2062 /**
2063  * Handles a host channel Channel Halted interrupt.
2064  *
2065  * In slave mode, this handler is called only when the driver specifically
2066  * requests a halt. This occurs during handling other host channel interrupts
2067  * (e.g. nak, xacterr, stall, nyet, etc.).
2068  *
2069  * In DMA mode, this is the interrupt that occurs when the core has finished
2070  * processing a transfer on a channel. Other host channel interrupts (except
2071  * ahberr) are disabled in DMA mode.
2072  */
2073 static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *hcd,
2074                                      dwc_hc_t *hc,
2075                                      dwc_otg_hc_regs_t *hc_regs,
2076                                      dwc_otg_qtd_t *qtd)
2077 {
2078         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
2079                     "Channel Halted--\n", hc->hc_num);
2080
2081         if (hcd->core_if->dma_enable) {
2082                 handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
2083         } else {
2084 #ifdef DEBUG
2085                 if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
2086                         return 1;
2087                 }
2088 #endif
2089                 release_channel(hcd, hc, qtd, hc->halt_status);
2090         }
2091
2092         return 1;
2093 }
2094
2095 /** Handles interrupt for a specific Host Channel */
2096 int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
2097 {
2098         int retval = 0;
2099         hcint_data_t hcint;
2100         hcintmsk_data_t hcintmsk;
2101         dwc_hc_t *hc;
2102         dwc_otg_hc_regs_t *hc_regs;
2103         dwc_otg_qtd_t *qtd;
2104
2105         DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
2106
2107         hc = dwc_otg_hcd->hc_ptr_array[num];
2108         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
2109         if (DWC_CIRCLEQ_EMPTY(&hc->qh->qtd_list)) {
2110                 /* All transfer had been killed, clear panding interrupts */
2111                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2112                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2113                 release_channel(dwc_otg_hcd, hc, NULL,
2114                                 DWC_OTG_HC_XFER_URB_DEQUEUE);
2115                 return retval;
2116         }
2117         qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
2118
2119         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2120         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
2121         DWC_DEBUGPL(DBG_HCDV,
2122                     "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2123                     hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
2124         hcint.d32 = hcint.d32 & hcintmsk.d32;
2125
2126         if (!dwc_otg_hcd->core_if->dma_enable) {
2127                 if (hcint.b.chhltd && hcint.d32 != 0x2) {
2128                         hcint.b.chhltd = 0;
2129                 }
2130         }
2131
2132         if (hcint.b.chhltd) {
2133                 retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2134         }
2135         if (hcint.b.xfercomp) {
2136                 retval |=
2137                     handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2138                 /*
2139                  * If NYET occurred at same time as Xfer Complete, the NYET is
2140                  * handled by the Xfer Complete interrupt handler. Don't want
2141                  * to call the NYET interrupt handler in this case.
2142                  */
2143                 hcint.b.nyet = 0;
2144         }
2145         if (hcint.b.ahberr) {
2146                 retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2147         }
2148         if (hcint.b.stall) {
2149                 retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2150         }
2151         if (hcint.b.nak) {
2152                 retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2153         }
2154         if (hcint.b.ack) {
2155                 if (!hcint.b.chhltd)
2156                         retval |=
2157                             handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2158         }
2159         if (hcint.b.nyet) {
2160                 retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2161         }
2162         if (hcint.b.xacterr) {
2163                 retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2164         }
2165         if (hcint.b.bblerr) {
2166                 retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2167         }
2168         if (hcint.b.frmovrun) {
2169                 retval |=
2170                     handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2171         }
2172         if (hcint.b.datatglerr) {
2173                 disable_hc_int(hc_regs, datatglerr);
2174                 clear_hc_int(hc_regs, chhltd);
2175         }
2176
2177         return retval;
2178 }
2179
2180 #endif /* DWC_DEVICE_ONLY */