drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
   3  * $Revision: #92 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 #include "dwc_otg_hcd.h"
  36 #include "dwc_otg_regs.h"
  37 #include <linux/usb.h>
  38 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
  39 #include <../drivers/usb/core/hcd.h>
  40 #else
  41 #include <linux/usb/hcd.h>
  42 #endif
  43 /** @file
  44  * This file contains the implementation of the HCD Interrupt handlers.
  45  */
  46
  47 /** This function handles interrupts for the HCD. */
  48 int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd)
  49 {
  50         int retval = 0;
  51
  52         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
  53         gintsts_data_t gintsts;
  54 #ifdef DEBUG
  55         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
  56 #endif
  57
  58         if (dwc_otg_check_haps_status(core_if) == -1) {
  59                 DWC_WARN("HAPS is disconnected");
  60                 return retval;
  61         }
  62
  63         /* Exit from ISR if core is hibernated */
  64         if (core_if->hibernation_suspend == 1) {
  65                 return retval;
  66         }
  67         DWC_SPINLOCK(dwc_otg_hcd->lock);
  68         /* Check if HOST Mode */
  69         if (dwc_otg_is_host_mode(core_if)) {
  70                 gintsts.d32 = dwc_otg_read_core_intr(core_if);
  71                 if (!gintsts.d32) {
  72                         DWC_SPINUNLOCK(dwc_otg_hcd->lock);
  73                         return 0;
  74                 }
  75 #ifdef DEBUG
  76                 /* Don't print debug message in the interrupt handler on SOF */
  77 #ifndef DEBUG_SOF
  78                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
  79 #endif
  80                         DWC_DEBUGPL(DBG_HCD, "\n");
  81 #endif
  82
  83 #ifdef DEBUG
  84 #ifndef DEBUG_SOF
  85                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
  86 #endif
  87                         DWC_DEBUGPL(DBG_HCD,
  88                                     "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
  89                                     gintsts.d32);
  90 #endif
  91
  92                 if (gintsts.b.sofintr) {
  93                         retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
  94                 }
  95                 if (gintsts.b.rxstsqlvl) {
  96                         retval |=
  97                             dwc_otg_hcd_handle_rx_status_q_level_intr
  98                             (dwc_otg_hcd);
  99                 }
 100                 if (gintsts.b.nptxfempty) {
 101                         retval |=
 102                             dwc_otg_hcd_handle_np_tx_fifo_empty_intr
 103                             (dwc_otg_hcd);
 104                 }
 105                 if (gintsts.b.i2cintr) {
 106                         /** @todo Implement i2cintr handler. */
 107                 }
 108                 if (gintsts.b.portintr) {
 109                         retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
 110                 }
 111                 if (gintsts.b.hcintr) {
 112                         retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
 113                 }
 114                 if (gintsts.b.ptxfempty) {
 115                         retval |=
 116                             dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
 117                             (dwc_otg_hcd);
 118                 }
 119 #ifdef DEBUG
 120 #ifndef DEBUG_SOF
 121                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
 122 #endif
 123                 {
 124                         DWC_DEBUGPL(DBG_HCD,
 125                                     "DWC OTG HCD Finished Servicing Interrupts\n");
 126                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
 127                                     DWC_READ_REG32(&global_regs->gintsts));
 128                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
 129                                     DWC_READ_REG32(&global_regs->gintmsk));
 130                 }
 131 #endif
 132
 133 #ifdef DEBUG
 134 #ifndef DEBUG_SOF
 135                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
 136 #endif
 137                         DWC_DEBUGPL(DBG_HCD, "\n");
 138 #endif
 139
 140         }
 141         DWC_SPINUNLOCK(dwc_otg_hcd->lock);
 142         return retval;
 143 }
 144
 145 #ifdef DWC_TRACK_MISSED_SOFS
 146 #warning Compiling code to track missed SOFs
 147 #define FRAME_NUM_ARRAY_SIZE 1000
 148 /**
 149  * This function is for debug only.
 150  */
 151 static inline void track_missed_sofs(uint16_t curr_frame_number)
 152 {
 153         static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
 154         static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
 155         static int frame_num_idx;
 156         static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
 157         static int dumped_frame_num_array;
 158
 159         if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
 160                 if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
 161                     curr_frame_number) {
 162                         frame_num_array[frame_num_idx] = curr_frame_number;
 163                         last_frame_num_array[frame_num_idx++] = last_frame_num;
 164                 }
 165         } else if (!dumped_frame_num_array) {
 166                 int i;
 167                 DWC_PRINTF("Frame     Last Frame\n");
 168                 DWC_PRINTF("-----     ----------\n");
 169                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
 170                         DWC_PRINTF("0x%04x    0x%04x\n",
 171                                    frame_num_array[i], last_frame_num_array[i]);
 172                 }
 173                 dumped_frame_num_array = 1;
 174         }
 175         last_frame_num = curr_frame_number;
 176 }
 177 #endif
 178
 179 /**
 180  * Handles the start-of-frame interrupt in host mode. Non-periodic
 181  * transactions may be queued to the DWC_otg controller for the current
 182  * (micro)frame. Periodic transactions may be queued to the controller for the
 183  * next (micro)frame.
 184  */
 185 int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *hcd)
 186 {
 187         hfnum_data_t hfnum;
 188         dwc_list_link_t *qh_entry;
 189         dwc_otg_qh_t *qh;
 190         dwc_otg_transaction_type_e tr_type;
 191         gintsts_data_t gintsts = {.d32 = 0 };
 192
 193         hfnum.d32 =
 194             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
 195
 196 #ifdef DEBUG_SOF
 197         DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
 198 #endif
 199         hcd->frame_number = hfnum.b.frnum;
 200
 201 #ifdef DEBUG
 202         hcd->frrem_accum += hfnum.b.frrem;
 203         hcd->frrem_samples++;
 204 #endif
 205
 206 #ifdef DWC_TRACK_MISSED_SOFS
 207         track_missed_sofs(hcd->frame_number);
 208 #endif
 209         /* Determine whether any periodic QHs should be executed. */
 210         qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
 211         while (qh_entry != &hcd->periodic_sched_inactive) {
 212                 qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
 213                 qh_entry = qh_entry->next;
 214                 if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
 215                         /*
 216                          * Move QH to the ready list to be executed next
 217                          * (micro)frame.
 218                          */
 219                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
 220                                            &qh->qh_list_entry);
 221                 }
 222         }
 223         tr_type = dwc_otg_hcd_select_transactions(hcd);
 224         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 225                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
 226         }
 227
 228         /* Clear interrupt */
 229         gintsts.b.sofintr = 1;
 230         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
 231
 232         return 1;
 233 }
 234
 235 /** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
 236  * least one packet in the Rx FIFO.  The packets are moved from the FIFO to
 237  * memory if the DWC_otg controller is operating in Slave mode. */
 238 int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 239 {
 240         host_grxsts_data_t grxsts;
 241         dwc_hc_t *hc = NULL;
 242
 243         DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
 244
 245         grxsts.d32 =
 246             DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
 247
 248         hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
 249         if (!hc) {
 250                 DWC_ERROR("Unable to get corresponding channel\n");
 251                 return 0;
 252         }
 253
 254         /* Packet Status */
 255         DWC_DEBUGPL(DBG_HCDV, "    Ch num = %d\n", grxsts.b.chnum);
 256         DWC_DEBUGPL(DBG_HCDV, "    Count = %d\n", grxsts.b.bcnt);
 257         DWC_DEBUGPL(DBG_HCDV, "    DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
 258                     hc->data_pid_start);
 259         DWC_DEBUGPL(DBG_HCDV, "    PStatus = %d\n", grxsts.b.pktsts);
 260
 261         switch (grxsts.b.pktsts) {
 262         case DWC_GRXSTS_PKTSTS_IN:
 263                 /* Read the data into the host buffer. */
 264                 if (grxsts.b.bcnt > 0) {
 265                         dwc_otg_read_packet(dwc_otg_hcd->core_if,
 266                                             hc->xfer_buff, grxsts.b.bcnt);
 267
 268                         /* Update the HC fields for the next packet received. */
 269                         hc->xfer_count += grxsts.b.bcnt;
 270                         hc->xfer_buff += grxsts.b.bcnt;
 271                 }
 272
 273         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
 274         case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
 275         case DWC_GRXSTS_PKTSTS_CH_HALTED:
 276                 /* Handled in interrupt, just ignore data */
 277                 break;
 278         default:
 279                 DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
 280                           grxsts.b.pktsts);
 281                 break;
 282         }
 283
 284         return 1;
 285 }
 286
 287 /** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 288  * data packets may be written to the FIFO for OUT transfers. More requests
 289  * may be written to the non-periodic request queue for IN transfers. This
 290  * interrupt is enabled only in Slave mode. */
 291 int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 292 {
 293         DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 294         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
 295                                        DWC_OTG_TRANSACTION_NON_PERIODIC);
 296         return 1;
 297 }
 298
 299 /** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 300  * packets may be written to the FIFO for OUT transfers. More requests may be
 301  * written to the periodic request queue for IN transfers. This interrupt is
 302  * enabled only in Slave mode. */
 303 int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 304 {
 305         DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
 306         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
 307                                        DWC_OTG_TRANSACTION_PERIODIC);
 308         return 1;
 309 }
 310
 311 /** There are multiple conditions that can cause a port interrupt. This function
 312  * determines which interrupt conditions have occurred and handles them
 313  * appropriately. */
 314 int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 315 {
 316         int retval = 0;
 317         hprt0_data_t hprt0;
 318         hprt0_data_t hprt0_modify;
 319         struct usb_hcd *hcd = dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
 320         struct usb_bus *bus = hcd_to_bus(hcd);
 321
 322         hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 323         hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 324
 325         /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
 326          * GINTSTS */
 327
 328         hprt0_modify.b.prtena = 0;
 329         hprt0_modify.b.prtconndet = 0;
 330         hprt0_modify.b.prtenchng = 0;
 331         hprt0_modify.b.prtovrcurrchng = 0;
 332
 333         /* Port Connect Detected
 334          * Set flag and clear if detected */
 335         if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
 336                 /* Dont modify port status if we are in hibernation state */
 337                 hprt0_modify.b.prtconndet = 1;
 338                 hprt0_modify.b.prtenchng = 1;
 339                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
 340                                 hprt0_modify.d32);
 341                 hprt0.d32 =
 342                     DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 343                 return retval;
 344         }
 345
 346         if (hprt0.b.prtconndet) {
 347                 /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
 348                 if (dwc_otg_hcd->core_if->adp_enable &&
 349                     dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
 350                         DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
 351                         DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.
 352                                          vbuson_timer);
 353                         dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
 354                         /* TODO - check if this is required, as
 355                          * host initialization was already performed
 356                          * after initial ADP probing
 357                          */
 358                         /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
 359                            dwc_otg_core_init(dwc_otg_hcd->core_if);
 360                            dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
 361                            cil_hcd_start(dwc_otg_hcd->core_if); */
 362                 } else {
 363                         hprt0_data_t hprt0_local;
 364                         /* check if root hub is in suspend state
 365                          * if root hub in suspend, resume it.
 366                          */
 367                         if ((bus->root_hub)
 368                             && (hcd->state == HC_STATE_SUSPENDED)) {
 369                                 DWC_PRINTF
 370                                     ("%s: hcd->state = %d, hcd->flags = %ld\n",
 371                                      __func__, hcd->state, hcd->flags);
 372                                 usb_hcd_resume_root_hub(hcd);
 373                         }
 374                         DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
 375                                     "Port Connect Detected--\n", hprt0.d32);
 376                         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 377                         dwc_otg_hcd->flags.b.port_connect_status = 1;
 378                         hprt0_modify.b.prtconndet = 1;
 379                         /* PET testing */
 380                         if (dwc_otg_hcd->core_if->otg_ver
 381                             && (dwc_otg_hcd->core_if->test_mode == 7)) {
 382                                 hprt0_local.d32 =
 383                                     dwc_otg_read_hprt0(dwc_otg_hcd->core_if);
 384                                 hprt0_local.b.prtrst = 1;
 385                                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->
 386                                                 hprt0, hprt0_local.d32);
 387                                 dwc_mdelay(60);
 388                                 hprt0.d32 =
 389                                     dwc_otg_read_hprt0(dwc_otg_hcd->core_if);
 390                                 hprt0.b.prtrst = 0;
 391                                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->
 392                                                 hprt0, hprt0.d32);
 393                         }
 394
 395                         /* B-Device has connected, Delete the connection timer. */
 396                         DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
 397                 }
 398                 /* The Hub driver asserts a reset when it sees port connect
 399                  * status change flag */
 400                 retval |= 1;
 401         }
 402
 403         /* Port Enable Changed
 404          * Clear if detected - Set internal flag if disabled */
 405         if (hprt0.b.prtenchng) {
 406                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
 407                             "Port Enable Changed--\n", hprt0.d32);
 408                 hprt0_modify.b.prtenchng = 1;
 409                 if (hprt0.b.prtena == 1) {
 410                         hfir_data_t hfir;
 411                         int do_reset = 0;
 412                         dwc_otg_core_params_t *params =
 413                             dwc_otg_hcd->core_if->core_params;
 414                         dwc_otg_core_global_regs_t *global_regs =
 415                             dwc_otg_hcd->core_if->core_global_regs;
 416                         dwc_otg_host_if_t *host_if =
 417                             dwc_otg_hcd->core_if->host_if;
 418
 419                         /* Every time when port enables calculate
 420                          * HFIR.FrInterval
 421                          */
 422                         hfir.d32 =
 423                             DWC_READ_REG32(&host_if->host_global_regs->hfir);
 424                         hfir.b.frint =
 425                             calc_frame_interval(dwc_otg_hcd->core_if);
 426                         DWC_WRITE_REG32(&host_if->host_global_regs->hfir,
 427                                         hfir.d32);
 428
 429                         /* Check if we need to adjust the PHY clock speed for
 430                          * low power and adjust it */
 431                         if (params->host_support_fs_ls_low_power) {
 432                                 gusbcfg_data_t usbcfg;
 433
 434                                 usbcfg.d32 =
 435                                     DWC_READ_REG32(&global_regs->gusbcfg);
 436
 437                                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
 438                                     || hprt0.b.prtspd ==
 439                                     DWC_HPRT0_PRTSPD_FULL_SPEED) {
 440                                         /*
 441                                          * Low power
 442                                          */
 443                                         hcfg_data_t hcfg;
 444                                         if (usbcfg.b.phylpwrclksel == 0) {
 445                                                 /* Set PHY low power clock select for FS/LS devices */
 446                                                 usbcfg.b.phylpwrclksel = 1;
 447                                                 DWC_WRITE_REG32
 448                                                     (&global_regs->gusbcfg,
 449                                                      usbcfg.d32);
 450                                                 do_reset = 1;
 451                                         }
 452
 453                                         hcfg.d32 =
 454                                             DWC_READ_REG32
 455                                             (&host_if->host_global_regs->hcfg);
 456
 457                                         if (hprt0.b.prtspd ==
 458                                             DWC_HPRT0_PRTSPD_LOW_SPEED
 459                                             && params->host_ls_low_power_phy_clk
 460                                             ==
 461                                             DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
 462                                                 /* 6 MHZ */
 463                                                 DWC_DEBUGPL(DBG_CIL,
 464                                                             "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
 465                                                 if (hcfg.b.fslspclksel !=
 466                                                     DWC_HCFG_6_MHZ) {
 467                                                         hcfg.b.fslspclksel =
 468                                                             DWC_HCFG_6_MHZ;
 469                                                         DWC_WRITE_REG32
 470                                                             (&host_if->
 471                                                              host_global_regs->
 472                                                              hcfg, hcfg.d32);
 473                                                         do_reset = 1;
 474                                                 }
 475                                         } else {
 476                                                 /* 48 MHZ */
 477                                                 DWC_DEBUGPL(DBG_CIL,
 478                                                             "FS_PHY programming HCFG to 48 MHz ()\n");
 479                                                 if (hcfg.b.fslspclksel !=
 480                                                     DWC_HCFG_48_MHZ) {
 481                                                         hcfg.b.fslspclksel =
 482                                                             DWC_HCFG_48_MHZ;
 483                                                         DWC_WRITE_REG32
 484                                                             (&host_if->
 485                                                              host_global_regs->
 486                                                              hcfg, hcfg.d32);
 487                                                         do_reset = 1;
 488                                                 }
 489                                         }
 490                                 } else {
 491                                         /*
 492                                          * Not low power
 493                                          */
 494                                         if (usbcfg.b.phylpwrclksel == 1) {
 495                                                 usbcfg.b.phylpwrclksel = 0;
 496                                                 DWC_WRITE_REG32
 497                                                     (&global_regs->gusbcfg,
 498                                                      usbcfg.d32);
 499                                                 do_reset = 1;
 500                                         }
 501                                 }
 502
 503                                 if (do_reset) {
 504                                         DWC_TASK_SCHEDULE(dwc_otg_hcd->
 505                                                           reset_tasklet);
 506                                 }
 507                         }
 508
 509                         if (!do_reset) {
 510                                 /* Port has been enabled set the reset change flag */
 511                                 dwc_otg_hcd->flags.b.port_reset_change = 1;
 512                         }
 513                 } else {
 514                         dwc_otg_hcd->flags.b.port_enable_change = 1;
 515                 }
 516                 retval |= 1;
 517         }
 518
 519         /** Overcurrent Change Interrupt */
 520         if (hprt0.b.prtovrcurrchng) {
 521                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
 522                             "Port Overcurrent Changed--\n", hprt0.d32);
 523                 dwc_otg_hcd->flags.b.port_over_current_change = 1;
 524                 hprt0_modify.b.prtovrcurrchng = 1;
 525                 retval |= 1;
 526         }
 527
 528         /* Clear Port Interrupts */
 529         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
 530
 531         return retval;
 532 }
 533
 534 /** This interrupt indicates that one or more host channels has a pending
 535  * interrupt. There are multiple conditions that can cause each host channel
 536  * interrupt. This function determines which conditions have occurred for each
 537  * host channel interrupt and handles them appropriately. */
 538 int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 539 {
 540         int i;
 541         int retval = 0;
 542         haint_data_t haint;
 543
 544         /* Clear appropriate bits in HCINTn to clear the interrupt bit in
 545          * GINTSTS */
 546
 547         haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
 548
 549         for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
 550                 if (haint.b2.chint & (1 << i)) {
 551                         retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
 552                 }
 553         }
 554
 555         return retval;
 556 }
 557
 558 /**
 559  * Gets the actual length of a transfer after the transfer halts. _halt_status
 560  * holds the reason for the halt.
 561  *
 562  * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
 563  * *short_read is set to 1 upon return if less than the requested
 564  * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
 565  * return. short_read may also be NULL on entry, in which case it remains
 566  * unchanged.
 567  */
 568 static uint32_t get_actual_xfer_length(dwc_hc_t *hc,
 569                                        dwc_otg_hc_regs_t *hc_regs,
 570                                        dwc_otg_qtd_t *qtd,
 571                                        dwc_otg_halt_status_e halt_status,
 572                                        int *short_read)
 573 {
 574         hctsiz_data_t hctsiz;
 575         uint32_t length;
 576
 577         if (short_read != NULL) {
 578                 *short_read = 0;
 579         }
 580         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 581
 582         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
 583                 if (hc->ep_is_in) {
 584                         length = hc->xfer_len - hctsiz.b.xfersize;
 585                         if (short_read != NULL) {
 586                                 *short_read = (hctsiz.b.xfersize != 0);
 587                         }
 588                 } else if (hc->qh->do_split) {
 589                         length = qtd->ssplit_out_xfer_count;
 590                 } else {
 591                         length = hc->xfer_len;
 592                 }
 593         } else {
 594                 /*
 595                  * Must use the hctsiz.pktcnt field to determine how much data
 596                  * has been transferred. This field reflects the number of
 597                  * packets that have been transferred via the USB. This is
 598                  * always an integral number of packets if the transfer was
 599                  * halted before its normal completion. (Can't use the
 600                  * hctsiz.xfersize field because that reflects the number of
 601                  * bytes transferred via the AHB, not the USB).
 602                  */
 603                 length =
 604                     (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
 605         }
 606
 607         return length;
 608 }
 609
 610 /**
 611  * Updates the state of the URB after a Transfer Complete interrupt on the
 612  * host channel. Updates the actual_length field of the URB based on the
 613  * number of bytes transferred via the host channel. Sets the URB status
 614  * if the data transfer is finished.
 615  *
 616  * @return 1 if the data transfer specified by the URB is completely finished,
 617  * 0 otherwise.
 618  */
 619 static int update_urb_state_xfer_comp(dwc_hc_t *hc,
 620                                       dwc_otg_hc_regs_t *hc_regs,
 621                                       dwc_otg_hcd_urb_t *urb,
 622                                       dwc_otg_qtd_t *qtd)
 623 {
 624         int xfer_done = 0;
 625         int short_read = 0;
 626
 627         int xfer_length;
 628
 629         xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
 630                                              DWC_OTG_HC_XFER_COMPLETE,
 631                                              &short_read);
 632
 633         /* non DWORD-aligned buffer case handling. */
 634         if (hc->align_buff && xfer_length && hc->ep_is_in) {
 635                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
 636                            xfer_length);
 637         }
 638
 639         urb->actual_length += xfer_length;
 640
 641         if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
 642             (urb->flags & URB_SEND_ZERO_PACKET)
 643             && (urb->actual_length == urb->length)
 644             && !(urb->length % hc->max_packet)) {
 645                 xfer_done = 0;
 646         } else if (short_read || urb->actual_length >= urb->length) {
 647                 xfer_done = 1;
 648                 urb->status = 0;
 649         }
 650 #ifdef DEBUG
 651         {
 652                 hctsiz_data_t hctsiz;
 653                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 654                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
 655                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
 656                             hc->hc_num);
 657                 DWC_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", hc->xfer_len);
 658                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n",
 659                             hctsiz.b.xfersize);
 660                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
 661                             urb->length);
 662                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
 663                             urb->actual_length);
 664                 DWC_DEBUGPL(DBG_HCDV, "  short_read %d, xfer_done %d\n",
 665                             short_read, xfer_done);
 666         }
 667 #endif
 668
 669         return xfer_done;
 670 }
 671
 672 /*
 673  * Save the starting data toggle for the next transfer. The data toggle is
 674  * saved in the QH for non-control transfers and it's saved in the QTD for
 675  * control transfers.
 676  */
 677 void dwc_otg_hcd_save_data_toggle(dwc_hc_t *hc,
 678                                   dwc_otg_hc_regs_t *hc_regs,
 679                                   dwc_otg_qtd_t *qtd)
 680 {
 681         hctsiz_data_t hctsiz;
 682         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 683
 684         if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
 685                 dwc_otg_qh_t *qh = hc->qh;
 686                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
 687                         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
 688                 } else {
 689                         qh->data_toggle = DWC_OTG_HC_PID_DATA1;
 690                 }
 691         } else {
 692                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
 693                         qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
 694                 } else {
 695                         qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
 696                 }
 697         }
 698 }
 699
 700 /**
 701  * Updates the state of an Isochronous URB when the transfer is stopped for
 702  * any reason. The fields of the current entry in the frame descriptor array
 703  * are set based on the transfer state and the input _halt_status. Completes
 704  * the Isochronous URB if all the URB frames have been completed.
 705  *
 706  * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
 707  * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
 708  */
 709 static dwc_otg_halt_status_e
 710 update_isoc_urb_state(dwc_otg_hcd_t *hcd,
 711                       dwc_hc_t *hc,
 712                       dwc_otg_hc_regs_t *hc_regs,
 713                       dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
 714 {
 715         dwc_otg_hcd_urb_t *urb = qtd->urb;
 716         dwc_otg_halt_status_e ret_val = halt_status;
 717         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
 718
 719         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 720         switch (halt_status) {
 721         case DWC_OTG_HC_XFER_COMPLETE:
 722                 frame_desc->status = 0;
 723                 frame_desc->actual_length =
 724                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
 725
 726                 /* non DWORD-aligned buffer case handling. */
 727                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
 728                         dwc_memcpy(urb->buf + frame_desc->offset +
 729                                    qtd->isoc_split_offset, hc->qh->dw_align_buf,
 730                                    frame_desc->actual_length);
 731                 }
 732
 733                 break;
 734         case DWC_OTG_HC_XFER_FRAME_OVERRUN:
 735                 urb->error_count++;
 736                 if (hc->ep_is_in) {
 737                         frame_desc->status = -DWC_E_NO_STREAM_RES;
 738                 } else {
 739                         frame_desc->status = -DWC_E_COMMUNICATION;
 740                 }
 741                 frame_desc->actual_length = 0;
 742                 break;
 743         case DWC_OTG_HC_XFER_BABBLE_ERR:
 744                 urb->error_count++;
 745                 frame_desc->status = -DWC_E_OVERFLOW;
 746                 /* Don't need to update actual_length in this case. */
 747                 break;
 748         case DWC_OTG_HC_XFER_XACT_ERR:
 749                 urb->error_count++;
 750                 frame_desc->status = -DWC_E_PROTOCOL;
 751                 frame_desc->actual_length =
 752                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
 753
 754                 /* non DWORD-aligned buffer case handling. */
 755                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
 756                         dwc_memcpy(urb->buf + frame_desc->offset +
 757                                    qtd->isoc_split_offset, hc->qh->dw_align_buf,
 758                                    frame_desc->actual_length);
 759                 }
 760                 /* Skip whole frame */
 761                 if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
 762                     hc->ep_is_in && hcd->core_if->dma_enable) {
 763                         qtd->complete_split = 0;
 764                         qtd->isoc_split_offset = 0;
 765                 }
 766
 767                 break;
 768         default:
 769                 DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
 770                 break;
 771         }
 772         if (++qtd->isoc_frame_index == urb->packet_count) {
 773                 /*
 774                  * urb->status is not used for isoc transfers.
 775                  * The individual frame_desc statuses are used instead.
 776                  */
 777                 hcd->fops->complete(hcd, urb->priv, urb, 0);
 778                 ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
 779         } else {
 780                 ret_val = DWC_OTG_HC_XFER_COMPLETE;
 781         }
 782         return ret_val;
 783 }
 784
 785 /**
 786  * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 787  * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 788  * still linked to the QH, the QH is added to the end of the inactive
 789  * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 790  * schedule if no more QTDs are linked to the QH.
 791  */
 792 static void deactivate_qh(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int free_qtd)
 793 {
 794         int continue_split = 0;
 795         dwc_otg_qtd_t *qtd;
 796
 797         DWC_DEBUGPL(DBG_HCDV, "  %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
 798
 799         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
 800
 801         if (qtd->complete_split) {
 802                 continue_split = 1;
 803         } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
 804                    qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
 805                 continue_split = 1;
 806         }
 807
 808         if (free_qtd) {
 809                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
 810                 continue_split = 0;
 811         }
 812
 813         qh->channel = NULL;
 814         dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
 815 }
 816
 817 /**
 818  * Releases a host channel for use by other transfers. Attempts to select and
 819  * queue more transactions since at least one host channel is available.
 820  *
 821  * @param hcd The HCD state structure.
 822  * @param hc The host channel to release.
 823  * @param qtd The QTD associated with the host channel. This QTD may be freed
 824  * if the transfer is complete or an error has occurred.
 825  * @param halt_status Reason the channel is being released. This status
 826  * determines the actions taken by this function.
 827  */
 828 static void release_channel(dwc_otg_hcd_t *hcd,
 829                             dwc_hc_t *hc,
 830                             dwc_otg_qtd_t *qtd,
 831                             dwc_otg_halt_status_e halt_status)
 832 {
 833         dwc_otg_transaction_type_e tr_type;
 834         int free_qtd;
 835         int continue_trans = 1;
 836
 837         DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d\n",
 838                     __func__, hc->hc_num, halt_status);
 839
 840         switch (halt_status) {
 841         case DWC_OTG_HC_XFER_URB_COMPLETE:
 842                 free_qtd = 1;
 843                 break;
 844         case DWC_OTG_HC_XFER_AHB_ERR:
 845         case DWC_OTG_HC_XFER_STALL:
 846         case DWC_OTG_HC_XFER_BABBLE_ERR:
 847                 free_qtd = 1;
 848                 break;
 849         case DWC_OTG_HC_XFER_XACT_ERR:
 850                 if (qtd->error_count >= 3) {
 851                         DWC_DEBUGPL(DBG_HCDV,
 852                                     "  Complete URB with transaction error\n");
 853                         free_qtd = 1;
 854                         qtd->urb->status = -DWC_E_PROTOCOL;
 855                         hcd->fops->complete(hcd, qtd->urb->priv,
 856                                             qtd->urb, -DWC_E_PROTOCOL);
 857                 } else {
 858                         free_qtd = 0;
 859                 }
 860                 break;
 861         case DWC_OTG_HC_XFER_URB_DEQUEUE:
 862                 /*
 863                  * The QTD has already been removed and the QH has been
 864                  * deactivated. Don't want to do anything except release the
 865                  * host channel and try to queue more transfers.
 866                  */
 867                 continue_trans = 0;
 868                 goto cleanup;
 869         case DWC_OTG_HC_XFER_NO_HALT_STATUS:
 870                 free_qtd = 0;
 871                 break;
 872         case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
 873                 DWC_DEBUGPL(DBG_HCDV, "  Complete URB with I/O error\n");
 874                 free_qtd = 1;
 875                 qtd->urb->status = -DWC_E_IO;
 876                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, -DWC_E_IO);
 877                 break;
 878         default:
 879                 free_qtd = 0;
 880                 break;
 881         }
 882
 883         if (hc->csplit_nak) {
 884                 continue_trans = 0;
 885                 hc->csplit_nak = 0;
 886         }
 887         deactivate_qh(hcd, hc->qh, free_qtd);
 888
 889 cleanup:
 890         /*
 891          * Release the host channel for use by other transfers. The cleanup
 892          * function clears the channel interrupt enables and conditions, so
 893          * there's no need to clear the Channel Halted interrupt separately.
 894          */
 895         dwc_otg_hc_cleanup(hcd->core_if, hc);
 896         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
 897
 898         switch (hc->ep_type) {
 899         case DWC_OTG_EP_TYPE_CONTROL:
 900         case DWC_OTG_EP_TYPE_BULK:
 901                 hcd->non_periodic_channels--;
 902                 break;
 903
 904         default:
 905                 /*
 906                  * Don't release reservations for periodic channels here.
 907                  * That's done when a periodic transfer is descheduled (i.e.
 908                  * when the QH is removed from the periodic schedule).
 909                  */
 910                 break;
 911         }
 912
 913         /* Try to queue more transfers now that there's a free channel. */
 914         if (continue_trans) {
 915                 tr_type = dwc_otg_hcd_select_transactions(hcd);
 916                 if (tr_type != DWC_OTG_TRANSACTION_NONE)
 917                         dwc_otg_hcd_queue_transactions(hcd, tr_type);
 918         }
 919 }
 920
 921 /**
 922  * Halts a host channel. If the channel cannot be halted immediately because
 923  * the request queue is full, this function ensures that the FIFO empty
 924  * interrupt for the appropriate queue is enabled so that the halt request can
 925  * be queued when there is space in the request queue.
 926  *
 927  * This function may also be called in DMA mode. In that case, the channel is
 928  * simply released since the core always halts the channel automatically in
 929  * DMA mode.
 930  */
 931 static void halt_channel(dwc_otg_hcd_t *hcd,
 932                          dwc_hc_t *hc,
 933                          dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
 934 {
 935         if (hcd->core_if->dma_enable) {
 936                 release_channel(hcd, hc, qtd, halt_status);
 937                 return;
 938         }
 939
 940         /* Slave mode processing... */
 941         dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
 942
 943         if (hc->halt_on_queue) {
 944                 gintmsk_data_t gintmsk = {.d32 = 0 };
 945                 dwc_otg_core_global_regs_t *global_regs;
 946                 global_regs = hcd->core_if->core_global_regs;
 947
 948                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
 949                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
 950                         /*
 951                          * Make sure the Non-periodic Tx FIFO empty interrupt
 952                          * is enabled so that the non-periodic schedule will
 953                          * be processed.
 954                          */
 955                         gintmsk.b.nptxfempty = 1;
 956                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
 957                 } else {
 958                         /*
 959                          * Move the QH from the periodic queued schedule to
 960                          * the periodic assigned schedule. This allows the
 961                          * halt to be queued when the periodic schedule is
 962                          * processed.
 963                          */
 964                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
 965                                            &hc->qh->qh_list_entry);
 966
 967                         /*
 968                          * Make sure the Periodic Tx FIFO Empty interrupt is
 969                          * enabled so that the periodic schedule will be
 970                          * processed.
 971                          */
 972                         gintmsk.b.ptxfempty = 1;
 973                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
 974                 }
 975         }
 976 }
 977
 978 /**
 979  * Performs common cleanup for non-periodic transfers after a Transfer
 980  * Complete interrupt. This function should be called after any endpoint type
 981  * specific handling is finished to release the host channel.
 982  */
 983 static void complete_non_periodic_xfer(dwc_otg_hcd_t *hcd,
 984                                        dwc_hc_t *hc,
 985                                        dwc_otg_hc_regs_t *hc_regs,
 986                                        dwc_otg_qtd_t *qtd,
 987                                        dwc_otg_halt_status_e halt_status)
 988 {
 989         hcint_data_t hcint;
 990
 991         qtd->error_count = 0;
 992
 993         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
 994         if (hcint.b.nyet) {
 995                 /*
 996                  * Got a NYET on the last transaction of the transfer. This
 997                  * means that the endpoint should be in the PING state at the
 998                  * beginning of the next transfer.
 999                  */
1000                 hc->qh->ping_state = 1;
1001                 clear_hc_int(hc_regs, nyet);
1002         }
1003
1004         /*
1005          * Always halt and release the host channel to make it available for
1006          * more transfers. There may still be more phases for a control
1007          * transfer or more data packets for a bulk transfer at this point,
1008          * but the host channel is still halted. A channel will be reassigned
1009          * to the transfer when the non-periodic schedule is processed after
1010          * the channel is released. This allows transactions to be queued
1011          * properly via dwc_otg_hcd_queue_transactions, which also enables the
1012          * Tx FIFO Empty interrupt if necessary.
1013          */
1014         if (hc->ep_is_in) {
1015                 /*
1016                  * IN transfers in Slave mode require an explicit disable to
1017                  * halt the channel. (In DMA mode, this call simply releases
1018                  * the channel.)
1019                  */
1020                 halt_channel(hcd, hc, qtd, halt_status);
1021         } else {
1022                 /*
1023                  * The channel is automatically disabled by the core for OUT
1024                  * transfers in Slave mode.
1025                  */
1026                 release_channel(hcd, hc, qtd, halt_status);
1027         }
1028 }
1029
1030 /**
1031  * Performs common cleanup for periodic transfers after a Transfer Complete
1032  * interrupt. This function should be called after any endpoint type specific
1033  * handling is finished to release the host channel.
1034  */
1035 static void complete_periodic_xfer(dwc_otg_hcd_t *hcd,
1036                                    dwc_hc_t *hc,
1037                                    dwc_otg_hc_regs_t *hc_regs,
1038                                    dwc_otg_qtd_t *qtd,
1039                                    dwc_otg_halt_status_e halt_status)
1040 {
1041         hctsiz_data_t hctsiz;
1042         qtd->error_count = 0;
1043
1044         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1045         if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
1046                 /* Core halts channel in these cases. */
1047                 release_channel(hcd, hc, qtd, halt_status);
1048         } else {
1049                 /* Flush any outstanding requests from the Tx queue. */
1050                 halt_channel(hcd, hc, qtd, halt_status);
1051         }
1052 }
1053
1054 static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t *hcd,
1055                                              dwc_hc_t *hc,
1056                                              dwc_otg_hc_regs_t *hc_regs,
1057                                              dwc_otg_qtd_t *qtd)
1058 {
1059         uint32_t len;
1060         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1061         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
1062
1063         len = get_actual_xfer_length(hc, hc_regs, qtd,
1064                                      DWC_OTG_HC_XFER_COMPLETE, NULL);
1065
1066         if (!len) {
1067                 qtd->complete_split = 0;
1068                 qtd->isoc_split_offset = 0;
1069                 return 0;
1070         }
1071         frame_desc->actual_length += len;
1072
1073         if (hc->align_buff && len)
1074                 dwc_memcpy(qtd->urb->buf + frame_desc->offset +
1075                            qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
1076         qtd->isoc_split_offset += len;
1077
1078         if (frame_desc->length == frame_desc->actual_length) {
1079                 frame_desc->status = 0;
1080                 qtd->isoc_frame_index++;
1081                 qtd->complete_split = 0;
1082                 qtd->isoc_split_offset = 0;
1083         }
1084
1085         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
1086                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
1087                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
1088         } else {
1089                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
1090         }
1091
1092         return 1;               /* Indicates that channel released */
1093 }
1094
1095 /**
1096  * Handles a host channel Transfer Complete interrupt. This handler may be
1097  * called in either DMA mode or Slave mode.
1098  */
1099 static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *hcd,
1100                                        dwc_hc_t *hc,
1101                                        dwc_otg_hc_regs_t *hc_regs,
1102                                        dwc_otg_qtd_t *qtd)
1103 {
1104         int urb_xfer_done;
1105         dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
1106         dwc_otg_hcd_urb_t *urb;
1107         int pipe_type;
1108
1109         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1110                     "Transfer Complete--\n", hc->hc_num);
1111
1112         if (!qtd) {
1113                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_DEQUEUE);
1114                 goto handle_xfercomp_done;
1115         }
1116
1117         urb = qtd->urb;
1118         if (!urb) {
1119                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_DEQUEUE);
1120                 goto handle_xfercomp_done;
1121         }
1122
1123         pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
1124
1125         if (hcd->core_if->dma_desc_enable) {
1126                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
1127                 if (pipe_type == UE_ISOCHRONOUS) {
1128                         /* Do not disable the interrupt, just clear it */
1129                         clear_hc_int(hc_regs, xfercomp);
1130                         return 1;
1131                 }
1132                 goto handle_xfercomp_done;
1133         }
1134
1135         /*
1136          * Handle xfer complete on CSPLIT.
1137          */
1138
1139         if (hc->qh->do_split) {
1140                 if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
1141                     && hcd->core_if->dma_enable) {
1142                         if (qtd->complete_split
1143                             && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
1144                                                              qtd))
1145                                 goto handle_xfercomp_done;
1146                 } else {
1147                         qtd->complete_split = 0;
1148                 }
1149         }
1150
1151         /* Update the QTD and URB states. */
1152         switch (pipe_type) {
1153         case UE_CONTROL:
1154                 switch (qtd->control_phase) {
1155                 case DWC_OTG_CONTROL_SETUP:
1156                         if (urb->length > 0) {
1157                                 qtd->control_phase = DWC_OTG_CONTROL_DATA;
1158                         } else {
1159                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
1160                         }
1161                         DWC_DEBUGPL(DBG_HCDV,
1162                                     "  Control setup transaction done\n");
1163                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1164                         break;
1165                 case DWC_OTG_CONTROL_DATA:{
1166                                 urb_xfer_done =
1167                                     update_urb_state_xfer_comp(hc, hc_regs, urb,
1168                                                                qtd);
1169                                 if (urb_xfer_done) {
1170                                         qtd->control_phase =
1171                                             DWC_OTG_CONTROL_STATUS;
1172                                         DWC_DEBUGPL(DBG_HCDV,
1173                                                     "  Control data transfer done\n");
1174                                 } else {
1175                                         dwc_otg_hcd_save_data_toggle(hc,
1176                                                                      hc_regs,
1177                                                                      qtd);
1178                                 }
1179                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1180                                 break;
1181                         }
1182                 case DWC_OTG_CONTROL_STATUS:
1183                         DWC_DEBUGPL(DBG_HCDV, "  Control transfer complete\n");
1184                         if (urb->status == -DWC_E_IN_PROGRESS) {
1185                                 urb->status = 0;
1186                         }
1187                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1188                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1189                         break;
1190                 }
1191
1192                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1193                 break;
1194         case UE_BULK:
1195                 DWC_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
1196                 urb_xfer_done =
1197                     update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1198                 if (urb_xfer_done) {
1199                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1200                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1201                 } else {
1202                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1203                 }
1204
1205                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1206                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1207                 break;
1208         case UE_INTERRUPT:
1209                 DWC_DEBUGPL(DBG_HCDV, "  Interrupt transfer complete\n");
1210                 urb_xfer_done =
1211                     update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1212
1213                 /*
1214                  * Interrupt URB is done on the first transfer complete
1215                  * interrupt.
1216                  */
1217                 if (urb_xfer_done) {
1218                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1219                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1220                 } else {
1221                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1222                 }
1223
1224                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1225                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1226                 break;
1227         case UE_ISOCHRONOUS:
1228                 DWC_DEBUGPL(DBG_HCDV, "  Isochronous transfer complete\n");
1229                 if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1230                         halt_status =
1231                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1232                                                   DWC_OTG_HC_XFER_COMPLETE);
1233                 }
1234                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1235                 break;
1236         }
1237
1238 handle_xfercomp_done:
1239         disable_hc_int(hc_regs, xfercompl);
1240
1241         return 1;
1242 }
1243
1244 /**
1245  * Handles a host channel STALL interrupt. This handler may be called in
1246  * either DMA mode or Slave mode.
1247  */
1248 static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *hcd,
1249                                     dwc_hc_t *hc,
1250                                     dwc_otg_hc_regs_t *hc_regs,
1251                                     dwc_otg_qtd_t *qtd)
1252 {
1253         dwc_otg_hcd_urb_t *urb = qtd->urb;
1254         int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
1255
1256         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1257                     "STALL Received--\n", hc->hc_num);
1258
1259         if (hcd->core_if->dma_desc_enable) {
1260                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1261                                                DWC_OTG_HC_XFER_STALL);
1262                 goto handle_stall_done;
1263         }
1264
1265         if (pipe_type == UE_CONTROL) {
1266                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
1267         }
1268
1269         if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
1270                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
1271                 /*
1272                  * USB protocol requires resetting the data toggle for bulk
1273                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1274                  * setup command is issued to the endpoint. Anticipate the
1275                  * CLEAR_FEATURE command since a STALL has occurred and reset
1276                  * the data toggle now.
1277                  */
1278                 hc->qh->data_toggle = 0;
1279         }
1280
1281         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
1282
1283 handle_stall_done:
1284         disable_hc_int(hc_regs, stall);
1285
1286         return 1;
1287 }
1288
1289 /*
1290  * Updates the state of the URB when a transfer has been stopped due to an
1291  * abnormal condition before the transfer completes. Modifies the
1292  * actual_length field of the URB to reflect the number of bytes that have
1293  * actually been transferred via the host channel.
1294  */
1295 static void update_urb_state_xfer_intr(dwc_hc_t *hc,
1296                                        dwc_otg_hc_regs_t *hc_regs,
1297                                        dwc_otg_hcd_urb_t *urb,
1298                                        dwc_otg_qtd_t *qtd,
1299                                        dwc_otg_halt_status_e halt_status)
1300 {
1301         uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
1302                                                             halt_status, NULL);
1303         /* non DWORD-aligned buffer case handling. */
1304         if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
1305                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
1306                            bytes_transferred);
1307         }
1308
1309         urb->actual_length += bytes_transferred;
1310
1311 #ifdef DEBUG
1312         {
1313                 hctsiz_data_t hctsiz;
1314                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1315                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
1316                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
1317                             hc->hc_num);
1318                 DWC_DEBUGPL(DBG_HCDV, "  hc->start_pkt_count %d\n",
1319                             hc->start_pkt_count);
1320                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
1321                 DWC_DEBUGPL(DBG_HCDV, "  hc->max_packet %d\n", hc->max_packet);
1322                 DWC_DEBUGPL(DBG_HCDV, "  bytes_transferred %d\n",
1323                             bytes_transferred);
1324                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
1325                             urb->actual_length);
1326                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
1327                             urb->length);
1328         }
1329 #endif
1330 }
1331
1332 /**
1333  * Handles a host channel NAK interrupt. This handler may be called in either
1334  * DMA mode or Slave mode.
1335  */
1336 static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *hcd,
1337                                   dwc_hc_t *hc,
1338                                   dwc_otg_hc_regs_t *hc_regs,
1339                                   dwc_otg_qtd_t *qtd)
1340 {
1341         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1342                     "NAK Received--\n", hc->hc_num);
1343
1344         /*
1345          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1346          * interrupt.  Re-start the SSPLIT transfer.
1347          */
1348         if (hc->do_split) {
1349                 if (hc->complete_split) {
1350                         qtd->error_count = 0;
1351                 }
1352                 hc->csplit_nak = 1;
1353                 qtd->complete_split = 0;
1354                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1355                 goto handle_nak_done;
1356         }
1357
1358         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1359         case UE_CONTROL:
1360         case UE_BULK:
1361                 if (hcd->core_if->dma_enable && hc->ep_is_in) {
1362                         /*
1363                          * NAK interrupts are enabled on bulk/control IN
1364                          * transfers in DMA mode for the sole purpose of
1365                          * resetting the error count after a transaction error
1366                          * occurs. The core will continue transferring data.
1367                          */
1368                         qtd->error_count = 0;
1369                         goto handle_nak_done;
1370                 }
1371
1372                 /*
1373                  * NAK interrupts normally occur during OUT transfers in DMA
1374                  * or Slave mode. For IN transfers, more requests will be
1375                  * queued as request queue space is available.
1376                  */
1377                 qtd->error_count = 0;
1378
1379                 if (!hc->qh->ping_state) {
1380                         update_urb_state_xfer_intr(hc, hc_regs,
1381                                                    qtd->urb, qtd,
1382                                                    DWC_OTG_HC_XFER_NAK);
1383                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1384
1385                         if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
1386                                 hc->qh->ping_state = 1;
1387                 }
1388
1389                 /*
1390                  * Halt the channel so the transfer can be re-started from
1391                  * the appropriate point or the PING protocol will
1392                  * start/continue.
1393                  */
1394                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1395                 break;
1396         case UE_INTERRUPT:
1397                 qtd->error_count = 0;
1398                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1399                 break;
1400         case UE_ISOCHRONOUS:
1401                 /* Should never get called for isochronous transfers. */
1402                 DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
1403                 break;
1404         }
1405
1406 handle_nak_done:
1407         disable_hc_int(hc_regs, nak);
1408
1409         return 1;
1410 }
1411
1412 /**
1413  * Handles a host channel ACK interrupt. This interrupt is enabled when
1414  * performing the PING protocol in Slave mode, when errors occur during
1415  * either Slave mode or DMA mode, and during Start Split transactions.
1416  */
1417 static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *hcd,
1418                                   dwc_hc_t *hc,
1419                                   dwc_otg_hc_regs_t *hc_regs,
1420                                   dwc_otg_qtd_t *qtd)
1421 {
1422         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1423                     "ACK Received--\n", hc->hc_num);
1424
1425         if (hc->do_split) {
1426                 /*
1427                  * Handle ACK on SSPLIT.
1428                  * ACK should not occur in CSPLIT.
1429                  */
1430                 if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
1431                         qtd->ssplit_out_xfer_count = hc->xfer_len;
1432                 }
1433                 if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
1434                         /* Don't need complete for isochronous out transfers. */
1435                         qtd->complete_split = 1;
1436                 }
1437
1438                 /* ISOC OUT */
1439                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1440                         switch (hc->xact_pos) {
1441                         case DWC_HCSPLIT_XACTPOS_ALL:
1442                                 break;
1443                         case DWC_HCSPLIT_XACTPOS_END:
1444                                 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
1445                                 qtd->isoc_split_offset = 0;
1446                                 break;
1447                         case DWC_HCSPLIT_XACTPOS_BEGIN:
1448                         case DWC_HCSPLIT_XACTPOS_MID:
1449                                 /*
1450                                  * For BEGIN or MID, calculate the length for
1451                                  * the next microframe to determine the correct
1452                                  * SSPLIT token, either MID or END.
1453                                  */
1454                                 {
1455                                         struct dwc_otg_hcd_iso_packet_desc
1456                                         *frame_desc;
1457
1458                                         frame_desc =
1459                                             &qtd->urb->iso_descs[qtd->
1460                                                                  isoc_frame_index];
1461                                         qtd->isoc_split_offset += 188;
1462
1463                                         if ((frame_desc->length -
1464                                              qtd->isoc_split_offset) <= 188) {
1465                                                 qtd->isoc_split_pos =
1466                                                     DWC_HCSPLIT_XACTPOS_END;
1467                                         } else {
1468                                                 qtd->isoc_split_pos =
1469                                                     DWC_HCSPLIT_XACTPOS_MID;
1470                                         }
1471
1472                                 }
1473                                 break;
1474                         }
1475                 } else {
1476                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1477                 }
1478         } else {
1479                 qtd->error_count = 0;
1480
1481                 if (hc->qh->ping_state) {
1482                         hc->qh->ping_state = 0;
1483                         /*
1484                          * Halt the channel so the transfer can be re-started
1485                          * from the appropriate point. This only happens in
1486                          * Slave mode. In DMA mode, the ping_state is cleared
1487                          * when the transfer is started because the core
1488                          * automatically executes the PING, then the transfer.
1489                          */
1490                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1491                 }
1492         }
1493
1494         /*
1495          * If the ACK occurred when _not_ in the PING state, let the channel
1496          * continue transferring data after clearing the error count.
1497          */
1498
1499         disable_hc_int(hc_regs, ack);
1500
1501         return 1;
1502 }
1503
1504 /**
1505  * Handles a host channel NYET interrupt. This interrupt should only occur on
1506  * Bulk and Control OUT endpoints and for complete split transactions. If a
1507  * NYET occurs at the same time as a Transfer Complete interrupt, it is
1508  * handled in the xfercomp interrupt handler, not here. This handler may be
1509  * called in either DMA mode or Slave mode.
1510  */
1511 static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *hcd,
1512                                    dwc_hc_t *hc,
1513                                    dwc_otg_hc_regs_t *hc_regs,
1514                                    dwc_otg_qtd_t *qtd)
1515 {
1516         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1517                     "NYET Received--\n", hc->hc_num);
1518
1519         /*
1520          * NYET on CSPLIT
1521          * re-do the CSPLIT immediately on non-periodic
1522          */
1523         if (hc->do_split && hc->complete_split) {
1524                 if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
1525                     && hcd->core_if->dma_enable) {
1526                         qtd->complete_split = 0;
1527                         qtd->isoc_split_offset = 0;
1528                         if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
1529                                 hcd->fops->complete(hcd, qtd->urb->priv,
1530                                                     qtd->urb, 0);
1531                                 release_channel(hcd, hc, qtd,
1532                                                 DWC_OTG_HC_XFER_URB_COMPLETE);
1533                         } else
1534                                 release_channel(hcd, hc, qtd,
1535                                                 DWC_OTG_HC_XFER_NO_HALT_STATUS);
1536                         goto handle_nyet_done;
1537                 }
1538
1539                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1540                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1541                         int frnum = dwc_otg_hcd_get_frame_number(hcd);
1542
1543                         if (dwc_full_frame_num(frnum) !=
1544                             dwc_full_frame_num(hc->qh->sched_frame)) {
1545                                 /*
1546                                  * No longer in the same full speed frame.
1547                                  * Treat this as a transaction error.
1548                                  */
1549 #if 0
1550                                 /** @todo Fix system performance so this can
1551                                  * be treated as an error. Right now complete
1552                                  * splits cannot be scheduled precisely enough
1553                                  * due to other system activity, so this error
1554                                  * occurs regularly in Slave mode.
1555                                  */
1556                                 qtd->error_count++;
1557 #endif
1558                                 qtd->complete_split = 0;
1559                                 halt_channel(hcd, hc, qtd,
1560                                              DWC_OTG_HC_XFER_XACT_ERR);
1561                                 /** @todo add support for isoc release */
1562                                 goto handle_nyet_done;
1563                         }
1564                 }
1565
1566                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1567                 goto handle_nyet_done;
1568         }
1569
1570         hc->qh->ping_state = 1;
1571         qtd->error_count = 0;
1572
1573         update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
1574                                    DWC_OTG_HC_XFER_NYET);
1575         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1576
1577         /*
1578          * Halt the channel and re-start the transfer so the PING
1579          * protocol will start.
1580          */
1581         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1582
1583 handle_nyet_done:
1584         disable_hc_int(hc_regs, nyet);
1585         return 1;
1586 }
1587
1588 /**
1589  * Handles a host channel babble interrupt. This handler may be called in
1590  * either DMA mode or Slave mode.
1591  */
1592 static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *hcd,
1593                                      dwc_hc_t *hc,
1594                                      dwc_otg_hc_regs_t *hc_regs,
1595                                      dwc_otg_qtd_t *qtd)
1596 {
1597         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1598                     "Babble Error--\n", hc->hc_num);
1599
1600         if (hcd->core_if->dma_desc_enable) {
1601                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1602                                                DWC_OTG_HC_XFER_BABBLE_ERR);
1603                 goto handle_babble_done;
1604         }
1605
1606         if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1607                 hcd->fops->complete(hcd, qtd->urb->priv,
1608                                     qtd->urb, -DWC_E_OVERFLOW);
1609                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
1610         } else {
1611                 dwc_otg_halt_status_e halt_status;
1612                 halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1613                                                     DWC_OTG_HC_XFER_BABBLE_ERR);
1614                 halt_channel(hcd, hc, qtd, halt_status);
1615         }
1616
1617 handle_babble_done:
1618         disable_hc_int(hc_regs, bblerr);
1619         return 1;
1620 }
1621
1622 /**
1623  * Handles a host channel AHB error interrupt. This handler is only called in
1624  * DMA mode.
1625  */
1626 static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *hcd,
1627                                      dwc_hc_t *hc,
1628                                      dwc_otg_hc_regs_t *hc_regs,
1629                                      dwc_otg_qtd_t *qtd)
1630 {
1631         hcchar_data_t hcchar;
1632         hcsplt_data_t hcsplt;
1633         hctsiz_data_t hctsiz;
1634         uint32_t hcdma;
1635         char *pipetype, *speed;
1636
1637         dwc_otg_hcd_urb_t *urb = qtd->urb;
1638
1639         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1640                     "AHB Error--\n", hc->hc_num);
1641
1642         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1643         hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
1644         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1645         hcdma = DWC_READ_REG32(&hc_regs->hcdma);
1646
1647         DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
1648         DWC_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1649         DWC_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1650         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
1651         DWC_ERROR("  Device address: %d\n",
1652                   dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
1653         DWC_ERROR("  Endpoint: %d, %s\n",
1654                   dwc_otg_hcd_get_ep_num(&urb->pipe_info),
1655                   (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
1656
1657         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1658         case UE_CONTROL:
1659                 pipetype = "CONTROL";
1660                 break;
1661         case UE_BULK:
1662                 pipetype = "BULK";
1663                 break;
1664         case UE_INTERRUPT:
1665                 pipetype = "INTERRUPT";
1666                 break;
1667         case UE_ISOCHRONOUS:
1668                 pipetype = "ISOCHRONOUS";
1669                 break;
1670         default:
1671                 pipetype = "UNKNOWN";
1672                 break;
1673         }
1674
1675         DWC_ERROR("  Endpoint type: %s\n", pipetype);
1676
1677         switch (hc->speed) {
1678         case DWC_OTG_EP_SPEED_HIGH:
1679                 speed = "HIGH";
1680                 break;
1681         case DWC_OTG_EP_SPEED_FULL:
1682                 speed = "FULL";
1683                 break;
1684         case DWC_OTG_EP_SPEED_LOW:
1685                 speed = "LOW";
1686                 break;
1687         default:
1688                 speed = "UNKNOWN";
1689                 break;
1690         };
1691
1692         DWC_ERROR("  Speed: %s\n", speed);
1693
1694         DWC_ERROR("  Max packet size: %d\n",
1695                   dwc_otg_hcd_get_mps(&urb->pipe_info));
1696         DWC_ERROR("  Data buffer length: %d\n", urb->length);
1697         DWC_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
1698                   urb->buf, (void *)urb->dma);
1699         DWC_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
1700                   urb->setup_packet, (void *)urb->setup_dma);
1701         DWC_ERROR("  Interval: %d\n", urb->interval);
1702
1703         /* Core haltes the channel for Descriptor DMA mode */
1704         if (hcd->core_if->dma_desc_enable) {
1705                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1706                                                DWC_OTG_HC_XFER_AHB_ERR);
1707                 goto handle_ahberr_done;
1708         }
1709
1710         hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
1711
1712         /*
1713          * Force a channel halt. Don't call halt_channel because that won't
1714          * write to the HCCHARn register in DMA mode to force the halt.
1715          */
1716         dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
1717 handle_ahberr_done:
1718         disable_hc_int(hc_regs, ahberr);
1719         return 1;
1720 }
1721
1722 /**
1723  * Handles a host channel transaction error interrupt. This handler may be
1724  * called in either DMA mode or Slave mode.
1725  */
1726 static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *hcd,
1727                                       dwc_hc_t *hc,
1728                                       dwc_otg_hc_regs_t *hc_regs,
1729                                       dwc_otg_qtd_t *qtd)
1730 {
1731         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1732                     "Transaction Error--\n", hc->hc_num);
1733
1734         if (hcd->core_if->dma_desc_enable) {
1735                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1736                                                DWC_OTG_HC_XFER_XACT_ERR);
1737                 goto handle_xacterr_done;
1738         }
1739
1740         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1741         case UE_CONTROL:
1742         case UE_BULK:
1743                 qtd->error_count++;
1744                 if (!hc->qh->ping_state) {
1745
1746                         update_urb_state_xfer_intr(hc, hc_regs,
1747                                                    qtd->urb, qtd,
1748                                                    DWC_OTG_HC_XFER_XACT_ERR);
1749                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1750                         if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
1751                                 hc->qh->ping_state = 1;
1752                         }
1753                 }
1754
1755                 /*
1756                  * Halt the channel so the transfer can be re-started from
1757                  * the appropriate point or the PING protocol will start.
1758                  */
1759                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1760                 break;
1761         case UE_INTERRUPT:
1762                 qtd->error_count++;
1763                 if (hc->do_split && hc->complete_split) {
1764                         qtd->complete_split = 0;
1765                 }
1766                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1767                 break;
1768         case UE_ISOCHRONOUS:
1769                 {
1770                         dwc_otg_halt_status_e halt_status;
1771                         halt_status =
1772                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1773                                                   DWC_OTG_HC_XFER_XACT_ERR);
1774
1775                         halt_channel(hcd, hc, qtd, halt_status);
1776                 }
1777                 break;
1778         }
1779 handle_xacterr_done:
1780         disable_hc_int(hc_regs, xacterr);
1781
1782         return 1;
1783 }
1784
1785 /**
1786  * Handles a host channel frame overrun interrupt. This handler may be called
1787  * in either DMA mode or Slave mode.
1788  */
1789 static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *hcd,
1790                                        dwc_hc_t *hc,
1791                                        dwc_otg_hc_regs_t *hc_regs,
1792                                        dwc_otg_qtd_t *qtd)
1793 {
1794         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1795                     "Frame Overrun--\n", hc->hc_num);
1796
1797         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1798         case UE_CONTROL:
1799         case UE_BULK:
1800                 break;
1801         case UE_INTERRUPT:
1802                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
1803                 break;
1804         case UE_ISOCHRONOUS:
1805                 {
1806                         dwc_otg_halt_status_e halt_status;
1807                         halt_status =
1808                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1809                                                   DWC_OTG_HC_XFER_FRAME_OVERRUN);
1810
1811                         halt_channel(hcd, hc, qtd, halt_status);
1812                 }
1813                 break;
1814         }
1815
1816         disable_hc_int(hc_regs, frmovrun);
1817
1818         return 1;
1819 }
1820
1821 /**
1822  * Handles a host channel data toggle error interrupt. This handler may be
1823  * called in either DMA mode or Slave mode.
1824  */
1825 static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *hcd,
1826                                          dwc_hc_t *hc,
1827                                          dwc_otg_hc_regs_t *hc_regs,
1828                                          dwc_otg_qtd_t *qtd)
1829 {
1830         DWC_ERROR("--Host Channel %d Interrupt: "
1831                   "Data Toggle Error--\n", hc->hc_num);
1832         if (!hcd->flags.b.port_connect_status) {
1833                 /* No longer connected. */
1834                 DWC_ERROR("Not connected\n");
1835                 return 1;
1836         }
1837         if (hc->ep_is_in) {
1838                 qtd->error_count += 3;  /* Complete the error URB immediately */
1839         } else {
1840                 DWC_ERROR("Data Toggle Error on OUT transfer,"
1841                           "channel %d\n", hc->hc_num);
1842         }
1843         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1844         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1845         clear_hc_int(hc_regs, chhltd);
1846
1847         return 1;
1848 }
1849
1850 #ifdef DEBUG
1851 /**
1852  * This function is for debug only. It checks that a valid halt status is set
1853  * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
1854  * taken and a warning is issued.
1855  * @return 1 if halt status is ok, 0 otherwise.
1856  */
1857 static inline int halt_status_ok(dwc_otg_hcd_t *hcd,
1858                                  dwc_hc_t *hc,
1859                                  dwc_otg_hc_regs_t *hc_regs,
1860                                  dwc_otg_qtd_t *qtd)
1861 {
1862         hcchar_data_t hcchar;
1863         hctsiz_data_t hctsiz;
1864         hcint_data_t hcint;
1865         hcintmsk_data_t hcintmsk;
1866         hcsplt_data_t hcsplt;
1867
1868         if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
1869                 /*
1870                  * This code is here only as a check. This condition should
1871                  * never happen. Ignore the halt if it does occur.
1872                  */
1873                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1874                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1875                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1876                 hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
1877                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
1878                 DWC_WARN
1879                     ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
1880                      "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
1881                      "hcint 0x%08x, hcintmsk 0x%08x, "
1882                      "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
1883                      hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
1884                      hcintmsk.d32, hcsplt.d32, qtd->complete_split);
1885
1886                 DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
1887                          __func__, hc->hc_num);
1888                 DWC_WARN("\n");
1889                 clear_hc_int(hc_regs, chhltd);
1890                 return 0;
1891         }
1892
1893         /*
1894          * This code is here only as a check. hcchar.chdis should
1895          * never be set when the halt interrupt occurs. Halt the
1896          * channel again if it does occur.
1897          */
1898         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1899         if (hcchar.b.chdis) {
1900                 DWC_WARN("%s: hcchar.chdis set unexpectedly, "
1901                          "hcchar 0x%08x, trying to halt again\n",
1902                          __func__, hcchar.d32);
1903                 clear_hc_int(hc_regs, chhltd);
1904                 hc->halt_pending = 0;
1905                 halt_channel(hcd, hc, qtd, hc->halt_status);
1906                 return 0;
1907         }
1908
1909         return 1;
1910 }
1911 #endif
1912
1913 /**
1914  * Handles a host Channel Halted interrupt in DMA mode. This handler
1915  * determines the reason the channel halted and proceeds accordingly.
1916  */
1917 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd,
1918                                       dwc_hc_t *hc,
1919                                       dwc_otg_hc_regs_t *hc_regs,
1920                                       dwc_otg_qtd_t *qtd)
1921 {
1922         hcint_data_t hcint;
1923         hcintmsk_data_t hcintmsk;
1924         int out_nak_enh = 0;
1925
1926         /* For core with OUT NAK enhancement, the flow for high-
1927          * speed CONTROL/BULK OUT is handled a little differently.
1928          */
1929         if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
1930                 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
1931                     (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
1932                      hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
1933                         out_nak_enh = 1;
1934                 }
1935         }
1936
1937         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
1938             (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
1939              && !hcd->core_if->dma_desc_enable)) {
1940                 /*
1941                  * Just release the channel. A dequeue can happen on a
1942                  * transfer timeout. In the case of an AHB Error, the channel
1943                  * was forced to halt because there's no way to gracefully
1944                  * recover.
1945                  */
1946                 if (hcd->core_if->dma_desc_enable)
1947                         dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1948                                                        hc->halt_status);
1949                 else
1950                         release_channel(hcd, hc, qtd, hc->halt_status);
1951                 return;
1952         }
1953
1954         /* Read the HCINTn register to determine the cause for the halt. */
1955         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1956         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
1957
1958         if (hcint.b.xfercomp) {
1959                 /** @todo This is here because of a possible hardware bug.  Spec
1960                  * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1961                  * interrupt w/ACK bit set should occur, but I only see the
1962                  * XFERCOMP bit, even with it masked out.  This is a workaround
1963                  * for that behavior.  Should fix this when hardware is fixed.
1964                  */
1965                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1966                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1967                 }
1968                 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
1969         } else if (hcint.b.stall) {
1970                 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
1971         } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
1972                 if (out_nak_enh) {
1973                         if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
1974                                 DWC_DEBUG("XactErr with NYET/NAK/ACK\n");
1975                                 qtd->error_count = 0;
1976                         } else {
1977                                 DWC_DEBUG("XactErr without NYET/NAK/ACK\n");
1978                         }
1979                 }
1980
1981                 /*
1982                  * Must handle xacterr before nak or ack. Could get a xacterr
1983                  * at the same time as either of these on a BULK/CONTROL OUT
1984                  * that started with a PING. The xacterr takes precedence.
1985                  */
1986                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1987         } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
1988                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1989         } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
1990                 handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
1991         } else if (hcint.b.bblerr) {
1992                 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
1993         } else if (hcint.b.frmovrun) {
1994                 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
1995         } else if (hcint.b.datatglerr) {
1996                 handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
1997         } else if (!out_nak_enh) {
1998                 if (hcint.b.nyet) {
1999                         /*
2000                          * Must handle nyet before nak or ack. Could get a nyet at the
2001                          * same time as either of those on a BULK/CONTROL OUT that
2002                          * started with a PING. The nyet takes precedence.
2003                          */
2004                         handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
2005                 } else if (hcint.b.nak && !hcintmsk.b.nak) {
2006                         /*
2007                          * If nak is not masked, it's because a non-split IN transfer
2008                          * is in an error state. In that case, the nak is handled by
2009                          * the nak interrupt handler, not here. Handle nak here for
2010                          * BULK/CONTROL OUT transfers, which halt on a NAK to allow
2011                          * rewinding the buffer pointer.
2012                          */
2013                         handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
2014                 } else if (hcint.b.ack && !hcintmsk.b.ack) {
2015                         /*
2016                          * If ack is not masked, it's because a non-split IN transfer
2017                          * is in an error state. In that case, the ack is handled by
2018                          * the ack interrupt handler, not here. Handle ack here for
2019                          * split transfers. Start splits halt on ACK.
2020                          */
2021                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
2022                 } else {
2023                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2024                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2025                                 /*
2026                                  * A periodic transfer halted with no other channel
2027                                  * interrupts set. Assume it was halted by the core
2028                                  * because it could not be completed in its scheduled
2029                                  * (micro)frame.
2030                                  */
2031 #ifdef DEBUG
2032                                 DWC_PRINTF
2033                                     ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
2034                                      __func__, hc->hc_num);
2035 #endif
2036                                 halt_channel(hcd, hc, qtd,
2037                                              DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
2038                         } else {
2039                                 DWC_ERROR
2040                                     ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
2041                                      "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
2042                                      __func__, hc->hc_num, hcint.d32,
2043                                      DWC_READ_REG32(&hcd->core_if->
2044                                                     core_global_regs->gintsts));
2045                                 clear_hc_int(hc_regs, chhltd);
2046                         }
2047
2048                 }
2049         } else {
2050                 DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
2051                            hcint.d32);
2052                 if (!hcint.b.nyet && !hcint.b.nak && !hcint.b.ack)
2053                         clear_hc_int(hc_regs, chhltd);
2054         }
2055 }
2056
2057 /**
2058  * Handles a host channel Channel Halted interrupt.
2059  *
2060  * In slave mode, this handler is called only when the driver specifically
2061  * requests a halt. This occurs during handling other host channel interrupts
2062  * (e.g. nak, xacterr, stall, nyet, etc.).
2063  *
2064  * In DMA mode, this is the interrupt that occurs when the core has finished
2065  * processing a transfer on a channel. Other host channel interrupts (except
2066  * ahberr) are disabled in DMA mode.
2067  */
2068 static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *hcd,
2069                                      dwc_hc_t *hc,
2070                                      dwc_otg_hc_regs_t *hc_regs,
2071                                      dwc_otg_qtd_t *qtd)
2072 {
2073         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
2074                     "Channel Halted--\n", hc->hc_num);
2075
2076         if (hcd->core_if->dma_enable) {
2077                 handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
2078         } else {
2079 #ifdef DEBUG
2080                 if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
2081                         return 1;
2082                 }
2083 #endif
2084                 release_channel(hcd, hc, qtd, hc->halt_status);
2085         }
2086
2087         return 1;
2088 }
2089
2090 /** Handles interrupt for a specific Host Channel */
2091 int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
2092 {
2093         int retval = 0;
2094         hcint_data_t hcint;
2095         hcintmsk_data_t hcintmsk;
2096         dwc_hc_t *hc;
2097         dwc_otg_hc_regs_t *hc_regs;
2098         dwc_otg_qtd_t *qtd;
2099
2100         DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
2101
2102         hc = dwc_otg_hcd->hc_ptr_array[num];
2103         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
2104         qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
2105
2106         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2107         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
2108         DWC_DEBUGPL(DBG_HCDV,
2109                     "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2110                     hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
2111         hcint.d32 = hcint.d32 & hcintmsk.d32;
2112
2113         if (!dwc_otg_hcd->core_if->dma_enable) {
2114                 if (hcint.b.chhltd && hcint.d32 != 0x2) {
2115                         hcint.b.chhltd = 0;
2116                 }
2117         }
2118
2119         if (hcint.b.chhltd) {
2120                 retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2121         }
2122         if (hcint.b.xfercomp) {
2123                 retval |=
2124                     handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2125                 /*
2126                  * If NYET occurred at same time as Xfer Complete, the NYET is
2127                  * handled by the Xfer Complete interrupt handler. Don't want
2128                  * to call the NYET interrupt handler in this case.
2129                  */
2130                 hcint.b.nyet = 0;
2131         }
2132         if (hcint.b.ahberr) {
2133                 retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2134         }
2135         if (hcint.b.stall) {
2136                 retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2137         }
2138         if (hcint.b.nak) {
2139                 retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2140         }
2141         if (hcint.b.ack) {
2142                 if (!hcint.b.chhltd)
2143                         retval |=
2144                             handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2145         }
2146         if (hcint.b.nyet) {
2147                 retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2148         }
2149         if (hcint.b.xacterr) {
2150                 retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2151         }
2152         if (hcint.b.bblerr) {
2153                 retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2154         }
2155         if (hcint.b.frmovrun) {
2156                 retval |=
2157                     handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2158         }
2159         if (hcint.b.datatglerr) {
2160                 disable_hc_int(hc_regs, datatglerr);
2161                 clear_hc_int(hc_regs, chhltd);
2162         }
2163
2164         return retval;
2165 }
2166
2167 #endif /* DWC_DEVICE_ONLY */