1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
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19 * below, then you are not authorized to use the Software.
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22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
38 * This file contains the functions to manage Queue Heads and Queue
39 * Transfer Descriptors.
42 #include "dwc_otg_hcd.h"
43 #include "dwc_otg_regs.h"
46 * Free each QTD in the QH's QTD-list then free the QH. QH should already be
47 * removed from a list. QTD list should already be empty if called from URB
50 * @param hcd HCD instance.
51 * @param qh The QH to free.
53 void dwc_otg_hcd_qh_free(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
55 dwc_otg_qtd_t *qtd, *qtd_tmp;
58 /* Free each QTD in the QTD list */
59 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
60 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
61 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
64 if (hcd->core_if->dma_desc_enable) {
65 dwc_otg_hcd_qh_free_ddma(hcd, qh);
66 } else if (qh->dw_align_buf) {
68 if (qh->ep_type == UE_ISOCHRONOUS) {
71 buf_size = hcd->core_if->core_params->max_transfer_size;
73 DWC_DMA_FREE(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma);
77 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
81 #define BitStuffTime(bytecount) ((8*7*bytecount) / 6)
82 #define HS_HOST_DELAY 5 /* nanoseconds */
83 #define FS_LS_HOST_DELAY 1000 /* nanoseconds */
84 #define HUB_LS_SETUP 333 /* nanoseconds */
85 #define NS_TO_US(ns) ((ns + 500) / 1000)
86 /* convert & round nanoseconds to microseconds */
88 static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount)
97 (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
102 (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
109 (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
111 retval = 7268 + FS_LS_HOST_DELAY + retval;
113 retval = 6265 + FS_LS_HOST_DELAY + retval;
117 (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
118 retval = 9107 + FS_LS_HOST_DELAY + retval;
124 (67667 * (31 + 10 * BitStuffTime(bytecount))) /
127 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
131 (66700 * (31 + 10 * BitStuffTime(bytecount))) /
134 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
139 DWC_WARN("Unknown device speed\n");
143 return NS_TO_US(retval);
147 * Initializes a QH structure.
149 * @param hcd The HCD state structure for the DWC OTG controller.
150 * @param qh The QH to init.
151 * @param urb Holds the information about the device/endpoint that we need
152 * to initialize the QH.
154 #define SCHEDULE_SLOP 10
155 void qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_hcd_urb_t *urb)
159 uint32_t hub_addr, hub_port;
161 dwc_memset(qh, 0, sizeof(dwc_otg_qh_t));
164 qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
165 qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
167 qh->data_toggle = DWC_OTG_HC_PID_DATA0;
168 qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info);
169 DWC_CIRCLEQ_INIT(&qh->qtd_list);
170 DWC_LIST_INIT(&qh->qh_list_entry);
173 /* FS/LS Enpoint on HS Hub
174 * NOT virtual root hub */
175 dev_speed = hcd->fops->speed(hcd, urb->priv);
177 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port);
180 if (((dev_speed == USB_SPEED_LOW) ||
181 (dev_speed == USB_SPEED_FULL)) &&
182 (hub_addr != 0 && hub_addr != 1)) {
184 "QH init: EP %d: TT found at hub addr %d, for port %d\n",
185 dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr,
190 if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) {
191 /* Compute scheduling parameters once and save them. */
194 /** @todo Account for split transfers in the bus time. */
196 dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
199 calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed),
200 qh->ep_is_in, (qh->ep_type == UE_ISOCHRONOUS),
202 /* Start in a slightly future (micro)frame. */
203 qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
205 qh->interval = urb->interval;
208 /* Increase interrupt polling rate for debugging. */
209 if (qh->ep_type == UE_INTERRUPT) {
213 hprt.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
214 if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
215 ((dev_speed == USB_SPEED_LOW) ||
216 (dev_speed == USB_SPEED_FULL))) {
218 qh->sched_frame |= 0x7;
219 qh->start_split_frame = qh->sched_frame;
224 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
225 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh);
226 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
227 dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
228 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
229 dwc_otg_hcd_get_ep_num(&urb->pipe_info),
230 dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
233 qh->dev_speed = DWC_OTG_EP_SPEED_LOW;
237 qh->dev_speed = DWC_OTG_EP_SPEED_FULL;
241 qh->dev_speed = DWC_OTG_EP_SPEED_HIGH;
248 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed);
250 switch (qh->ep_type) {
252 type = "isochronous";
268 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n", type);
271 if (qh->ep_type == UE_INTERRUPT) {
272 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
274 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
282 * This function allocates and initializes a QH.
284 * @param hcd The HCD state structure for the DWC OTG controller.
285 * @param urb Holds the information about the device/endpoint that we need
286 * to initialize the QH.
287 * @param atomic_alloc Flag to do atomic allocation if needed
289 * @return Returns pointer to the newly allocated QH, or NULL on error. */
290 dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t *hcd,
291 dwc_otg_hcd_urb_t *urb, int atomic_alloc)
295 /* Allocate memory */
296 /** @todo add memflags argument */
297 qh = dwc_otg_hcd_qh_alloc(atomic_alloc);
299 DWC_ERROR("qh allocation failed");
303 qh_init(hcd, qh, urb);
305 if (hcd->core_if->dma_desc_enable
306 && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) {
307 dwc_otg_hcd_qh_free(hcd, qh);
315 * Checks that a channel is available for a periodic transfer.
317 * @return 0 if successful, negative error code otherise.
319 static int periodic_channel_available(dwc_otg_hcd_t *hcd)
322 * Currently assuming that there is a dedicated host channnel for each
323 * periodic transaction plus at least one host channel for
324 * non-periodic transactions.
329 num_channels = hcd->core_if->core_params->host_channels;
330 if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels)
331 && (hcd->periodic_channels < num_channels - 1)) {
334 DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
335 __func__, num_channels, hcd->periodic_channels,
336 hcd->non_periodic_channels);
337 status = -DWC_E_NO_SPACE;
344 * Checks that there is sufficient bandwidth for the specified QH in the
345 * periodic schedule. For simplicity, this calculation assumes that all the
346 * transfers in the periodic schedule may occur in the same (micro)frame.
348 * @param hcd The HCD state structure for the DWC OTG controller.
349 * @param qh QH containing periodic bandwidth required.
351 * @return 0 if successful, negative error code otherwise.
353 static int check_periodic_bandwidth(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
356 int16_t max_claimed_usecs;
360 if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) {
363 * Max periodic usecs is 80% x 125 usec = 100 usec.
366 max_claimed_usecs = 100 - qh->usecs;
370 * Max periodic usecs is 90% x 1000 usec = 900 usec.
372 max_claimed_usecs = 900 - qh->usecs;
375 if (hcd->periodic_usecs > max_claimed_usecs) {
376 DWC_INFO("%s: already claimed usecs %d, required usecs %d\n",
377 __func__, hcd->periodic_usecs, qh->usecs);
378 status = -DWC_E_NO_SPACE;
385 * Checks that the max transfer size allowed in a host channel is large enough
386 * to handle the maximum data transfer in a single (micro)frame for a periodic
389 * @param hcd The HCD state structure for the DWC OTG controller.
390 * @param qh QH for a periodic endpoint.
392 * @return 0 if successful, negative error code otherwise.
394 static int check_max_xfer_size(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
397 uint32_t max_xfer_size;
398 uint32_t max_channel_xfer_size;
402 max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
403 max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
405 if (max_xfer_size > max_channel_xfer_size) {
406 DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n",
407 __func__, max_xfer_size, max_channel_xfer_size);
408 status = -DWC_E_NO_SPACE;
415 * Schedules an interrupt or isochronous transfer in the periodic schedule.
417 * @param hcd The HCD state structure for the DWC OTG controller.
418 * @param qh QH for the periodic transfer. The QH should already contain the
419 * scheduling information.
421 * @return 0 if successful, negative error code otherwise.
423 static int schedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
427 status = periodic_channel_available(hcd);
429 DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__);
433 status = check_periodic_bandwidth(hcd, qh);
435 DWC_INFO("%s: Insufficient periodic bandwidth for " "periodic transfer.\n", __func__);
439 status = check_max_xfer_size(hcd, qh);
441 DWC_INFO("%s: Channel max transfer size too small " "for periodic transfer.\n", __func__);
445 if (hcd->core_if->dma_desc_enable) {
446 /* Don't rely on SOF and start in ready schedule */
447 DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready,
450 /* Always start in the inactive schedule. */
451 DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive,
455 /* Reserve the periodic channel. */
456 hcd->periodic_channels++;
458 /* Update claimed usecs per (micro)frame. */
459 hcd->periodic_usecs += qh->usecs;
465 * This function adds a QH to either the non periodic or periodic schedule if
466 * it is not already in the schedule. If the QH is already in the schedule, no
469 * @return 0 if successful, negative error code otherwise.
471 int dwc_otg_hcd_qh_add(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
474 gintmsk_data_t intr_mask = {.d32 = 0 };
476 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
477 /* QH already in a schedule. */
481 /* Add the new QH to the appropriate schedule */
482 if (dwc_qh_is_non_per(qh)) {
483 /* Always start in the inactive schedule. */
484 DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive,
487 status = schedule_periodic(hcd, qh);
488 if (!hcd->periodic_qh_count) {
489 intr_mask.b.sofintr = 1;
490 DWC_MODIFY_REG32(&hcd->core_if->
491 core_global_regs->gintmsk,
492 intr_mask.d32, intr_mask.d32);
494 hcd->periodic_qh_count++;
501 * Removes an interrupt or isochronous transfer from the periodic schedule.
503 * @param hcd The HCD state structure for the DWC OTG controller.
504 * @param qh QH for the periodic transfer.
506 static void deschedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
508 DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
510 /* Release the periodic channel reservation. */
511 hcd->periodic_channels--;
513 /* Update claimed usecs per (micro)frame. */
514 hcd->periodic_usecs -= qh->usecs;
518 * Removes a QH from either the non-periodic or periodic schedule. Memory is
521 * @param hcd The HCD state structure.
522 * @param qh QH to remove from schedule. */
523 void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
525 gintmsk_data_t intr_mask = {.d32 = 0 };
527 if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
528 /* QH is not in a schedule. */
532 if (dwc_qh_is_non_per(qh)) {
533 if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
534 hcd->non_periodic_qh_ptr =
535 hcd->non_periodic_qh_ptr->next;
537 DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
539 deschedule_periodic(hcd, qh);
540 hcd->periodic_qh_count--;
541 if (!hcd->periodic_qh_count) {
542 intr_mask.b.sofintr = 1;
543 DWC_MODIFY_REG32(&hcd->core_if->
544 core_global_regs->gintmsk,
551 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
552 * non-periodic schedule. The QH is added to the inactive non-periodic
553 * schedule if any QTDs are still attached to the QH.
555 * For periodic QHs, the QH is removed from the periodic queued schedule. If
556 * there are any QTDs still attached to the QH, the QH is added to either the
557 * periodic inactive schedule or the periodic ready schedule and its next
558 * scheduled frame is calculated. The QH is placed in the ready schedule if
559 * the scheduled frame has been reached already. Otherwise it's placed in the
560 * inactive schedule. If there are no QTDs attached to the QH, the QH is
561 * completely removed from the periodic schedule.
563 void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh,
564 int sched_next_periodic_split)
566 if (dwc_qh_is_non_per(qh)) {
567 dwc_otg_hcd_qh_remove(hcd, qh);
568 if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
569 /* Add back to inactive non-periodic schedule. */
570 dwc_otg_hcd_qh_add(hcd, qh);
573 uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd);
576 /* Schedule the next continuing periodic split transfer */
577 if (sched_next_periodic_split) {
579 qh->sched_frame = frame_number;
580 if (dwc_frame_num_le(frame_number,
582 (qh->start_split_frame,
585 * Allow one frame to elapse after start
586 * split microframe before scheduling
587 * complete split, but DONT if we are
588 * doing the next start split in the
589 * same frame for an ISOC out.
591 if ((qh->ep_type != UE_ISOCHRONOUS) ||
592 (qh->ep_is_in != 0)) {
595 (qh->sched_frame, 1);
600 dwc_frame_num_inc(qh->start_split_frame,
603 (qh->sched_frame, frame_number)) {
604 qh->sched_frame = frame_number;
606 qh->sched_frame |= 0x7;
607 qh->start_split_frame = qh->sched_frame;
611 dwc_frame_num_inc(qh->sched_frame, qh->interval);
612 if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
613 qh->sched_frame = frame_number;
617 if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
618 dwc_otg_hcd_qh_remove(hcd, qh);
621 * Remove from periodic_sched_queued and move to
624 if (qh->sched_frame == frame_number) {
625 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
629 (&hcd->periodic_sched_inactive,
637 * This function allocates and initializes a QTD.
639 * @param urb The URB to create a QTD from. Each URB-QTD pair will end up
640 * pointing to each other so each pair should have a unique correlation.
641 * @param atomic_alloc Flag to do atomic alloc if needed
643 * @return Returns pointer to the newly allocated QTD, or NULL on error. */
644 dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t *urb, int atomic_alloc)
648 qtd = dwc_otg_hcd_qtd_alloc(atomic_alloc);
653 dwc_otg_hcd_qtd_init(qtd, urb);
658 * Initializes a QTD structure.
660 * @param qtd The QTD to initialize.
661 * @param urb The URB to use for initialization. */
662 void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t *qtd, dwc_otg_hcd_urb_t *urb)
664 dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t));
666 if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) {
668 * The only time the QTD data toggle is used is on the data
669 * phase of control transfers. This phase always starts with
672 qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
673 qtd->control_phase = DWC_OTG_CONTROL_SETUP;
677 qtd->complete_split = 0;
678 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
679 qtd->isoc_split_offset = 0;
682 /* Store the qtd ptr in the urb to reference what QTD. */
688 * This function adds a QTD to the QTD-list of a QH. It will find the correct
689 * QH to place the QTD into. If it does not find a QH, then it will create a
690 * new QH. If the QH to which the QTD is added is not currently scheduled, it
691 * is placed into the proper schedule based on its EP type.
693 * @param[in] qtd The QTD to add
694 * @param[in] hcd The DWC HCD structure
695 * @param[out] qh out parameter to return queue head
696 * @param atomic_alloc Flag to do atomic alloc if needed
698 * @return 0 if successful, negative error code otherwise.
700 int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t *qtd,
701 dwc_otg_hcd_t *hcd, dwc_otg_qh_t **qh,
706 dwc_otg_hcd_urb_t *urb = qtd->urb;
709 * Get the QH which holds the QTD-list to insert to. Create QH if it
713 *qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc);
720 retval = dwc_otg_hcd_qh_add(hcd, *qh);
722 DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd,
731 #endif /* DWC_DEVICE_ONLY */