2 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
4 * Copyright (C) 2005-2007 AMD (http://www.amd.com)
5 * Author: Thomas Dahlmann
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
14 * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
15 * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
16 * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
18 * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
19 * be used as host port) and UOC bits PAD_EN and APU are set (should be done
22 * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
23 * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
24 * can be used with gadget ether.
28 /* #define UDC_VERBOSE */
31 #define UDC_MOD_DESCRIPTION "AMD 5536 UDC - USB Device Controller"
32 #define UDC_DRIVER_VERSION_STRING "01.00.0206"
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/ioport.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/errno.h>
43 #include <linux/init.h>
44 #include <linux/timer.h>
45 #include <linux/list.h>
46 #include <linux/interrupt.h>
47 #include <linux/ioctl.h>
49 #include <linux/dmapool.h>
50 #include <linux/moduleparam.h>
51 #include <linux/device.h>
53 #include <linux/irq.h>
54 #include <linux/prefetch.h>
56 #include <asm/byteorder.h>
57 #include <asm/unaligned.h>
60 #include <linux/usb/ch9.h>
61 #include <linux/usb/gadget.h>
64 #include "amd5536udc.h"
67 static void udc_tasklet_disconnect(unsigned long);
68 static void empty_req_queue(struct udc_ep *);
69 static int udc_probe(struct udc *dev);
70 static void udc_basic_init(struct udc *dev);
71 static void udc_setup_endpoints(struct udc *dev);
72 static void udc_soft_reset(struct udc *dev);
73 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
74 static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
75 static int udc_free_dma_chain(struct udc *dev, struct udc_request *req);
76 static int udc_create_dma_chain(struct udc_ep *ep, struct udc_request *req,
77 unsigned long buf_len, gfp_t gfp_flags);
78 static int udc_remote_wakeup(struct udc *dev);
79 static int udc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
80 static void udc_pci_remove(struct pci_dev *pdev);
83 static const char mod_desc[] = UDC_MOD_DESCRIPTION;
84 static const char name[] = "amd5536udc";
86 /* structure to hold endpoint function pointers */
87 static const struct usb_ep_ops udc_ep_ops;
89 /* received setup data */
90 static union udc_setup_data setup_data;
92 /* pointer to device object */
93 static struct udc *udc;
95 /* irq spin lock for soft reset */
96 static DEFINE_SPINLOCK(udc_irq_spinlock);
98 static DEFINE_SPINLOCK(udc_stall_spinlock);
101 * slave mode: pending bytes in rx fifo after nyet,
102 * used if EPIN irq came but no req was available
104 static unsigned int udc_rxfifo_pending;
106 /* count soft resets after suspend to avoid loop */
107 static int soft_reset_occured;
108 static int soft_reset_after_usbreset_occured;
111 static struct timer_list udc_timer;
112 static int stop_timer;
114 /* set_rde -- Is used to control enabling of RX DMA. Problem is
115 * that UDC has only one bit (RDE) to enable/disable RX DMA for
116 * all OUT endpoints. So we have to handle race conditions like
117 * when OUT data reaches the fifo but no request was queued yet.
118 * This cannot be solved by letting the RX DMA disabled until a
119 * request gets queued because there may be other OUT packets
120 * in the FIFO (important for not blocking control traffic).
121 * The value of set_rde controls the correspondig timer.
123 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
124 * set_rde 0 == do not touch RDE, do no start the RDE timer
125 * set_rde 1 == timer function will look whether FIFO has data
126 * set_rde 2 == set by timer function to enable RX DMA on next call
128 static int set_rde = -1;
130 static DECLARE_COMPLETION(on_exit);
131 static struct timer_list udc_pollstall_timer;
132 static int stop_pollstall_timer;
133 static DECLARE_COMPLETION(on_pollstall_exit);
135 /* tasklet for usb disconnect */
136 static DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect,
137 (unsigned long) &udc);
140 /* endpoint names used for print */
141 static const char ep0_string[] = "ep0in";
142 static const char *const ep_string[] = {
144 "ep1in-int", "ep2in-bulk", "ep3in-bulk", "ep4in-bulk", "ep5in-bulk",
145 "ep6in-bulk", "ep7in-bulk", "ep8in-bulk", "ep9in-bulk", "ep10in-bulk",
146 "ep11in-bulk", "ep12in-bulk", "ep13in-bulk", "ep14in-bulk",
147 "ep15in-bulk", "ep0out", "ep1out-bulk", "ep2out-bulk", "ep3out-bulk",
148 "ep4out-bulk", "ep5out-bulk", "ep6out-bulk", "ep7out-bulk",
149 "ep8out-bulk", "ep9out-bulk", "ep10out-bulk", "ep11out-bulk",
150 "ep12out-bulk", "ep13out-bulk", "ep14out-bulk", "ep15out-bulk"
154 static bool use_dma = 1;
155 /* packet per buffer dma */
156 static bool use_dma_ppb = 1;
157 /* with per descr. update */
158 static bool use_dma_ppb_du;
159 /* buffer fill mode */
160 static int use_dma_bufferfill_mode;
161 /* full speed only mode */
162 static bool use_fullspeed;
163 /* tx buffer size for high speed */
164 static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
166 /* module parameters */
167 module_param(use_dma, bool, S_IRUGO);
168 MODULE_PARM_DESC(use_dma, "true for DMA");
169 module_param(use_dma_ppb, bool, S_IRUGO);
170 MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode");
171 module_param(use_dma_ppb_du, bool, S_IRUGO);
172 MODULE_PARM_DESC(use_dma_ppb_du,
173 "true for DMA in packet per buffer mode with descriptor update");
174 module_param(use_fullspeed, bool, S_IRUGO);
175 MODULE_PARM_DESC(use_fullspeed, "true for fullspeed only");
177 /*---------------------------------------------------------------------------*/
178 /* Prints UDC device registers and endpoint irq registers */
179 static void print_regs(struct udc *dev)
181 DBG(dev, "------- Device registers -------\n");
182 DBG(dev, "dev config = %08x\n", readl(&dev->regs->cfg));
183 DBG(dev, "dev control = %08x\n", readl(&dev->regs->ctl));
184 DBG(dev, "dev status = %08x\n", readl(&dev->regs->sts));
186 DBG(dev, "dev int's = %08x\n", readl(&dev->regs->irqsts));
187 DBG(dev, "dev intmask = %08x\n", readl(&dev->regs->irqmsk));
189 DBG(dev, "dev ep int's = %08x\n", readl(&dev->regs->ep_irqsts));
190 DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk));
192 DBG(dev, "USE DMA = %d\n", use_dma);
193 if (use_dma && use_dma_ppb && !use_dma_ppb_du) {
194 DBG(dev, "DMA mode = PPBNDU (packet per buffer "
195 "WITHOUT desc. update)\n");
196 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBNDU");
197 } else if (use_dma && use_dma_ppb && use_dma_ppb_du) {
198 DBG(dev, "DMA mode = PPBDU (packet per buffer "
199 "WITH desc. update)\n");
200 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBDU");
202 if (use_dma && use_dma_bufferfill_mode) {
203 DBG(dev, "DMA mode = BF (buffer fill mode)\n");
204 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "BF");
207 dev_info(&dev->pdev->dev, "FIFO mode\n");
208 DBG(dev, "-------------------------------------------------------\n");
211 /* Masks unused interrupts */
212 static int udc_mask_unused_interrupts(struct udc *dev)
216 /* mask all dev interrupts */
217 tmp = AMD_BIT(UDC_DEVINT_SVC) |
218 AMD_BIT(UDC_DEVINT_ENUM) |
219 AMD_BIT(UDC_DEVINT_US) |
220 AMD_BIT(UDC_DEVINT_UR) |
221 AMD_BIT(UDC_DEVINT_ES) |
222 AMD_BIT(UDC_DEVINT_SI) |
223 AMD_BIT(UDC_DEVINT_SOF)|
224 AMD_BIT(UDC_DEVINT_SC);
225 writel(tmp, &dev->regs->irqmsk);
227 /* mask all ep interrupts */
228 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
233 /* Enables endpoint 0 interrupts */
234 static int udc_enable_ep0_interrupts(struct udc *dev)
238 DBG(dev, "udc_enable_ep0_interrupts()\n");
241 tmp = readl(&dev->regs->ep_irqmsk);
242 /* enable ep0 irq's */
243 tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
244 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0);
245 writel(tmp, &dev->regs->ep_irqmsk);
250 /* Enables device interrupts for SET_INTF and SET_CONFIG */
251 static int udc_enable_dev_setup_interrupts(struct udc *dev)
255 DBG(dev, "enable device interrupts for setup data\n");
258 tmp = readl(&dev->regs->irqmsk);
260 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
261 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
262 & AMD_UNMASK_BIT(UDC_DEVINT_SC)
263 & AMD_UNMASK_BIT(UDC_DEVINT_UR)
264 & AMD_UNMASK_BIT(UDC_DEVINT_SVC)
265 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM);
266 writel(tmp, &dev->regs->irqmsk);
271 /* Calculates fifo start of endpoint based on preceding endpoints */
272 static int udc_set_txfifo_addr(struct udc_ep *ep)
278 if (!ep || !(ep->in))
282 ep->txfifo = dev->txfifo;
285 for (i = 0; i < ep->num; i++) {
286 if (dev->ep[i].regs) {
288 tmp = readl(&dev->ep[i].regs->bufin_framenum);
289 tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
296 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
297 static u32 cnak_pending;
299 static void UDC_QUEUE_CNAK(struct udc_ep *ep, unsigned num)
301 if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {
302 DBG(ep->dev, "NAK could not be cleared for ep%d\n", num);
303 cnak_pending |= 1 << (num);
306 cnak_pending = cnak_pending & (~(1 << (num)));
310 /* Enables endpoint, is called by gadget driver */
312 udc_ep_enable(struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc)
317 unsigned long iflags;
322 || usbep->name == ep0_string
324 || desc->bDescriptorType != USB_DT_ENDPOINT)
327 ep = container_of(usbep, struct udc_ep, ep);
330 DBG(dev, "udc_ep_enable() ep %d\n", ep->num);
332 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
335 spin_lock_irqsave(&dev->lock, iflags);
340 /* set traffic type */
341 tmp = readl(&dev->ep[ep->num].regs->ctl);
342 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
343 writel(tmp, &dev->ep[ep->num].regs->ctl);
345 /* set max packet size */
346 maxpacket = usb_endpoint_maxp(desc);
347 tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
348 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
349 ep->ep.maxpacket = maxpacket;
350 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
355 /* ep ix in UDC CSR register space */
356 udc_csr_epix = ep->num;
358 /* set buffer size (tx fifo entries) */
359 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
360 /* double buffering: fifo size = 2 x max packet size */
363 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
366 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
368 /* calc. tx fifo base addr */
369 udc_set_txfifo_addr(ep);
372 tmp = readl(&ep->regs->ctl);
373 tmp |= AMD_BIT(UDC_EPCTL_F);
374 writel(tmp, &ep->regs->ctl);
378 /* ep ix in UDC CSR register space */
379 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
381 /* set max packet size UDC CSR */
382 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
383 tmp = AMD_ADDBITS(tmp, maxpacket,
385 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
387 if (use_dma && !ep->in) {
388 /* alloc and init BNA dummy request */
389 ep->bna_dummy_req = udc_alloc_bna_dummy(ep);
390 ep->bna_occurred = 0;
393 if (ep->num != UDC_EP0OUT_IX)
394 dev->data_ep_enabled = 1;
398 tmp = readl(&dev->csr->ne[udc_csr_epix]);
400 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
402 tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
404 tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
406 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
408 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
410 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
412 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
414 writel(tmp, &dev->csr->ne[udc_csr_epix]);
417 tmp = readl(&dev->regs->ep_irqmsk);
418 tmp &= AMD_UNMASK_BIT(ep->num);
419 writel(tmp, &dev->regs->ep_irqmsk);
422 * clear NAK by writing CNAK
423 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
425 if (!use_dma || ep->in) {
426 tmp = readl(&ep->regs->ctl);
427 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
428 writel(tmp, &ep->regs->ctl);
430 UDC_QUEUE_CNAK(ep, ep->num);
432 tmp = desc->bEndpointAddress;
433 DBG(dev, "%s enabled\n", usbep->name);
435 spin_unlock_irqrestore(&dev->lock, iflags);
439 /* Resets endpoint */
440 static void ep_init(struct udc_regs __iomem *regs, struct udc_ep *ep)
444 VDBG(ep->dev, "ep-%d reset\n", ep->num);
446 ep->ep.ops = &udc_ep_ops;
447 INIT_LIST_HEAD(&ep->queue);
449 usb_ep_set_maxpacket_limit(&ep->ep,(u16) ~0);
451 tmp = readl(&ep->regs->ctl);
452 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
453 writel(tmp, &ep->regs->ctl);
456 /* disable interrupt */
457 tmp = readl(®s->ep_irqmsk);
458 tmp |= AMD_BIT(ep->num);
459 writel(tmp, ®s->ep_irqmsk);
462 /* unset P and IN bit of potential former DMA */
463 tmp = readl(&ep->regs->ctl);
464 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
465 writel(tmp, &ep->regs->ctl);
467 tmp = readl(&ep->regs->sts);
468 tmp |= AMD_BIT(UDC_EPSTS_IN);
469 writel(tmp, &ep->regs->sts);
472 tmp = readl(&ep->regs->ctl);
473 tmp |= AMD_BIT(UDC_EPCTL_F);
474 writel(tmp, &ep->regs->ctl);
477 /* reset desc pointer */
478 writel(0, &ep->regs->desptr);
481 /* Disables endpoint, is called by gadget driver */
482 static int udc_ep_disable(struct usb_ep *usbep)
484 struct udc_ep *ep = NULL;
485 unsigned long iflags;
490 ep = container_of(usbep, struct udc_ep, ep);
491 if (usbep->name == ep0_string || !ep->ep.desc)
494 DBG(ep->dev, "Disable ep-%d\n", ep->num);
496 spin_lock_irqsave(&ep->dev->lock, iflags);
497 udc_free_request(&ep->ep, &ep->bna_dummy_req->req);
499 ep_init(ep->dev->regs, ep);
500 spin_unlock_irqrestore(&ep->dev->lock, iflags);
505 /* Allocates request packet, called by gadget driver */
506 static struct usb_request *
507 udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
509 struct udc_request *req;
510 struct udc_data_dma *dma_desc;
516 ep = container_of(usbep, struct udc_ep, ep);
518 VDBG(ep->dev, "udc_alloc_req(): ep%d\n", ep->num);
519 req = kzalloc(sizeof(struct udc_request), gfp);
523 req->req.dma = DMA_DONT_USE;
524 INIT_LIST_HEAD(&req->queue);
527 /* ep0 in requests are allocated from data pool here */
528 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
535 VDBG(ep->dev, "udc_alloc_req: req = %p dma_desc = %p, "
538 (unsigned long)req->td_phys);
539 /* prevent from using desc. - set HOST BUSY */
540 dma_desc->status = AMD_ADDBITS(dma_desc->status,
541 UDC_DMA_STP_STS_BS_HOST_BUSY,
543 dma_desc->bufptr = cpu_to_le32(DMA_DONT_USE);
544 req->td_data = dma_desc;
545 req->td_data_last = NULL;
552 /* Frees request packet, called by gadget driver */
554 udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
557 struct udc_request *req;
559 if (!usbep || !usbreq)
562 ep = container_of(usbep, struct udc_ep, ep);
563 req = container_of(usbreq, struct udc_request, req);
564 VDBG(ep->dev, "free_req req=%p\n", req);
565 BUG_ON(!list_empty(&req->queue));
567 VDBG(ep->dev, "req->td_data=%p\n", req->td_data);
569 /* free dma chain if created */
570 if (req->chain_len > 1)
571 udc_free_dma_chain(ep->dev, req);
573 pci_pool_free(ep->dev->data_requests, req->td_data,
579 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
580 static void udc_init_bna_dummy(struct udc_request *req)
584 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
585 /* set next pointer to itself */
586 req->td_data->next = req->td_phys;
589 = AMD_ADDBITS(req->td_data->status,
590 UDC_DMA_STP_STS_BS_DMA_DONE,
593 pr_debug("bna desc = %p, sts = %08x\n",
594 req->td_data, req->td_data->status);
599 /* Allocate BNA dummy descriptor */
600 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep)
602 struct udc_request *req = NULL;
603 struct usb_request *_req = NULL;
605 /* alloc the dummy request */
606 _req = udc_alloc_request(&ep->ep, GFP_ATOMIC);
608 req = container_of(_req, struct udc_request, req);
609 ep->bna_dummy_req = req;
610 udc_init_bna_dummy(req);
615 /* Write data to TX fifo for IN packets */
617 udc_txfifo_write(struct udc_ep *ep, struct usb_request *req)
623 unsigned remaining = 0;
628 req_buf = req->buf + req->actual;
630 remaining = req->length - req->actual;
632 buf = (u32 *) req_buf;
634 bytes = ep->ep.maxpacket;
635 if (bytes > remaining)
639 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
640 writel(*(buf + i), ep->txfifo);
642 /* remaining bytes must be written by byte access */
643 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
644 writeb((u8)(*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)),
648 /* dummy write confirm */
649 writel(0, &ep->regs->confirm);
652 /* Read dwords from RX fifo for OUT transfers */
653 static int udc_rxfifo_read_dwords(struct udc *dev, u32 *buf, int dwords)
657 VDBG(dev, "udc_read_dwords(): %d dwords\n", dwords);
659 for (i = 0; i < dwords; i++)
660 *(buf + i) = readl(dev->rxfifo);
664 /* Read bytes from RX fifo for OUT transfers */
665 static int udc_rxfifo_read_bytes(struct udc *dev, u8 *buf, int bytes)
670 VDBG(dev, "udc_read_bytes(): %d bytes\n", bytes);
673 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
674 *((u32 *)(buf + (i<<2))) = readl(dev->rxfifo);
676 /* remaining bytes must be read by byte access */
677 if (bytes % UDC_DWORD_BYTES) {
678 tmp = readl(dev->rxfifo);
679 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
680 *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
681 tmp = tmp >> UDC_BITS_PER_BYTE;
688 /* Read data from RX fifo for OUT transfers */
690 udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req)
695 unsigned finished = 0;
697 /* received number bytes */
698 bytes = readl(&ep->regs->sts);
699 bytes = AMD_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE);
701 buf_space = req->req.length - req->req.actual;
702 buf = req->req.buf + req->req.actual;
703 if (bytes > buf_space) {
704 if ((buf_space % ep->ep.maxpacket) != 0) {
706 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
707 ep->ep.name, bytes, buf_space);
708 req->req.status = -EOVERFLOW;
712 req->req.actual += bytes;
715 if (((bytes % ep->ep.maxpacket) != 0) || (!bytes)
716 || ((req->req.actual == req->req.length) && !req->req.zero))
719 /* read rx fifo bytes */
720 VDBG(ep->dev, "ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes);
721 udc_rxfifo_read_bytes(ep->dev, buf, bytes);
726 /* create/re-init a DMA descriptor or a DMA descriptor chain */
727 static int prep_dma(struct udc_ep *ep, struct udc_request *req, gfp_t gfp)
732 VDBG(ep->dev, "prep_dma\n");
733 VDBG(ep->dev, "prep_dma ep%d req->td_data=%p\n",
734 ep->num, req->td_data);
736 /* set buffer pointer */
737 req->td_data->bufptr = req->req.dma;
740 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
742 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
745 retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
747 if (retval == -ENOMEM)
748 DBG(ep->dev, "Out of DMA memory\n");
752 if (req->req.length == ep->ep.maxpacket) {
754 req->td_data->status =
755 AMD_ADDBITS(req->td_data->status,
757 UDC_DMA_IN_STS_TXBYTES);
765 VDBG(ep->dev, "IN: use_dma_ppb=%d req->req.len=%d "
766 "maxpacket=%d ep%d\n",
767 use_dma_ppb, req->req.length,
768 ep->ep.maxpacket, ep->num);
770 * if bytes < max packet then tx bytes must
771 * be written in packet per buffer mode
773 if (!use_dma_ppb || req->req.length < ep->ep.maxpacket
774 || ep->num == UDC_EP0OUT_IX
775 || ep->num == UDC_EP0IN_IX) {
777 req->td_data->status =
778 AMD_ADDBITS(req->td_data->status,
780 UDC_DMA_IN_STS_TXBYTES);
781 /* reset frame num */
782 req->td_data->status =
783 AMD_ADDBITS(req->td_data->status,
785 UDC_DMA_IN_STS_FRAMENUM);
788 req->td_data->status =
789 AMD_ADDBITS(req->td_data->status,
790 UDC_DMA_STP_STS_BS_HOST_BUSY,
793 VDBG(ep->dev, "OUT set host ready\n");
795 req->td_data->status =
796 AMD_ADDBITS(req->td_data->status,
797 UDC_DMA_STP_STS_BS_HOST_READY,
801 /* clear NAK by writing CNAK */
803 tmp = readl(&ep->regs->ctl);
804 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
805 writel(tmp, &ep->regs->ctl);
807 UDC_QUEUE_CNAK(ep, ep->num);
815 /* Completes request packet ... caller MUST hold lock */
817 complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
818 __releases(ep->dev->lock)
819 __acquires(ep->dev->lock)
824 VDBG(ep->dev, "complete_req(): ep%d\n", ep->num);
829 usb_gadget_unmap_request(&dev->gadget, &req->req, ep->in);
834 /* set new status if pending */
835 if (req->req.status == -EINPROGRESS)
836 req->req.status = sts;
838 /* remove from ep queue */
839 list_del_init(&req->queue);
841 VDBG(ep->dev, "req %p => complete %d bytes at %s with sts %d\n",
842 &req->req, req->req.length, ep->ep.name, sts);
844 spin_unlock(&dev->lock);
845 req->req.complete(&ep->ep, &req->req);
846 spin_lock(&dev->lock);
850 /* frees pci pool descriptors of a DMA chain */
851 static int udc_free_dma_chain(struct udc *dev, struct udc_request *req)
855 struct udc_data_dma *td;
856 struct udc_data_dma *td_last = NULL;
859 DBG(dev, "free chain req = %p\n", req);
861 /* do not free first desc., will be done by free for request */
862 td_last = req->td_data;
863 td = phys_to_virt(td_last->next);
865 for (i = 1; i < req->chain_len; i++) {
867 pci_pool_free(dev->data_requests, td,
868 (dma_addr_t) td_last->next);
870 td = phys_to_virt(td_last->next);
876 /* Iterates to the end of a DMA chain and returns last descriptor */
877 static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
879 struct udc_data_dma *td;
882 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L)))
883 td = phys_to_virt(td->next);
889 /* Iterates to the end of a DMA chain and counts bytes received */
890 static u32 udc_get_ppbdu_rxbytes(struct udc_request *req)
892 struct udc_data_dma *td;
896 /* received number bytes */
897 count = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES);
899 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
900 td = phys_to_virt(td->next);
901 /* received number bytes */
903 count += AMD_GETBITS(td->status,
904 UDC_DMA_OUT_STS_RXBYTES);
912 /* Creates or re-inits a DMA chain */
913 static int udc_create_dma_chain(
915 struct udc_request *req,
916 unsigned long buf_len, gfp_t gfp_flags
919 unsigned long bytes = req->req.length;
922 struct udc_data_dma *td = NULL;
923 struct udc_data_dma *last = NULL;
924 unsigned long txbytes;
925 unsigned create_new_chain = 0;
928 VDBG(ep->dev, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
930 dma_addr = DMA_DONT_USE;
932 /* unset L bit in first desc for OUT */
934 req->td_data->status &= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L);
936 /* alloc only new desc's if not already available */
937 len = req->req.length / ep->ep.maxpacket;
938 if (req->req.length % ep->ep.maxpacket)
941 if (len > req->chain_len) {
942 /* shorter chain already allocated before */
943 if (req->chain_len > 1)
944 udc_free_dma_chain(ep->dev, req);
945 req->chain_len = len;
946 create_new_chain = 1;
950 /* gen. required number of descriptors and buffers */
951 for (i = buf_len; i < bytes; i += buf_len) {
952 /* create or determine next desc. */
953 if (create_new_chain) {
955 td = pci_pool_alloc(ep->dev->data_requests,
956 gfp_flags, &dma_addr);
961 } else if (i == buf_len) {
963 td = (struct udc_data_dma *) phys_to_virt(
967 td = (struct udc_data_dma *) phys_to_virt(last->next);
973 td->bufptr = req->req.dma + i; /* assign buffer */
978 if ((bytes - i) >= buf_len) {
985 /* link td and assign tx bytes */
987 if (create_new_chain)
988 req->td_data->next = dma_addr;
991 req->td_data->next = virt_to_phys(td);
996 req->td_data->status =
997 AMD_ADDBITS(req->td_data->status,
999 UDC_DMA_IN_STS_TXBYTES);
1001 td->status = AMD_ADDBITS(td->status,
1003 UDC_DMA_IN_STS_TXBYTES);
1006 if (create_new_chain)
1007 last->next = dma_addr;
1010 last->next = virt_to_phys(td);
1013 /* write tx bytes */
1014 td->status = AMD_ADDBITS(td->status,
1016 UDC_DMA_IN_STS_TXBYTES);
1023 td->status |= AMD_BIT(UDC_DMA_IN_STS_L);
1024 /* last desc. points to itself */
1025 req->td_data_last = td;
1031 /* Enabling RX DMA */
1032 static void udc_set_rde(struct udc *dev)
1036 VDBG(dev, "udc_set_rde()\n");
1037 /* stop RDE timer */
1038 if (timer_pending(&udc_timer)) {
1040 mod_timer(&udc_timer, jiffies - 1);
1043 tmp = readl(&dev->regs->ctl);
1044 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1045 writel(tmp, &dev->regs->ctl);
1048 /* Queues a request packet, called by gadget driver */
1050 udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
1054 unsigned long iflags;
1056 struct udc_request *req;
1060 /* check the inputs */
1061 req = container_of(usbreq, struct udc_request, req);
1063 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf
1064 || !list_empty(&req->queue))
1067 ep = container_of(usbep, struct udc_ep, ep);
1068 if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1071 VDBG(ep->dev, "udc_queue(): ep%d-in=%d\n", ep->num, ep->in);
1074 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1077 /* map dma (usually done before) */
1079 VDBG(dev, "DMA map req %p\n", req);
1080 retval = usb_gadget_map_request(&udc->gadget, usbreq, ep->in);
1085 VDBG(dev, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1086 usbep->name, usbreq, usbreq->length,
1087 req->td_data, usbreq->buf);
1089 spin_lock_irqsave(&dev->lock, iflags);
1091 usbreq->status = -EINPROGRESS;
1094 /* on empty queue just do first transfer */
1095 if (list_empty(&ep->queue)) {
1097 if (usbreq->length == 0) {
1098 /* IN zlp's are handled by hardware */
1099 complete_req(ep, req, 0);
1100 VDBG(dev, "%s: zlp\n", ep->ep.name);
1102 * if set_config or set_intf is waiting for ack by zlp
1105 if (dev->set_cfg_not_acked) {
1106 tmp = readl(&dev->regs->ctl);
1107 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1108 writel(tmp, &dev->regs->ctl);
1109 dev->set_cfg_not_acked = 0;
1111 /* setup command is ACK'ed now by zlp */
1112 if (dev->waiting_zlp_ack_ep0in) {
1113 /* clear NAK by writing CNAK in EP0_IN */
1114 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1115 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1116 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1117 dev->ep[UDC_EP0IN_IX].naking = 0;
1118 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],
1120 dev->waiting_zlp_ack_ep0in = 0;
1125 retval = prep_dma(ep, req, GFP_ATOMIC);
1128 /* write desc pointer to enable DMA */
1130 /* set HOST READY */
1131 req->td_data->status =
1132 AMD_ADDBITS(req->td_data->status,
1133 UDC_DMA_IN_STS_BS_HOST_READY,
1137 /* disabled rx dma while descriptor update */
1139 /* stop RDE timer */
1140 if (timer_pending(&udc_timer)) {
1142 mod_timer(&udc_timer, jiffies - 1);
1145 tmp = readl(&dev->regs->ctl);
1146 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1147 writel(tmp, &dev->regs->ctl);
1151 * if BNA occurred then let BNA dummy desc.
1152 * point to current desc.
1154 if (ep->bna_occurred) {
1155 VDBG(dev, "copy to BNA dummy desc.\n");
1156 memcpy(ep->bna_dummy_req->td_data,
1158 sizeof(struct udc_data_dma));
1161 /* write desc pointer */
1162 writel(req->td_phys, &ep->regs->desptr);
1164 /* clear NAK by writing CNAK */
1166 tmp = readl(&ep->regs->ctl);
1167 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1168 writel(tmp, &ep->regs->ctl);
1170 UDC_QUEUE_CNAK(ep, ep->num);
1175 tmp = readl(&dev->regs->ep_irqmsk);
1176 tmp &= AMD_UNMASK_BIT(ep->num);
1177 writel(tmp, &dev->regs->ep_irqmsk);
1179 } else if (ep->in) {
1181 tmp = readl(&dev->regs->ep_irqmsk);
1182 tmp &= AMD_UNMASK_BIT(ep->num);
1183 writel(tmp, &dev->regs->ep_irqmsk);
1186 } else if (ep->dma) {
1189 * prep_dma not used for OUT ep's, this is not possible
1190 * for PPB modes, because of chain creation reasons
1193 retval = prep_dma(ep, req, GFP_ATOMIC);
1198 VDBG(dev, "list_add\n");
1199 /* add request to ep queue */
1202 list_add_tail(&req->queue, &ep->queue);
1204 /* open rxfifo if out data queued */
1209 if (ep->num != UDC_EP0OUT_IX)
1210 dev->data_ep_queued = 1;
1212 /* stop OUT naking */
1214 if (!use_dma && udc_rxfifo_pending) {
1215 DBG(dev, "udc_queue(): pending bytes in "
1216 "rxfifo after nyet\n");
1218 * read pending bytes afer nyet:
1221 if (udc_rxfifo_read(ep, req)) {
1223 complete_req(ep, req, 0);
1225 udc_rxfifo_pending = 0;
1232 spin_unlock_irqrestore(&dev->lock, iflags);
1236 /* Empty request queue of an endpoint; caller holds spinlock */
1237 static void empty_req_queue(struct udc_ep *ep)
1239 struct udc_request *req;
1242 while (!list_empty(&ep->queue)) {
1243 req = list_entry(ep->queue.next,
1246 complete_req(ep, req, -ESHUTDOWN);
1250 /* Dequeues a request packet, called by gadget driver */
1251 static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
1254 struct udc_request *req;
1256 unsigned long iflags;
1258 ep = container_of(usbep, struct udc_ep, ep);
1259 if (!usbep || !usbreq || (!ep->ep.desc && (ep->num != 0
1260 && ep->num != UDC_EP0OUT_IX)))
1263 req = container_of(usbreq, struct udc_request, req);
1265 spin_lock_irqsave(&ep->dev->lock, iflags);
1266 halted = ep->halted;
1268 /* request in processing or next one */
1269 if (ep->queue.next == &req->queue) {
1270 if (ep->dma && req->dma_going) {
1272 ep->cancel_transfer = 1;
1276 /* stop potential receive DMA */
1277 tmp = readl(&udc->regs->ctl);
1278 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1281 * Cancel transfer later in ISR
1282 * if descriptor was touched.
1284 dma_sts = AMD_GETBITS(req->td_data->status,
1285 UDC_DMA_OUT_STS_BS);
1286 if (dma_sts != UDC_DMA_OUT_STS_BS_HOST_READY)
1287 ep->cancel_transfer = 1;
1289 udc_init_bna_dummy(ep->req);
1290 writel(ep->bna_dummy_req->td_phys,
1293 writel(tmp, &udc->regs->ctl);
1297 complete_req(ep, req, -ECONNRESET);
1298 ep->halted = halted;
1300 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1304 /* Halt or clear halt of endpoint */
1306 udc_set_halt(struct usb_ep *usbep, int halt)
1310 unsigned long iflags;
1316 pr_debug("set_halt %s: halt=%d\n", usbep->name, halt);
1318 ep = container_of(usbep, struct udc_ep, ep);
1319 if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1321 if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
1324 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1325 /* halt or clear halt */
1328 ep->dev->stall_ep0in = 1;
1332 * rxfifo empty not taken into acount
1334 tmp = readl(&ep->regs->ctl);
1335 tmp |= AMD_BIT(UDC_EPCTL_S);
1336 writel(tmp, &ep->regs->ctl);
1339 /* setup poll timer */
1340 if (!timer_pending(&udc_pollstall_timer)) {
1341 udc_pollstall_timer.expires = jiffies +
1342 HZ * UDC_POLLSTALL_TIMER_USECONDS
1344 if (!stop_pollstall_timer) {
1345 DBG(ep->dev, "start polltimer\n");
1346 add_timer(&udc_pollstall_timer);
1351 /* ep is halted by set_halt() before */
1353 tmp = readl(&ep->regs->ctl);
1354 /* clear stall bit */
1355 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1356 /* clear NAK by writing CNAK */
1357 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1358 writel(tmp, &ep->regs->ctl);
1360 UDC_QUEUE_CNAK(ep, ep->num);
1363 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1367 /* gadget interface */
1368 static const struct usb_ep_ops udc_ep_ops = {
1369 .enable = udc_ep_enable,
1370 .disable = udc_ep_disable,
1372 .alloc_request = udc_alloc_request,
1373 .free_request = udc_free_request,
1376 .dequeue = udc_dequeue,
1378 .set_halt = udc_set_halt,
1379 /* fifo ops not implemented */
1382 /*-------------------------------------------------------------------------*/
1384 /* Get frame counter (not implemented) */
1385 static int udc_get_frame(struct usb_gadget *gadget)
1390 /* Remote wakeup gadget interface */
1391 static int udc_wakeup(struct usb_gadget *gadget)
1397 dev = container_of(gadget, struct udc, gadget);
1398 udc_remote_wakeup(dev);
1403 static int amd5536_udc_start(struct usb_gadget *g,
1404 struct usb_gadget_driver *driver);
1405 static int amd5536_udc_stop(struct usb_gadget *g,
1406 struct usb_gadget_driver *driver);
1407 /* gadget operations */
1408 static const struct usb_gadget_ops udc_ops = {
1409 .wakeup = udc_wakeup,
1410 .get_frame = udc_get_frame,
1411 .udc_start = amd5536_udc_start,
1412 .udc_stop = amd5536_udc_stop,
1415 /* Setups endpoint parameters, adds endpoints to linked list */
1416 static void make_ep_lists(struct udc *dev)
1418 /* make gadget ep lists */
1419 INIT_LIST_HEAD(&dev->gadget.ep_list);
1420 list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
1421 &dev->gadget.ep_list);
1422 list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list,
1423 &dev->gadget.ep_list);
1424 list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
1425 &dev->gadget.ep_list);
1428 dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
1429 if (dev->gadget.speed == USB_SPEED_FULL)
1430 dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
1431 else if (dev->gadget.speed == USB_SPEED_HIGH)
1432 dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
1433 dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
1436 /* init registers at driver load time */
1437 static int startup_registers(struct udc *dev)
1441 /* init controller by soft reset */
1442 udc_soft_reset(dev);
1444 /* mask not needed interrupts */
1445 udc_mask_unused_interrupts(dev);
1447 /* put into initial config */
1448 udc_basic_init(dev);
1449 /* link up all endpoints */
1450 udc_setup_endpoints(dev);
1453 tmp = readl(&dev->regs->cfg);
1455 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1457 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
1458 writel(tmp, &dev->regs->cfg);
1463 /* Inits UDC context */
1464 static void udc_basic_init(struct udc *dev)
1468 DBG(dev, "udc_basic_init()\n");
1470 dev->gadget.speed = USB_SPEED_UNKNOWN;
1472 /* stop RDE timer */
1473 if (timer_pending(&udc_timer)) {
1475 mod_timer(&udc_timer, jiffies - 1);
1477 /* stop poll stall timer */
1478 if (timer_pending(&udc_pollstall_timer))
1479 mod_timer(&udc_pollstall_timer, jiffies - 1);
1481 tmp = readl(&dev->regs->ctl);
1482 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1483 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1484 writel(tmp, &dev->regs->ctl);
1486 /* enable dynamic CSR programming */
1487 tmp = readl(&dev->regs->cfg);
1488 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1489 /* set self powered */
1490 tmp |= AMD_BIT(UDC_DEVCFG_SP);
1491 /* set remote wakeupable */
1492 tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1493 writel(tmp, &dev->regs->cfg);
1497 dev->data_ep_enabled = 0;
1498 dev->data_ep_queued = 0;
1501 /* Sets initial endpoint parameters */
1502 static void udc_setup_endpoints(struct udc *dev)
1508 DBG(dev, "udc_setup_endpoints()\n");
1510 /* read enum speed */
1511 tmp = readl(&dev->regs->sts);
1512 tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
1513 if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH)
1514 dev->gadget.speed = USB_SPEED_HIGH;
1515 else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL)
1516 dev->gadget.speed = USB_SPEED_FULL;
1518 /* set basic ep parameters */
1519 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1522 ep->ep.name = ep_string[tmp];
1524 /* txfifo size is calculated at enable time */
1525 ep->txfifo = dev->txfifo;
1528 if (tmp < UDC_EPIN_NUM) {
1529 ep->fifo_depth = UDC_TXFIFO_SIZE;
1532 ep->fifo_depth = UDC_RXFIFO_SIZE;
1536 ep->regs = &dev->ep_regs[tmp];
1538 * ep will be reset only if ep was not enabled before to avoid
1539 * disabling ep interrupts when ENUM interrupt occurs but ep is
1540 * not enabled by gadget driver
1543 ep_init(dev->regs, ep);
1547 * ep->dma is not really used, just to indicate that
1548 * DMA is active: remove this
1549 * dma regs = dev control regs
1551 ep->dma = &dev->regs->ctl;
1553 /* nak OUT endpoints until enable - not for ep0 */
1554 if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1555 && tmp > UDC_EPIN_NUM) {
1557 reg = readl(&dev->ep[tmp].regs->ctl);
1558 reg |= AMD_BIT(UDC_EPCTL_SNAK);
1559 writel(reg, &dev->ep[tmp].regs->ctl);
1560 dev->ep[tmp].naking = 1;
1565 /* EP0 max packet */
1566 if (dev->gadget.speed == USB_SPEED_FULL) {
1567 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,
1568 UDC_FS_EP0IN_MAX_PKT_SIZE);
1569 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
1570 UDC_FS_EP0OUT_MAX_PKT_SIZE);
1571 } else if (dev->gadget.speed == USB_SPEED_HIGH) {
1572 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,
1573 UDC_EP0IN_MAX_PKT_SIZE);
1574 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
1575 UDC_EP0OUT_MAX_PKT_SIZE);
1579 * with suspend bug workaround, ep0 params for gadget driver
1580 * are set at gadget driver bind() call
1582 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
1583 dev->ep[UDC_EP0IN_IX].halted = 0;
1584 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1586 /* init cfg/alt/int */
1587 dev->cur_config = 0;
1592 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1593 static void usb_connect(struct udc *dev)
1596 dev_info(&dev->pdev->dev, "USB Connect\n");
1600 /* put into initial config */
1601 udc_basic_init(dev);
1603 /* enable device setup interrupts */
1604 udc_enable_dev_setup_interrupts(dev);
1608 * Calls gadget with disconnect event and resets the UDC and makes
1609 * initial bringup to be ready for ep0 events
1611 static void usb_disconnect(struct udc *dev)
1614 dev_info(&dev->pdev->dev, "USB Disconnect\n");
1618 /* mask interrupts */
1619 udc_mask_unused_interrupts(dev);
1621 /* REVISIT there doesn't seem to be a point to having this
1622 * talk to a tasklet ... do it directly, we already hold
1623 * the spinlock needed to process the disconnect.
1626 tasklet_schedule(&disconnect_tasklet);
1629 /* Tasklet for disconnect to be outside of interrupt context */
1630 static void udc_tasklet_disconnect(unsigned long par)
1632 struct udc *dev = (struct udc *)(*((struct udc **) par));
1635 DBG(dev, "Tasklet disconnect\n");
1636 spin_lock_irq(&dev->lock);
1639 spin_unlock(&dev->lock);
1640 dev->driver->disconnect(&dev->gadget);
1641 spin_lock(&dev->lock);
1644 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1645 empty_req_queue(&dev->ep[tmp]);
1651 &dev->ep[UDC_EP0IN_IX]);
1654 if (!soft_reset_occured) {
1655 /* init controller by soft reset */
1656 udc_soft_reset(dev);
1657 soft_reset_occured++;
1660 /* re-enable dev interrupts */
1661 udc_enable_dev_setup_interrupts(dev);
1662 /* back to full speed ? */
1663 if (use_fullspeed) {
1664 tmp = readl(&dev->regs->cfg);
1665 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1666 writel(tmp, &dev->regs->cfg);
1669 spin_unlock_irq(&dev->lock);
1672 /* Reset the UDC core */
1673 static void udc_soft_reset(struct udc *dev)
1675 unsigned long flags;
1677 DBG(dev, "Soft reset\n");
1679 * reset possible waiting interrupts, because int.
1680 * status is lost after soft reset,
1681 * ep int. status reset
1683 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
1684 /* device int. status reset */
1685 writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
1687 spin_lock_irqsave(&udc_irq_spinlock, flags);
1688 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
1689 readl(&dev->regs->cfg);
1690 spin_unlock_irqrestore(&udc_irq_spinlock, flags);
1694 /* RDE timer callback to set RDE bit */
1695 static void udc_timer_function(unsigned long v)
1699 spin_lock_irq(&udc_irq_spinlock);
1703 * open the fifo if fifo was filled on last timer call
1707 /* set RDE to receive setup data */
1708 tmp = readl(&udc->regs->ctl);
1709 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1710 writel(tmp, &udc->regs->ctl);
1712 } else if (readl(&udc->regs->sts)
1713 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
1715 * if fifo empty setup polling, do not just
1718 udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV;
1720 add_timer(&udc_timer);
1723 * fifo contains data now, setup timer for opening
1724 * the fifo when timer expires to be able to receive
1725 * setup packets, when data packets gets queued by
1726 * gadget layer then timer will forced to expire with
1727 * set_rde=0 (RDE is set in udc_queue())
1730 /* debug: lhadmot_timer_start = 221070 */
1731 udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS;
1733 add_timer(&udc_timer);
1737 set_rde = -1; /* RDE was set by udc_queue() */
1738 spin_unlock_irq(&udc_irq_spinlock);
1744 /* Handle halt state, used in stall poll timer */
1745 static void udc_handle_halt_state(struct udc_ep *ep)
1748 /* set stall as long not halted */
1749 if (ep->halted == 1) {
1750 tmp = readl(&ep->regs->ctl);
1751 /* STALL cleared ? */
1752 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1754 * FIXME: MSC spec requires that stall remains
1755 * even on receivng of CLEAR_FEATURE HALT. So
1756 * we would set STALL again here to be compliant.
1757 * But with current mass storage drivers this does
1758 * not work (would produce endless host retries).
1759 * So we clear halt on CLEAR_FEATURE.
1761 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1762 tmp |= AMD_BIT(UDC_EPCTL_S);
1763 writel(tmp, &ep->regs->ctl);*/
1765 /* clear NAK by writing CNAK */
1766 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1767 writel(tmp, &ep->regs->ctl);
1769 UDC_QUEUE_CNAK(ep, ep->num);
1774 /* Stall timer callback to poll S bit and set it again after */
1775 static void udc_pollstall_timer_function(unsigned long v)
1780 spin_lock_irq(&udc_stall_spinlock);
1782 * only one IN and OUT endpoints are handled
1785 ep = &udc->ep[UDC_EPIN_IX];
1786 udc_handle_halt_state(ep);
1789 /* OUT poll stall */
1790 ep = &udc->ep[UDC_EPOUT_IX];
1791 udc_handle_halt_state(ep);
1795 /* setup timer again when still halted */
1796 if (!stop_pollstall_timer && halted) {
1797 udc_pollstall_timer.expires = jiffies +
1798 HZ * UDC_POLLSTALL_TIMER_USECONDS
1800 add_timer(&udc_pollstall_timer);
1802 spin_unlock_irq(&udc_stall_spinlock);
1804 if (stop_pollstall_timer)
1805 complete(&on_pollstall_exit);
1808 /* Inits endpoint 0 so that SETUP packets are processed */
1809 static void activate_control_endpoints(struct udc *dev)
1813 DBG(dev, "activate_control_endpoints\n");
1816 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1817 tmp |= AMD_BIT(UDC_EPCTL_F);
1818 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1820 /* set ep0 directions */
1821 dev->ep[UDC_EP0IN_IX].in = 1;
1822 dev->ep[UDC_EP0OUT_IX].in = 0;
1824 /* set buffer size (tx fifo entries) of EP0_IN */
1825 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1826 if (dev->gadget.speed == USB_SPEED_FULL)
1827 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1828 UDC_EPIN_BUFF_SIZE);
1829 else if (dev->gadget.speed == USB_SPEED_HIGH)
1830 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1831 UDC_EPIN_BUFF_SIZE);
1832 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1834 /* set max packet size of EP0_IN */
1835 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1836 if (dev->gadget.speed == USB_SPEED_FULL)
1837 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1838 UDC_EP_MAX_PKT_SIZE);
1839 else if (dev->gadget.speed == USB_SPEED_HIGH)
1840 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1841 UDC_EP_MAX_PKT_SIZE);
1842 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1844 /* set max packet size of EP0_OUT */
1845 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1846 if (dev->gadget.speed == USB_SPEED_FULL)
1847 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1848 UDC_EP_MAX_PKT_SIZE);
1849 else if (dev->gadget.speed == USB_SPEED_HIGH)
1850 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1851 UDC_EP_MAX_PKT_SIZE);
1852 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1854 /* set max packet size of EP0 in UDC CSR */
1855 tmp = readl(&dev->csr->ne[0]);
1856 if (dev->gadget.speed == USB_SPEED_FULL)
1857 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1858 UDC_CSR_NE_MAX_PKT);
1859 else if (dev->gadget.speed == USB_SPEED_HIGH)
1860 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1861 UDC_CSR_NE_MAX_PKT);
1862 writel(tmp, &dev->csr->ne[0]);
1865 dev->ep[UDC_EP0OUT_IX].td->status |=
1866 AMD_BIT(UDC_DMA_OUT_STS_L);
1867 /* write dma desc address */
1868 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
1869 &dev->ep[UDC_EP0OUT_IX].regs->subptr);
1870 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
1871 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
1872 /* stop RDE timer */
1873 if (timer_pending(&udc_timer)) {
1875 mod_timer(&udc_timer, jiffies - 1);
1877 /* stop pollstall timer */
1878 if (timer_pending(&udc_pollstall_timer))
1879 mod_timer(&udc_pollstall_timer, jiffies - 1);
1881 tmp = readl(&dev->regs->ctl);
1882 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1883 | AMD_BIT(UDC_DEVCTL_RDE)
1884 | AMD_BIT(UDC_DEVCTL_TDE);
1885 if (use_dma_bufferfill_mode)
1886 tmp |= AMD_BIT(UDC_DEVCTL_BF);
1887 else if (use_dma_ppb_du)
1888 tmp |= AMD_BIT(UDC_DEVCTL_DU);
1889 writel(tmp, &dev->regs->ctl);
1892 /* clear NAK by writing CNAK for EP0IN */
1893 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1894 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1895 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1896 dev->ep[UDC_EP0IN_IX].naking = 0;
1897 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
1899 /* clear NAK by writing CNAK for EP0OUT */
1900 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1901 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1902 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1903 dev->ep[UDC_EP0OUT_IX].naking = 0;
1904 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
1907 /* Make endpoint 0 ready for control traffic */
1908 static int setup_ep0(struct udc *dev)
1910 activate_control_endpoints(dev);
1911 /* enable ep0 interrupts */
1912 udc_enable_ep0_interrupts(dev);
1913 /* enable device setup interrupts */
1914 udc_enable_dev_setup_interrupts(dev);
1919 /* Called by gadget driver to register itself */
1920 static int amd5536_udc_start(struct usb_gadget *g,
1921 struct usb_gadget_driver *driver)
1923 struct udc *dev = to_amd5536_udc(g);
1926 driver->driver.bus = NULL;
1927 dev->driver = driver;
1929 /* Some gadget drivers use both ep0 directions.
1930 * NOTE: to gadget driver, ep0 is just one endpoint...
1932 dev->ep[UDC_EP0OUT_IX].ep.driver_data =
1933 dev->ep[UDC_EP0IN_IX].ep.driver_data;
1935 /* get ready for ep0 traffic */
1939 tmp = readl(&dev->regs->ctl);
1940 tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
1941 writel(tmp, &dev->regs->ctl);
1948 /* shutdown requests and disconnect from gadget */
1950 shutdown(struct udc *dev, struct usb_gadget_driver *driver)
1951 __releases(dev->lock)
1952 __acquires(dev->lock)
1956 /* empty queues and init hardware */
1957 udc_basic_init(dev);
1959 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1960 empty_req_queue(&dev->ep[tmp]);
1962 udc_setup_endpoints(dev);
1965 /* Called by gadget driver to unregister itself */
1966 static int amd5536_udc_stop(struct usb_gadget *g,
1967 struct usb_gadget_driver *driver)
1969 struct udc *dev = to_amd5536_udc(g);
1970 unsigned long flags;
1973 spin_lock_irqsave(&dev->lock, flags);
1974 udc_mask_unused_interrupts(dev);
1975 shutdown(dev, driver);
1976 spin_unlock_irqrestore(&dev->lock, flags);
1981 tmp = readl(&dev->regs->ctl);
1982 tmp |= AMD_BIT(UDC_DEVCTL_SD);
1983 writel(tmp, &dev->regs->ctl);
1988 /* Clear pending NAK bits */
1989 static void udc_process_cnak_queue(struct udc *dev)
1995 DBG(dev, "CNAK pending queue processing\n");
1996 for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
1997 if (cnak_pending & (1 << tmp)) {
1998 DBG(dev, "CNAK pending for ep%d\n", tmp);
1999 /* clear NAK by writing CNAK */
2000 reg = readl(&dev->ep[tmp].regs->ctl);
2001 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2002 writel(reg, &dev->ep[tmp].regs->ctl);
2003 dev->ep[tmp].naking = 0;
2004 UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2007 /* ... and ep0out */
2008 if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
2009 DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
2010 /* clear NAK by writing CNAK */
2011 reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2012 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2013 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2014 dev->ep[UDC_EP0OUT_IX].naking = 0;
2015 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
2016 dev->ep[UDC_EP0OUT_IX].num);
2020 /* Enabling RX DMA after setup packet */
2021 static void udc_ep0_set_rde(struct udc *dev)
2025 * only enable RXDMA when no data endpoint enabled
2028 if (!dev->data_ep_enabled || dev->data_ep_queued) {
2032 * setup timer for enabling RDE (to not enable
2033 * RXFIFO DMA for data endpoints to early)
2035 if (set_rde != 0 && !timer_pending(&udc_timer)) {
2037 jiffies + HZ/UDC_RDE_TIMER_DIV;
2040 add_timer(&udc_timer);
2047 /* Interrupt handler for data OUT traffic */
2048 static irqreturn_t udc_data_out_isr(struct udc *dev, int ep_ix)
2050 irqreturn_t ret_val = IRQ_NONE;
2053 struct udc_request *req;
2055 struct udc_data_dma *td = NULL;
2058 VDBG(dev, "ep%d irq\n", ep_ix);
2059 ep = &dev->ep[ep_ix];
2061 tmp = readl(&ep->regs->sts);
2064 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2065 DBG(dev, "BNA ep%dout occurred - DESPTR = %x\n",
2066 ep->num, readl(&ep->regs->desptr));
2068 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2069 if (!ep->cancel_transfer)
2070 ep->bna_occurred = 1;
2072 ep->cancel_transfer = 0;
2073 ret_val = IRQ_HANDLED;
2078 if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
2079 dev_err(&dev->pdev->dev, "HE ep%dout occurred\n", ep->num);
2082 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2083 ret_val = IRQ_HANDLED;
2087 if (!list_empty(&ep->queue)) {
2090 req = list_entry(ep->queue.next,
2091 struct udc_request, queue);
2094 udc_rxfifo_pending = 1;
2096 VDBG(dev, "req = %p\n", req);
2101 if (req && udc_rxfifo_read(ep, req)) {
2102 ret_val = IRQ_HANDLED;
2105 complete_req(ep, req, 0);
2107 if (!list_empty(&ep->queue) && !ep->halted) {
2108 req = list_entry(ep->queue.next,
2109 struct udc_request, queue);
2115 } else if (!ep->cancel_transfer && req != NULL) {
2116 ret_val = IRQ_HANDLED;
2118 /* check for DMA done */
2120 dma_done = AMD_GETBITS(req->td_data->status,
2121 UDC_DMA_OUT_STS_BS);
2122 /* packet per buffer mode - rx bytes */
2125 * if BNA occurred then recover desc. from
2128 if (ep->bna_occurred) {
2129 VDBG(dev, "Recover desc. from BNA dummy\n");
2130 memcpy(req->td_data, ep->bna_dummy_req->td_data,
2131 sizeof(struct udc_data_dma));
2132 ep->bna_occurred = 0;
2133 udc_init_bna_dummy(ep->req);
2135 td = udc_get_last_dma_desc(req);
2136 dma_done = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_BS);
2138 if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
2139 /* buffer fill mode - rx bytes */
2141 /* received number bytes */
2142 count = AMD_GETBITS(req->td_data->status,
2143 UDC_DMA_OUT_STS_RXBYTES);
2144 VDBG(dev, "rx bytes=%u\n", count);
2145 /* packet per buffer mode - rx bytes */
2147 VDBG(dev, "req->td_data=%p\n", req->td_data);
2148 VDBG(dev, "last desc = %p\n", td);
2149 /* received number bytes */
2150 if (use_dma_ppb_du) {
2151 /* every desc. counts bytes */
2152 count = udc_get_ppbdu_rxbytes(req);
2154 /* last desc. counts bytes */
2155 count = AMD_GETBITS(td->status,
2156 UDC_DMA_OUT_STS_RXBYTES);
2157 if (!count && req->req.length
2158 == UDC_DMA_MAXPACKET) {
2160 * on 64k packets the RXBYTES
2163 count = UDC_DMA_MAXPACKET;
2166 VDBG(dev, "last desc rx bytes=%u\n", count);
2169 tmp = req->req.length - req->req.actual;
2171 if ((tmp % ep->ep.maxpacket) != 0) {
2172 DBG(dev, "%s: rx %db, space=%db\n",
2173 ep->ep.name, count, tmp);
2174 req->req.status = -EOVERFLOW;
2178 req->req.actual += count;
2180 /* complete request */
2181 complete_req(ep, req, 0);
2184 if (!list_empty(&ep->queue) && !ep->halted) {
2185 req = list_entry(ep->queue.next,
2189 * DMA may be already started by udc_queue()
2190 * called by gadget drivers completion
2191 * routine. This happens when queue
2192 * holds one request only.
2194 if (req->dma_going == 0) {
2196 if (prep_dma(ep, req, GFP_ATOMIC) != 0)
2198 /* write desc pointer */
2199 writel(req->td_phys,
2207 * implant BNA dummy descriptor to allow
2208 * RXFIFO opening by RDE
2210 if (ep->bna_dummy_req) {
2211 /* write desc pointer */
2212 writel(ep->bna_dummy_req->td_phys,
2214 ep->bna_occurred = 0;
2218 * schedule timer for setting RDE if queue
2219 * remains empty to allow ep0 packets pass
2223 && !timer_pending(&udc_timer)) {
2226 + HZ*UDC_RDE_TIMER_SECONDS;
2229 add_timer(&udc_timer);
2231 if (ep->num != UDC_EP0OUT_IX)
2232 dev->data_ep_queued = 0;
2237 * RX DMA must be reenabled for each desc in PPBDU mode
2238 * and must be enabled for PPBNDU mode in case of BNA
2243 } else if (ep->cancel_transfer) {
2244 ret_val = IRQ_HANDLED;
2245 ep->cancel_transfer = 0;
2248 /* check pending CNAKS */
2250 /* CNAk processing when rxfifo empty only */
2251 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2252 udc_process_cnak_queue(dev);
2255 /* clear OUT bits in ep status */
2256 writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
2261 /* Interrupt handler for data IN traffic */
2262 static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
2264 irqreturn_t ret_val = IRQ_NONE;
2268 struct udc_request *req;
2269 struct udc_data_dma *td;
2273 ep = &dev->ep[ep_ix];
2275 epsts = readl(&ep->regs->sts);
2278 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) {
2279 dev_err(&dev->pdev->dev,
2280 "BNA ep%din occurred - DESPTR = %08lx\n",
2282 (unsigned long) readl(&ep->regs->desptr));
2285 writel(epsts, &ep->regs->sts);
2286 ret_val = IRQ_HANDLED;
2291 if (epsts & AMD_BIT(UDC_EPSTS_HE)) {
2292 dev_err(&dev->pdev->dev,
2293 "HE ep%dn occurred - DESPTR = %08lx\n",
2294 ep->num, (unsigned long) readl(&ep->regs->desptr));
2297 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2298 ret_val = IRQ_HANDLED;
2302 /* DMA completion */
2303 if (epsts & AMD_BIT(UDC_EPSTS_TDC)) {
2304 VDBG(dev, "TDC set- completion\n");
2305 ret_val = IRQ_HANDLED;
2306 if (!ep->cancel_transfer && !list_empty(&ep->queue)) {
2307 req = list_entry(ep->queue.next,
2308 struct udc_request, queue);
2310 * length bytes transferred
2311 * check dma done of last desc. in PPBDU mode
2313 if (use_dma_ppb_du) {
2314 td = udc_get_last_dma_desc(req);
2317 AMD_GETBITS(td->status,
2319 /* don't care DMA done */
2320 req->req.actual = req->req.length;
2323 /* assume all bytes transferred */
2324 req->req.actual = req->req.length;
2327 if (req->req.actual == req->req.length) {
2329 complete_req(ep, req, 0);
2331 /* further request available ? */
2332 if (list_empty(&ep->queue)) {
2333 /* disable interrupt */
2334 tmp = readl(&dev->regs->ep_irqmsk);
2335 tmp |= AMD_BIT(ep->num);
2336 writel(tmp, &dev->regs->ep_irqmsk);
2340 ep->cancel_transfer = 0;
2344 * status reg has IN bit set and TDC not set (if TDC was handled,
2345 * IN must not be handled (UDC defect) ?
2347 if ((epsts & AMD_BIT(UDC_EPSTS_IN))
2348 && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) {
2349 ret_val = IRQ_HANDLED;
2350 if (!list_empty(&ep->queue)) {
2352 req = list_entry(ep->queue.next,
2353 struct udc_request, queue);
2357 udc_txfifo_write(ep, &req->req);
2358 len = req->req.length - req->req.actual;
2359 if (len > ep->ep.maxpacket)
2360 len = ep->ep.maxpacket;
2361 req->req.actual += len;
2362 if (req->req.actual == req->req.length
2363 || (len != ep->ep.maxpacket)) {
2365 complete_req(ep, req, 0);
2368 } else if (req && !req->dma_going) {
2369 VDBG(dev, "IN DMA : req=%p req->td_data=%p\n",
2376 * unset L bit of first desc.
2379 if (use_dma_ppb && req->req.length >
2381 req->td_data->status &=
2386 /* write desc pointer */
2387 writel(req->td_phys, &ep->regs->desptr);
2389 /* set HOST READY */
2390 req->td_data->status =
2392 req->td_data->status,
2393 UDC_DMA_IN_STS_BS_HOST_READY,
2396 /* set poll demand bit */
2397 tmp = readl(&ep->regs->ctl);
2398 tmp |= AMD_BIT(UDC_EPCTL_P);
2399 writel(tmp, &ep->regs->ctl);
2403 } else if (!use_dma && ep->in) {
2404 /* disable interrupt */
2406 &dev->regs->ep_irqmsk);
2407 tmp |= AMD_BIT(ep->num);
2409 &dev->regs->ep_irqmsk);
2412 /* clear status bits */
2413 writel(epsts, &ep->regs->sts);
2420 /* Interrupt handler for Control OUT traffic */
2421 static irqreturn_t udc_control_out_isr(struct udc *dev)
2422 __releases(dev->lock)
2423 __acquires(dev->lock)
2425 irqreturn_t ret_val = IRQ_NONE;
2427 int setup_supported;
2431 struct udc_ep *ep_tmp;
2433 ep = &dev->ep[UDC_EP0OUT_IX];
2436 writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2438 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2439 /* check BNA and clear if set */
2440 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2441 VDBG(dev, "ep0: BNA set\n");
2442 writel(AMD_BIT(UDC_EPSTS_BNA),
2443 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2444 ep->bna_occurred = 1;
2445 ret_val = IRQ_HANDLED;
2449 /* type of data: SETUP or DATA 0 bytes */
2450 tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2451 VDBG(dev, "data_typ = %x\n", tmp);
2454 if (tmp == UDC_EPSTS_OUT_SETUP) {
2455 ret_val = IRQ_HANDLED;
2457 ep->dev->stall_ep0in = 0;
2458 dev->waiting_zlp_ack_ep0in = 0;
2460 /* set NAK for EP0_IN */
2461 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2462 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2463 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2464 dev->ep[UDC_EP0IN_IX].naking = 1;
2465 /* get setup data */
2468 /* clear OUT bits in ep status */
2469 writel(UDC_EPSTS_OUT_CLEAR,
2470 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2472 setup_data.data[0] =
2473 dev->ep[UDC_EP0OUT_IX].td_stp->data12;
2474 setup_data.data[1] =
2475 dev->ep[UDC_EP0OUT_IX].td_stp->data34;
2476 /* set HOST READY */
2477 dev->ep[UDC_EP0OUT_IX].td_stp->status =
2478 UDC_DMA_STP_STS_BS_HOST_READY;
2481 udc_rxfifo_read_dwords(dev, setup_data.data, 2);
2484 /* determine direction of control data */
2485 if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) {
2486 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
2488 udc_ep0_set_rde(dev);
2491 dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
2493 * implant BNA dummy descriptor to allow RXFIFO opening
2496 if (ep->bna_dummy_req) {
2497 /* write desc pointer */
2498 writel(ep->bna_dummy_req->td_phys,
2499 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2500 ep->bna_occurred = 0;
2504 dev->ep[UDC_EP0OUT_IX].naking = 1;
2506 * setup timer for enabling RDE (to not enable
2507 * RXFIFO DMA for data to early)
2510 if (!timer_pending(&udc_timer)) {
2511 udc_timer.expires = jiffies +
2512 HZ/UDC_RDE_TIMER_DIV;
2514 add_timer(&udc_timer);
2519 * mass storage reset must be processed here because
2520 * next packet may be a CLEAR_FEATURE HALT which would not
2521 * clear the stall bit when no STALL handshake was received
2522 * before (autostall can cause this)
2524 if (setup_data.data[0] == UDC_MSCRES_DWORD0
2525 && setup_data.data[1] == UDC_MSCRES_DWORD1) {
2526 DBG(dev, "MSC Reset\n");
2529 * only one IN and OUT endpoints are handled
2531 ep_tmp = &udc->ep[UDC_EPIN_IX];
2532 udc_set_halt(&ep_tmp->ep, 0);
2533 ep_tmp = &udc->ep[UDC_EPOUT_IX];
2534 udc_set_halt(&ep_tmp->ep, 0);
2537 /* call gadget with setup data received */
2538 spin_unlock(&dev->lock);
2539 setup_supported = dev->driver->setup(&dev->gadget,
2540 &setup_data.request);
2541 spin_lock(&dev->lock);
2543 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2544 /* ep0 in returns data (not zlp) on IN phase */
2545 if (setup_supported >= 0 && setup_supported <
2546 UDC_EP0IN_MAXPACKET) {
2547 /* clear NAK by writing CNAK in EP0_IN */
2548 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2549 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2550 dev->ep[UDC_EP0IN_IX].naking = 0;
2551 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
2553 /* if unsupported request then stall */
2554 } else if (setup_supported < 0) {
2555 tmp |= AMD_BIT(UDC_EPCTL_S);
2556 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2558 dev->waiting_zlp_ack_ep0in = 1;
2561 /* clear NAK by writing CNAK in EP0_OUT */
2563 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2564 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2565 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2566 dev->ep[UDC_EP0OUT_IX].naking = 0;
2567 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
2571 /* clear OUT bits in ep status */
2572 writel(UDC_EPSTS_OUT_CLEAR,
2573 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2576 /* data packet 0 bytes */
2577 } else if (tmp == UDC_EPSTS_OUT_DATA) {
2578 /* clear OUT bits in ep status */
2579 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2581 /* get setup data: only 0 packet */
2583 /* no req if 0 packet, just reactivate */
2584 if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
2587 /* set HOST READY */
2588 dev->ep[UDC_EP0OUT_IX].td->status =
2590 dev->ep[UDC_EP0OUT_IX].td->status,
2591 UDC_DMA_OUT_STS_BS_HOST_READY,
2592 UDC_DMA_OUT_STS_BS);
2594 udc_ep0_set_rde(dev);
2595 ret_val = IRQ_HANDLED;
2599 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2600 /* re-program desc. pointer for possible ZLPs */
2601 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2602 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2604 udc_ep0_set_rde(dev);
2608 /* received number bytes */
2609 count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2610 count = AMD_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE);
2611 /* out data for fifo mode not working */
2614 /* 0 packet or real data ? */
2616 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2618 /* dummy read confirm */
2619 readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
2620 ret_val = IRQ_HANDLED;
2625 /* check pending CNAKS */
2627 /* CNAk processing when rxfifo empty only */
2628 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2629 udc_process_cnak_queue(dev);
2636 /* Interrupt handler for Control IN traffic */
2637 static irqreturn_t udc_control_in_isr(struct udc *dev)
2639 irqreturn_t ret_val = IRQ_NONE;
2642 struct udc_request *req;
2645 ep = &dev->ep[UDC_EP0IN_IX];
2648 writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
2650 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2651 /* DMA completion */
2652 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
2653 VDBG(dev, "isr: TDC clear\n");
2654 ret_val = IRQ_HANDLED;
2657 writel(AMD_BIT(UDC_EPSTS_TDC),
2658 &dev->ep[UDC_EP0IN_IX].regs->sts);
2660 /* status reg has IN bit set ? */
2661 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2662 ret_val = IRQ_HANDLED;
2666 writel(AMD_BIT(UDC_EPSTS_IN),
2667 &dev->ep[UDC_EP0IN_IX].regs->sts);
2669 if (dev->stall_ep0in) {
2670 DBG(dev, "stall ep0in\n");
2672 tmp = readl(&ep->regs->ctl);
2673 tmp |= AMD_BIT(UDC_EPCTL_S);
2674 writel(tmp, &ep->regs->ctl);
2676 if (!list_empty(&ep->queue)) {
2678 req = list_entry(ep->queue.next,
2679 struct udc_request, queue);
2682 /* write desc pointer */
2683 writel(req->td_phys, &ep->regs->desptr);
2684 /* set HOST READY */
2685 req->td_data->status =
2687 req->td_data->status,
2688 UDC_DMA_STP_STS_BS_HOST_READY,
2689 UDC_DMA_STP_STS_BS);
2691 /* set poll demand bit */
2693 readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2694 tmp |= AMD_BIT(UDC_EPCTL_P);
2696 &dev->ep[UDC_EP0IN_IX].regs->ctl);
2698 /* all bytes will be transferred */
2699 req->req.actual = req->req.length;
2702 complete_req(ep, req, 0);
2706 udc_txfifo_write(ep, &req->req);
2708 /* lengh bytes transferred */
2709 len = req->req.length - req->req.actual;
2710 if (len > ep->ep.maxpacket)
2711 len = ep->ep.maxpacket;
2713 req->req.actual += len;
2714 if (req->req.actual == req->req.length
2715 || (len != ep->ep.maxpacket)) {
2717 complete_req(ep, req, 0);
2724 dev->stall_ep0in = 0;
2727 writel(AMD_BIT(UDC_EPSTS_IN),
2728 &dev->ep[UDC_EP0IN_IX].regs->sts);
2736 /* Interrupt handler for global device events */
2737 static irqreturn_t udc_dev_isr(struct udc *dev, u32 dev_irq)
2738 __releases(dev->lock)
2739 __acquires(dev->lock)
2741 irqreturn_t ret_val = IRQ_NONE;
2748 /* SET_CONFIG irq ? */
2749 if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) {
2750 ret_val = IRQ_HANDLED;
2752 /* read config value */
2753 tmp = readl(&dev->regs->sts);
2754 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2755 DBG(dev, "SET_CONFIG interrupt: config=%d\n", cfg);
2756 dev->cur_config = cfg;
2757 dev->set_cfg_not_acked = 1;
2759 /* make usb request for gadget driver */
2760 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2761 setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
2762 setup_data.request.wValue = cpu_to_le16(dev->cur_config);
2764 /* programm the NE registers */
2765 for (i = 0; i < UDC_EP_NUM; i++) {
2769 /* ep ix in UDC CSR register space */
2770 udc_csr_epix = ep->num;
2775 /* ep ix in UDC CSR register space */
2776 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2779 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2781 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2784 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2786 /* clear stall bits */
2788 tmp = readl(&ep->regs->ctl);
2789 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2790 writel(tmp, &ep->regs->ctl);
2792 /* call gadget zero with setup data received */
2793 spin_unlock(&dev->lock);
2794 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2795 spin_lock(&dev->lock);
2797 } /* SET_INTERFACE ? */
2798 if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) {
2799 ret_val = IRQ_HANDLED;
2801 dev->set_cfg_not_acked = 1;
2802 /* read interface and alt setting values */
2803 tmp = readl(&dev->regs->sts);
2804 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2805 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2807 /* make usb request for gadget driver */
2808 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2809 setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
2810 setup_data.request.bRequestType = USB_RECIP_INTERFACE;
2811 setup_data.request.wValue = cpu_to_le16(dev->cur_alt);
2812 setup_data.request.wIndex = cpu_to_le16(dev->cur_intf);
2814 DBG(dev, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2815 dev->cur_alt, dev->cur_intf);
2817 /* programm the NE registers */
2818 for (i = 0; i < UDC_EP_NUM; i++) {
2822 /* ep ix in UDC CSR register space */
2823 udc_csr_epix = ep->num;
2828 /* ep ix in UDC CSR register space */
2829 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2834 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2836 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2838 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2840 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2843 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2845 /* clear stall bits */
2847 tmp = readl(&ep->regs->ctl);
2848 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2849 writel(tmp, &ep->regs->ctl);
2852 /* call gadget zero with setup data received */
2853 spin_unlock(&dev->lock);
2854 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2855 spin_lock(&dev->lock);
2858 if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) {
2859 DBG(dev, "USB Reset interrupt\n");
2860 ret_val = IRQ_HANDLED;
2862 /* allow soft reset when suspend occurs */
2863 soft_reset_occured = 0;
2865 dev->waiting_zlp_ack_ep0in = 0;
2866 dev->set_cfg_not_acked = 0;
2868 /* mask not needed interrupts */
2869 udc_mask_unused_interrupts(dev);
2871 /* call gadget to resume and reset configs etc. */
2872 spin_unlock(&dev->lock);
2873 if (dev->sys_suspended && dev->driver->resume) {
2874 dev->driver->resume(&dev->gadget);
2875 dev->sys_suspended = 0;
2877 dev->driver->disconnect(&dev->gadget);
2878 spin_lock(&dev->lock);
2880 /* disable ep0 to empty req queue */
2881 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2882 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2884 /* soft reset when rxfifo not empty */
2885 tmp = readl(&dev->regs->sts);
2886 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2887 && !soft_reset_after_usbreset_occured) {
2888 udc_soft_reset(dev);
2889 soft_reset_after_usbreset_occured++;
2893 * DMA reset to kill potential old DMA hw hang,
2894 * POLL bit is already reset by ep_init() through
2897 DBG(dev, "DMA machine reset\n");
2898 tmp = readl(&dev->regs->cfg);
2899 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2900 writel(tmp, &dev->regs->cfg);
2902 /* put into initial config */
2903 udc_basic_init(dev);
2905 /* enable device setup interrupts */
2906 udc_enable_dev_setup_interrupts(dev);
2908 /* enable suspend interrupt */
2909 tmp = readl(&dev->regs->irqmsk);
2910 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2911 writel(tmp, &dev->regs->irqmsk);
2914 if (dev_irq & AMD_BIT(UDC_DEVINT_US)) {
2915 DBG(dev, "USB Suspend interrupt\n");
2916 ret_val = IRQ_HANDLED;
2917 if (dev->driver->suspend) {
2918 spin_unlock(&dev->lock);
2919 dev->sys_suspended = 1;
2920 dev->driver->suspend(&dev->gadget);
2921 spin_lock(&dev->lock);
2924 if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) {
2925 DBG(dev, "ENUM interrupt\n");
2926 ret_val = IRQ_HANDLED;
2927 soft_reset_after_usbreset_occured = 0;
2929 /* disable ep0 to empty req queue */
2930 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2931 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2933 /* link up all endpoints */
2934 udc_setup_endpoints(dev);
2935 dev_info(&dev->pdev->dev, "Connect: %s\n",
2936 usb_speed_string(dev->gadget.speed));
2939 activate_control_endpoints(dev);
2941 /* enable ep0 interrupts */
2942 udc_enable_ep0_interrupts(dev);
2944 /* session valid change interrupt */
2945 if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) {
2946 DBG(dev, "USB SVC interrupt\n");
2947 ret_val = IRQ_HANDLED;
2949 /* check that session is not valid to detect disconnect */
2950 tmp = readl(&dev->regs->sts);
2951 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
2952 /* disable suspend interrupt */
2953 tmp = readl(&dev->regs->irqmsk);
2954 tmp |= AMD_BIT(UDC_DEVINT_US);
2955 writel(tmp, &dev->regs->irqmsk);
2956 DBG(dev, "USB Disconnect (session valid low)\n");
2957 /* cleanup on disconnect */
2958 usb_disconnect(udc);
2966 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
2967 static irqreturn_t udc_irq(int irq, void *pdev)
2969 struct udc *dev = pdev;
2973 irqreturn_t ret_val = IRQ_NONE;
2975 spin_lock(&dev->lock);
2977 /* check for ep irq */
2978 reg = readl(&dev->regs->ep_irqsts);
2980 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0))
2981 ret_val |= udc_control_out_isr(dev);
2982 if (reg & AMD_BIT(UDC_EPINT_IN_EP0))
2983 ret_val |= udc_control_in_isr(dev);
2989 for (i = 1; i < UDC_EP_NUM; i++) {
2991 if (!(reg & ep_irq) || i == UDC_EPINT_OUT_EP0)
2994 /* clear irq status */
2995 writel(ep_irq, &dev->regs->ep_irqsts);
2997 /* irq for out ep ? */
2998 if (i > UDC_EPIN_NUM)
2999 ret_val |= udc_data_out_isr(dev, i);
3001 ret_val |= udc_data_in_isr(dev, i);
3007 /* check for dev irq */
3008 reg = readl(&dev->regs->irqsts);
3011 writel(reg, &dev->regs->irqsts);
3012 ret_val |= udc_dev_isr(dev, reg);
3016 spin_unlock(&dev->lock);
3020 /* Tears down device */
3021 static void gadget_release(struct device *pdev)
3023 struct amd5536udc *dev = dev_get_drvdata(pdev);
3027 /* Cleanup on device remove */
3028 static void udc_remove(struct udc *dev)
3032 if (timer_pending(&udc_timer))
3033 wait_for_completion(&on_exit);
3035 del_timer_sync(&udc_timer);
3036 /* remove pollstall timer */
3037 stop_pollstall_timer++;
3038 if (timer_pending(&udc_pollstall_timer))
3039 wait_for_completion(&on_pollstall_exit);
3040 if (udc_pollstall_timer.data)
3041 del_timer_sync(&udc_pollstall_timer);
3045 /* Reset all pci context */
3046 static void udc_pci_remove(struct pci_dev *pdev)
3050 dev = pci_get_drvdata(pdev);
3052 usb_del_gadget_udc(&udc->gadget);
3053 /* gadget driver must not be registered */
3054 BUG_ON(dev->driver != NULL);
3056 /* dma pool cleanup */
3057 if (dev->data_requests)
3058 pci_pool_destroy(dev->data_requests);
3060 if (dev->stp_requests) {
3061 /* cleanup DMA desc's for ep0in */
3062 pci_pool_free(dev->stp_requests,
3063 dev->ep[UDC_EP0OUT_IX].td_stp,
3064 dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3065 pci_pool_free(dev->stp_requests,
3066 dev->ep[UDC_EP0OUT_IX].td,
3067 dev->ep[UDC_EP0OUT_IX].td_phys);
3069 pci_pool_destroy(dev->stp_requests);
3072 /* reset controller */
3073 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
3074 if (dev->irq_registered)
3075 free_irq(pdev->irq, dev);
3078 if (dev->mem_region)
3079 release_mem_region(pci_resource_start(pdev, 0),
3080 pci_resource_len(pdev, 0));
3082 pci_disable_device(pdev);
3087 /* create dma pools on init */
3088 static int init_dma_pools(struct udc *dev)
3090 struct udc_stp_dma *td_stp;
3091 struct udc_data_dma *td_data;
3094 /* consistent DMA mode setting ? */
3096 use_dma_bufferfill_mode = 0;
3099 use_dma_bufferfill_mode = 1;
3103 dev->data_requests = dma_pool_create("data_requests", NULL,
3104 sizeof(struct udc_data_dma), 0, 0);
3105 if (!dev->data_requests) {
3106 DBG(dev, "can't get request data pool\n");
3111 /* EP0 in dma regs = dev control regs */
3112 dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;
3114 /* dma desc for setup data */
3115 dev->stp_requests = dma_pool_create("setup requests", NULL,
3116 sizeof(struct udc_stp_dma), 0, 0);
3117 if (!dev->stp_requests) {
3118 DBG(dev, "can't get stp request pool\n");
3123 td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3124 &dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3125 if (td_stp == NULL) {
3129 dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
3131 /* data: 0 packets !? */
3132 td_data = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3133 &dev->ep[UDC_EP0OUT_IX].td_phys);
3134 if (td_data == NULL) {
3138 dev->ep[UDC_EP0OUT_IX].td = td_data;
3145 /* Called by pci bus driver to init pci context */
3146 static int udc_pci_probe(
3147 struct pci_dev *pdev,
3148 const struct pci_device_id *id
3152 unsigned long resource;
3158 dev_dbg(&pdev->dev, "already probed\n");
3163 dev = kzalloc(sizeof(struct udc), GFP_KERNEL);
3170 if (pci_enable_device(pdev) < 0) {
3178 /* PCI resource allocation */
3179 resource = pci_resource_start(pdev, 0);
3180 len = pci_resource_len(pdev, 0);
3182 if (!request_mem_region(resource, len, name)) {
3183 dev_dbg(&pdev->dev, "pci device used already\n");
3189 dev->mem_region = 1;
3191 dev->virt_addr = ioremap_nocache(resource, len);
3192 if (dev->virt_addr == NULL) {
3193 dev_dbg(&pdev->dev, "start address cannot be mapped\n");
3201 dev_err(&pdev->dev, "irq not set\n");
3208 spin_lock_init(&dev->lock);
3209 /* udc csr registers base */
3210 dev->csr = dev->virt_addr + UDC_CSR_ADDR;
3211 /* dev registers base */
3212 dev->regs = dev->virt_addr + UDC_DEVCFG_ADDR;
3213 /* ep registers base */
3214 dev->ep_regs = dev->virt_addr + UDC_EPREGS_ADDR;
3216 dev->rxfifo = (u32 __iomem *)(dev->virt_addr + UDC_RXFIFO_ADDR);
3217 dev->txfifo = (u32 __iomem *)(dev->virt_addr + UDC_TXFIFO_ADDR);
3219 if (request_irq(pdev->irq, udc_irq, IRQF_SHARED, name, dev) != 0) {
3220 dev_dbg(&pdev->dev, "request_irq(%d) fail\n", pdev->irq);
3226 dev->irq_registered = 1;
3228 pci_set_drvdata(pdev, dev);
3230 /* chip revision for Hs AMD5536 */
3231 dev->chiprev = pdev->revision;
3233 pci_set_master(pdev);
3234 pci_try_set_mwi(pdev);
3236 /* init dma pools */
3238 retval = init_dma_pools(dev);
3243 dev->phys_addr = resource;
3244 dev->irq = pdev->irq;
3247 /* general probing */
3248 if (udc_probe(dev) == 0)
3253 udc_pci_remove(pdev);
3258 static int udc_probe(struct udc *dev)
3264 /* mark timer as not initialized */
3266 udc_pollstall_timer.data = 0;
3268 /* device struct setup */
3269 dev->gadget.ops = &udc_ops;
3271 dev_set_name(&dev->gadget.dev, "gadget");
3272 dev->gadget.name = name;
3273 dev->gadget.max_speed = USB_SPEED_HIGH;
3275 /* init registers, interrupts, ... */
3276 startup_registers(dev);
3278 dev_info(&dev->pdev->dev, "%s\n", mod_desc);
3280 snprintf(tmp, sizeof tmp, "%d", dev->irq);
3281 dev_info(&dev->pdev->dev,
3282 "irq %s, pci mem %08lx, chip rev %02x(Geode5536 %s)\n",
3283 tmp, dev->phys_addr, dev->chiprev,
3284 (dev->chiprev == UDC_HSA0_REV) ? "A0" : "B1");
3285 strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3286 if (dev->chiprev == UDC_HSA0_REV) {
3287 dev_err(&dev->pdev->dev, "chip revision is A0; too old\n");
3291 dev_info(&dev->pdev->dev,
3292 "driver version: %s(for Geode5536 B1)\n", tmp);
3295 retval = usb_add_gadget_udc_release(&udc->pdev->dev, &dev->gadget,
3301 init_timer(&udc_timer);
3302 udc_timer.function = udc_timer_function;
3304 /* timer pollstall init */
3305 init_timer(&udc_pollstall_timer);
3306 udc_pollstall_timer.function = udc_pollstall_timer_function;
3307 udc_pollstall_timer.data = 1;
3310 reg = readl(&dev->regs->ctl);
3311 reg |= AMD_BIT(UDC_DEVCTL_SD);
3312 writel(reg, &dev->regs->ctl);
3314 /* print dev register info */
3323 /* Initiates a remote wakeup */
3324 static int udc_remote_wakeup(struct udc *dev)
3326 unsigned long flags;
3329 DBG(dev, "UDC initiates remote wakeup\n");
3331 spin_lock_irqsave(&dev->lock, flags);
3333 tmp = readl(&dev->regs->ctl);
3334 tmp |= AMD_BIT(UDC_DEVCTL_RES);
3335 writel(tmp, &dev->regs->ctl);
3336 tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES);
3337 writel(tmp, &dev->regs->ctl);
3339 spin_unlock_irqrestore(&dev->lock, flags);
3343 /* PCI device parameters */
3344 static const struct pci_device_id pci_id[] = {
3346 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x2096),
3347 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3348 .class_mask = 0xffffffff,
3352 MODULE_DEVICE_TABLE(pci, pci_id);
3355 static struct pci_driver udc_pci_driver = {
3356 .name = (char *) name,
3358 .probe = udc_pci_probe,
3359 .remove = udc_pci_remove,
3362 module_pci_driver(udc_pci_driver);
3364 MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION);
3365 MODULE_AUTHOR("Thomas Dahlmann");
3366 MODULE_LICENSE("GPL");