2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 * Author: Chao Xie <chao.xie@marvell.com>
4 * Neil Zhang <zhangwm@marvell.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmapool.h>
16 #include <linux/kernel.h>
17 #include <linux/delay.h>
18 #include <linux/ioport.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <linux/init.h>
24 #include <linux/timer.h>
25 #include <linux/list.h>
26 #include <linux/interrupt.h>
27 #include <linux/moduleparam.h>
28 #include <linux/device.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/otg.h>
34 #include <linux/irq.h>
35 #include <linux/platform_device.h>
36 #include <linux/clk.h>
37 #include <linux/platform_data/mv_usb.h>
38 #include <asm/unaligned.h>
42 #define DRIVER_DESC "Marvell PXA USB Device Controller driver"
43 #define DRIVER_VERSION "8 Nov 2010"
45 #define ep_dir(ep) (((ep)->ep_num == 0) ? \
46 ((ep)->udc->ep0_dir) : ((ep)->direction))
48 /* timeout value -- usec */
49 #define RESET_TIMEOUT 10000
50 #define FLUSH_TIMEOUT 10000
51 #define EPSTATUS_TIMEOUT 10000
52 #define PRIME_TIMEOUT 10000
53 #define READSAFE_TIMEOUT 1000
54 #define DTD_TIMEOUT 1000
56 #define LOOPS_USEC_SHIFT 4
57 #define LOOPS_USEC (1 << LOOPS_USEC_SHIFT)
58 #define LOOPS(timeout) ((timeout) >> LOOPS_USEC_SHIFT)
60 static DECLARE_COMPLETION(release_done);
62 static const char driver_name[] = "mv_udc";
63 static const char driver_desc[] = DRIVER_DESC;
65 /* controller device global variable */
66 static struct mv_udc *the_controller;
69 static void nuke(struct mv_ep *ep, int status);
70 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver);
72 /* for endpoint 0 operations */
73 static const struct usb_endpoint_descriptor mv_ep0_desc = {
74 .bLength = USB_DT_ENDPOINT_SIZE,
75 .bDescriptorType = USB_DT_ENDPOINT,
76 .bEndpointAddress = 0,
77 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
78 .wMaxPacketSize = EP0_MAX_PKT_SIZE,
81 static void ep0_reset(struct mv_udc *udc)
88 for (i = 0; i < 2; i++) {
93 ep->dqh = &udc->ep_dqh[i];
95 /* configure ep0 endpoint capabilities in dQH */
96 ep->dqh->max_packet_length =
97 (EP0_MAX_PKT_SIZE << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
100 ep->dqh->next_dtd_ptr = EP_QUEUE_HEAD_NEXT_TERMINATE;
102 epctrlx = readl(&udc->op_regs->epctrlx[0]);
104 epctrlx |= EPCTRL_TX_ENABLE
105 | (USB_ENDPOINT_XFER_CONTROL
106 << EPCTRL_TX_EP_TYPE_SHIFT);
109 epctrlx |= EPCTRL_RX_ENABLE
110 | (USB_ENDPOINT_XFER_CONTROL
111 << EPCTRL_RX_EP_TYPE_SHIFT);
114 writel(epctrlx, &udc->op_regs->epctrlx[0]);
118 /* protocol ep0 stall, will automatically be cleared on new transaction */
119 static void ep0_stall(struct mv_udc *udc)
123 /* set TX and RX to stall */
124 epctrlx = readl(&udc->op_regs->epctrlx[0]);
125 epctrlx |= EPCTRL_RX_EP_STALL | EPCTRL_TX_EP_STALL;
126 writel(epctrlx, &udc->op_regs->epctrlx[0]);
128 /* update ep0 state */
129 udc->ep0_state = WAIT_FOR_SETUP;
130 udc->ep0_dir = EP_DIR_OUT;
133 static int process_ep_req(struct mv_udc *udc, int index,
134 struct mv_req *curr_req)
136 struct mv_dtd *curr_dtd;
137 struct mv_dqh *curr_dqh;
138 int td_complete, actual, remaining_length;
144 curr_dqh = &udc->ep_dqh[index];
145 direction = index % 2;
147 curr_dtd = curr_req->head;
149 actual = curr_req->req.length;
151 for (i = 0; i < curr_req->dtd_count; i++) {
152 if (curr_dtd->size_ioc_sts & DTD_STATUS_ACTIVE) {
153 dev_dbg(&udc->dev->dev, "%s, dTD not completed\n",
154 udc->eps[index].name);
158 errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK;
161 (curr_dtd->size_ioc_sts & DTD_PACKET_SIZE)
162 >> DTD_LENGTH_BIT_POS;
163 actual -= remaining_length;
165 if (remaining_length) {
167 dev_dbg(&udc->dev->dev,
168 "TX dTD remains data\n");
175 dev_info(&udc->dev->dev,
176 "complete_tr error: ep=%d %s: error = 0x%x\n",
177 index >> 1, direction ? "SEND" : "RECV",
179 if (errors & DTD_STATUS_HALTED) {
180 /* Clear the errors and Halt condition */
181 curr_dqh->size_ioc_int_sts &= ~errors;
183 } else if (errors & DTD_STATUS_DATA_BUFF_ERR) {
185 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
189 if (i != curr_req->dtd_count - 1)
190 curr_dtd = (struct mv_dtd *)curr_dtd->next_dtd_virt;
195 if (direction == EP_DIR_OUT)
196 bit_pos = 1 << curr_req->ep->ep_num;
198 bit_pos = 1 << (16 + curr_req->ep->ep_num);
200 while ((curr_dqh->curr_dtd_ptr == curr_dtd->td_dma)) {
201 if (curr_dtd->dtd_next == EP_QUEUE_HEAD_NEXT_TERMINATE) {
202 while (readl(&udc->op_regs->epstatus) & bit_pos)
209 curr_req->req.actual = actual;
215 * done() - retire a request; caller blocked irqs
216 * @status : request status to be set, only works when
217 * request is still in progress.
219 static void done(struct mv_ep *ep, struct mv_req *req, int status)
221 struct mv_udc *udc = NULL;
222 unsigned char stopped = ep->stopped;
223 struct mv_dtd *curr_td, *next_td;
226 udc = (struct mv_udc *)ep->udc;
227 /* Removed the req from fsl_ep->queue */
228 list_del_init(&req->queue);
230 /* req.status should be set as -EINPROGRESS in ep_queue() */
231 if (req->req.status == -EINPROGRESS)
232 req->req.status = status;
234 status = req->req.status;
236 /* Free dtd for the request */
238 for (j = 0; j < req->dtd_count; j++) {
240 if (j != req->dtd_count - 1)
241 next_td = curr_td->next_dtd_virt;
242 dma_pool_free(udc->dtd_pool, curr_td, curr_td->td_dma);
246 dma_unmap_single(ep->udc->gadget.dev.parent,
247 req->req.dma, req->req.length,
248 ((ep_dir(ep) == EP_DIR_IN) ?
249 DMA_TO_DEVICE : DMA_FROM_DEVICE));
250 req->req.dma = DMA_ADDR_INVALID;
253 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
254 req->req.dma, req->req.length,
255 ((ep_dir(ep) == EP_DIR_IN) ?
256 DMA_TO_DEVICE : DMA_FROM_DEVICE));
258 if (status && (status != -ESHUTDOWN))
259 dev_info(&udc->dev->dev, "complete %s req %p stat %d len %u/%u",
260 ep->ep.name, &req->req, status,
261 req->req.actual, req->req.length);
265 spin_unlock(&ep->udc->lock);
267 * complete() is from gadget layer,
268 * eg fsg->bulk_in_complete()
270 if (req->req.complete)
271 req->req.complete(&ep->ep, &req->req);
273 spin_lock(&ep->udc->lock);
274 ep->stopped = stopped;
277 static int queue_dtd(struct mv_ep *ep, struct mv_req *req)
281 u32 bit_pos, direction;
282 u32 usbcmd, epstatus;
287 direction = ep_dir(ep);
288 dqh = &(udc->ep_dqh[ep->ep_num * 2 + direction]);
289 bit_pos = 1 << (((direction == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
291 /* check if the pipe is empty */
292 if (!(list_empty(&ep->queue))) {
293 struct mv_req *lastreq;
294 lastreq = list_entry(ep->queue.prev, struct mv_req, queue);
295 lastreq->tail->dtd_next =
296 req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
300 if (readl(&udc->op_regs->epprime) & bit_pos)
303 loops = LOOPS(READSAFE_TIMEOUT);
305 /* start with setting the semaphores */
306 usbcmd = readl(&udc->op_regs->usbcmd);
307 usbcmd |= USBCMD_ATDTW_TRIPWIRE_SET;
308 writel(usbcmd, &udc->op_regs->usbcmd);
310 /* read the endpoint status */
311 epstatus = readl(&udc->op_regs->epstatus) & bit_pos;
314 * Reread the ATDTW semaphore bit to check if it is
315 * cleared. When hardware see a hazard, it will clear
316 * the bit or else we remain set to 1 and we can
317 * proceed with priming of endpoint if not already
320 if (readl(&udc->op_regs->usbcmd)
321 & USBCMD_ATDTW_TRIPWIRE_SET)
326 dev_err(&udc->dev->dev,
327 "Timeout for ATDTW_TRIPWIRE...\n");
334 /* Clear the semaphore */
335 usbcmd = readl(&udc->op_regs->usbcmd);
336 usbcmd &= USBCMD_ATDTW_TRIPWIRE_CLEAR;
337 writel(usbcmd, &udc->op_regs->usbcmd);
343 /* Write dQH next pointer and terminate bit to 0 */
344 dqh->next_dtd_ptr = req->head->td_dma
345 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
347 /* clear active and halt bit, in case set from a previous error */
348 dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
350 /* Ensure that updates to the QH will occure before priming. */
353 /* Prime the Endpoint */
354 writel(bit_pos, &udc->op_regs->epprime);
361 static struct mv_dtd *build_dtd(struct mv_req *req, unsigned *length,
362 dma_addr_t *dma, int *is_last)
368 /* how big will this transfer be? */
369 *length = min(req->req.length - req->req.actual,
370 (unsigned)EP_MAX_LENGTH_TRANSFER);
375 * Be careful that no _GFP_HIGHMEM is set,
376 * or we can not use dma_to_virt
378 dtd = dma_pool_alloc(udc->dtd_pool, GFP_KERNEL, dma);
383 /* initialize buffer page pointers */
384 temp = (u32)(req->req.dma + req->req.actual);
385 dtd->buff_ptr0 = cpu_to_le32(temp);
387 dtd->buff_ptr1 = cpu_to_le32(temp + 0x1000);
388 dtd->buff_ptr2 = cpu_to_le32(temp + 0x2000);
389 dtd->buff_ptr3 = cpu_to_le32(temp + 0x3000);
390 dtd->buff_ptr4 = cpu_to_le32(temp + 0x4000);
392 req->req.actual += *length;
394 /* zlp is needed if req->req.zero is set */
396 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
400 } else if (req->req.length == req->req.actual)
405 /* Fill in the transfer size; set active bit */
406 temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
408 /* Enable interrupt for the last dtd of a request */
409 if (*is_last && !req->req.no_interrupt)
412 dtd->size_ioc_sts = temp;
419 /* generate dTD linked list for a request */
420 static int req_to_dtd(struct mv_req *req)
423 int is_last, is_first = 1;
424 struct mv_dtd *dtd, *last_dtd = NULL;
431 dtd = build_dtd(req, &count, &dma, &is_last);
439 last_dtd->dtd_next = dma;
440 last_dtd->next_dtd_virt = dtd;
446 /* set terminate bit to 1 for the last dTD */
447 dtd->dtd_next = DTD_NEXT_TERMINATE;
454 static int mv_ep_enable(struct usb_ep *_ep,
455 const struct usb_endpoint_descriptor *desc)
461 u32 bit_pos, epctrlx, direction;
462 unsigned char zlt = 0, ios = 0, mult = 0;
465 ep = container_of(_ep, struct mv_ep, ep);
469 || desc->bDescriptorType != USB_DT_ENDPOINT)
472 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
475 direction = ep_dir(ep);
476 max = usb_endpoint_maxp(desc);
479 * disable HW zero length termination select
480 * driver handles zero length packet through req->req.zero
484 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
486 /* Check if the Endpoint is Primed */
487 if ((readl(&udc->op_regs->epprime) & bit_pos)
488 || (readl(&udc->op_regs->epstatus) & bit_pos)) {
489 dev_info(&udc->dev->dev,
490 "ep=%d %s: Init ERROR: ENDPTPRIME=0x%x,"
491 " ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
492 (unsigned)ep->ep_num, direction ? "SEND" : "RECV",
493 (unsigned)readl(&udc->op_regs->epprime),
494 (unsigned)readl(&udc->op_regs->epstatus),
498 /* Set the max packet length, interrupt on Setup and Mult fields */
499 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
500 case USB_ENDPOINT_XFER_BULK:
504 case USB_ENDPOINT_XFER_CONTROL:
506 case USB_ENDPOINT_XFER_INT:
509 case USB_ENDPOINT_XFER_ISOC:
510 /* Calculate transactions needed for high bandwidth iso */
511 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
512 max = max & 0x7ff; /* bit 0~10 */
513 /* 3 transactions at most */
521 spin_lock_irqsave(&udc->lock, flags);
522 /* Get the endpoint queue head address */
524 dqh->max_packet_length = (max << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
525 | (mult << EP_QUEUE_HEAD_MULT_POS)
526 | (zlt ? EP_QUEUE_HEAD_ZLT_SEL : 0)
527 | (ios ? EP_QUEUE_HEAD_IOS : 0);
528 dqh->next_dtd_ptr = 1;
529 dqh->size_ioc_int_sts = 0;
531 ep->ep.maxpacket = max;
535 /* Enable the endpoint for Rx or Tx and set the endpoint type */
536 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
537 if (direction == EP_DIR_IN) {
538 epctrlx &= ~EPCTRL_TX_ALL_MASK;
539 epctrlx |= EPCTRL_TX_ENABLE | EPCTRL_TX_DATA_TOGGLE_RST
540 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
541 << EPCTRL_TX_EP_TYPE_SHIFT);
543 epctrlx &= ~EPCTRL_RX_ALL_MASK;
544 epctrlx |= EPCTRL_RX_ENABLE | EPCTRL_RX_DATA_TOGGLE_RST
545 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
546 << EPCTRL_RX_EP_TYPE_SHIFT);
548 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
551 * Implement Guideline (GL# USB-7) The unused endpoint type must
552 * be programmed to bulk.
554 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
555 if ((epctrlx & EPCTRL_RX_ENABLE) == 0) {
556 epctrlx |= (USB_ENDPOINT_XFER_BULK
557 << EPCTRL_RX_EP_TYPE_SHIFT);
558 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
561 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
562 if ((epctrlx & EPCTRL_TX_ENABLE) == 0) {
563 epctrlx |= (USB_ENDPOINT_XFER_BULK
564 << EPCTRL_TX_EP_TYPE_SHIFT);
565 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
568 spin_unlock_irqrestore(&udc->lock, flags);
575 static int mv_ep_disable(struct usb_ep *_ep)
580 u32 bit_pos, epctrlx, direction;
583 ep = container_of(_ep, struct mv_ep, ep);
584 if ((_ep == NULL) || !ep->ep.desc)
589 /* Get the endpoint queue head address */
592 spin_lock_irqsave(&udc->lock, flags);
594 direction = ep_dir(ep);
595 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
597 /* Reset the max packet length and the interrupt on Setup */
598 dqh->max_packet_length = 0;
600 /* Disable the endpoint for Rx or Tx and reset the endpoint type */
601 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
602 epctrlx &= ~((direction == EP_DIR_IN)
603 ? (EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE)
604 : (EPCTRL_RX_ENABLE | EPCTRL_RX_TYPE));
605 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
607 /* nuke all pending requests (does flush) */
608 nuke(ep, -ESHUTDOWN);
613 spin_unlock_irqrestore(&udc->lock, flags);
618 static struct usb_request *
619 mv_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
621 struct mv_req *req = NULL;
623 req = kzalloc(sizeof *req, gfp_flags);
627 req->req.dma = DMA_ADDR_INVALID;
628 INIT_LIST_HEAD(&req->queue);
633 static void mv_free_request(struct usb_ep *_ep, struct usb_request *_req)
635 struct mv_req *req = NULL;
637 req = container_of(_req, struct mv_req, req);
643 static void mv_ep_fifo_flush(struct usb_ep *_ep)
646 u32 bit_pos, direction;
653 ep = container_of(_ep, struct mv_ep, ep);
658 direction = ep_dir(ep);
661 bit_pos = (1 << 16) | 1;
662 else if (direction == EP_DIR_OUT)
663 bit_pos = 1 << ep->ep_num;
665 bit_pos = 1 << (16 + ep->ep_num);
667 loops = LOOPS(EPSTATUS_TIMEOUT);
669 unsigned int inter_loops;
672 dev_err(&udc->dev->dev,
673 "TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
674 (unsigned)readl(&udc->op_regs->epstatus),
678 /* Write 1 to the Flush register */
679 writel(bit_pos, &udc->op_regs->epflush);
681 /* Wait until flushing completed */
682 inter_loops = LOOPS(FLUSH_TIMEOUT);
683 while (readl(&udc->op_regs->epflush)) {
685 * ENDPTFLUSH bit should be cleared to indicate this
686 * operation is complete
688 if (inter_loops == 0) {
689 dev_err(&udc->dev->dev,
690 "TIMEOUT for ENDPTFLUSH=0x%x,"
692 (unsigned)readl(&udc->op_regs->epflush),
700 } while (readl(&udc->op_regs->epstatus) & bit_pos);
703 /* queues (submits) an I/O request to an endpoint */
705 mv_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
707 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
708 struct mv_req *req = container_of(_req, struct mv_req, req);
709 struct mv_udc *udc = ep->udc;
712 /* catch various bogus parameters */
713 if (!_req || !req->req.complete || !req->req.buf
714 || !list_empty(&req->queue)) {
715 dev_err(&udc->dev->dev, "%s, bad params", __func__);
718 if (unlikely(!_ep || !ep->ep.desc)) {
719 dev_err(&udc->dev->dev, "%s, bad ep", __func__);
722 if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
723 if (req->req.length > ep->ep.maxpacket)
728 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
733 /* map virtual address to hardware */
734 if (req->req.dma == DMA_ADDR_INVALID) {
735 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
737 req->req.length, ep_dir(ep)
742 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
743 req->req.dma, req->req.length,
750 req->req.status = -EINPROGRESS;
754 spin_lock_irqsave(&udc->lock, flags);
756 /* build dtds and push them to device queue */
757 if (!req_to_dtd(req)) {
759 retval = queue_dtd(ep, req);
761 spin_unlock_irqrestore(&udc->lock, flags);
765 spin_unlock_irqrestore(&udc->lock, flags);
769 /* Update ep0 state */
771 udc->ep0_state = DATA_STATE_XMIT;
773 /* irq handler advances the queue */
774 list_add_tail(&req->queue, &ep->queue);
775 spin_unlock_irqrestore(&udc->lock, flags);
780 static void mv_prime_ep(struct mv_ep *ep, struct mv_req *req)
782 struct mv_dqh *dqh = ep->dqh;
785 /* Write dQH next pointer and terminate bit to 0 */
786 dqh->next_dtd_ptr = req->head->td_dma
787 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
789 /* clear active and halt bit, in case set from a previous error */
790 dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
792 /* Ensure that updates to the QH will occure before priming. */
795 bit_pos = 1 << (((ep_dir(ep) == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
797 /* Prime the Endpoint */
798 writel(bit_pos, &ep->udc->op_regs->epprime);
801 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
802 static int mv_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
804 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
806 struct mv_udc *udc = ep->udc;
808 int stopped, ret = 0;
814 spin_lock_irqsave(&ep->udc->lock, flags);
815 stopped = ep->stopped;
817 /* Stop the ep before we deal with the queue */
819 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
820 if (ep_dir(ep) == EP_DIR_IN)
821 epctrlx &= ~EPCTRL_TX_ENABLE;
823 epctrlx &= ~EPCTRL_RX_ENABLE;
824 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
826 /* make sure it's actually queued on this endpoint */
827 list_for_each_entry(req, &ep->queue, queue) {
828 if (&req->req == _req)
831 if (&req->req != _req) {
836 /* The request is in progress, or completed but not dequeued */
837 if (ep->queue.next == &req->queue) {
838 _req->status = -ECONNRESET;
839 mv_ep_fifo_flush(_ep); /* flush current transfer */
841 /* The request isn't the last request in this ep queue */
842 if (req->queue.next != &ep->queue) {
843 struct mv_req *next_req;
845 next_req = list_entry(req->queue.next,
846 struct mv_req, queue);
848 /* Point the QH to the first TD of next request */
849 mv_prime_ep(ep, next_req);
854 qh->next_dtd_ptr = 1;
855 qh->size_ioc_int_sts = 0;
858 /* The request hasn't been processed, patch up the TD chain */
860 struct mv_req *prev_req;
862 prev_req = list_entry(req->queue.prev, struct mv_req, queue);
863 writel(readl(&req->tail->dtd_next),
864 &prev_req->tail->dtd_next);
868 done(ep, req, -ECONNRESET);
872 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
873 if (ep_dir(ep) == EP_DIR_IN)
874 epctrlx |= EPCTRL_TX_ENABLE;
876 epctrlx |= EPCTRL_RX_ENABLE;
877 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
878 ep->stopped = stopped;
880 spin_unlock_irqrestore(&ep->udc->lock, flags);
884 static void ep_set_stall(struct mv_udc *udc, u8 ep_num, u8 direction, int stall)
888 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
891 if (direction == EP_DIR_IN)
892 epctrlx |= EPCTRL_TX_EP_STALL;
894 epctrlx |= EPCTRL_RX_EP_STALL;
896 if (direction == EP_DIR_IN) {
897 epctrlx &= ~EPCTRL_TX_EP_STALL;
898 epctrlx |= EPCTRL_TX_DATA_TOGGLE_RST;
900 epctrlx &= ~EPCTRL_RX_EP_STALL;
901 epctrlx |= EPCTRL_RX_DATA_TOGGLE_RST;
904 writel(epctrlx, &udc->op_regs->epctrlx[ep_num]);
907 static int ep_is_stall(struct mv_udc *udc, u8 ep_num, u8 direction)
911 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
913 if (direction == EP_DIR_OUT)
914 return (epctrlx & EPCTRL_RX_EP_STALL) ? 1 : 0;
916 return (epctrlx & EPCTRL_TX_EP_STALL) ? 1 : 0;
919 static int mv_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
922 unsigned long flags = 0;
926 ep = container_of(_ep, struct mv_ep, ep);
928 if (!_ep || !ep->ep.desc) {
933 if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
934 status = -EOPNOTSUPP;
939 * Attempt to halt IN ep will fail if any transfer requests
942 if (halt && (ep_dir(ep) == EP_DIR_IN) && !list_empty(&ep->queue)) {
947 spin_lock_irqsave(&ep->udc->lock, flags);
948 ep_set_stall(udc, ep->ep_num, ep_dir(ep), halt);
953 spin_unlock_irqrestore(&ep->udc->lock, flags);
955 if (ep->ep_num == 0) {
956 udc->ep0_state = WAIT_FOR_SETUP;
957 udc->ep0_dir = EP_DIR_OUT;
963 static int mv_ep_set_halt(struct usb_ep *_ep, int halt)
965 return mv_ep_set_halt_wedge(_ep, halt, 0);
968 static int mv_ep_set_wedge(struct usb_ep *_ep)
970 return mv_ep_set_halt_wedge(_ep, 1, 1);
973 static struct usb_ep_ops mv_ep_ops = {
974 .enable = mv_ep_enable,
975 .disable = mv_ep_disable,
977 .alloc_request = mv_alloc_request,
978 .free_request = mv_free_request,
980 .queue = mv_ep_queue,
981 .dequeue = mv_ep_dequeue,
983 .set_wedge = mv_ep_set_wedge,
984 .set_halt = mv_ep_set_halt,
985 .fifo_flush = mv_ep_fifo_flush, /* flush fifo */
988 static void udc_clock_enable(struct mv_udc *udc)
992 for (i = 0; i < udc->clknum; i++)
993 clk_enable(udc->clk[i]);
996 static void udc_clock_disable(struct mv_udc *udc)
1000 for (i = 0; i < udc->clknum; i++)
1001 clk_disable(udc->clk[i]);
1004 static void udc_stop(struct mv_udc *udc)
1008 /* Disable interrupts */
1009 tmp = readl(&udc->op_regs->usbintr);
1010 tmp &= ~(USBINTR_INT_EN | USBINTR_ERR_INT_EN |
1011 USBINTR_PORT_CHANGE_DETECT_EN | USBINTR_RESET_EN);
1012 writel(tmp, &udc->op_regs->usbintr);
1016 /* Reset the Run the bit in the command register to stop VUSB */
1017 tmp = readl(&udc->op_regs->usbcmd);
1018 tmp &= ~USBCMD_RUN_STOP;
1019 writel(tmp, &udc->op_regs->usbcmd);
1022 static void udc_start(struct mv_udc *udc)
1026 usbintr = USBINTR_INT_EN | USBINTR_ERR_INT_EN
1027 | USBINTR_PORT_CHANGE_DETECT_EN
1028 | USBINTR_RESET_EN | USBINTR_DEVICE_SUSPEND;
1029 /* Enable interrupts */
1030 writel(usbintr, &udc->op_regs->usbintr);
1034 /* Set the Run bit in the command register */
1035 writel(USBCMD_RUN_STOP, &udc->op_regs->usbcmd);
1038 static int udc_reset(struct mv_udc *udc)
1043 /* Stop the controller */
1044 tmp = readl(&udc->op_regs->usbcmd);
1045 tmp &= ~USBCMD_RUN_STOP;
1046 writel(tmp, &udc->op_regs->usbcmd);
1048 /* Reset the controller to get default values */
1049 writel(USBCMD_CTRL_RESET, &udc->op_regs->usbcmd);
1051 /* wait for reset to complete */
1052 loops = LOOPS(RESET_TIMEOUT);
1053 while (readl(&udc->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
1055 dev_err(&udc->dev->dev,
1056 "Wait for RESET completed TIMEOUT\n");
1063 /* set controller to device mode */
1064 tmp = readl(&udc->op_regs->usbmode);
1065 tmp |= USBMODE_CTRL_MODE_DEVICE;
1067 /* turn setup lockout off, require setup tripwire in usbcmd */
1068 tmp |= USBMODE_SETUP_LOCK_OFF | USBMODE_STREAM_DISABLE;
1070 writel(tmp, &udc->op_regs->usbmode);
1072 writel(0x0, &udc->op_regs->epsetupstat);
1074 /* Configure the Endpoint List Address */
1075 writel(udc->ep_dqh_dma & USB_EP_LIST_ADDRESS_MASK,
1076 &udc->op_regs->eplistaddr);
1078 portsc = readl(&udc->op_regs->portsc[0]);
1079 if (readl(&udc->cap_regs->hcsparams) & HCSPARAMS_PPC)
1080 portsc &= (~PORTSCX_W1C_BITS | ~PORTSCX_PORT_POWER);
1083 portsc |= PORTSCX_FORCE_FULL_SPEED_CONNECT;
1085 portsc &= (~PORTSCX_FORCE_FULL_SPEED_CONNECT);
1087 writel(portsc, &udc->op_regs->portsc[0]);
1089 tmp = readl(&udc->op_regs->epctrlx[0]);
1090 tmp &= ~(EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL);
1091 writel(tmp, &udc->op_regs->epctrlx[0]);
1096 static int mv_udc_enable_internal(struct mv_udc *udc)
1103 dev_dbg(&udc->dev->dev, "enable udc\n");
1104 udc_clock_enable(udc);
1105 if (udc->pdata->phy_init) {
1106 retval = udc->pdata->phy_init(udc->phy_regs);
1108 dev_err(&udc->dev->dev,
1109 "init phy error %d\n", retval);
1110 udc_clock_disable(udc);
1119 static int mv_udc_enable(struct mv_udc *udc)
1121 if (udc->clock_gating)
1122 return mv_udc_enable_internal(udc);
1127 static void mv_udc_disable_internal(struct mv_udc *udc)
1130 dev_dbg(&udc->dev->dev, "disable udc\n");
1131 if (udc->pdata->phy_deinit)
1132 udc->pdata->phy_deinit(udc->phy_regs);
1133 udc_clock_disable(udc);
1138 static void mv_udc_disable(struct mv_udc *udc)
1140 if (udc->clock_gating)
1141 mv_udc_disable_internal(udc);
1144 static int mv_udc_get_frame(struct usb_gadget *gadget)
1152 udc = container_of(gadget, struct mv_udc, gadget);
1154 retval = readl(&udc->op_regs->frindex) & USB_FRINDEX_MASKS;
1159 /* Tries to wake up the host connected to this gadget */
1160 static int mv_udc_wakeup(struct usb_gadget *gadget)
1162 struct mv_udc *udc = container_of(gadget, struct mv_udc, gadget);
1165 /* Remote wakeup feature not enabled by host */
1166 if (!udc->remote_wakeup)
1169 portsc = readl(&udc->op_regs->portsc);
1170 /* not suspended? */
1171 if (!(portsc & PORTSCX_PORT_SUSPEND))
1173 /* trigger force resume */
1174 portsc |= PORTSCX_PORT_FORCE_RESUME;
1175 writel(portsc, &udc->op_regs->portsc[0]);
1179 static int mv_udc_vbus_session(struct usb_gadget *gadget, int is_active)
1182 unsigned long flags;
1185 udc = container_of(gadget, struct mv_udc, gadget);
1186 spin_lock_irqsave(&udc->lock, flags);
1188 udc->vbus_active = (is_active != 0);
1190 dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1191 __func__, udc->softconnect, udc->vbus_active);
1193 if (udc->driver && udc->softconnect && udc->vbus_active) {
1194 retval = mv_udc_enable(udc);
1196 /* Clock is disabled, need re-init registers */
1201 } else if (udc->driver && udc->softconnect) {
1202 /* stop all the transfer in queue*/
1203 stop_activity(udc, udc->driver);
1205 mv_udc_disable(udc);
1208 spin_unlock_irqrestore(&udc->lock, flags);
1212 static int mv_udc_pullup(struct usb_gadget *gadget, int is_on)
1215 unsigned long flags;
1218 udc = container_of(gadget, struct mv_udc, gadget);
1219 spin_lock_irqsave(&udc->lock, flags);
1221 udc->softconnect = (is_on != 0);
1223 dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1224 __func__, udc->softconnect, udc->vbus_active);
1226 if (udc->driver && udc->softconnect && udc->vbus_active) {
1227 retval = mv_udc_enable(udc);
1229 /* Clock is disabled, need re-init registers */
1234 } else if (udc->driver && udc->vbus_active) {
1235 /* stop all the transfer in queue*/
1236 stop_activity(udc, udc->driver);
1238 mv_udc_disable(udc);
1241 spin_unlock_irqrestore(&udc->lock, flags);
1245 static int mv_udc_start(struct usb_gadget_driver *driver,
1246 int (*bind)(struct usb_gadget *));
1247 static int mv_udc_stop(struct usb_gadget_driver *driver);
1248 /* device controller usb_gadget_ops structure */
1249 static const struct usb_gadget_ops mv_ops = {
1251 /* returns the current frame number */
1252 .get_frame = mv_udc_get_frame,
1254 /* tries to wake up the host connected to this gadget */
1255 .wakeup = mv_udc_wakeup,
1257 /* notify controller that VBUS is powered or not */
1258 .vbus_session = mv_udc_vbus_session,
1260 /* D+ pullup, software-controlled connect/disconnect to USB host */
1261 .pullup = mv_udc_pullup,
1262 .start = mv_udc_start,
1263 .stop = mv_udc_stop,
1266 static int eps_init(struct mv_udc *udc)
1272 /* initialize ep0 */
1275 strncpy(ep->name, "ep0", sizeof(ep->name));
1276 ep->ep.name = ep->name;
1277 ep->ep.ops = &mv_ep_ops;
1280 ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1282 ep->ep.desc = &mv_ep0_desc;
1283 INIT_LIST_HEAD(&ep->queue);
1285 ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1287 /* initialize other endpoints */
1288 for (i = 2; i < udc->max_eps * 2; i++) {
1291 snprintf(name, sizeof(name), "ep%din", i / 2);
1292 ep->direction = EP_DIR_IN;
1294 snprintf(name, sizeof(name), "ep%dout", i / 2);
1295 ep->direction = EP_DIR_OUT;
1298 strncpy(ep->name, name, sizeof(ep->name));
1299 ep->ep.name = ep->name;
1301 ep->ep.ops = &mv_ep_ops;
1303 ep->ep.maxpacket = (unsigned short) ~0;
1306 INIT_LIST_HEAD(&ep->queue);
1307 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1309 ep->dqh = &udc->ep_dqh[i];
1315 /* delete all endpoint requests, called with spinlock held */
1316 static void nuke(struct mv_ep *ep, int status)
1318 /* called with spinlock held */
1321 /* endpoint fifo flush */
1322 mv_ep_fifo_flush(&ep->ep);
1324 while (!list_empty(&ep->queue)) {
1325 struct mv_req *req = NULL;
1326 req = list_entry(ep->queue.next, struct mv_req, queue);
1327 done(ep, req, status);
1331 /* stop all USB activities */
1332 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver)
1336 nuke(&udc->eps[0], -ESHUTDOWN);
1338 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1339 nuke(ep, -ESHUTDOWN);
1342 /* report disconnect; the driver is already quiesced */
1344 spin_unlock(&udc->lock);
1345 driver->disconnect(&udc->gadget);
1346 spin_lock(&udc->lock);
1350 static int mv_udc_start(struct usb_gadget_driver *driver,
1351 int (*bind)(struct usb_gadget *))
1353 struct mv_udc *udc = the_controller;
1355 unsigned long flags;
1363 spin_lock_irqsave(&udc->lock, flags);
1365 /* hook up the driver ... */
1366 driver->driver.bus = NULL;
1367 udc->driver = driver;
1368 udc->gadget.dev.driver = &driver->driver;
1370 udc->usb_state = USB_STATE_ATTACHED;
1371 udc->ep0_state = WAIT_FOR_SETUP;
1372 udc->ep0_dir = EP_DIR_OUT;
1374 spin_unlock_irqrestore(&udc->lock, flags);
1376 retval = bind(&udc->gadget);
1378 dev_err(&udc->dev->dev, "bind to driver %s --> %d\n",
1379 driver->driver.name, retval);
1381 udc->gadget.dev.driver = NULL;
1385 if (!IS_ERR_OR_NULL(udc->transceiver)) {
1386 retval = otg_set_peripheral(udc->transceiver->otg,
1389 dev_err(&udc->dev->dev,
1390 "unable to register peripheral to otg\n");
1391 if (driver->unbind) {
1392 driver->unbind(&udc->gadget);
1393 udc->gadget.dev.driver = NULL;
1400 /* pullup is always on */
1401 mv_udc_pullup(&udc->gadget, 1);
1403 /* When boot with cable attached, there will be no vbus irq occurred */
1405 queue_work(udc->qwork, &udc->vbus_work);
1410 static int mv_udc_stop(struct usb_gadget_driver *driver)
1412 struct mv_udc *udc = the_controller;
1413 unsigned long flags;
1418 spin_lock_irqsave(&udc->lock, flags);
1423 /* stop all usb activities */
1424 udc->gadget.speed = USB_SPEED_UNKNOWN;
1425 stop_activity(udc, driver);
1426 mv_udc_disable(udc);
1428 spin_unlock_irqrestore(&udc->lock, flags);
1430 /* unbind gadget driver */
1431 driver->unbind(&udc->gadget);
1432 udc->gadget.dev.driver = NULL;
1438 static void mv_set_ptc(struct mv_udc *udc, u32 mode)
1442 portsc = readl(&udc->op_regs->portsc[0]);
1443 portsc |= mode << 16;
1444 writel(portsc, &udc->op_regs->portsc[0]);
1447 static void prime_status_complete(struct usb_ep *ep, struct usb_request *_req)
1449 struct mv_udc *udc = the_controller;
1450 struct mv_req *req = container_of(_req, struct mv_req, req);
1451 unsigned long flags;
1453 dev_info(&udc->dev->dev, "switch to test mode %d\n", req->test_mode);
1455 spin_lock_irqsave(&udc->lock, flags);
1456 if (req->test_mode) {
1457 mv_set_ptc(udc, req->test_mode);
1460 spin_unlock_irqrestore(&udc->lock, flags);
1464 udc_prime_status(struct mv_udc *udc, u8 direction, u16 status, bool empty)
1471 udc->ep0_dir = direction;
1472 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1474 req = udc->status_req;
1476 /* fill in the reqest structure */
1477 if (empty == false) {
1478 *((u16 *) req->req.buf) = cpu_to_le16(status);
1479 req->req.length = 2;
1481 req->req.length = 0;
1484 req->req.status = -EINPROGRESS;
1485 req->req.actual = 0;
1486 if (udc->test_mode) {
1487 req->req.complete = prime_status_complete;
1488 req->test_mode = udc->test_mode;
1491 req->req.complete = NULL;
1494 if (req->req.dma == DMA_ADDR_INVALID) {
1495 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1496 req->req.buf, req->req.length,
1497 ep_dir(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1501 /* prime the data phase */
1502 if (!req_to_dtd(req))
1503 retval = queue_dtd(ep, req);
1510 dev_err(&udc->dev->dev, "response error on GET_STATUS request\n");
1514 list_add_tail(&req->queue, &ep->queue);
1521 static void mv_udc_testmode(struct mv_udc *udc, u16 index)
1523 if (index <= TEST_FORCE_EN) {
1524 udc->test_mode = index;
1525 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1528 dev_err(&udc->dev->dev,
1529 "This test mode(%d) is not supported\n", index);
1532 static void ch9setaddress(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1534 udc->dev_addr = (u8)setup->wValue;
1536 /* update usb state */
1537 udc->usb_state = USB_STATE_ADDRESS;
1539 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1543 static void ch9getstatus(struct mv_udc *udc, u8 ep_num,
1544 struct usb_ctrlrequest *setup)
1549 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1550 != (USB_DIR_IN | USB_TYPE_STANDARD))
1553 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1554 status = 1 << USB_DEVICE_SELF_POWERED;
1555 status |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1556 } else if ((setup->bRequestType & USB_RECIP_MASK)
1557 == USB_RECIP_INTERFACE) {
1558 /* get interface status */
1560 } else if ((setup->bRequestType & USB_RECIP_MASK)
1561 == USB_RECIP_ENDPOINT) {
1562 u8 ep_num, direction;
1564 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1565 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1566 ? EP_DIR_IN : EP_DIR_OUT;
1567 status = ep_is_stall(udc, ep_num, direction)
1568 << USB_ENDPOINT_HALT;
1571 retval = udc_prime_status(udc, EP_DIR_IN, status, false);
1575 udc->ep0_state = DATA_STATE_XMIT;
1578 static void ch9clearfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1584 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1585 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1586 switch (setup->wValue) {
1587 case USB_DEVICE_REMOTE_WAKEUP:
1588 udc->remote_wakeup = 0;
1593 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1594 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1595 switch (setup->wValue) {
1596 case USB_ENDPOINT_HALT:
1597 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1598 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1599 ? EP_DIR_IN : EP_DIR_OUT;
1600 if (setup->wValue != 0 || setup->wLength != 0
1601 || ep_num > udc->max_eps)
1603 ep = &udc->eps[ep_num * 2 + direction];
1606 spin_unlock(&udc->lock);
1607 ep_set_stall(udc, ep_num, direction, 0);
1608 spin_lock(&udc->lock);
1616 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1622 static void ch9setfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1627 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1628 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1629 switch (setup->wValue) {
1630 case USB_DEVICE_REMOTE_WAKEUP:
1631 udc->remote_wakeup = 1;
1633 case USB_DEVICE_TEST_MODE:
1634 if (setup->wIndex & 0xFF
1635 || udc->gadget.speed != USB_SPEED_HIGH)
1638 if (udc->usb_state != USB_STATE_CONFIGURED
1639 && udc->usb_state != USB_STATE_ADDRESS
1640 && udc->usb_state != USB_STATE_DEFAULT)
1643 mv_udc_testmode(udc, (setup->wIndex >> 8));
1648 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1649 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1650 switch (setup->wValue) {
1651 case USB_ENDPOINT_HALT:
1652 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1653 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1654 ? EP_DIR_IN : EP_DIR_OUT;
1655 if (setup->wValue != 0 || setup->wLength != 0
1656 || ep_num > udc->max_eps)
1658 spin_unlock(&udc->lock);
1659 ep_set_stall(udc, ep_num, direction, 1);
1660 spin_lock(&udc->lock);
1668 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1674 static void handle_setup_packet(struct mv_udc *udc, u8 ep_num,
1675 struct usb_ctrlrequest *setup)
1677 bool delegate = false;
1679 nuke(&udc->eps[ep_num * 2 + EP_DIR_OUT], -ESHUTDOWN);
1681 dev_dbg(&udc->dev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1682 setup->bRequestType, setup->bRequest,
1683 setup->wValue, setup->wIndex, setup->wLength);
1684 /* We process some stardard setup requests here */
1685 if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1686 switch (setup->bRequest) {
1687 case USB_REQ_GET_STATUS:
1688 ch9getstatus(udc, ep_num, setup);
1691 case USB_REQ_SET_ADDRESS:
1692 ch9setaddress(udc, setup);
1695 case USB_REQ_CLEAR_FEATURE:
1696 ch9clearfeature(udc, setup);
1699 case USB_REQ_SET_FEATURE:
1700 ch9setfeature(udc, setup);
1709 /* delegate USB standard requests to the gadget driver */
1710 if (delegate == true) {
1711 /* USB requests handled by gadget */
1712 if (setup->wLength) {
1713 /* DATA phase from gadget, STATUS phase from udc */
1714 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1715 ? EP_DIR_IN : EP_DIR_OUT;
1716 spin_unlock(&udc->lock);
1717 if (udc->driver->setup(&udc->gadget,
1718 &udc->local_setup_buff) < 0)
1720 spin_lock(&udc->lock);
1721 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1722 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1724 /* no DATA phase, IN STATUS phase from gadget */
1725 udc->ep0_dir = EP_DIR_IN;
1726 spin_unlock(&udc->lock);
1727 if (udc->driver->setup(&udc->gadget,
1728 &udc->local_setup_buff) < 0)
1730 spin_lock(&udc->lock);
1731 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1736 /* complete DATA or STATUS phase of ep0 prime status phase if needed */
1737 static void ep0_req_complete(struct mv_udc *udc,
1738 struct mv_ep *ep0, struct mv_req *req)
1742 if (udc->usb_state == USB_STATE_ADDRESS) {
1743 /* set the new address */
1744 new_addr = (u32)udc->dev_addr;
1745 writel(new_addr << USB_DEVICE_ADDRESS_BIT_SHIFT,
1746 &udc->op_regs->deviceaddr);
1751 switch (udc->ep0_state) {
1752 case DATA_STATE_XMIT:
1753 /* receive status phase */
1754 if (udc_prime_status(udc, EP_DIR_OUT, 0, true))
1757 case DATA_STATE_RECV:
1758 /* send status phase */
1759 if (udc_prime_status(udc, EP_DIR_IN, 0 , true))
1762 case WAIT_FOR_OUT_STATUS:
1763 udc->ep0_state = WAIT_FOR_SETUP;
1765 case WAIT_FOR_SETUP:
1766 dev_err(&udc->dev->dev, "unexpect ep0 packets\n");
1774 static void get_setup_data(struct mv_udc *udc, u8 ep_num, u8 *buffer_ptr)
1779 dqh = &udc->ep_dqh[ep_num * 2 + EP_DIR_OUT];
1781 /* Clear bit in ENDPTSETUPSTAT */
1782 writel((1 << ep_num), &udc->op_regs->epsetupstat);
1784 /* while a hazard exists when setup package arrives */
1786 /* Set Setup Tripwire */
1787 temp = readl(&udc->op_regs->usbcmd);
1788 writel(temp | USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1790 /* Copy the setup packet to local buffer */
1791 memcpy(buffer_ptr, (u8 *) dqh->setup_buffer, 8);
1792 } while (!(readl(&udc->op_regs->usbcmd) & USBCMD_SETUP_TRIPWIRE_SET));
1794 /* Clear Setup Tripwire */
1795 temp = readl(&udc->op_regs->usbcmd);
1796 writel(temp & ~USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1799 static void irq_process_tr_complete(struct mv_udc *udc)
1802 int i, ep_num = 0, direction = 0;
1803 struct mv_ep *curr_ep;
1804 struct mv_req *curr_req, *temp_req;
1808 * We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE
1809 * because the setup packets are to be read ASAP
1812 /* Process all Setup packet received interrupts */
1813 tmp = readl(&udc->op_regs->epsetupstat);
1816 for (i = 0; i < udc->max_eps; i++) {
1817 if (tmp & (1 << i)) {
1818 get_setup_data(udc, i,
1819 (u8 *)(&udc->local_setup_buff));
1820 handle_setup_packet(udc, i,
1821 &udc->local_setup_buff);
1826 /* Don't clear the endpoint setup status register here.
1827 * It is cleared as a setup packet is read out of the buffer
1830 /* Process non-setup transaction complete interrupts */
1831 tmp = readl(&udc->op_regs->epcomplete);
1836 writel(tmp, &udc->op_regs->epcomplete);
1838 for (i = 0; i < udc->max_eps * 2; i++) {
1842 bit_pos = 1 << (ep_num + 16 * direction);
1844 if (!(bit_pos & tmp))
1848 curr_ep = &udc->eps[0];
1850 curr_ep = &udc->eps[i];
1851 /* process the req queue until an uncomplete request */
1852 list_for_each_entry_safe(curr_req, temp_req,
1853 &curr_ep->queue, queue) {
1854 status = process_ep_req(udc, i, curr_req);
1858 /* write back status to req */
1859 curr_req->req.status = status;
1861 /* ep0 request completion */
1863 ep0_req_complete(udc, curr_ep, curr_req);
1866 done(curr_ep, curr_req, status);
1872 void irq_process_reset(struct mv_udc *udc)
1877 udc->ep0_dir = EP_DIR_OUT;
1878 udc->ep0_state = WAIT_FOR_SETUP;
1879 udc->remote_wakeup = 0; /* default to 0 on reset */
1881 /* The address bits are past bit 25-31. Set the address */
1882 tmp = readl(&udc->op_regs->deviceaddr);
1883 tmp &= ~(USB_DEVICE_ADDRESS_MASK);
1884 writel(tmp, &udc->op_regs->deviceaddr);
1886 /* Clear all the setup token semaphores */
1887 tmp = readl(&udc->op_regs->epsetupstat);
1888 writel(tmp, &udc->op_regs->epsetupstat);
1890 /* Clear all the endpoint complete status bits */
1891 tmp = readl(&udc->op_regs->epcomplete);
1892 writel(tmp, &udc->op_regs->epcomplete);
1894 /* wait until all endptprime bits cleared */
1895 loops = LOOPS(PRIME_TIMEOUT);
1896 while (readl(&udc->op_regs->epprime) & 0xFFFFFFFF) {
1898 dev_err(&udc->dev->dev,
1899 "Timeout for ENDPTPRIME = 0x%x\n",
1900 readl(&udc->op_regs->epprime));
1907 /* Write 1s to the Flush register */
1908 writel((u32)~0, &udc->op_regs->epflush);
1910 if (readl(&udc->op_regs->portsc[0]) & PORTSCX_PORT_RESET) {
1911 dev_info(&udc->dev->dev, "usb bus reset\n");
1912 udc->usb_state = USB_STATE_DEFAULT;
1913 /* reset all the queues, stop all USB activities */
1914 stop_activity(udc, udc->driver);
1916 dev_info(&udc->dev->dev, "USB reset portsc 0x%x\n",
1917 readl(&udc->op_regs->portsc));
1925 /* reset all the queues, stop all USB activities */
1926 stop_activity(udc, udc->driver);
1928 /* reset ep0 dQH and endptctrl */
1931 /* enable interrupt and set controller to run state */
1934 udc->usb_state = USB_STATE_ATTACHED;
1938 static void handle_bus_resume(struct mv_udc *udc)
1940 udc->usb_state = udc->resume_state;
1941 udc->resume_state = 0;
1943 /* report resume to the driver */
1945 if (udc->driver->resume) {
1946 spin_unlock(&udc->lock);
1947 udc->driver->resume(&udc->gadget);
1948 spin_lock(&udc->lock);
1953 static void irq_process_suspend(struct mv_udc *udc)
1955 udc->resume_state = udc->usb_state;
1956 udc->usb_state = USB_STATE_SUSPENDED;
1958 if (udc->driver->suspend) {
1959 spin_unlock(&udc->lock);
1960 udc->driver->suspend(&udc->gadget);
1961 spin_lock(&udc->lock);
1965 static void irq_process_port_change(struct mv_udc *udc)
1969 portsc = readl(&udc->op_regs->portsc[0]);
1970 if (!(portsc & PORTSCX_PORT_RESET)) {
1972 u32 speed = portsc & PORTSCX_PORT_SPEED_MASK;
1974 case PORTSCX_PORT_SPEED_HIGH:
1975 udc->gadget.speed = USB_SPEED_HIGH;
1977 case PORTSCX_PORT_SPEED_FULL:
1978 udc->gadget.speed = USB_SPEED_FULL;
1980 case PORTSCX_PORT_SPEED_LOW:
1981 udc->gadget.speed = USB_SPEED_LOW;
1984 udc->gadget.speed = USB_SPEED_UNKNOWN;
1989 if (portsc & PORTSCX_PORT_SUSPEND) {
1990 udc->resume_state = udc->usb_state;
1991 udc->usb_state = USB_STATE_SUSPENDED;
1992 if (udc->driver->suspend) {
1993 spin_unlock(&udc->lock);
1994 udc->driver->suspend(&udc->gadget);
1995 spin_lock(&udc->lock);
1999 if (!(portsc & PORTSCX_PORT_SUSPEND)
2000 && udc->usb_state == USB_STATE_SUSPENDED) {
2001 handle_bus_resume(udc);
2004 if (!udc->resume_state)
2005 udc->usb_state = USB_STATE_DEFAULT;
2008 static void irq_process_error(struct mv_udc *udc)
2010 /* Increment the error count */
2014 static irqreturn_t mv_udc_irq(int irq, void *dev)
2016 struct mv_udc *udc = (struct mv_udc *)dev;
2019 /* Disable ISR when stopped bit is set */
2023 spin_lock(&udc->lock);
2025 status = readl(&udc->op_regs->usbsts);
2026 intr = readl(&udc->op_regs->usbintr);
2030 spin_unlock(&udc->lock);
2034 /* Clear all the interrupts occurred */
2035 writel(status, &udc->op_regs->usbsts);
2037 if (status & USBSTS_ERR)
2038 irq_process_error(udc);
2040 if (status & USBSTS_RESET)
2041 irq_process_reset(udc);
2043 if (status & USBSTS_PORT_CHANGE)
2044 irq_process_port_change(udc);
2046 if (status & USBSTS_INT)
2047 irq_process_tr_complete(udc);
2049 if (status & USBSTS_SUSPEND)
2050 irq_process_suspend(udc);
2052 spin_unlock(&udc->lock);
2057 static irqreturn_t mv_udc_vbus_irq(int irq, void *dev)
2059 struct mv_udc *udc = (struct mv_udc *)dev;
2061 /* polling VBUS and init phy may cause too much time*/
2063 queue_work(udc->qwork, &udc->vbus_work);
2068 static void mv_udc_vbus_work(struct work_struct *work)
2073 udc = container_of(work, struct mv_udc, vbus_work);
2074 if (!udc->pdata->vbus)
2077 vbus = udc->pdata->vbus->poll();
2078 dev_info(&udc->dev->dev, "vbus is %d\n", vbus);
2080 if (vbus == VBUS_HIGH)
2081 mv_udc_vbus_session(&udc->gadget, 1);
2082 else if (vbus == VBUS_LOW)
2083 mv_udc_vbus_session(&udc->gadget, 0);
2086 /* release device structure */
2087 static void gadget_release(struct device *_dev)
2089 struct mv_udc *udc = the_controller;
2091 complete(udc->done);
2094 static int __devexit mv_udc_remove(struct platform_device *dev)
2096 struct mv_udc *udc = the_controller;
2099 usb_del_gadget_udc(&udc->gadget);
2102 flush_workqueue(udc->qwork);
2103 destroy_workqueue(udc->qwork);
2107 * If we have transceiver inited,
2108 * then vbus irq will not be requested in udc driver.
2110 if (udc->pdata && udc->pdata->vbus
2111 && udc->clock_gating && IS_ERR_OR_NULL(udc->transceiver))
2112 free_irq(udc->pdata->vbus->irq, &dev->dev);
2114 /* free memory allocated in probe */
2116 dma_pool_destroy(udc->dtd_pool);
2119 dma_free_coherent(&dev->dev, udc->ep_dqh_size,
2120 udc->ep_dqh, udc->ep_dqh_dma);
2125 free_irq(udc->irq, &dev->dev);
2127 mv_udc_disable(udc);
2130 iounmap(udc->cap_regs);
2133 iounmap(udc->phy_regs);
2135 if (udc->status_req) {
2136 kfree(udc->status_req->req.buf);
2137 kfree(udc->status_req);
2140 for (clk_i = 0; clk_i <= udc->clknum; clk_i++)
2141 clk_put(udc->clk[clk_i]);
2143 device_unregister(&udc->gadget.dev);
2145 /* free dev, wait for the release() finished */
2146 wait_for_completion(udc->done);
2149 the_controller = NULL;
2154 static int __devinit mv_udc_probe(struct platform_device *dev)
2156 struct mv_usb_platform_data *pdata = dev->dev.platform_data;
2163 if (pdata == NULL) {
2164 dev_err(&dev->dev, "missing platform_data\n");
2168 size = sizeof(*udc) + sizeof(struct clk *) * pdata->clknum;
2169 udc = kzalloc(size, GFP_KERNEL);
2171 dev_err(&dev->dev, "failed to allocate memory for udc\n");
2175 the_controller = udc;
2176 udc->done = &release_done;
2177 udc->pdata = dev->dev.platform_data;
2178 spin_lock_init(&udc->lock);
2182 #ifdef CONFIG_USB_OTG_UTILS
2183 if (pdata->mode == MV_USB_MODE_OTG)
2184 udc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
2187 udc->clknum = pdata->clknum;
2188 for (clk_i = 0; clk_i < udc->clknum; clk_i++) {
2189 udc->clk[clk_i] = clk_get(&dev->dev, pdata->clkname[clk_i]);
2190 if (IS_ERR(udc->clk[clk_i])) {
2191 retval = PTR_ERR(udc->clk[clk_i]);
2196 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "capregs");
2198 dev_err(&dev->dev, "no I/O memory resource defined\n");
2203 udc->cap_regs = (struct mv_cap_regs __iomem *)
2204 ioremap(r->start, resource_size(r));
2205 if (udc->cap_regs == NULL) {
2206 dev_err(&dev->dev, "failed to map I/O memory\n");
2211 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "phyregs");
2213 dev_err(&dev->dev, "no phy I/O memory resource defined\n");
2215 goto err_iounmap_capreg;
2218 udc->phy_regs = ioremap(r->start, resource_size(r));
2219 if (udc->phy_regs == NULL) {
2220 dev_err(&dev->dev, "failed to map phy I/O memory\n");
2222 goto err_iounmap_capreg;
2225 /* we will acces controller register, so enable the clk */
2226 retval = mv_udc_enable_internal(udc);
2228 goto err_iounmap_phyreg;
2231 (struct mv_op_regs __iomem *)((unsigned long)udc->cap_regs
2232 + (readl(&udc->cap_regs->caplength_hciversion)
2234 udc->max_eps = readl(&udc->cap_regs->dccparams) & DCCPARAMS_DEN_MASK;
2237 * some platform will use usb to download image, it may not disconnect
2238 * usb gadget before loading kernel. So first stop udc here.
2241 writel(0xFFFFFFFF, &udc->op_regs->usbsts);
2243 size = udc->max_eps * sizeof(struct mv_dqh) *2;
2244 size = (size + DQH_ALIGNMENT - 1) & ~(DQH_ALIGNMENT - 1);
2245 udc->ep_dqh = dma_alloc_coherent(&dev->dev, size,
2246 &udc->ep_dqh_dma, GFP_KERNEL);
2248 if (udc->ep_dqh == NULL) {
2249 dev_err(&dev->dev, "allocate dQH memory failed\n");
2251 goto err_disable_clock;
2253 udc->ep_dqh_size = size;
2255 /* create dTD dma_pool resource */
2256 udc->dtd_pool = dma_pool_create("mv_dtd",
2258 sizeof(struct mv_dtd),
2262 if (!udc->dtd_pool) {
2267 size = udc->max_eps * sizeof(struct mv_ep) *2;
2268 udc->eps = kzalloc(size, GFP_KERNEL);
2269 if (udc->eps == NULL) {
2270 dev_err(&dev->dev, "allocate ep memory failed\n");
2272 goto err_destroy_dma;
2275 /* initialize ep0 status request structure */
2276 udc->status_req = kzalloc(sizeof(struct mv_req), GFP_KERNEL);
2277 if (!udc->status_req) {
2278 dev_err(&dev->dev, "allocate status_req memory failed\n");
2282 INIT_LIST_HEAD(&udc->status_req->queue);
2284 /* allocate a small amount of memory to get valid address */
2285 udc->status_req->req.buf = kzalloc(8, GFP_KERNEL);
2286 udc->status_req->req.dma = DMA_ADDR_INVALID;
2288 udc->resume_state = USB_STATE_NOTATTACHED;
2289 udc->usb_state = USB_STATE_POWERED;
2290 udc->ep0_dir = EP_DIR_OUT;
2291 udc->remote_wakeup = 0;
2293 r = platform_get_resource(udc->dev, IORESOURCE_IRQ, 0);
2295 dev_err(&dev->dev, "no IRQ resource defined\n");
2297 goto err_free_status_req;
2299 udc->irq = r->start;
2300 if (request_irq(udc->irq, mv_udc_irq,
2301 IRQF_SHARED, driver_name, udc)) {
2302 dev_err(&dev->dev, "Request irq %d for UDC failed\n",
2305 goto err_free_status_req;
2308 /* initialize gadget structure */
2309 udc->gadget.ops = &mv_ops; /* usb_gadget_ops */
2310 udc->gadget.ep0 = &udc->eps[0].ep; /* gadget ep0 */
2311 INIT_LIST_HEAD(&udc->gadget.ep_list); /* ep_list */
2312 udc->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
2313 udc->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */
2315 /* the "gadget" abstracts/virtualizes the controller */
2316 dev_set_name(&udc->gadget.dev, "gadget");
2317 udc->gadget.dev.parent = &dev->dev;
2318 udc->gadget.dev.dma_mask = dev->dev.dma_mask;
2319 udc->gadget.dev.release = gadget_release;
2320 udc->gadget.name = driver_name; /* gadget name */
2322 retval = device_register(&udc->gadget.dev);
2328 /* VBUS detect: we can disable/enable clock on demand.*/
2329 if (!IS_ERR_OR_NULL(udc->transceiver))
2330 udc->clock_gating = 1;
2331 else if (pdata->vbus) {
2332 udc->clock_gating = 1;
2333 retval = request_threaded_irq(pdata->vbus->irq, NULL,
2334 mv_udc_vbus_irq, IRQF_ONESHOT, "vbus", udc);
2337 "Can not request irq for VBUS, "
2338 "disable clock gating\n");
2339 udc->clock_gating = 0;
2342 udc->qwork = create_singlethread_workqueue("mv_udc_queue");
2344 dev_err(&dev->dev, "cannot create workqueue\n");
2346 goto err_unregister;
2349 INIT_WORK(&udc->vbus_work, mv_udc_vbus_work);
2353 * When clock gating is supported, we can disable clk and phy.
2354 * If not, it means that VBUS detection is not supported, we
2355 * have to enable vbus active all the time to let controller work.
2357 if (udc->clock_gating)
2358 mv_udc_disable_internal(udc);
2360 udc->vbus_active = 1;
2362 retval = usb_add_gadget_udc(&dev->dev, &udc->gadget);
2364 goto err_unregister;
2366 dev_info(&dev->dev, "successful probe UDC device %s clock gating.\n",
2367 udc->clock_gating ? "with" : "without");
2372 if (udc->pdata && udc->pdata->vbus
2373 && udc->clock_gating && IS_ERR_OR_NULL(udc->transceiver))
2374 free_irq(pdata->vbus->irq, &dev->dev);
2375 device_unregister(&udc->gadget.dev);
2377 free_irq(udc->irq, &dev->dev);
2378 err_free_status_req:
2379 kfree(udc->status_req->req.buf);
2380 kfree(udc->status_req);
2384 dma_pool_destroy(udc->dtd_pool);
2386 dma_free_coherent(&dev->dev, udc->ep_dqh_size,
2387 udc->ep_dqh, udc->ep_dqh_dma);
2389 mv_udc_disable_internal(udc);
2391 iounmap(udc->phy_regs);
2393 iounmap(udc->cap_regs);
2395 for (clk_i--; clk_i >= 0; clk_i--)
2396 clk_put(udc->clk[clk_i]);
2397 the_controller = NULL;
2403 static int mv_udc_suspend(struct device *_dev)
2405 struct mv_udc *udc = the_controller;
2407 /* if OTG is enabled, the following will be done in OTG driver*/
2408 if (!IS_ERR_OR_NULL(udc->transceiver))
2411 if (udc->pdata->vbus && udc->pdata->vbus->poll)
2412 if (udc->pdata->vbus->poll() == VBUS_HIGH) {
2413 dev_info(&udc->dev->dev, "USB cable is connected!\n");
2418 * only cable is unplugged, udc can suspend.
2419 * So do not care about clock_gating == 1.
2421 if (!udc->clock_gating) {
2424 spin_lock_irq(&udc->lock);
2425 /* stop all usb activities */
2426 stop_activity(udc, udc->driver);
2427 spin_unlock_irq(&udc->lock);
2429 mv_udc_disable_internal(udc);
2435 static int mv_udc_resume(struct device *_dev)
2437 struct mv_udc *udc = the_controller;
2440 /* if OTG is enabled, the following will be done in OTG driver*/
2441 if (!IS_ERR_OR_NULL(udc->transceiver))
2444 if (!udc->clock_gating) {
2445 retval = mv_udc_enable_internal(udc);
2449 if (udc->driver && udc->softconnect) {
2459 static const struct dev_pm_ops mv_udc_pm_ops = {
2460 .suspend = mv_udc_suspend,
2461 .resume = mv_udc_resume,
2465 static void mv_udc_shutdown(struct platform_device *dev)
2467 struct mv_udc *udc = the_controller;
2470 /* reset controller mode to IDLE */
2471 mode = readl(&udc->op_regs->usbmode);
2473 writel(mode, &udc->op_regs->usbmode);
2476 static struct platform_driver udc_driver = {
2477 .probe = mv_udc_probe,
2478 .remove = __exit_p(mv_udc_remove),
2479 .shutdown = mv_udc_shutdown,
2481 .owner = THIS_MODULE,
2484 .pm = &mv_udc_pm_ops,
2489 module_platform_driver(udc_driver);
2490 MODULE_ALIAS("platform:mv-udc");
2491 MODULE_DESCRIPTION(DRIVER_DESC);
2492 MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
2493 MODULE_VERSION(DRIVER_VERSION);
2494 MODULE_LICENSE("GPL");