2 * linux/drivers/usb/gadget/s3c-hsotg.c
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Copyright 2008 Openmoko, Inc.
8 * Copyright 2008 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
10 * http://armlinux.simtec.co.uk/
12 * S3C USB2.0 High-speed / OtG driver
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/debugfs.h>
26 #include <linux/seq_file.h>
27 #include <linux/delay.h>
29 #include <linux/slab.h>
30 #include <linux/clk.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/of_platform.h>
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 #include <linux/usb/phy.h>
37 #include <linux/platform_data/s3c-hsotg.h>
41 #include "s3c-hsotg.h"
43 static const char * const s3c_hsotg_supply_names[] = {
44 "vusb_d", /* digital USB supply, 1.2V */
45 "vusb_a", /* analog USB supply, 1.1V */
51 * Unfortunately there seems to be a limit of the amount of data that can
52 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
53 * packets (which practically means 1 packet and 63 bytes of data) when the
56 * This means if we are wanting to move >127 bytes of data, we need to
57 * split the transactions up, but just doing one packet at a time does
58 * not work (this may be an implicit DATA0 PID on first packet of the
59 * transaction) and doing 2 packets is outside the controller's limits.
61 * If we try to lower the MPS size for EP0, then no transfers work properly
62 * for EP0, and the system will fail basic enumeration. As no cause for this
63 * has currently been found, we cannot support any large IN transfers for
66 #define EP0_MPS_LIMIT 64
72 * struct s3c_hsotg_ep - driver endpoint definition.
73 * @ep: The gadget layer representation of the endpoint.
74 * @name: The driver generated name for the endpoint.
75 * @queue: Queue of requests for this endpoint.
76 * @parent: Reference back to the parent device structure.
77 * @req: The current request that the endpoint is processing. This is
78 * used to indicate an request has been loaded onto the endpoint
79 * and has yet to be completed (maybe due to data move, or simply
80 * awaiting an ack from the core all the data has been completed).
81 * @debugfs: File entry for debugfs file for this endpoint.
82 * @lock: State lock to protect contents of endpoint.
83 * @dir_in: Set to true if this endpoint is of the IN direction, which
84 * means that it is sending data to the Host.
85 * @index: The index for the endpoint registers.
86 * @mc: Multi Count - number of transactions per microframe
87 * @interval - Interval for periodic endpoints
88 * @name: The name array passed to the USB core.
89 * @halted: Set if the endpoint has been halted.
90 * @periodic: Set if this is a periodic ep, such as Interrupt
91 * @isochronous: Set if this is a isochronous ep
92 * @sent_zlp: Set if we've sent a zero-length packet.
93 * @total_data: The total number of data bytes done.
94 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
95 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
96 * @last_load: The offset of data for the last start of request.
97 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
99 * This is the driver's state for each registered enpoint, allowing it
100 * to keep track of transactions that need doing. Each endpoint has a
101 * lock to protect the state, to try and avoid using an overall lock
102 * for the host controller as much as possible.
104 * For periodic IN endpoints, we have fifo_size and fifo_load to try
105 * and keep track of the amount of data in the periodic FIFO for each
106 * of these as we don't have a status register that tells us how much
107 * is in each of them. (note, this may actually be useless information
108 * as in shared-fifo mode periodic in acts like a single-frame packet
109 * buffer than a fifo)
111 struct s3c_hsotg_ep {
113 struct list_head queue;
114 struct s3c_hsotg *parent;
115 struct s3c_hsotg_req *req;
116 struct dentry *debugfs;
119 unsigned long total_data;
120 unsigned int size_loaded;
121 unsigned int last_load;
122 unsigned int fifo_load;
123 unsigned short fifo_size;
125 unsigned char dir_in;
128 unsigned char interval;
130 unsigned int halted:1;
131 unsigned int periodic:1;
132 unsigned int isochronous:1;
133 unsigned int sent_zlp:1;
139 * struct s3c_hsotg - driver state.
140 * @dev: The parent device supplied to the probe function
141 * @driver: USB gadget driver
142 * @phy: The otg phy transceiver structure for phy control.
143 * @plat: The platform specific configuration data. This can be removed once
144 * all SoCs support usb transceiver.
145 * @regs: The memory area mapped for accessing registers.
146 * @irq: The IRQ number we are using
147 * @supplies: Definition of USB power supplies
148 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
149 * @num_of_eps: Number of available EPs (excluding EP0)
150 * @debug_root: root directrory for debugfs.
151 * @debug_file: main status file for debugfs.
152 * @debug_fifo: FIFO status file for debugfs.
153 * @ep0_reply: Request used for ep0 reply.
154 * @ep0_buff: Buffer for EP0 reply data, if needed.
155 * @ctrl_buff: Buffer for EP0 control requests.
156 * @ctrl_req: Request for EP0 control packets.
157 * @setup: NAK management for EP0 SETUP
158 * @last_rst: Time of last reset
159 * @eps: The endpoints being supplied to the gadget framework
163 struct usb_gadget_driver *driver;
165 struct s3c_hsotg_plat *plat;
173 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)];
175 unsigned int dedicated_fifos:1;
176 unsigned char num_of_eps;
178 struct dentry *debug_root;
179 struct dentry *debug_file;
180 struct dentry *debug_fifo;
182 struct usb_request *ep0_reply;
183 struct usb_request *ctrl_req;
187 struct usb_gadget gadget;
189 unsigned long last_rst;
190 struct s3c_hsotg_ep *eps;
194 * struct s3c_hsotg_req - data transfer request
195 * @req: The USB gadget request
196 * @queue: The list of requests for the endpoint this is queued for.
197 * @in_progress: Has already had size/packets written to core
198 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
200 struct s3c_hsotg_req {
201 struct usb_request req;
202 struct list_head queue;
203 unsigned char in_progress;
204 unsigned char mapped;
207 /* conversion functions */
208 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
210 return container_of(req, struct s3c_hsotg_req, req);
213 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
215 return container_of(ep, struct s3c_hsotg_ep, ep);
218 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
220 return container_of(gadget, struct s3c_hsotg, gadget);
223 static inline void __orr32(void __iomem *ptr, u32 val)
225 writel(readl(ptr) | val, ptr);
228 static inline void __bic32(void __iomem *ptr, u32 val)
230 writel(readl(ptr) & ~val, ptr);
233 /* forward decleration of functions */
234 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
237 * using_dma - return the DMA status of the driver.
238 * @hsotg: The driver state.
240 * Return true if we're using DMA.
242 * Currently, we have the DMA support code worked into everywhere
243 * that needs it, but the AMBA DMA implementation in the hardware can
244 * only DMA from 32bit aligned addresses. This means that gadgets such
245 * as the CDC Ethernet cannot work as they often pass packets which are
248 * Unfortunately the choice to use DMA or not is global to the controller
249 * and seems to be only settable when the controller is being put through
250 * a core reset. This means we either need to fix the gadgets to take
251 * account of DMA alignment, or add bounce buffers (yuerk).
253 * Until this issue is sorted out, we always return 'false'.
255 static inline bool using_dma(struct s3c_hsotg *hsotg)
257 return false; /* support is not complete */
261 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
262 * @hsotg: The device state
263 * @ints: A bitmask of the interrupts to enable
265 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
267 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
270 new_gsintmsk = gsintmsk | ints;
272 if (new_gsintmsk != gsintmsk) {
273 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
274 writel(new_gsintmsk, hsotg->regs + GINTMSK);
279 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
280 * @hsotg: The device state
281 * @ints: A bitmask of the interrupts to enable
283 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
285 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
288 new_gsintmsk = gsintmsk & ~ints;
290 if (new_gsintmsk != gsintmsk)
291 writel(new_gsintmsk, hsotg->regs + GINTMSK);
295 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
296 * @hsotg: The device state
297 * @ep: The endpoint index
298 * @dir_in: True if direction is in.
299 * @en: The enable value, true to enable
301 * Set or clear the mask for an individual endpoint's interrupt
304 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
305 unsigned int ep, unsigned int dir_in,
315 local_irq_save(flags);
316 daint = readl(hsotg->regs + DAINTMSK);
321 writel(daint, hsotg->regs + DAINTMSK);
322 local_irq_restore(flags);
326 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
327 * @hsotg: The device instance.
329 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
337 /* set FIFO sizes to 2048/1024 */
339 writel(2048, hsotg->regs + GRXFSIZ);
340 writel(GNPTXFSIZ_NPTxFStAddr(2048) |
341 GNPTXFSIZ_NPTxFDep(1024),
342 hsotg->regs + GNPTXFSIZ);
345 * arange all the rest of the TX FIFOs, as some versions of this
346 * block have overlapping default addresses. This also ensures
347 * that if the settings have been changed, then they are set to
351 /* start at the end of the GNPTXFSIZ, rounded up */
356 * currently we allocate TX FIFOs for all possible endpoints,
357 * and assume that they are all the same size.
360 for (ep = 1; ep <= 15; ep++) {
362 val |= size << DPTXFSIZn_DPTxFSize_SHIFT;
365 writel(val, hsotg->regs + DPTXFSIZn(ep));
369 * according to p428 of the design guide, we need to ensure that
370 * all fifos are flushed before continuing
373 writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh |
374 GRSTCTL_RxFFlsh, hsotg->regs + GRSTCTL);
376 /* wait until the fifos are both flushed */
379 val = readl(hsotg->regs + GRSTCTL);
381 if ((val & (GRSTCTL_TxFFlsh | GRSTCTL_RxFFlsh)) == 0)
384 if (--timeout == 0) {
386 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
393 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
397 * @ep: USB endpoint to allocate request for.
398 * @flags: Allocation flags
400 * Allocate a new USB request structure appropriate for the specified endpoint
402 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
405 struct s3c_hsotg_req *req;
407 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
411 INIT_LIST_HEAD(&req->queue);
417 * is_ep_periodic - return true if the endpoint is in periodic mode.
418 * @hs_ep: The endpoint to query.
420 * Returns true if the endpoint is in periodic mode, meaning it is being
421 * used for an Interrupt or ISO transfer.
423 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
425 return hs_ep->periodic;
429 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
430 * @hsotg: The device state.
431 * @hs_ep: The endpoint for the request
432 * @hs_req: The request being processed.
434 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
435 * of a request to ensure the buffer is ready for access by the caller.
437 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
438 struct s3c_hsotg_ep *hs_ep,
439 struct s3c_hsotg_req *hs_req)
441 struct usb_request *req = &hs_req->req;
443 /* ignore this if we're not moving any data */
444 if (hs_req->req.length == 0)
447 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
451 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
452 * @hsotg: The controller state.
453 * @hs_ep: The endpoint we're going to write for.
454 * @hs_req: The request to write data for.
456 * This is called when the TxFIFO has some space in it to hold a new
457 * transmission and we have something to give it. The actual setup of
458 * the data size is done elsewhere, so all we have to do is to actually
461 * The return value is zero if there is more space (or nothing was done)
462 * otherwise -ENOSPC is returned if the FIFO space was used up.
464 * This routine is only needed for PIO
466 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
467 struct s3c_hsotg_ep *hs_ep,
468 struct s3c_hsotg_req *hs_req)
470 bool periodic = is_ep_periodic(hs_ep);
471 u32 gnptxsts = readl(hsotg->regs + GNPTXSTS);
472 int buf_pos = hs_req->req.actual;
473 int to_write = hs_ep->size_loaded;
479 to_write -= (buf_pos - hs_ep->last_load);
481 /* if there's nothing to write, get out early */
485 if (periodic && !hsotg->dedicated_fifos) {
486 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
491 * work out how much data was loaded so we can calculate
492 * how much data is left in the fifo.
495 size_left = DxEPTSIZ_XferSize_GET(epsize);
498 * if shared fifo, we cannot write anything until the
499 * previous data has been completely sent.
501 if (hs_ep->fifo_load != 0) {
502 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp);
506 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
508 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
510 /* how much of the data has moved */
511 size_done = hs_ep->size_loaded - size_left;
513 /* how much data is left in the fifo */
514 can_write = hs_ep->fifo_load - size_done;
515 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
516 __func__, can_write);
518 can_write = hs_ep->fifo_size - can_write;
519 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
520 __func__, can_write);
522 if (can_write <= 0) {
523 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp);
526 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
527 can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index));
532 if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
534 "%s: no queue slots available (0x%08x)\n",
537 s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTxFEmp);
541 can_write = GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
542 can_write *= 4; /* fifo size is in 32bit quantities. */
545 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
547 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
548 __func__, gnptxsts, can_write, to_write, max_transfer);
551 * limit to 512 bytes of data, it seems at least on the non-periodic
552 * FIFO, requests of >512 cause the endpoint to get stuck with a
553 * fragment of the end of the transfer in it.
559 * limit the write to one max-packet size worth of data, but allow
560 * the transfer to return that it did not run out of fifo space
563 if (to_write > max_transfer) {
564 to_write = max_transfer;
566 s3c_hsotg_en_gsint(hsotg,
567 periodic ? GINTSTS_PTxFEmp :
571 /* see if we can write data */
573 if (to_write > can_write) {
574 to_write = can_write;
575 pkt_round = to_write % max_transfer;
578 * Round the write down to an
579 * exact number of packets.
581 * Note, we do not currently check to see if we can ever
582 * write a full packet or not to the FIFO.
586 to_write -= pkt_round;
589 * enable correct FIFO interrupt to alert us when there
593 s3c_hsotg_en_gsint(hsotg,
594 periodic ? GINTSTS_PTxFEmp :
598 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
599 to_write, hs_req->req.length, can_write, buf_pos);
604 hs_req->req.actual = buf_pos + to_write;
605 hs_ep->total_data += to_write;
608 hs_ep->fifo_load += to_write;
610 to_write = DIV_ROUND_UP(to_write, 4);
611 data = hs_req->req.buf + buf_pos;
613 writesl(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
615 return (to_write >= can_write) ? -ENOSPC : 0;
619 * get_ep_limit - get the maximum data legnth for this endpoint
620 * @hs_ep: The endpoint
622 * Return the maximum data that can be queued in one go on a given endpoint
623 * so that transfers that are too long can be split.
625 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
627 int index = hs_ep->index;
632 maxsize = DxEPTSIZ_XferSize_LIMIT + 1;
633 maxpkt = DxEPTSIZ_PktCnt_LIMIT + 1;
637 maxpkt = DIEPTSIZ0_PktCnt_LIMIT + 1;
642 /* we made the constant loading easier above by using +1 */
647 * constrain by packet count if maxpkts*pktsize is greater
648 * than the length register size.
651 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
652 maxsize = maxpkt * hs_ep->ep.maxpacket;
658 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
659 * @hsotg: The controller state.
660 * @hs_ep: The endpoint to process a request for
661 * @hs_req: The request to start.
662 * @continuing: True if we are doing more for the current request.
664 * Start the given request running by setting the endpoint registers
665 * appropriately, and writing any data to the FIFOs.
667 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
668 struct s3c_hsotg_ep *hs_ep,
669 struct s3c_hsotg_req *hs_req,
672 struct usb_request *ureq = &hs_req->req;
673 int index = hs_ep->index;
674 int dir_in = hs_ep->dir_in;
684 if (hs_ep->req && !continuing) {
685 dev_err(hsotg->dev, "%s: active request\n", __func__);
688 } else if (hs_ep->req != hs_req && continuing) {
690 "%s: continue different req\n", __func__);
696 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
697 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
699 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
700 __func__, readl(hsotg->regs + epctrl_reg), index,
701 hs_ep->dir_in ? "in" : "out");
703 /* If endpoint is stalled, we will restart request later */
704 ctrl = readl(hsotg->regs + epctrl_reg);
706 if (ctrl & DxEPCTL_Stall) {
707 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
711 length = ureq->length - ureq->actual;
712 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
713 ureq->length, ureq->actual);
716 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
717 ureq->buf, length, ureq->dma,
718 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
720 maxreq = get_ep_limit(hs_ep);
721 if (length > maxreq) {
722 int round = maxreq % hs_ep->ep.maxpacket;
724 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
725 __func__, length, maxreq, round);
727 /* round down to multiple of packets */
735 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
737 packets = 1; /* send one packet if length is zero. */
739 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
740 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
744 if (dir_in && index != 0)
745 if (hs_ep->isochronous)
746 epsize = DxEPTSIZ_MC(packets);
748 epsize = DxEPTSIZ_MC(1);
752 if (index != 0 && ureq->zero) {
754 * test for the packets being exactly right for the
758 if (length == (packets * hs_ep->ep.maxpacket))
762 epsize |= DxEPTSIZ_PktCnt(packets);
763 epsize |= DxEPTSIZ_XferSize(length);
765 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
766 __func__, packets, length, ureq->length, epsize, epsize_reg);
768 /* store the request as the current one we're doing */
771 /* write size / packets */
772 writel(epsize, hsotg->regs + epsize_reg);
774 if (using_dma(hsotg) && !continuing) {
775 unsigned int dma_reg;
778 * write DMA address to control register, buffer already
779 * synced by s3c_hsotg_ep_queue().
782 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
783 writel(ureq->dma, hsotg->regs + dma_reg);
785 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
786 __func__, ureq->dma, dma_reg);
789 ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */
790 ctrl |= DxEPCTL_USBActEp;
792 dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup);
794 /* For Setup request do not clear NAK */
795 if (hsotg->setup && index == 0)
798 ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */
801 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
802 writel(ctrl, hsotg->regs + epctrl_reg);
805 * set these, it seems that DMA support increments past the end
806 * of the packet buffer so we need to calculate the length from
809 hs_ep->size_loaded = length;
810 hs_ep->last_load = ureq->actual;
812 if (dir_in && !using_dma(hsotg)) {
813 /* set these anyway, we may need them for non-periodic in */
814 hs_ep->fifo_load = 0;
816 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
820 * clear the INTknTXFEmpMsk when we start request, more as a aide
821 * to debugging to see what is going on.
824 writel(DIEPMSK_INTknTXFEmpMsk,
825 hsotg->regs + DIEPINT(index));
828 * Note, trying to clear the NAK here causes problems with transmit
829 * on the S3C6400 ending up with the TXFIFO becoming full.
832 /* check ep is enabled */
833 if (!(readl(hsotg->regs + epctrl_reg) & DxEPCTL_EPEna))
835 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
836 index, readl(hsotg->regs + epctrl_reg));
838 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
839 __func__, readl(hsotg->regs + epctrl_reg));
843 * s3c_hsotg_map_dma - map the DMA memory being used for the request
844 * @hsotg: The device state.
845 * @hs_ep: The endpoint the request is on.
846 * @req: The request being processed.
848 * We've been asked to queue a request, so ensure that the memory buffer
849 * is correctly setup for DMA. If we've been passed an extant DMA address
850 * then ensure the buffer has been synced to memory. If our buffer has no
851 * DMA memory, then we map the memory and mark our request to allow us to
852 * cleanup on completion.
854 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
855 struct s3c_hsotg_ep *hs_ep,
856 struct usb_request *req)
858 struct s3c_hsotg_req *hs_req = our_req(req);
861 /* if the length is zero, ignore the DMA data */
862 if (hs_req->req.length == 0)
865 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
872 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
873 __func__, req->buf, req->length);
878 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
881 struct s3c_hsotg_req *hs_req = our_req(req);
882 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
883 struct s3c_hsotg *hs = hs_ep->parent;
886 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
887 ep->name, req, req->length, req->buf, req->no_interrupt,
888 req->zero, req->short_not_ok);
890 /* initialise status of the request */
891 INIT_LIST_HEAD(&hs_req->queue);
893 req->status = -EINPROGRESS;
895 /* if we're using DMA, sync the buffers as necessary */
897 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
902 first = list_empty(&hs_ep->queue);
903 list_add_tail(&hs_req->queue, &hs_ep->queue);
906 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
911 static int s3c_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
914 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
915 struct s3c_hsotg *hs = hs_ep->parent;
916 unsigned long flags = 0;
919 spin_lock_irqsave(&hs->lock, flags);
920 ret = s3c_hsotg_ep_queue(ep, req, gfp_flags);
921 spin_unlock_irqrestore(&hs->lock, flags);
926 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
927 struct usb_request *req)
929 struct s3c_hsotg_req *hs_req = our_req(req);
935 * s3c_hsotg_complete_oursetup - setup completion callback
936 * @ep: The endpoint the request was on.
937 * @req: The request completed.
939 * Called on completion of any requests the driver itself
940 * submitted that need cleaning up.
942 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
943 struct usb_request *req)
945 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
946 struct s3c_hsotg *hsotg = hs_ep->parent;
948 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
950 s3c_hsotg_ep_free_request(ep, req);
954 * ep_from_windex - convert control wIndex value to endpoint
955 * @hsotg: The driver state.
956 * @windex: The control request wIndex field (in host order).
958 * Convert the given wIndex into a pointer to an driver endpoint
959 * structure, or return NULL if it is not a valid endpoint.
961 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
964 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
965 int dir = (windex & USB_DIR_IN) ? 1 : 0;
966 int idx = windex & 0x7F;
971 if (idx > hsotg->num_of_eps)
974 if (idx && ep->dir_in != dir)
981 * s3c_hsotg_send_reply - send reply to control request
982 * @hsotg: The device state
984 * @buff: Buffer for request
985 * @length: Length of reply.
987 * Create a request and queue it on the given endpoint. This is useful as
988 * an internal method of sending replies to certain control requests, etc.
990 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
991 struct s3c_hsotg_ep *ep,
995 struct usb_request *req;
998 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1000 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1001 hsotg->ep0_reply = req;
1003 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1007 req->buf = hsotg->ep0_buff;
1008 req->length = length;
1009 req->zero = 1; /* always do zero-length final transfer */
1010 req->complete = s3c_hsotg_complete_oursetup;
1013 memcpy(req->buf, buff, length);
1017 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1019 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1027 * s3c_hsotg_process_req_status - process request GET_STATUS
1028 * @hsotg: The device state
1029 * @ctrl: USB control request
1031 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
1032 struct usb_ctrlrequest *ctrl)
1034 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1035 struct s3c_hsotg_ep *ep;
1039 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1042 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1046 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1047 case USB_RECIP_DEVICE:
1048 reply = cpu_to_le16(0); /* bit 0 => self powered,
1049 * bit 1 => remote wakeup */
1052 case USB_RECIP_INTERFACE:
1053 /* currently, the data result should be zero */
1054 reply = cpu_to_le16(0);
1057 case USB_RECIP_ENDPOINT:
1058 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1062 reply = cpu_to_le16(ep->halted ? 1 : 0);
1069 if (le16_to_cpu(ctrl->wLength) != 2)
1072 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
1074 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1081 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1084 * get_ep_head - return the first request on the endpoint
1085 * @hs_ep: The controller endpoint to get
1087 * Get the first request on the endpoint.
1089 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1091 if (list_empty(&hs_ep->queue))
1094 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1098 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1099 * @hsotg: The device state
1100 * @ctrl: USB control request
1102 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
1103 struct usb_ctrlrequest *ctrl)
1105 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1106 struct s3c_hsotg_req *hs_req;
1108 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1109 struct s3c_hsotg_ep *ep;
1112 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1113 __func__, set ? "SET" : "CLEAR");
1115 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
1116 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1118 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1119 __func__, le16_to_cpu(ctrl->wIndex));
1123 switch (le16_to_cpu(ctrl->wValue)) {
1124 case USB_ENDPOINT_HALT:
1125 s3c_hsotg_ep_sethalt(&ep->ep, set);
1127 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1130 "%s: failed to send reply\n", __func__);
1136 * If we have request in progress,
1142 list_del_init(&hs_req->queue);
1143 hs_req->req.complete(&ep->ep,
1147 /* If we have pending request, then start it */
1148 restart = !list_empty(&ep->queue);
1150 hs_req = get_ep_head(ep);
1151 s3c_hsotg_start_req(hsotg, ep,
1162 return -ENOENT; /* currently only deal with endpoint */
1167 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1170 * s3c_hsotg_process_control - process a control request
1171 * @hsotg: The device state
1172 * @ctrl: The control request received
1174 * The controller has received the SETUP phase of a control request, and
1175 * needs to work out what to do next (and whether to pass it on to the
1178 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1179 struct usb_ctrlrequest *ctrl)
1181 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1187 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1188 ctrl->bRequest, ctrl->bRequestType,
1189 ctrl->wValue, ctrl->wLength);
1192 * record the direction of the request, for later use when enquing
1196 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1197 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1200 * if we've no data with this request, then the last part of the
1201 * transaction is going to implicitly be IN.
1203 if (ctrl->wLength == 0)
1206 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1207 switch (ctrl->bRequest) {
1208 case USB_REQ_SET_ADDRESS:
1209 dcfg = readl(hsotg->regs + DCFG);
1210 dcfg &= ~DCFG_DevAddr_MASK;
1211 dcfg |= ctrl->wValue << DCFG_DevAddr_SHIFT;
1212 writel(dcfg, hsotg->regs + DCFG);
1214 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1216 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1219 case USB_REQ_GET_STATUS:
1220 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1223 case USB_REQ_CLEAR_FEATURE:
1224 case USB_REQ_SET_FEATURE:
1225 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1230 /* as a fallback, try delivering it to the driver to deal with */
1232 if (ret == 0 && hsotg->driver) {
1233 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1235 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1239 * the request is either unhandlable, or is not formatted correctly
1240 * so respond with a STALL for the status stage to indicate failure.
1247 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1248 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1251 * DxEPCTL_Stall will be cleared by EP once it has
1252 * taken effect, so no need to clear later.
1255 ctrl = readl(hsotg->regs + reg);
1256 ctrl |= DxEPCTL_Stall;
1257 ctrl |= DxEPCTL_CNAK;
1258 writel(ctrl, hsotg->regs + reg);
1261 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1262 ctrl, reg, readl(hsotg->regs + reg));
1265 * don't believe we need to anything more to get the EP
1266 * to reply with a STALL packet
1270 * complete won't be called, so we enqueue
1271 * setup request here
1273 s3c_hsotg_enqueue_setup(hsotg);
1278 * s3c_hsotg_complete_setup - completion of a setup transfer
1279 * @ep: The endpoint the request was on.
1280 * @req: The request completed.
1282 * Called on completion of any requests the driver itself submitted for
1285 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1286 struct usb_request *req)
1288 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1289 struct s3c_hsotg *hsotg = hs_ep->parent;
1291 if (req->status < 0) {
1292 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1296 if (req->actual == 0)
1297 s3c_hsotg_enqueue_setup(hsotg);
1299 s3c_hsotg_process_control(hsotg, req->buf);
1303 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1304 * @hsotg: The device state.
1306 * Enqueue a request on EP0 if necessary to received any SETUP packets
1307 * received from the host.
1309 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1311 struct usb_request *req = hsotg->ctrl_req;
1312 struct s3c_hsotg_req *hs_req = our_req(req);
1315 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1319 req->buf = hsotg->ctrl_buff;
1320 req->complete = s3c_hsotg_complete_setup;
1322 if (!list_empty(&hs_req->queue)) {
1323 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1327 hsotg->eps[0].dir_in = 0;
1329 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1331 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1333 * Don't think there's much we can do other than watch the
1340 * s3c_hsotg_complete_request - complete a request given to us
1341 * @hsotg: The device state.
1342 * @hs_ep: The endpoint the request was on.
1343 * @hs_req: The request to complete.
1344 * @result: The result code (0 => Ok, otherwise errno)
1346 * The given request has finished, so call the necessary completion
1347 * if it has one and then look to see if we can start a new request
1350 * Note, expects the ep to already be locked as appropriate.
1352 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1353 struct s3c_hsotg_ep *hs_ep,
1354 struct s3c_hsotg_req *hs_req,
1360 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1364 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1365 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1368 * only replace the status if we've not already set an error
1369 * from a previous transaction
1372 if (hs_req->req.status == -EINPROGRESS)
1373 hs_req->req.status = result;
1376 list_del_init(&hs_req->queue);
1378 if (using_dma(hsotg))
1379 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1382 * call the complete request with the locks off, just in case the
1383 * request tries to queue more work for this endpoint.
1386 if (hs_req->req.complete) {
1387 spin_unlock(&hsotg->lock);
1388 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1389 spin_lock(&hsotg->lock);
1393 * Look to see if there is anything else to do. Note, the completion
1394 * of the previous request may have caused a new request to be started
1395 * so be careful when doing this.
1398 if (!hs_ep->req && result >= 0) {
1399 restart = !list_empty(&hs_ep->queue);
1401 hs_req = get_ep_head(hs_ep);
1402 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1408 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1409 * @hsotg: The device state.
1410 * @ep_idx: The endpoint index for the data
1411 * @size: The size of data in the fifo, in bytes
1413 * The FIFO status shows there is data to read from the FIFO for a given
1414 * endpoint, so sort out whether we need to read the data into a request
1415 * that has been made for that endpoint.
1417 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1419 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1420 struct s3c_hsotg_req *hs_req = hs_ep->req;
1421 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1428 u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
1431 dev_warn(hsotg->dev,
1432 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1433 __func__, size, ep_idx, epctl);
1435 /* dump the data from the FIFO, we've nothing we can do */
1436 for (ptr = 0; ptr < size; ptr += 4)
1443 read_ptr = hs_req->req.actual;
1444 max_req = hs_req->req.length - read_ptr;
1446 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1447 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1449 if (to_read > max_req) {
1451 * more data appeared than we where willing
1452 * to deal with in this request.
1455 /* currently we don't deal this */
1459 hs_ep->total_data += to_read;
1460 hs_req->req.actual += to_read;
1461 to_read = DIV_ROUND_UP(to_read, 4);
1464 * note, we might over-write the buffer end by 3 bytes depending on
1465 * alignment of the data.
1467 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1471 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1472 * @hsotg: The device instance
1473 * @req: The request currently on this endpoint
1475 * Generate a zero-length IN packet request for terminating a SETUP
1478 * Note, since we don't write any data to the TxFIFO, then it is
1479 * currently believed that we do not need to wait for any space in
1482 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1483 struct s3c_hsotg_req *req)
1488 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1492 if (req->req.length == 0) {
1493 hsotg->eps[0].sent_zlp = 1;
1494 s3c_hsotg_enqueue_setup(hsotg);
1498 hsotg->eps[0].dir_in = 1;
1499 hsotg->eps[0].sent_zlp = 1;
1501 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1503 /* issue a zero-sized packet to terminate this */
1504 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
1505 DxEPTSIZ_XferSize(0), hsotg->regs + DIEPTSIZ(0));
1507 ctrl = readl(hsotg->regs + DIEPCTL0);
1508 ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */
1509 ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */
1510 ctrl |= DxEPCTL_USBActEp;
1511 writel(ctrl, hsotg->regs + DIEPCTL0);
1515 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1516 * @hsotg: The device instance
1517 * @epnum: The endpoint received from
1518 * @was_setup: Set if processing a SetupDone event.
1520 * The RXFIFO has delivered an OutDone event, which means that the data
1521 * transfer for an OUT endpoint has been completed, either by a short
1522 * packet or by the finish of a transfer.
1524 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1525 int epnum, bool was_setup)
1527 u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
1528 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1529 struct s3c_hsotg_req *hs_req = hs_ep->req;
1530 struct usb_request *req = &hs_req->req;
1531 unsigned size_left = DxEPTSIZ_XferSize_GET(epsize);
1535 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1539 if (using_dma(hsotg)) {
1543 * Calculate the size of the transfer by checking how much
1544 * is left in the endpoint size register and then working it
1545 * out from the amount we loaded for the transfer.
1547 * We need to do this as DMA pointers are always 32bit aligned
1548 * so may overshoot/undershoot the transfer.
1551 size_done = hs_ep->size_loaded - size_left;
1552 size_done += hs_ep->last_load;
1554 req->actual = size_done;
1557 /* if there is more request to do, schedule new transfer */
1558 if (req->actual < req->length && size_left == 0) {
1559 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1561 } else if (epnum == 0) {
1563 * After was_setup = 1 =>
1564 * set CNAK for non Setup requests
1566 hsotg->setup = was_setup ? 0 : 1;
1569 if (req->actual < req->length && req->short_not_ok) {
1570 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1571 __func__, req->actual, req->length);
1574 * todo - what should we return here? there's no one else
1575 * even bothering to check the status.
1581 * Condition req->complete != s3c_hsotg_complete_setup says:
1582 * send ZLP when we have an asynchronous request from gadget
1584 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1585 s3c_hsotg_send_zlp(hsotg, hs_req);
1588 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1592 * s3c_hsotg_read_frameno - read current frame number
1593 * @hsotg: The device instance
1595 * Return the current frame number
1597 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1601 dsts = readl(hsotg->regs + DSTS);
1602 dsts &= DSTS_SOFFN_MASK;
1603 dsts >>= DSTS_SOFFN_SHIFT;
1609 * s3c_hsotg_handle_rx - RX FIFO has data
1610 * @hsotg: The device instance
1612 * The IRQ handler has detected that the RX FIFO has some data in it
1613 * that requires processing, so find out what is in there and do the
1616 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1617 * chunks, so if you have x packets received on an endpoint you'll get x
1618 * FIFO events delivered, each with a packet's worth of data in it.
1620 * When using DMA, we should not be processing events from the RXFIFO
1621 * as the actual data should be sent to the memory directly and we turn
1622 * on the completion interrupts to get notifications of transfer completion.
1624 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1626 u32 grxstsr = readl(hsotg->regs + GRXSTSP);
1627 u32 epnum, status, size;
1629 WARN_ON(using_dma(hsotg));
1631 epnum = grxstsr & GRXSTS_EPNum_MASK;
1632 status = grxstsr & GRXSTS_PktSts_MASK;
1634 size = grxstsr & GRXSTS_ByteCnt_MASK;
1635 size >>= GRXSTS_ByteCnt_SHIFT;
1638 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1639 __func__, grxstsr, size, epnum);
1641 #define __status(x) ((x) >> GRXSTS_PktSts_SHIFT)
1643 switch (status >> GRXSTS_PktSts_SHIFT) {
1644 case __status(GRXSTS_PktSts_GlobalOutNAK):
1645 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1648 case __status(GRXSTS_PktSts_OutDone):
1649 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1650 s3c_hsotg_read_frameno(hsotg));
1652 if (!using_dma(hsotg))
1653 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1656 case __status(GRXSTS_PktSts_SetupDone):
1658 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1659 s3c_hsotg_read_frameno(hsotg),
1660 readl(hsotg->regs + DOEPCTL(0)));
1662 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1665 case __status(GRXSTS_PktSts_OutRX):
1666 s3c_hsotg_rx_data(hsotg, epnum, size);
1669 case __status(GRXSTS_PktSts_SetupRX):
1671 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1672 s3c_hsotg_read_frameno(hsotg),
1673 readl(hsotg->regs + DOEPCTL(0)));
1675 s3c_hsotg_rx_data(hsotg, epnum, size);
1679 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1682 s3c_hsotg_dump(hsotg);
1688 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1689 * @mps: The maximum packet size in bytes.
1691 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1695 return D0EPCTL_MPS_64;
1697 return D0EPCTL_MPS_32;
1699 return D0EPCTL_MPS_16;
1701 return D0EPCTL_MPS_8;
1704 /* bad max packet size, warn and return invalid result */
1710 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1711 * @hsotg: The driver state.
1712 * @ep: The index number of the endpoint
1713 * @mps: The maximum packet size in bytes
1715 * Configure the maximum packet size for the given endpoint, updating
1716 * the hardware control registers to reflect this.
1718 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1719 unsigned int ep, unsigned int mps)
1721 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1722 void __iomem *regs = hsotg->regs;
1728 /* EP0 is a special case */
1729 mpsval = s3c_hsotg_ep0_mps(mps);
1732 hs_ep->ep.maxpacket = mps;
1735 mpsval = mps & DxEPCTL_MPS_MASK;
1738 mcval = ((mps >> 11) & 0x3) + 1;
1742 hs_ep->ep.maxpacket = mpsval;
1746 * update both the in and out endpoint controldir_ registers, even
1747 * if one of the directions may not be in use.
1750 reg = readl(regs + DIEPCTL(ep));
1751 reg &= ~DxEPCTL_MPS_MASK;
1753 writel(reg, regs + DIEPCTL(ep));
1756 reg = readl(regs + DOEPCTL(ep));
1757 reg &= ~DxEPCTL_MPS_MASK;
1759 writel(reg, regs + DOEPCTL(ep));
1765 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1769 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1770 * @hsotg: The driver state
1771 * @idx: The index for the endpoint (0..15)
1773 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx)
1778 writel(GRSTCTL_TxFNum(idx) | GRSTCTL_TxFFlsh,
1779 hsotg->regs + GRSTCTL);
1781 /* wait until the fifo is flushed */
1785 val = readl(hsotg->regs + GRSTCTL);
1787 if ((val & (GRSTCTL_TxFFlsh)) == 0)
1790 if (--timeout == 0) {
1792 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1801 * s3c_hsotg_trytx - check to see if anything needs transmitting
1802 * @hsotg: The driver state
1803 * @hs_ep: The driver endpoint to check.
1805 * Check to see if there is a request that has data to send, and if so
1806 * make an attempt to write data into the FIFO.
1808 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1809 struct s3c_hsotg_ep *hs_ep)
1811 struct s3c_hsotg_req *hs_req = hs_ep->req;
1813 if (!hs_ep->dir_in || !hs_req)
1816 if (hs_req->req.actual < hs_req->req.length) {
1817 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1819 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1826 * s3c_hsotg_complete_in - complete IN transfer
1827 * @hsotg: The device state.
1828 * @hs_ep: The endpoint that has just completed.
1830 * An IN transfer has been completed, update the transfer's state and then
1831 * call the relevant completion routines.
1833 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1834 struct s3c_hsotg_ep *hs_ep)
1836 struct s3c_hsotg_req *hs_req = hs_ep->req;
1837 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1838 int size_left, size_done;
1841 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1845 /* Finish ZLP handling for IN EP0 transactions */
1846 if (hsotg->eps[0].sent_zlp) {
1847 dev_dbg(hsotg->dev, "zlp packet received\n");
1848 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1853 * Calculate the size of the transfer by checking how much is left
1854 * in the endpoint size register and then working it out from
1855 * the amount we loaded for the transfer.
1857 * We do this even for DMA, as the transfer may have incremented
1858 * past the end of the buffer (DMA transfers are always 32bit
1862 size_left = DxEPTSIZ_XferSize_GET(epsize);
1864 size_done = hs_ep->size_loaded - size_left;
1865 size_done += hs_ep->last_load;
1867 if (hs_req->req.actual != size_done)
1868 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1869 __func__, hs_req->req.actual, size_done);
1871 hs_req->req.actual = size_done;
1872 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1873 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1876 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1877 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1878 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1879 * inform the host that no more data is available.
1880 * The state of req.zero member is checked to be sure that the value to
1881 * send is smaller than wValue expected from host.
1882 * Check req.length to NOT send another ZLP when the current one is
1883 * under completion (the one for which this completion has been called).
1885 if (hs_req->req.length && hs_ep->index == 0 && hs_req->req.zero &&
1886 hs_req->req.length == hs_req->req.actual &&
1887 !(hs_req->req.length % hs_ep->ep.maxpacket)) {
1889 dev_dbg(hsotg->dev, "ep0 zlp IN packet sent\n");
1890 s3c_hsotg_send_zlp(hsotg, hs_req);
1895 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1896 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1897 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1899 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1903 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1904 * @hsotg: The driver state
1905 * @idx: The index for the endpoint (0..15)
1906 * @dir_in: Set if this is an IN endpoint
1908 * Process and clear any interrupt pending for an individual endpoint
1910 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1913 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1914 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1915 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1916 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1920 ints = readl(hsotg->regs + epint_reg);
1921 ctrl = readl(hsotg->regs + epctl_reg);
1923 /* Clear endpoint interrupts */
1924 writel(ints, hsotg->regs + epint_reg);
1926 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1927 __func__, idx, dir_in ? "in" : "out", ints);
1929 if (ints & DxEPINT_XferCompl) {
1930 if (hs_ep->isochronous && hs_ep->interval == 1) {
1931 if (ctrl & DxEPCTL_EOFrNum)
1932 ctrl |= DxEPCTL_SetEvenFr;
1934 ctrl |= DxEPCTL_SetOddFr;
1935 writel(ctrl, hsotg->regs + epctl_reg);
1939 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1940 __func__, readl(hsotg->regs + epctl_reg),
1941 readl(hsotg->regs + epsiz_reg));
1944 * we get OutDone from the FIFO, so we only need to look
1945 * at completing IN requests here
1948 s3c_hsotg_complete_in(hsotg, hs_ep);
1950 if (idx == 0 && !hs_ep->req)
1951 s3c_hsotg_enqueue_setup(hsotg);
1952 } else if (using_dma(hsotg)) {
1954 * We're using DMA, we need to fire an OutDone here
1955 * as we ignore the RXFIFO.
1958 s3c_hsotg_handle_outdone(hsotg, idx, false);
1962 if (ints & DxEPINT_EPDisbld) {
1963 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1966 int epctl = readl(hsotg->regs + epctl_reg);
1968 s3c_hsotg_txfifo_flush(hsotg, idx);
1970 if ((epctl & DxEPCTL_Stall) &&
1971 (epctl & DxEPCTL_EPType_Bulk)) {
1972 int dctl = readl(hsotg->regs + DCTL);
1974 dctl |= DCTL_CGNPInNAK;
1975 writel(dctl, hsotg->regs + DCTL);
1980 if (ints & DxEPINT_AHBErr)
1981 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1983 if (ints & DxEPINT_Setup) { /* Setup or Timeout */
1984 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1986 if (using_dma(hsotg) && idx == 0) {
1988 * this is the notification we've received a
1989 * setup packet. In non-DMA mode we'd get this
1990 * from the RXFIFO, instead we need to process
1997 s3c_hsotg_handle_outdone(hsotg, 0, true);
2001 if (ints & DxEPINT_Back2BackSetup)
2002 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2004 if (dir_in && !hs_ep->isochronous) {
2005 /* not sure if this is important, but we'll clear it anyway */
2006 if (ints & DIEPMSK_INTknTXFEmpMsk) {
2007 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2011 /* this probably means something bad is happening */
2012 if (ints & DIEPMSK_INTknEPMisMsk) {
2013 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2017 /* FIFO has space or is empty (see GAHBCFG) */
2018 if (hsotg->dedicated_fifos &&
2019 ints & DIEPMSK_TxFIFOEmpty) {
2020 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2022 if (!using_dma(hsotg))
2023 s3c_hsotg_trytx(hsotg, hs_ep);
2029 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2030 * @hsotg: The device state.
2032 * Handle updating the device settings after the enumeration phase has
2035 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
2037 u32 dsts = readl(hsotg->regs + DSTS);
2038 int ep0_mps = 0, ep_mps;
2041 * This should signal the finish of the enumeration phase
2042 * of the USB handshaking, so we should now know what rate
2046 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2049 * note, since we're limited by the size of transfer on EP0, and
2050 * it seems IN transfers must be a even number of packets we do
2051 * not advertise a 64byte MPS on EP0.
2054 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2055 switch (dsts & DSTS_EnumSpd_MASK) {
2056 case DSTS_EnumSpd_FS:
2057 case DSTS_EnumSpd_FS48:
2058 hsotg->gadget.speed = USB_SPEED_FULL;
2059 ep0_mps = EP0_MPS_LIMIT;
2063 case DSTS_EnumSpd_HS:
2064 hsotg->gadget.speed = USB_SPEED_HIGH;
2065 ep0_mps = EP0_MPS_LIMIT;
2069 case DSTS_EnumSpd_LS:
2070 hsotg->gadget.speed = USB_SPEED_LOW;
2072 * note, we don't actually support LS in this driver at the
2073 * moment, and the documentation seems to imply that it isn't
2074 * supported by the PHYs on some of the devices.
2078 dev_info(hsotg->dev, "new device is %s\n",
2079 usb_speed_string(hsotg->gadget.speed));
2082 * we should now know the maximum packet size for an
2083 * endpoint, so set the endpoints to a default value.
2088 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
2089 for (i = 1; i < hsotg->num_of_eps; i++)
2090 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
2093 /* ensure after enumeration our EP0 is active */
2095 s3c_hsotg_enqueue_setup(hsotg);
2097 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2098 readl(hsotg->regs + DIEPCTL0),
2099 readl(hsotg->regs + DOEPCTL0));
2103 * kill_all_requests - remove all requests from the endpoint's queue
2104 * @hsotg: The device state.
2105 * @ep: The endpoint the requests may be on.
2106 * @result: The result code to use.
2107 * @force: Force removal of any current requests
2109 * Go through the requests on the given endpoint and mark them
2110 * completed with the given result code.
2112 static void kill_all_requests(struct s3c_hsotg *hsotg,
2113 struct s3c_hsotg_ep *ep,
2114 int result, bool force)
2116 struct s3c_hsotg_req *req, *treq;
2118 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2120 * currently, we can't do much about an already
2121 * running request on an in endpoint
2124 if (ep->req == req && ep->dir_in && !force)
2127 s3c_hsotg_complete_request(hsotg, ep, req,
2132 #define call_gadget(_hs, _entry) \
2134 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
2135 (_hs)->driver && (_hs)->driver->_entry) { \
2136 spin_unlock(&_hs->lock); \
2137 (_hs)->driver->_entry(&(_hs)->gadget); \
2138 spin_lock(&_hs->lock); \
2143 * s3c_hsotg_disconnect - disconnect service
2144 * @hsotg: The device state.
2146 * The device has been disconnected. Remove all current
2147 * transactions and signal the gadget driver that this
2150 static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg)
2154 for (ep = 0; ep < hsotg->num_of_eps; ep++)
2155 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
2157 call_gadget(hsotg, disconnect);
2161 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2162 * @hsotg: The device state:
2163 * @periodic: True if this is a periodic FIFO interrupt
2165 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2167 struct s3c_hsotg_ep *ep;
2170 /* look through for any more data to transmit */
2172 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2173 ep = &hsotg->eps[epno];
2178 if ((periodic && !ep->periodic) ||
2179 (!periodic && ep->periodic))
2182 ret = s3c_hsotg_trytx(hsotg, ep);
2188 /* IRQ flags which will trigger a retry around the IRQ loop */
2189 #define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \
2194 * s3c_hsotg_corereset - issue softreset to the core
2195 * @hsotg: The device state
2197 * Issue a soft reset to the core, and await the core finishing it.
2199 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2204 dev_dbg(hsotg->dev, "resetting core\n");
2206 /* issue soft reset */
2207 writel(GRSTCTL_CSftRst, hsotg->regs + GRSTCTL);
2211 grstctl = readl(hsotg->regs + GRSTCTL);
2212 } while ((grstctl & GRSTCTL_CSftRst) && timeout-- > 0);
2214 if (grstctl & GRSTCTL_CSftRst) {
2215 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2222 u32 grstctl = readl(hsotg->regs + GRSTCTL);
2224 if (timeout-- < 0) {
2225 dev_info(hsotg->dev,
2226 "%s: reset failed, GRSTCTL=%08x\n",
2231 if (!(grstctl & GRSTCTL_AHBIdle))
2234 break; /* reset done */
2237 dev_dbg(hsotg->dev, "reset successful\n");
2242 * s3c_hsotg_core_init - issue softreset to the core
2243 * @hsotg: The device state
2245 * Issue a soft reset to the core, and await the core finishing it.
2247 static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2249 s3c_hsotg_corereset(hsotg);
2252 * we must now enable ep0 ready for host detection and then
2253 * set configuration.
2256 /* set the PLL on, remove the HNP/SRP and set the PHY */
2257 writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) |
2258 (0x5 << 10), hsotg->regs + GUSBCFG);
2260 s3c_hsotg_init_fifo(hsotg);
2262 __orr32(hsotg->regs + DCTL, DCTL_SftDiscon);
2264 writel(1 << 18 | DCFG_DevSpd_HS, hsotg->regs + DCFG);
2266 /* Clear any pending OTG interrupts */
2267 writel(0xffffffff, hsotg->regs + GOTGINT);
2269 /* Clear any pending interrupts */
2270 writel(0xffffffff, hsotg->regs + GINTSTS);
2272 writel(GINTSTS_ErlySusp | GINTSTS_SessReqInt |
2273 GINTSTS_GOUTNakEff | GINTSTS_GINNakEff |
2274 GINTSTS_ConIDStsChng | GINTSTS_USBRst |
2275 GINTSTS_EnumDone | GINTSTS_OTGInt |
2276 GINTSTS_USBSusp | GINTSTS_WkUpInt,
2277 hsotg->regs + GINTMSK);
2279 if (using_dma(hsotg))
2280 writel(GAHBCFG_GlblIntrEn | GAHBCFG_DMAEn |
2281 GAHBCFG_HBstLen_Incr4,
2282 hsotg->regs + GAHBCFG);
2284 writel(GAHBCFG_GlblIntrEn, hsotg->regs + GAHBCFG);
2287 * Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2288 * up being flooded with interrupts if the host is polling the
2289 * endpoint to try and read data.
2292 writel(((hsotg->dedicated_fifos) ? DIEPMSK_TxFIFOEmpty : 0) |
2293 DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk |
2294 DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
2295 DIEPMSK_INTknEPMisMsk,
2296 hsotg->regs + DIEPMSK);
2299 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2300 * DMA mode we may need this.
2302 writel((using_dma(hsotg) ? (DIEPMSK_XferComplMsk |
2303 DIEPMSK_TimeOUTMsk) : 0) |
2304 DOEPMSK_EPDisbldMsk | DOEPMSK_AHBErrMsk |
2306 hsotg->regs + DOEPMSK);
2308 writel(0, hsotg->regs + DAINTMSK);
2310 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2311 readl(hsotg->regs + DIEPCTL0),
2312 readl(hsotg->regs + DOEPCTL0));
2314 /* enable in and out endpoint interrupts */
2315 s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPInt | GINTSTS_IEPInt);
2318 * Enable the RXFIFO when in slave mode, as this is how we collect
2319 * the data. In DMA mode, we get events from the FIFO but also
2320 * things we cannot process, so do not use it.
2322 if (!using_dma(hsotg))
2323 s3c_hsotg_en_gsint(hsotg, GINTSTS_RxFLvl);
2325 /* Enable interrupts for EP0 in and out */
2326 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2327 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2329 __orr32(hsotg->regs + DCTL, DCTL_PWROnPrgDone);
2330 udelay(10); /* see openiboot */
2331 __bic32(hsotg->regs + DCTL, DCTL_PWROnPrgDone);
2333 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL));
2336 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2337 * writing to the EPCTL register..
2340 /* set to read 1 8byte packet */
2341 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
2342 DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2344 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2345 DxEPCTL_CNAK | DxEPCTL_EPEna |
2347 hsotg->regs + DOEPCTL0);
2349 /* enable, but don't activate EP0in */
2350 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2351 DxEPCTL_USBActEp, hsotg->regs + DIEPCTL0);
2353 s3c_hsotg_enqueue_setup(hsotg);
2355 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2356 readl(hsotg->regs + DIEPCTL0),
2357 readl(hsotg->regs + DOEPCTL0));
2359 /* clear global NAKs */
2360 writel(DCTL_CGOUTNak | DCTL_CGNPInNAK,
2361 hsotg->regs + DCTL);
2363 /* must be at-least 3ms to allow bus to see disconnect */
2366 /* remove the soft-disconnect and let's go */
2367 __bic32(hsotg->regs + DCTL, DCTL_SftDiscon);
2371 * s3c_hsotg_irq - handle device interrupt
2372 * @irq: The IRQ number triggered
2373 * @pw: The pw value when registered the handler.
2375 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2377 struct s3c_hsotg *hsotg = pw;
2378 int retry_count = 8;
2382 spin_lock(&hsotg->lock);
2384 gintsts = readl(hsotg->regs + GINTSTS);
2385 gintmsk = readl(hsotg->regs + GINTMSK);
2387 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2388 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2392 if (gintsts & GINTSTS_OTGInt) {
2393 u32 otgint = readl(hsotg->regs + GOTGINT);
2395 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2397 writel(otgint, hsotg->regs + GOTGINT);
2400 if (gintsts & GINTSTS_SessReqInt) {
2401 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2402 writel(GINTSTS_SessReqInt, hsotg->regs + GINTSTS);
2405 if (gintsts & GINTSTS_EnumDone) {
2406 writel(GINTSTS_EnumDone, hsotg->regs + GINTSTS);
2408 s3c_hsotg_irq_enumdone(hsotg);
2411 if (gintsts & GINTSTS_ConIDStsChng) {
2412 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2413 readl(hsotg->regs + DSTS),
2414 readl(hsotg->regs + GOTGCTL));
2416 writel(GINTSTS_ConIDStsChng, hsotg->regs + GINTSTS);
2419 if (gintsts & (GINTSTS_OEPInt | GINTSTS_IEPInt)) {
2420 u32 daint = readl(hsotg->regs + DAINT);
2421 u32 daint_out = daint >> DAINT_OutEP_SHIFT;
2422 u32 daint_in = daint & ~(daint_out << DAINT_OutEP_SHIFT);
2425 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2427 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2429 s3c_hsotg_epint(hsotg, ep, 0);
2432 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2434 s3c_hsotg_epint(hsotg, ep, 1);
2438 if (gintsts & GINTSTS_USBRst) {
2440 u32 usb_status = readl(hsotg->regs + GOTGCTL);
2442 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2443 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2444 readl(hsotg->regs + GNPTXSTS));
2446 writel(GINTSTS_USBRst, hsotg->regs + GINTSTS);
2448 if (usb_status & GOTGCTL_BSESVLD) {
2449 if (time_after(jiffies, hsotg->last_rst +
2450 msecs_to_jiffies(200))) {
2452 kill_all_requests(hsotg, &hsotg->eps[0],
2455 s3c_hsotg_core_init(hsotg);
2456 hsotg->last_rst = jiffies;
2461 /* check both FIFOs */
2463 if (gintsts & GINTSTS_NPTxFEmp) {
2464 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2467 * Disable the interrupt to stop it happening again
2468 * unless one of these endpoint routines decides that
2469 * it needs re-enabling
2472 s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTxFEmp);
2473 s3c_hsotg_irq_fifoempty(hsotg, false);
2476 if (gintsts & GINTSTS_PTxFEmp) {
2477 dev_dbg(hsotg->dev, "PTxFEmp\n");
2479 /* See note in GINTSTS_NPTxFEmp */
2481 s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTxFEmp);
2482 s3c_hsotg_irq_fifoempty(hsotg, true);
2485 if (gintsts & GINTSTS_RxFLvl) {
2487 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2488 * we need to retry s3c_hsotg_handle_rx if this is still
2492 s3c_hsotg_handle_rx(hsotg);
2495 if (gintsts & GINTSTS_ModeMis) {
2496 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2497 writel(GINTSTS_ModeMis, hsotg->regs + GINTSTS);
2500 if (gintsts & GINTSTS_USBSusp) {
2501 dev_info(hsotg->dev, "GINTSTS_USBSusp\n");
2502 writel(GINTSTS_USBSusp, hsotg->regs + GINTSTS);
2504 call_gadget(hsotg, suspend);
2505 s3c_hsotg_disconnect(hsotg);
2508 if (gintsts & GINTSTS_WkUpInt) {
2509 dev_info(hsotg->dev, "GINTSTS_WkUpIn\n");
2510 writel(GINTSTS_WkUpInt, hsotg->regs + GINTSTS);
2512 call_gadget(hsotg, resume);
2515 if (gintsts & GINTSTS_ErlySusp) {
2516 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2517 writel(GINTSTS_ErlySusp, hsotg->regs + GINTSTS);
2521 * these next two seem to crop-up occasionally causing the core
2522 * to shutdown the USB transfer, so try clearing them and logging
2526 if (gintsts & GINTSTS_GOUTNakEff) {
2527 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2529 writel(DCTL_CGOUTNak, hsotg->regs + DCTL);
2531 s3c_hsotg_dump(hsotg);
2534 if (gintsts & GINTSTS_GINNakEff) {
2535 dev_info(hsotg->dev, "GINNakEff triggered\n");
2537 writel(DCTL_CGNPInNAK, hsotg->regs + DCTL);
2539 s3c_hsotg_dump(hsotg);
2543 * if we've had fifo events, we should try and go around the
2544 * loop again to see if there's any point in returning yet.
2547 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2550 spin_unlock(&hsotg->lock);
2556 * s3c_hsotg_ep_enable - enable the given endpoint
2557 * @ep: The USB endpint to configure
2558 * @desc: The USB endpoint descriptor to configure with.
2560 * This is called from the USB gadget code's usb_ep_enable().
2562 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2563 const struct usb_endpoint_descriptor *desc)
2565 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2566 struct s3c_hsotg *hsotg = hs_ep->parent;
2567 unsigned long flags;
2568 int index = hs_ep->index;
2576 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2577 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2578 desc->wMaxPacketSize, desc->bInterval);
2580 /* not to be called for EP0 */
2581 WARN_ON(index == 0);
2583 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2584 if (dir_in != hs_ep->dir_in) {
2585 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2589 mps = usb_endpoint_maxp(desc);
2591 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2593 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2594 epctrl = readl(hsotg->regs + epctrl_reg);
2596 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2597 __func__, epctrl, epctrl_reg);
2599 spin_lock_irqsave(&hsotg->lock, flags);
2601 epctrl &= ~(DxEPCTL_EPType_MASK | DxEPCTL_MPS_MASK);
2602 epctrl |= DxEPCTL_MPS(mps);
2605 * mark the endpoint as active, otherwise the core may ignore
2606 * transactions entirely for this endpoint
2608 epctrl |= DxEPCTL_USBActEp;
2611 * set the NAK status on the endpoint, otherwise we might try and
2612 * do something with data that we've yet got a request to process
2613 * since the RXFIFO will take data for an endpoint even if the
2614 * size register hasn't been set.
2617 epctrl |= DxEPCTL_SNAK;
2619 /* update the endpoint state */
2620 s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps);
2622 /* default, set to non-periodic */
2623 hs_ep->isochronous = 0;
2624 hs_ep->periodic = 0;
2625 hs_ep->interval = desc->bInterval;
2627 if (hs_ep->interval > 1 && hs_ep->mc > 1)
2628 dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
2630 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2631 case USB_ENDPOINT_XFER_ISOC:
2632 epctrl |= DxEPCTL_EPType_Iso;
2633 epctrl |= DxEPCTL_SetEvenFr;
2634 hs_ep->isochronous = 1;
2636 hs_ep->periodic = 1;
2639 case USB_ENDPOINT_XFER_BULK:
2640 epctrl |= DxEPCTL_EPType_Bulk;
2643 case USB_ENDPOINT_XFER_INT:
2646 * Allocate our TxFNum by simply using the index
2647 * of the endpoint for the moment. We could do
2648 * something better if the host indicates how
2649 * many FIFOs we are expecting to use.
2652 hs_ep->periodic = 1;
2653 epctrl |= DxEPCTL_TxFNum(index);
2656 epctrl |= DxEPCTL_EPType_Intterupt;
2659 case USB_ENDPOINT_XFER_CONTROL:
2660 epctrl |= DxEPCTL_EPType_Control;
2665 * if the hardware has dedicated fifos, we must give each IN EP
2666 * a unique tx-fifo even if it is non-periodic.
2668 if (dir_in && hsotg->dedicated_fifos)
2669 epctrl |= DxEPCTL_TxFNum(index);
2671 /* for non control endpoints, set PID to D0 */
2673 epctrl |= DxEPCTL_SetD0PID;
2675 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2678 writel(epctrl, hsotg->regs + epctrl_reg);
2679 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2680 __func__, readl(hsotg->regs + epctrl_reg));
2682 /* enable the endpoint interrupt */
2683 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2685 spin_unlock_irqrestore(&hsotg->lock, flags);
2690 * s3c_hsotg_ep_disable - disable given endpoint
2691 * @ep: The endpoint to disable.
2693 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2695 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2696 struct s3c_hsotg *hsotg = hs_ep->parent;
2697 int dir_in = hs_ep->dir_in;
2698 int index = hs_ep->index;
2699 unsigned long flags;
2703 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2705 if (ep == &hsotg->eps[0].ep) {
2706 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2710 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2712 spin_lock_irqsave(&hsotg->lock, flags);
2713 /* terminate all requests with shutdown */
2714 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2717 ctrl = readl(hsotg->regs + epctrl_reg);
2718 ctrl &= ~DxEPCTL_EPEna;
2719 ctrl &= ~DxEPCTL_USBActEp;
2720 ctrl |= DxEPCTL_SNAK;
2722 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2723 writel(ctrl, hsotg->regs + epctrl_reg);
2725 /* disable endpoint interrupts */
2726 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2728 spin_unlock_irqrestore(&hsotg->lock, flags);
2733 * on_list - check request is on the given endpoint
2734 * @ep: The endpoint to check.
2735 * @test: The request to test if it is on the endpoint.
2737 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2739 struct s3c_hsotg_req *req, *treq;
2741 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2750 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2751 * @ep: The endpoint to dequeue.
2752 * @req: The request to be removed from a queue.
2754 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2756 struct s3c_hsotg_req *hs_req = our_req(req);
2757 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2758 struct s3c_hsotg *hs = hs_ep->parent;
2759 unsigned long flags;
2761 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2763 spin_lock_irqsave(&hs->lock, flags);
2765 if (!on_list(hs_ep, hs_req)) {
2766 spin_unlock_irqrestore(&hs->lock, flags);
2770 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2771 spin_unlock_irqrestore(&hs->lock, flags);
2777 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2778 * @ep: The endpoint to set halt.
2779 * @value: Set or unset the halt.
2781 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2783 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2784 struct s3c_hsotg *hs = hs_ep->parent;
2785 int index = hs_ep->index;
2790 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2792 /* write both IN and OUT control registers */
2794 epreg = DIEPCTL(index);
2795 epctl = readl(hs->regs + epreg);
2798 epctl |= DxEPCTL_Stall + DxEPCTL_SNAK;
2799 if (epctl & DxEPCTL_EPEna)
2800 epctl |= DxEPCTL_EPDis;
2802 epctl &= ~DxEPCTL_Stall;
2803 xfertype = epctl & DxEPCTL_EPType_MASK;
2804 if (xfertype == DxEPCTL_EPType_Bulk ||
2805 xfertype == DxEPCTL_EPType_Intterupt)
2806 epctl |= DxEPCTL_SetD0PID;
2809 writel(epctl, hs->regs + epreg);
2811 epreg = DOEPCTL(index);
2812 epctl = readl(hs->regs + epreg);
2815 epctl |= DxEPCTL_Stall;
2817 epctl &= ~DxEPCTL_Stall;
2818 xfertype = epctl & DxEPCTL_EPType_MASK;
2819 if (xfertype == DxEPCTL_EPType_Bulk ||
2820 xfertype == DxEPCTL_EPType_Intterupt)
2821 epctl |= DxEPCTL_SetD0PID;
2824 writel(epctl, hs->regs + epreg);
2830 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2831 * @ep: The endpoint to set halt.
2832 * @value: Set or unset the halt.
2834 static int s3c_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
2836 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2837 struct s3c_hsotg *hs = hs_ep->parent;
2838 unsigned long flags = 0;
2841 spin_lock_irqsave(&hs->lock, flags);
2842 ret = s3c_hsotg_ep_sethalt(ep, value);
2843 spin_unlock_irqrestore(&hs->lock, flags);
2848 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2849 .enable = s3c_hsotg_ep_enable,
2850 .disable = s3c_hsotg_ep_disable,
2851 .alloc_request = s3c_hsotg_ep_alloc_request,
2852 .free_request = s3c_hsotg_ep_free_request,
2853 .queue = s3c_hsotg_ep_queue_lock,
2854 .dequeue = s3c_hsotg_ep_dequeue,
2855 .set_halt = s3c_hsotg_ep_sethalt_lock,
2856 /* note, don't believe we have any call for the fifo routines */
2860 * s3c_hsotg_phy_enable - enable platform phy dev
2861 * @hsotg: The driver state
2863 * A wrapper for platform code responsible for controlling
2864 * low-level USB code
2866 static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
2868 struct platform_device *pdev = to_platform_device(hsotg->dev);
2870 dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
2873 usb_phy_init(hsotg->phy);
2874 else if (hsotg->plat->phy_init)
2875 hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
2879 * s3c_hsotg_phy_disable - disable platform phy dev
2880 * @hsotg: The driver state
2882 * A wrapper for platform code responsible for controlling
2883 * low-level USB code
2885 static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
2887 struct platform_device *pdev = to_platform_device(hsotg->dev);
2890 usb_phy_shutdown(hsotg->phy);
2891 else if (hsotg->plat->phy_exit)
2892 hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
2896 * s3c_hsotg_init - initalize the usb core
2897 * @hsotg: The driver state
2899 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2901 /* unmask subset of endpoint interrupts */
2903 writel(DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
2904 DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk,
2905 hsotg->regs + DIEPMSK);
2907 writel(DOEPMSK_SetupMsk | DOEPMSK_AHBErrMsk |
2908 DOEPMSK_EPDisbldMsk | DOEPMSK_XferComplMsk,
2909 hsotg->regs + DOEPMSK);
2911 writel(0, hsotg->regs + DAINTMSK);
2913 /* Be in disconnected state until gadget is registered */
2914 __orr32(hsotg->regs + DCTL, DCTL_SftDiscon);
2917 /* post global nak until we're ready */
2918 writel(DCTL_SGNPInNAK | DCTL_SGOUTNak,
2919 hsotg->regs + DCTL);
2924 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2925 readl(hsotg->regs + GRXFSIZ),
2926 readl(hsotg->regs + GNPTXFSIZ));
2928 s3c_hsotg_init_fifo(hsotg);
2930 /* set the PLL on, remove the HNP/SRP and set the PHY */
2931 writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) | (0x5 << 10),
2932 hsotg->regs + GUSBCFG);
2934 writel(using_dma(hsotg) ? GAHBCFG_DMAEn : 0x0,
2935 hsotg->regs + GAHBCFG);
2939 * s3c_hsotg_udc_start - prepare the udc for work
2940 * @gadget: The usb gadget state
2941 * @driver: The usb gadget driver
2943 * Perform initialization to prepare udc device and driver
2946 static int s3c_hsotg_udc_start(struct usb_gadget *gadget,
2947 struct usb_gadget_driver *driver)
2949 struct s3c_hsotg *hsotg = to_hsotg(gadget);
2953 pr_err("%s: called with no device\n", __func__);
2958 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2962 if (driver->max_speed < USB_SPEED_FULL)
2963 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2965 if (!driver->setup) {
2966 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2970 WARN_ON(hsotg->driver);
2972 driver->driver.bus = NULL;
2973 hsotg->driver = driver;
2974 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
2975 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2977 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
2980 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
2984 hsotg->last_rst = jiffies;
2985 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2989 hsotg->driver = NULL;
2994 * s3c_hsotg_udc_stop - stop the udc
2995 * @gadget: The usb gadget state
2996 * @driver: The usb gadget driver
2998 * Stop udc hw block and stay tunned for future transmissions
3000 static int s3c_hsotg_udc_stop(struct usb_gadget *gadget,
3001 struct usb_gadget_driver *driver)
3003 struct s3c_hsotg *hsotg = to_hsotg(gadget);
3004 unsigned long flags = 0;
3010 /* all endpoints should be shutdown */
3011 for (ep = 0; ep < hsotg->num_of_eps; ep++)
3012 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
3014 spin_lock_irqsave(&hsotg->lock, flags);
3016 s3c_hsotg_phy_disable(hsotg);
3019 hsotg->driver = NULL;
3021 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3023 spin_unlock_irqrestore(&hsotg->lock, flags);
3025 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
3031 * s3c_hsotg_gadget_getframe - read the frame number
3032 * @gadget: The usb gadget state
3034 * Read the {micro} frame number
3036 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
3038 return s3c_hsotg_read_frameno(to_hsotg(gadget));
3042 * s3c_hsotg_pullup - connect/disconnect the USB PHY
3043 * @gadget: The usb gadget state
3044 * @is_on: Current state of the USB PHY
3046 * Connect/Disconnect the USB PHY pullup
3048 static int s3c_hsotg_pullup(struct usb_gadget *gadget, int is_on)
3050 struct s3c_hsotg *hsotg = to_hsotg(gadget);
3051 unsigned long flags = 0;
3053 dev_dbg(hsotg->dev, "%s: is_in: %d\n", __func__, is_on);
3055 spin_lock_irqsave(&hsotg->lock, flags);
3057 s3c_hsotg_phy_enable(hsotg);
3058 s3c_hsotg_core_init(hsotg);
3060 s3c_hsotg_disconnect(hsotg);
3061 s3c_hsotg_phy_disable(hsotg);
3064 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3065 spin_unlock_irqrestore(&hsotg->lock, flags);
3070 static const struct usb_gadget_ops s3c_hsotg_gadget_ops = {
3071 .get_frame = s3c_hsotg_gadget_getframe,
3072 .udc_start = s3c_hsotg_udc_start,
3073 .udc_stop = s3c_hsotg_udc_stop,
3074 .pullup = s3c_hsotg_pullup,
3078 * s3c_hsotg_initep - initialise a single endpoint
3079 * @hsotg: The device state.
3080 * @hs_ep: The endpoint to be initialised.
3081 * @epnum: The endpoint number
3083 * Initialise the given endpoint (as part of the probe and device state
3084 * creation) to give to the gadget driver. Setup the endpoint name, any
3085 * direction information and other state that may be required.
3087 static void s3c_hsotg_initep(struct s3c_hsotg *hsotg,
3088 struct s3c_hsotg_ep *hs_ep,
3096 else if ((epnum % 2) == 0) {
3103 hs_ep->index = epnum;
3105 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3107 INIT_LIST_HEAD(&hs_ep->queue);
3108 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3110 /* add to the list of endpoints known by the gadget driver */
3112 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3114 hs_ep->parent = hsotg;
3115 hs_ep->ep.name = hs_ep->name;
3116 hs_ep->ep.maxpacket = epnum ? 1024 : EP0_MPS_LIMIT;
3117 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
3120 * Read the FIFO size for the Periodic TX FIFO, even if we're
3121 * an OUT endpoint, we may as well do this if in future the
3122 * code is changed to make each endpoint's direction changeable.
3125 ptxfifo = readl(hsotg->regs + DPTXFSIZn(epnum));
3126 hs_ep->fifo_size = DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
3129 * if we're using dma, we need to set the next-endpoint pointer
3130 * to be something valid.
3133 if (using_dma(hsotg)) {
3134 u32 next = DxEPCTL_NextEp((epnum + 1) % 15);
3135 writel(next, hsotg->regs + DIEPCTL(epnum));
3136 writel(next, hsotg->regs + DOEPCTL(epnum));
3141 * s3c_hsotg_hw_cfg - read HW configuration registers
3142 * @param: The device state
3144 * Read the USB core HW configuration registers
3146 static void s3c_hsotg_hw_cfg(struct s3c_hsotg *hsotg)
3149 /* check hardware configuration */
3151 cfg2 = readl(hsotg->regs + 0x48);
3152 hsotg->num_of_eps = (cfg2 >> 10) & 0xF;
3154 dev_info(hsotg->dev, "EPs:%d\n", hsotg->num_of_eps);
3156 cfg4 = readl(hsotg->regs + 0x50);
3157 hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
3159 dev_info(hsotg->dev, "%s fifos\n",
3160 hsotg->dedicated_fifos ? "dedicated" : "shared");
3164 * s3c_hsotg_dump - dump state of the udc
3165 * @param: The device state
3167 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
3170 struct device *dev = hsotg->dev;
3171 void __iomem *regs = hsotg->regs;
3175 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3176 readl(regs + DCFG), readl(regs + DCTL),
3177 readl(regs + DIEPMSK));
3179 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3180 readl(regs + GAHBCFG), readl(regs + 0x44));
3182 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3183 readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
3185 /* show periodic fifo settings */
3187 for (idx = 1; idx <= 15; idx++) {
3188 val = readl(regs + DPTXFSIZn(idx));
3189 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3190 val >> DPTXFSIZn_DPTxFSize_SHIFT,
3191 val & DPTXFSIZn_DPTxFStAddr_MASK);
3194 for (idx = 0; idx < 15; idx++) {
3196 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3197 readl(regs + DIEPCTL(idx)),
3198 readl(regs + DIEPTSIZ(idx)),
3199 readl(regs + DIEPDMA(idx)));
3201 val = readl(regs + DOEPCTL(idx));
3203 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3204 idx, readl(regs + DOEPCTL(idx)),
3205 readl(regs + DOEPTSIZ(idx)),
3206 readl(regs + DOEPDMA(idx)));
3210 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3211 readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE));
3216 * state_show - debugfs: show overall driver and device state.
3217 * @seq: The seq file to write to.
3218 * @v: Unused parameter.
3220 * This debugfs entry shows the overall state of the hardware and
3221 * some general information about each of the endpoints available
3224 static int state_show(struct seq_file *seq, void *v)
3226 struct s3c_hsotg *hsotg = seq->private;
3227 void __iomem *regs = hsotg->regs;
3230 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3233 readl(regs + DSTS));
3235 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3236 readl(regs + DIEPMSK), readl(regs + DOEPMSK));
3238 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3239 readl(regs + GINTMSK),
3240 readl(regs + GINTSTS));
3242 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3243 readl(regs + DAINTMSK),
3244 readl(regs + DAINT));
3246 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3247 readl(regs + GNPTXSTS),
3248 readl(regs + GRXSTSR));
3250 seq_puts(seq, "\nEndpoint status:\n");
3252 for (idx = 0; idx < 15; idx++) {
3255 in = readl(regs + DIEPCTL(idx));
3256 out = readl(regs + DOEPCTL(idx));
3258 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3261 in = readl(regs + DIEPTSIZ(idx));
3262 out = readl(regs + DOEPTSIZ(idx));
3264 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3267 seq_puts(seq, "\n");
3273 static int state_open(struct inode *inode, struct file *file)
3275 return single_open(file, state_show, inode->i_private);
3278 static const struct file_operations state_fops = {
3279 .owner = THIS_MODULE,
3282 .llseek = seq_lseek,
3283 .release = single_release,
3287 * fifo_show - debugfs: show the fifo information
3288 * @seq: The seq_file to write data to.
3289 * @v: Unused parameter.
3291 * Show the FIFO information for the overall fifo and all the
3292 * periodic transmission FIFOs.
3294 static int fifo_show(struct seq_file *seq, void *v)
3296 struct s3c_hsotg *hsotg = seq->private;
3297 void __iomem *regs = hsotg->regs;
3301 seq_puts(seq, "Non-periodic FIFOs:\n");
3302 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ));
3304 val = readl(regs + GNPTXFSIZ);
3305 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3306 val >> GNPTXFSIZ_NPTxFDep_SHIFT,
3307 val & GNPTXFSIZ_NPTxFStAddr_MASK);
3309 seq_puts(seq, "\nPeriodic TXFIFOs:\n");
3311 for (idx = 1; idx <= 15; idx++) {
3312 val = readl(regs + DPTXFSIZn(idx));
3314 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3315 val >> DPTXFSIZn_DPTxFSize_SHIFT,
3316 val & DPTXFSIZn_DPTxFStAddr_MASK);
3322 static int fifo_open(struct inode *inode, struct file *file)
3324 return single_open(file, fifo_show, inode->i_private);
3327 static const struct file_operations fifo_fops = {
3328 .owner = THIS_MODULE,
3331 .llseek = seq_lseek,
3332 .release = single_release,
3336 static const char *decode_direction(int is_in)
3338 return is_in ? "in" : "out";
3342 * ep_show - debugfs: show the state of an endpoint.
3343 * @seq: The seq_file to write data to.
3344 * @v: Unused parameter.
3346 * This debugfs entry shows the state of the given endpoint (one is
3347 * registered for each available).
3349 static int ep_show(struct seq_file *seq, void *v)
3351 struct s3c_hsotg_ep *ep = seq->private;
3352 struct s3c_hsotg *hsotg = ep->parent;
3353 struct s3c_hsotg_req *req;
3354 void __iomem *regs = hsotg->regs;
3355 int index = ep->index;
3356 int show_limit = 15;
3357 unsigned long flags;
3359 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3360 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3362 /* first show the register state */
3364 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3365 readl(regs + DIEPCTL(index)),
3366 readl(regs + DOEPCTL(index)));
3368 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3369 readl(regs + DIEPDMA(index)),
3370 readl(regs + DOEPDMA(index)));
3372 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3373 readl(regs + DIEPINT(index)),
3374 readl(regs + DOEPINT(index)));
3376 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3377 readl(regs + DIEPTSIZ(index)),
3378 readl(regs + DOEPTSIZ(index)));
3380 seq_puts(seq, "\n");
3381 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3382 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3384 seq_printf(seq, "request list (%p,%p):\n",
3385 ep->queue.next, ep->queue.prev);
3387 spin_lock_irqsave(&hsotg->lock, flags);
3389 list_for_each_entry(req, &ep->queue, queue) {
3390 if (--show_limit < 0) {
3391 seq_puts(seq, "not showing more requests...\n");
3395 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3396 req == ep->req ? '*' : ' ',
3397 req, req->req.length, req->req.buf);
3398 seq_printf(seq, "%d done, res %d\n",
3399 req->req.actual, req->req.status);
3402 spin_unlock_irqrestore(&hsotg->lock, flags);
3407 static int ep_open(struct inode *inode, struct file *file)
3409 return single_open(file, ep_show, inode->i_private);
3412 static const struct file_operations ep_fops = {
3413 .owner = THIS_MODULE,
3416 .llseek = seq_lseek,
3417 .release = single_release,
3421 * s3c_hsotg_create_debug - create debugfs directory and files
3422 * @hsotg: The driver state
3424 * Create the debugfs files to allow the user to get information
3425 * about the state of the system. The directory name is created
3426 * with the same name as the device itself, in case we end up
3427 * with multiple blocks in future systems.
3429 static void s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3431 struct dentry *root;
3434 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3435 hsotg->debug_root = root;
3437 dev_err(hsotg->dev, "cannot create debug root\n");
3441 /* create general state file */
3443 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3444 hsotg, &state_fops);
3446 if (IS_ERR(hsotg->debug_file))
3447 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3449 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3452 if (IS_ERR(hsotg->debug_fifo))
3453 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3455 /* create one file for each endpoint */
3457 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3458 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3460 ep->debugfs = debugfs_create_file(ep->name, 0444,
3461 root, ep, &ep_fops);
3463 if (IS_ERR(ep->debugfs))
3464 dev_err(hsotg->dev, "failed to create %s debug file\n",
3470 * s3c_hsotg_delete_debug - cleanup debugfs entries
3471 * @hsotg: The driver state
3473 * Cleanup (remove) the debugfs files for use on module exit.
3475 static void s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3479 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3480 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3481 debugfs_remove(ep->debugfs);
3484 debugfs_remove(hsotg->debug_file);
3485 debugfs_remove(hsotg->debug_fifo);
3486 debugfs_remove(hsotg->debug_root);
3490 * s3c_hsotg_probe - probe function for hsotg driver
3491 * @pdev: The platform information for the driver
3494 static int s3c_hsotg_probe(struct platform_device *pdev)
3496 struct s3c_hsotg_plat *plat = dev_get_platdata(&pdev->dev);
3497 struct usb_phy *phy;
3498 struct device *dev = &pdev->dev;
3499 struct s3c_hsotg_ep *eps;
3500 struct s3c_hsotg *hsotg;
3501 struct resource *res;
3506 hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL);
3508 dev_err(dev, "cannot get memory\n");
3512 phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
3514 /* Fallback for pdata */
3515 plat = dev_get_platdata(&pdev->dev);
3517 dev_err(&pdev->dev, "no platform data or transceiver defined\n");
3518 return -EPROBE_DEFER;
3528 hsotg->clk = devm_clk_get(&pdev->dev, "otg");
3529 if (IS_ERR(hsotg->clk)) {
3530 dev_err(dev, "cannot get otg clock\n");
3531 return PTR_ERR(hsotg->clk);
3534 platform_set_drvdata(pdev, hsotg);
3536 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3538 hsotg->regs = devm_ioremap_resource(&pdev->dev, res);
3539 if (IS_ERR(hsotg->regs)) {
3540 ret = PTR_ERR(hsotg->regs);
3544 ret = platform_get_irq(pdev, 0);
3546 dev_err(dev, "cannot find IRQ\n");
3550 spin_lock_init(&hsotg->lock);
3554 ret = devm_request_irq(&pdev->dev, hsotg->irq, s3c_hsotg_irq, 0,
3555 dev_name(dev), hsotg);
3557 dev_err(dev, "cannot claim IRQ\n");
3561 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3563 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3564 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3565 hsotg->gadget.name = dev_name(dev);
3567 /* reset the system */
3569 clk_prepare_enable(hsotg->clk);
3573 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
3574 hsotg->supplies[i].supply = s3c_hsotg_supply_names[i];
3576 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies),
3579 dev_err(dev, "failed to request supplies: %d\n", ret);
3583 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3587 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
3591 /* usb phy enable */
3592 s3c_hsotg_phy_enable(hsotg);
3594 s3c_hsotg_corereset(hsotg);
3595 s3c_hsotg_init(hsotg);
3596 s3c_hsotg_hw_cfg(hsotg);
3598 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3600 if (hsotg->num_of_eps == 0) {
3601 dev_err(dev, "wrong number of EPs (zero)\n");
3606 eps = kcalloc(hsotg->num_of_eps + 1, sizeof(struct s3c_hsotg_ep),
3609 dev_err(dev, "cannot get memory\n");
3616 /* setup endpoint information */
3618 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3619 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3621 /* allocate EP0 request */
3623 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3625 if (!hsotg->ctrl_req) {
3626 dev_err(dev, "failed to allocate ctrl req\n");
3631 /* initialise the endpoints now the core has been initialised */
3632 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++)
3633 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3635 /* disable power and clock */
3637 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3640 dev_err(hsotg->dev, "failed to disable supplies: %d\n", ret);
3644 s3c_hsotg_phy_disable(hsotg);
3646 ret = usb_add_gadget_udc(&pdev->dev, &hsotg->gadget);
3650 s3c_hsotg_create_debug(hsotg);
3652 s3c_hsotg_dump(hsotg);
3659 s3c_hsotg_phy_disable(hsotg);
3661 clk_disable_unprepare(hsotg->clk);
3667 * s3c_hsotg_remove - remove function for hsotg driver
3668 * @pdev: The platform information for the driver
3670 static int s3c_hsotg_remove(struct platform_device *pdev)
3672 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3674 usb_del_gadget_udc(&hsotg->gadget);
3676 s3c_hsotg_delete_debug(hsotg);
3678 if (hsotg->driver) {
3679 /* should have been done already by driver model core */
3680 usb_gadget_unregister_driver(hsotg->driver);
3683 s3c_hsotg_phy_disable(hsotg);
3684 clk_disable_unprepare(hsotg->clk);
3690 #define s3c_hsotg_suspend NULL
3691 #define s3c_hsotg_resume NULL
3695 static const struct of_device_id s3c_hsotg_of_ids[] = {
3696 { .compatible = "samsung,s3c6400-hsotg", },
3699 MODULE_DEVICE_TABLE(of, s3c_hsotg_of_ids);
3702 static struct platform_driver s3c_hsotg_driver = {
3704 .name = "s3c-hsotg",
3705 .owner = THIS_MODULE,
3706 .of_match_table = of_match_ptr(s3c_hsotg_of_ids),
3708 .probe = s3c_hsotg_probe,
3709 .remove = s3c_hsotg_remove,
3710 .suspend = s3c_hsotg_suspend,
3711 .resume = s3c_hsotg_resume,
3714 module_platform_driver(s3c_hsotg_driver);
3716 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3717 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3718 MODULE_LICENSE("GPL");
3719 MODULE_ALIAS("platform:s3c-hsotg");