2 * linux/drivers/usb/gadget/s3c-hsotg.c
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Copyright 2008 Openmoko, Inc.
8 * Copyright 2008 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
10 * http://armlinux.simtec.co.uk/
12 * S3C USB2.0 High-speed / OtG driver
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/debugfs.h>
26 #include <linux/seq_file.h>
27 #include <linux/delay.h>
29 #include <linux/slab.h>
30 #include <linux/clk.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/of_platform.h>
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 #include <linux/usb/phy.h>
37 #include <linux/platform_data/s3c-hsotg.h>
41 #include "s3c-hsotg.h"
43 static const char * const s3c_hsotg_supply_names[] = {
44 "vusb_d", /* digital USB supply, 1.2V */
45 "vusb_a", /* analog USB supply, 1.1V */
51 * Unfortunately there seems to be a limit of the amount of data that can
52 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
53 * packets (which practically means 1 packet and 63 bytes of data) when the
56 * This means if we are wanting to move >127 bytes of data, we need to
57 * split the transactions up, but just doing one packet at a time does
58 * not work (this may be an implicit DATA0 PID on first packet of the
59 * transaction) and doing 2 packets is outside the controller's limits.
61 * If we try to lower the MPS size for EP0, then no transfers work properly
62 * for EP0, and the system will fail basic enumeration. As no cause for this
63 * has currently been found, we cannot support any large IN transfers for
66 #define EP0_MPS_LIMIT 64
72 * struct s3c_hsotg_ep - driver endpoint definition.
73 * @ep: The gadget layer representation of the endpoint.
74 * @name: The driver generated name for the endpoint.
75 * @queue: Queue of requests for this endpoint.
76 * @parent: Reference back to the parent device structure.
77 * @req: The current request that the endpoint is processing. This is
78 * used to indicate an request has been loaded onto the endpoint
79 * and has yet to be completed (maybe due to data move, or simply
80 * awaiting an ack from the core all the data has been completed).
81 * @debugfs: File entry for debugfs file for this endpoint.
82 * @lock: State lock to protect contents of endpoint.
83 * @dir_in: Set to true if this endpoint is of the IN direction, which
84 * means that it is sending data to the Host.
85 * @index: The index for the endpoint registers.
86 * @mc: Multi Count - number of transactions per microframe
87 * @interval - Interval for periodic endpoints
88 * @name: The name array passed to the USB core.
89 * @halted: Set if the endpoint has been halted.
90 * @periodic: Set if this is a periodic ep, such as Interrupt
91 * @isochronous: Set if this is a isochronous ep
92 * @sent_zlp: Set if we've sent a zero-length packet.
93 * @total_data: The total number of data bytes done.
94 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
95 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
96 * @last_load: The offset of data for the last start of request.
97 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
99 * This is the driver's state for each registered enpoint, allowing it
100 * to keep track of transactions that need doing. Each endpoint has a
101 * lock to protect the state, to try and avoid using an overall lock
102 * for the host controller as much as possible.
104 * For periodic IN endpoints, we have fifo_size and fifo_load to try
105 * and keep track of the amount of data in the periodic FIFO for each
106 * of these as we don't have a status register that tells us how much
107 * is in each of them. (note, this may actually be useless information
108 * as in shared-fifo mode periodic in acts like a single-frame packet
109 * buffer than a fifo)
111 struct s3c_hsotg_ep {
113 struct list_head queue;
114 struct s3c_hsotg *parent;
115 struct s3c_hsotg_req *req;
116 struct dentry *debugfs;
119 unsigned long total_data;
120 unsigned int size_loaded;
121 unsigned int last_load;
122 unsigned int fifo_load;
123 unsigned short fifo_size;
125 unsigned char dir_in;
128 unsigned char interval;
130 unsigned int halted:1;
131 unsigned int periodic:1;
132 unsigned int isochronous:1;
133 unsigned int sent_zlp:1;
139 * struct s3c_hsotg - driver state.
140 * @dev: The parent device supplied to the probe function
141 * @driver: USB gadget driver
142 * @phy: The otg phy transceiver structure for phy control.
143 * @plat: The platform specific configuration data. This can be removed once
144 * all SoCs support usb transceiver.
145 * @regs: The memory area mapped for accessing registers.
146 * @irq: The IRQ number we are using
147 * @supplies: Definition of USB power supplies
148 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
149 * @num_of_eps: Number of available EPs (excluding EP0)
150 * @debug_root: root directrory for debugfs.
151 * @debug_file: main status file for debugfs.
152 * @debug_fifo: FIFO status file for debugfs.
153 * @ep0_reply: Request used for ep0 reply.
154 * @ep0_buff: Buffer for EP0 reply data, if needed.
155 * @ctrl_buff: Buffer for EP0 control requests.
156 * @ctrl_req: Request for EP0 control packets.
157 * @setup: NAK management for EP0 SETUP
158 * @last_rst: Time of last reset
159 * @eps: The endpoints being supplied to the gadget framework
163 struct usb_gadget_driver *driver;
165 struct s3c_hsotg_plat *plat;
173 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)];
175 unsigned int dedicated_fifos:1;
176 unsigned char num_of_eps;
178 struct dentry *debug_root;
179 struct dentry *debug_file;
180 struct dentry *debug_fifo;
182 struct usb_request *ep0_reply;
183 struct usb_request *ctrl_req;
187 struct usb_gadget gadget;
189 unsigned long last_rst;
190 struct s3c_hsotg_ep *eps;
194 * struct s3c_hsotg_req - data transfer request
195 * @req: The USB gadget request
196 * @queue: The list of requests for the endpoint this is queued for.
197 * @in_progress: Has already had size/packets written to core
198 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
200 struct s3c_hsotg_req {
201 struct usb_request req;
202 struct list_head queue;
203 unsigned char in_progress;
204 unsigned char mapped;
207 /* conversion functions */
208 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
210 return container_of(req, struct s3c_hsotg_req, req);
213 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
215 return container_of(ep, struct s3c_hsotg_ep, ep);
218 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
220 return container_of(gadget, struct s3c_hsotg, gadget);
223 static inline void __orr32(void __iomem *ptr, u32 val)
225 writel(readl(ptr) | val, ptr);
228 static inline void __bic32(void __iomem *ptr, u32 val)
230 writel(readl(ptr) & ~val, ptr);
233 /* forward decleration of functions */
234 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
237 * using_dma - return the DMA status of the driver.
238 * @hsotg: The driver state.
240 * Return true if we're using DMA.
242 * Currently, we have the DMA support code worked into everywhere
243 * that needs it, but the AMBA DMA implementation in the hardware can
244 * only DMA from 32bit aligned addresses. This means that gadgets such
245 * as the CDC Ethernet cannot work as they often pass packets which are
248 * Unfortunately the choice to use DMA or not is global to the controller
249 * and seems to be only settable when the controller is being put through
250 * a core reset. This means we either need to fix the gadgets to take
251 * account of DMA alignment, or add bounce buffers (yuerk).
253 * Until this issue is sorted out, we always return 'false'.
255 static inline bool using_dma(struct s3c_hsotg *hsotg)
257 return false; /* support is not complete */
261 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
262 * @hsotg: The device state
263 * @ints: A bitmask of the interrupts to enable
265 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
267 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
270 new_gsintmsk = gsintmsk | ints;
272 if (new_gsintmsk != gsintmsk) {
273 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
274 writel(new_gsintmsk, hsotg->regs + GINTMSK);
279 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
280 * @hsotg: The device state
281 * @ints: A bitmask of the interrupts to enable
283 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
285 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
288 new_gsintmsk = gsintmsk & ~ints;
290 if (new_gsintmsk != gsintmsk)
291 writel(new_gsintmsk, hsotg->regs + GINTMSK);
295 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
296 * @hsotg: The device state
297 * @ep: The endpoint index
298 * @dir_in: True if direction is in.
299 * @en: The enable value, true to enable
301 * Set or clear the mask for an individual endpoint's interrupt
304 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
305 unsigned int ep, unsigned int dir_in,
315 local_irq_save(flags);
316 daint = readl(hsotg->regs + DAINTMSK);
321 writel(daint, hsotg->regs + DAINTMSK);
322 local_irq_restore(flags);
326 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
327 * @hsotg: The device instance.
329 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
337 /* set FIFO sizes to 2048/1024 */
339 writel(2048, hsotg->regs + GRXFSIZ);
340 writel(GNPTXFSIZ_NPTxFStAddr(2048) |
341 GNPTXFSIZ_NPTxFDep(1024),
342 hsotg->regs + GNPTXFSIZ);
345 * arange all the rest of the TX FIFOs, as some versions of this
346 * block have overlapping default addresses. This also ensures
347 * that if the settings have been changed, then they are set to
351 /* start at the end of the GNPTXFSIZ, rounded up */
356 * currently we allocate TX FIFOs for all possible endpoints,
357 * and assume that they are all the same size.
360 for (ep = 1; ep <= 15; ep++) {
362 val |= size << DPTXFSIZn_DPTxFSize_SHIFT;
365 writel(val, hsotg->regs + DPTXFSIZn(ep));
369 * according to p428 of the design guide, we need to ensure that
370 * all fifos are flushed before continuing
373 writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh |
374 GRSTCTL_RxFFlsh, hsotg->regs + GRSTCTL);
376 /* wait until the fifos are both flushed */
379 val = readl(hsotg->regs + GRSTCTL);
381 if ((val & (GRSTCTL_TxFFlsh | GRSTCTL_RxFFlsh)) == 0)
384 if (--timeout == 0) {
386 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
393 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
397 * @ep: USB endpoint to allocate request for.
398 * @flags: Allocation flags
400 * Allocate a new USB request structure appropriate for the specified endpoint
402 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
405 struct s3c_hsotg_req *req;
407 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
411 INIT_LIST_HEAD(&req->queue);
417 * is_ep_periodic - return true if the endpoint is in periodic mode.
418 * @hs_ep: The endpoint to query.
420 * Returns true if the endpoint is in periodic mode, meaning it is being
421 * used for an Interrupt or ISO transfer.
423 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
425 return hs_ep->periodic;
429 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
430 * @hsotg: The device state.
431 * @hs_ep: The endpoint for the request
432 * @hs_req: The request being processed.
434 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
435 * of a request to ensure the buffer is ready for access by the caller.
437 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
438 struct s3c_hsotg_ep *hs_ep,
439 struct s3c_hsotg_req *hs_req)
441 struct usb_request *req = &hs_req->req;
443 /* ignore this if we're not moving any data */
444 if (hs_req->req.length == 0)
447 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
451 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
452 * @hsotg: The controller state.
453 * @hs_ep: The endpoint we're going to write for.
454 * @hs_req: The request to write data for.
456 * This is called when the TxFIFO has some space in it to hold a new
457 * transmission and we have something to give it. The actual setup of
458 * the data size is done elsewhere, so all we have to do is to actually
461 * The return value is zero if there is more space (or nothing was done)
462 * otherwise -ENOSPC is returned if the FIFO space was used up.
464 * This routine is only needed for PIO
466 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
467 struct s3c_hsotg_ep *hs_ep,
468 struct s3c_hsotg_req *hs_req)
470 bool periodic = is_ep_periodic(hs_ep);
471 u32 gnptxsts = readl(hsotg->regs + GNPTXSTS);
472 int buf_pos = hs_req->req.actual;
473 int to_write = hs_ep->size_loaded;
479 to_write -= (buf_pos - hs_ep->last_load);
481 /* if there's nothing to write, get out early */
485 if (periodic && !hsotg->dedicated_fifos) {
486 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
491 * work out how much data was loaded so we can calculate
492 * how much data is left in the fifo.
495 size_left = DxEPTSIZ_XferSize_GET(epsize);
498 * if shared fifo, we cannot write anything until the
499 * previous data has been completely sent.
501 if (hs_ep->fifo_load != 0) {
502 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp);
506 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
508 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
510 /* how much of the data has moved */
511 size_done = hs_ep->size_loaded - size_left;
513 /* how much data is left in the fifo */
514 can_write = hs_ep->fifo_load - size_done;
515 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
516 __func__, can_write);
518 can_write = hs_ep->fifo_size - can_write;
519 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
520 __func__, can_write);
522 if (can_write <= 0) {
523 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp);
526 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
527 can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index));
532 if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
534 "%s: no queue slots available (0x%08x)\n",
537 s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTxFEmp);
541 can_write = GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
542 can_write *= 4; /* fifo size is in 32bit quantities. */
545 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
547 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
548 __func__, gnptxsts, can_write, to_write, max_transfer);
551 * limit to 512 bytes of data, it seems at least on the non-periodic
552 * FIFO, requests of >512 cause the endpoint to get stuck with a
553 * fragment of the end of the transfer in it.
555 if (can_write > 512 && !periodic)
559 * limit the write to one max-packet size worth of data, but allow
560 * the transfer to return that it did not run out of fifo space
563 if (to_write > max_transfer) {
564 to_write = max_transfer;
566 /* it's needed only when we do not use dedicated fifos */
567 if (!hsotg->dedicated_fifos)
568 s3c_hsotg_en_gsint(hsotg,
569 periodic ? GINTSTS_PTxFEmp :
573 /* see if we can write data */
575 if (to_write > can_write) {
576 to_write = can_write;
577 pkt_round = to_write % max_transfer;
580 * Round the write down to an
581 * exact number of packets.
583 * Note, we do not currently check to see if we can ever
584 * write a full packet or not to the FIFO.
588 to_write -= pkt_round;
591 * enable correct FIFO interrupt to alert us when there
595 /* it's needed only when we do not use dedicated fifos */
596 if (!hsotg->dedicated_fifos)
597 s3c_hsotg_en_gsint(hsotg,
598 periodic ? GINTSTS_PTxFEmp :
602 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
603 to_write, hs_req->req.length, can_write, buf_pos);
608 hs_req->req.actual = buf_pos + to_write;
609 hs_ep->total_data += to_write;
612 hs_ep->fifo_load += to_write;
614 to_write = DIV_ROUND_UP(to_write, 4);
615 data = hs_req->req.buf + buf_pos;
617 writesl(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
619 return (to_write >= can_write) ? -ENOSPC : 0;
623 * get_ep_limit - get the maximum data legnth for this endpoint
624 * @hs_ep: The endpoint
626 * Return the maximum data that can be queued in one go on a given endpoint
627 * so that transfers that are too long can be split.
629 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
631 int index = hs_ep->index;
636 maxsize = DxEPTSIZ_XferSize_LIMIT + 1;
637 maxpkt = DxEPTSIZ_PktCnt_LIMIT + 1;
641 maxpkt = DIEPTSIZ0_PktCnt_LIMIT + 1;
646 /* we made the constant loading easier above by using +1 */
651 * constrain by packet count if maxpkts*pktsize is greater
652 * than the length register size.
655 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
656 maxsize = maxpkt * hs_ep->ep.maxpacket;
662 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
663 * @hsotg: The controller state.
664 * @hs_ep: The endpoint to process a request for
665 * @hs_req: The request to start.
666 * @continuing: True if we are doing more for the current request.
668 * Start the given request running by setting the endpoint registers
669 * appropriately, and writing any data to the FIFOs.
671 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
672 struct s3c_hsotg_ep *hs_ep,
673 struct s3c_hsotg_req *hs_req,
676 struct usb_request *ureq = &hs_req->req;
677 int index = hs_ep->index;
678 int dir_in = hs_ep->dir_in;
688 if (hs_ep->req && !continuing) {
689 dev_err(hsotg->dev, "%s: active request\n", __func__);
692 } else if (hs_ep->req != hs_req && continuing) {
694 "%s: continue different req\n", __func__);
700 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
701 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
703 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
704 __func__, readl(hsotg->regs + epctrl_reg), index,
705 hs_ep->dir_in ? "in" : "out");
707 /* If endpoint is stalled, we will restart request later */
708 ctrl = readl(hsotg->regs + epctrl_reg);
710 if (ctrl & DxEPCTL_Stall) {
711 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
715 length = ureq->length - ureq->actual;
716 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
717 ureq->length, ureq->actual);
720 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
721 ureq->buf, length, ureq->dma,
722 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
724 maxreq = get_ep_limit(hs_ep);
725 if (length > maxreq) {
726 int round = maxreq % hs_ep->ep.maxpacket;
728 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
729 __func__, length, maxreq, round);
731 /* round down to multiple of packets */
739 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
741 packets = 1; /* send one packet if length is zero. */
743 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
744 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
748 if (dir_in && index != 0)
749 if (hs_ep->isochronous)
750 epsize = DxEPTSIZ_MC(packets);
752 epsize = DxEPTSIZ_MC(1);
756 if (index != 0 && ureq->zero) {
758 * test for the packets being exactly right for the
762 if (length == (packets * hs_ep->ep.maxpacket))
766 epsize |= DxEPTSIZ_PktCnt(packets);
767 epsize |= DxEPTSIZ_XferSize(length);
769 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
770 __func__, packets, length, ureq->length, epsize, epsize_reg);
772 /* store the request as the current one we're doing */
775 /* write size / packets */
776 writel(epsize, hsotg->regs + epsize_reg);
778 if (using_dma(hsotg) && !continuing) {
779 unsigned int dma_reg;
782 * write DMA address to control register, buffer already
783 * synced by s3c_hsotg_ep_queue().
786 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
787 writel(ureq->dma, hsotg->regs + dma_reg);
789 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
790 __func__, ureq->dma, dma_reg);
793 ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */
794 ctrl |= DxEPCTL_USBActEp;
796 dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup);
798 /* For Setup request do not clear NAK */
799 if (hsotg->setup && index == 0)
802 ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */
805 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
806 writel(ctrl, hsotg->regs + epctrl_reg);
809 * set these, it seems that DMA support increments past the end
810 * of the packet buffer so we need to calculate the length from
813 hs_ep->size_loaded = length;
814 hs_ep->last_load = ureq->actual;
816 if (dir_in && !using_dma(hsotg)) {
817 /* set these anyway, we may need them for non-periodic in */
818 hs_ep->fifo_load = 0;
820 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
824 * clear the INTknTXFEmpMsk when we start request, more as a aide
825 * to debugging to see what is going on.
828 writel(DIEPMSK_INTknTXFEmpMsk,
829 hsotg->regs + DIEPINT(index));
832 * Note, trying to clear the NAK here causes problems with transmit
833 * on the S3C6400 ending up with the TXFIFO becoming full.
836 /* check ep is enabled */
837 if (!(readl(hsotg->regs + epctrl_reg) & DxEPCTL_EPEna))
839 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
840 index, readl(hsotg->regs + epctrl_reg));
842 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
843 __func__, readl(hsotg->regs + epctrl_reg));
845 /* enable ep interrupts */
846 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
850 * s3c_hsotg_map_dma - map the DMA memory being used for the request
851 * @hsotg: The device state.
852 * @hs_ep: The endpoint the request is on.
853 * @req: The request being processed.
855 * We've been asked to queue a request, so ensure that the memory buffer
856 * is correctly setup for DMA. If we've been passed an extant DMA address
857 * then ensure the buffer has been synced to memory. If our buffer has no
858 * DMA memory, then we map the memory and mark our request to allow us to
859 * cleanup on completion.
861 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
862 struct s3c_hsotg_ep *hs_ep,
863 struct usb_request *req)
865 struct s3c_hsotg_req *hs_req = our_req(req);
868 /* if the length is zero, ignore the DMA data */
869 if (hs_req->req.length == 0)
872 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
879 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
880 __func__, req->buf, req->length);
885 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
888 struct s3c_hsotg_req *hs_req = our_req(req);
889 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
890 struct s3c_hsotg *hs = hs_ep->parent;
893 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
894 ep->name, req, req->length, req->buf, req->no_interrupt,
895 req->zero, req->short_not_ok);
897 /* initialise status of the request */
898 INIT_LIST_HEAD(&hs_req->queue);
900 req->status = -EINPROGRESS;
902 /* if we're using DMA, sync the buffers as necessary */
904 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
909 first = list_empty(&hs_ep->queue);
910 list_add_tail(&hs_req->queue, &hs_ep->queue);
913 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
918 static int s3c_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
921 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
922 struct s3c_hsotg *hs = hs_ep->parent;
923 unsigned long flags = 0;
926 spin_lock_irqsave(&hs->lock, flags);
927 ret = s3c_hsotg_ep_queue(ep, req, gfp_flags);
928 spin_unlock_irqrestore(&hs->lock, flags);
933 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
934 struct usb_request *req)
936 struct s3c_hsotg_req *hs_req = our_req(req);
942 * s3c_hsotg_complete_oursetup - setup completion callback
943 * @ep: The endpoint the request was on.
944 * @req: The request completed.
946 * Called on completion of any requests the driver itself
947 * submitted that need cleaning up.
949 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
950 struct usb_request *req)
952 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
953 struct s3c_hsotg *hsotg = hs_ep->parent;
955 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
957 s3c_hsotg_ep_free_request(ep, req);
961 * ep_from_windex - convert control wIndex value to endpoint
962 * @hsotg: The driver state.
963 * @windex: The control request wIndex field (in host order).
965 * Convert the given wIndex into a pointer to an driver endpoint
966 * structure, or return NULL if it is not a valid endpoint.
968 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
971 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
972 int dir = (windex & USB_DIR_IN) ? 1 : 0;
973 int idx = windex & 0x7F;
978 if (idx > hsotg->num_of_eps)
981 if (idx && ep->dir_in != dir)
988 * s3c_hsotg_send_reply - send reply to control request
989 * @hsotg: The device state
991 * @buff: Buffer for request
992 * @length: Length of reply.
994 * Create a request and queue it on the given endpoint. This is useful as
995 * an internal method of sending replies to certain control requests, etc.
997 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
998 struct s3c_hsotg_ep *ep,
1002 struct usb_request *req;
1005 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1007 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1008 hsotg->ep0_reply = req;
1010 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1014 req->buf = hsotg->ep0_buff;
1015 req->length = length;
1016 req->zero = 1; /* always do zero-length final transfer */
1017 req->complete = s3c_hsotg_complete_oursetup;
1020 memcpy(req->buf, buff, length);
1024 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1026 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1034 * s3c_hsotg_process_req_status - process request GET_STATUS
1035 * @hsotg: The device state
1036 * @ctrl: USB control request
1038 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
1039 struct usb_ctrlrequest *ctrl)
1041 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1042 struct s3c_hsotg_ep *ep;
1046 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1049 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1053 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1054 case USB_RECIP_DEVICE:
1055 reply = cpu_to_le16(0); /* bit 0 => self powered,
1056 * bit 1 => remote wakeup */
1059 case USB_RECIP_INTERFACE:
1060 /* currently, the data result should be zero */
1061 reply = cpu_to_le16(0);
1064 case USB_RECIP_ENDPOINT:
1065 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1069 reply = cpu_to_le16(ep->halted ? 1 : 0);
1076 if (le16_to_cpu(ctrl->wLength) != 2)
1079 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
1081 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1088 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1091 * get_ep_head - return the first request on the endpoint
1092 * @hs_ep: The controller endpoint to get
1094 * Get the first request on the endpoint.
1096 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1098 if (list_empty(&hs_ep->queue))
1101 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1105 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1106 * @hsotg: The device state
1107 * @ctrl: USB control request
1109 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
1110 struct usb_ctrlrequest *ctrl)
1112 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1113 struct s3c_hsotg_req *hs_req;
1115 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1116 struct s3c_hsotg_ep *ep;
1120 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1121 __func__, set ? "SET" : "CLEAR");
1123 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
1124 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1126 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1127 __func__, le16_to_cpu(ctrl->wIndex));
1131 switch (le16_to_cpu(ctrl->wValue)) {
1132 case USB_ENDPOINT_HALT:
1133 halted = ep->halted;
1135 s3c_hsotg_ep_sethalt(&ep->ep, set);
1137 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1140 "%s: failed to send reply\n", __func__);
1145 * we have to complete all requests for ep if it was
1146 * halted, and the halt was cleared by CLEAR_FEATURE
1149 if (!set && halted) {
1151 * If we have request in progress,
1157 list_del_init(&hs_req->queue);
1158 hs_req->req.complete(&ep->ep,
1162 /* If we have pending request, then start it */
1163 restart = !list_empty(&ep->queue);
1165 hs_req = get_ep_head(ep);
1166 s3c_hsotg_start_req(hsotg, ep,
1177 return -ENOENT; /* currently only deal with endpoint */
1182 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1185 * s3c_hsotg_process_control - process a control request
1186 * @hsotg: The device state
1187 * @ctrl: The control request received
1189 * The controller has received the SETUP phase of a control request, and
1190 * needs to work out what to do next (and whether to pass it on to the
1193 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1194 struct usb_ctrlrequest *ctrl)
1196 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1202 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1203 ctrl->bRequest, ctrl->bRequestType,
1204 ctrl->wValue, ctrl->wLength);
1207 * record the direction of the request, for later use when enquing
1211 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1212 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1215 * if we've no data with this request, then the last part of the
1216 * transaction is going to implicitly be IN.
1218 if (ctrl->wLength == 0)
1221 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1222 switch (ctrl->bRequest) {
1223 case USB_REQ_SET_ADDRESS:
1224 dcfg = readl(hsotg->regs + DCFG);
1225 dcfg &= ~DCFG_DevAddr_MASK;
1226 dcfg |= ctrl->wValue << DCFG_DevAddr_SHIFT;
1227 writel(dcfg, hsotg->regs + DCFG);
1229 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1231 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1234 case USB_REQ_GET_STATUS:
1235 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1238 case USB_REQ_CLEAR_FEATURE:
1239 case USB_REQ_SET_FEATURE:
1240 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1245 /* as a fallback, try delivering it to the driver to deal with */
1247 if (ret == 0 && hsotg->driver) {
1248 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1250 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1254 * the request is either unhandlable, or is not formatted correctly
1255 * so respond with a STALL for the status stage to indicate failure.
1262 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1263 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1266 * DxEPCTL_Stall will be cleared by EP once it has
1267 * taken effect, so no need to clear later.
1270 ctrl = readl(hsotg->regs + reg);
1271 ctrl |= DxEPCTL_Stall;
1272 ctrl |= DxEPCTL_CNAK;
1273 writel(ctrl, hsotg->regs + reg);
1276 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1277 ctrl, reg, readl(hsotg->regs + reg));
1280 * don't believe we need to anything more to get the EP
1281 * to reply with a STALL packet
1285 * complete won't be called, so we enqueue
1286 * setup request here
1288 s3c_hsotg_enqueue_setup(hsotg);
1293 * s3c_hsotg_complete_setup - completion of a setup transfer
1294 * @ep: The endpoint the request was on.
1295 * @req: The request completed.
1297 * Called on completion of any requests the driver itself submitted for
1300 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1301 struct usb_request *req)
1303 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1304 struct s3c_hsotg *hsotg = hs_ep->parent;
1306 if (req->status < 0) {
1307 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1311 if (req->actual == 0)
1312 s3c_hsotg_enqueue_setup(hsotg);
1314 s3c_hsotg_process_control(hsotg, req->buf);
1318 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1319 * @hsotg: The device state.
1321 * Enqueue a request on EP0 if necessary to received any SETUP packets
1322 * received from the host.
1324 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1326 struct usb_request *req = hsotg->ctrl_req;
1327 struct s3c_hsotg_req *hs_req = our_req(req);
1330 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1334 req->buf = hsotg->ctrl_buff;
1335 req->complete = s3c_hsotg_complete_setup;
1337 if (!list_empty(&hs_req->queue)) {
1338 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1342 hsotg->eps[0].dir_in = 0;
1344 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1346 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1348 * Don't think there's much we can do other than watch the
1355 * s3c_hsotg_complete_request - complete a request given to us
1356 * @hsotg: The device state.
1357 * @hs_ep: The endpoint the request was on.
1358 * @hs_req: The request to complete.
1359 * @result: The result code (0 => Ok, otherwise errno)
1361 * The given request has finished, so call the necessary completion
1362 * if it has one and then look to see if we can start a new request
1365 * Note, expects the ep to already be locked as appropriate.
1367 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1368 struct s3c_hsotg_ep *hs_ep,
1369 struct s3c_hsotg_req *hs_req,
1375 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1379 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1380 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1383 * only replace the status if we've not already set an error
1384 * from a previous transaction
1387 if (hs_req->req.status == -EINPROGRESS)
1388 hs_req->req.status = result;
1391 list_del_init(&hs_req->queue);
1393 if (using_dma(hsotg))
1394 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1397 * call the complete request with the locks off, just in case the
1398 * request tries to queue more work for this endpoint.
1401 if (hs_req->req.complete) {
1402 spin_unlock(&hsotg->lock);
1403 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1404 spin_lock(&hsotg->lock);
1408 * Look to see if there is anything else to do. Note, the completion
1409 * of the previous request may have caused a new request to be started
1410 * so be careful when doing this.
1413 if (!hs_ep->req && result >= 0) {
1414 restart = !list_empty(&hs_ep->queue);
1416 hs_req = get_ep_head(hs_ep);
1417 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1423 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1424 * @hsotg: The device state.
1425 * @ep_idx: The endpoint index for the data
1426 * @size: The size of data in the fifo, in bytes
1428 * The FIFO status shows there is data to read from the FIFO for a given
1429 * endpoint, so sort out whether we need to read the data into a request
1430 * that has been made for that endpoint.
1432 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1434 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1435 struct s3c_hsotg_req *hs_req = hs_ep->req;
1436 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1443 u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
1446 dev_warn(hsotg->dev,
1447 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1448 __func__, size, ep_idx, epctl);
1450 /* dump the data from the FIFO, we've nothing we can do */
1451 for (ptr = 0; ptr < size; ptr += 4)
1458 read_ptr = hs_req->req.actual;
1459 max_req = hs_req->req.length - read_ptr;
1461 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1462 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1464 if (to_read > max_req) {
1466 * more data appeared than we where willing
1467 * to deal with in this request.
1470 /* currently we don't deal this */
1474 hs_ep->total_data += to_read;
1475 hs_req->req.actual += to_read;
1476 to_read = DIV_ROUND_UP(to_read, 4);
1479 * note, we might over-write the buffer end by 3 bytes depending on
1480 * alignment of the data.
1482 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1486 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1487 * @hsotg: The device instance
1488 * @req: The request currently on this endpoint
1490 * Generate a zero-length IN packet request for terminating a SETUP
1493 * Note, since we don't write any data to the TxFIFO, then it is
1494 * currently believed that we do not need to wait for any space in
1497 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1498 struct s3c_hsotg_req *req)
1503 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1507 if (req->req.length == 0) {
1508 hsotg->eps[0].sent_zlp = 1;
1509 s3c_hsotg_enqueue_setup(hsotg);
1513 hsotg->eps[0].dir_in = 1;
1514 hsotg->eps[0].sent_zlp = 1;
1516 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1518 /* issue a zero-sized packet to terminate this */
1519 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
1520 DxEPTSIZ_XferSize(0), hsotg->regs + DIEPTSIZ(0));
1522 ctrl = readl(hsotg->regs + DIEPCTL0);
1523 ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */
1524 ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */
1525 ctrl |= DxEPCTL_USBActEp;
1526 writel(ctrl, hsotg->regs + DIEPCTL0);
1530 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1531 * @hsotg: The device instance
1532 * @epnum: The endpoint received from
1533 * @was_setup: Set if processing a SetupDone event.
1535 * The RXFIFO has delivered an OutDone event, which means that the data
1536 * transfer for an OUT endpoint has been completed, either by a short
1537 * packet or by the finish of a transfer.
1539 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1540 int epnum, bool was_setup)
1542 u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
1543 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1544 struct s3c_hsotg_req *hs_req = hs_ep->req;
1545 struct usb_request *req = &hs_req->req;
1546 unsigned size_left = DxEPTSIZ_XferSize_GET(epsize);
1550 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1554 if (using_dma(hsotg)) {
1558 * Calculate the size of the transfer by checking how much
1559 * is left in the endpoint size register and then working it
1560 * out from the amount we loaded for the transfer.
1562 * We need to do this as DMA pointers are always 32bit aligned
1563 * so may overshoot/undershoot the transfer.
1566 size_done = hs_ep->size_loaded - size_left;
1567 size_done += hs_ep->last_load;
1569 req->actual = size_done;
1572 /* if there is more request to do, schedule new transfer */
1573 if (req->actual < req->length && size_left == 0) {
1574 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1576 } else if (epnum == 0) {
1578 * After was_setup = 1 =>
1579 * set CNAK for non Setup requests
1581 hsotg->setup = was_setup ? 0 : 1;
1584 if (req->actual < req->length && req->short_not_ok) {
1585 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1586 __func__, req->actual, req->length);
1589 * todo - what should we return here? there's no one else
1590 * even bothering to check the status.
1596 * Condition req->complete != s3c_hsotg_complete_setup says:
1597 * send ZLP when we have an asynchronous request from gadget
1599 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1600 s3c_hsotg_send_zlp(hsotg, hs_req);
1603 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1607 * s3c_hsotg_read_frameno - read current frame number
1608 * @hsotg: The device instance
1610 * Return the current frame number
1612 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1616 dsts = readl(hsotg->regs + DSTS);
1617 dsts &= DSTS_SOFFN_MASK;
1618 dsts >>= DSTS_SOFFN_SHIFT;
1624 * s3c_hsotg_handle_rx - RX FIFO has data
1625 * @hsotg: The device instance
1627 * The IRQ handler has detected that the RX FIFO has some data in it
1628 * that requires processing, so find out what is in there and do the
1631 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1632 * chunks, so if you have x packets received on an endpoint you'll get x
1633 * FIFO events delivered, each with a packet's worth of data in it.
1635 * When using DMA, we should not be processing events from the RXFIFO
1636 * as the actual data should be sent to the memory directly and we turn
1637 * on the completion interrupts to get notifications of transfer completion.
1639 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1641 u32 grxstsr = readl(hsotg->regs + GRXSTSP);
1642 u32 epnum, status, size;
1644 WARN_ON(using_dma(hsotg));
1646 epnum = grxstsr & GRXSTS_EPNum_MASK;
1647 status = grxstsr & GRXSTS_PktSts_MASK;
1649 size = grxstsr & GRXSTS_ByteCnt_MASK;
1650 size >>= GRXSTS_ByteCnt_SHIFT;
1653 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1654 __func__, grxstsr, size, epnum);
1656 #define __status(x) ((x) >> GRXSTS_PktSts_SHIFT)
1658 switch (status >> GRXSTS_PktSts_SHIFT) {
1659 case __status(GRXSTS_PktSts_GlobalOutNAK):
1660 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1663 case __status(GRXSTS_PktSts_OutDone):
1664 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1665 s3c_hsotg_read_frameno(hsotg));
1667 if (!using_dma(hsotg))
1668 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1671 case __status(GRXSTS_PktSts_SetupDone):
1673 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1674 s3c_hsotg_read_frameno(hsotg),
1675 readl(hsotg->regs + DOEPCTL(0)));
1677 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1680 case __status(GRXSTS_PktSts_OutRX):
1681 s3c_hsotg_rx_data(hsotg, epnum, size);
1684 case __status(GRXSTS_PktSts_SetupRX):
1686 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1687 s3c_hsotg_read_frameno(hsotg),
1688 readl(hsotg->regs + DOEPCTL(0)));
1690 s3c_hsotg_rx_data(hsotg, epnum, size);
1694 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1697 s3c_hsotg_dump(hsotg);
1703 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1704 * @mps: The maximum packet size in bytes.
1706 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1710 return D0EPCTL_MPS_64;
1712 return D0EPCTL_MPS_32;
1714 return D0EPCTL_MPS_16;
1716 return D0EPCTL_MPS_8;
1719 /* bad max packet size, warn and return invalid result */
1725 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1726 * @hsotg: The driver state.
1727 * @ep: The index number of the endpoint
1728 * @mps: The maximum packet size in bytes
1730 * Configure the maximum packet size for the given endpoint, updating
1731 * the hardware control registers to reflect this.
1733 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1734 unsigned int ep, unsigned int mps)
1736 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1737 void __iomem *regs = hsotg->regs;
1743 /* EP0 is a special case */
1744 mpsval = s3c_hsotg_ep0_mps(mps);
1747 hs_ep->ep.maxpacket = mps;
1750 mpsval = mps & DxEPCTL_MPS_MASK;
1753 mcval = ((mps >> 11) & 0x3) + 1;
1757 hs_ep->ep.maxpacket = mpsval;
1761 * update both the in and out endpoint controldir_ registers, even
1762 * if one of the directions may not be in use.
1765 reg = readl(regs + DIEPCTL(ep));
1766 reg &= ~DxEPCTL_MPS_MASK;
1768 writel(reg, regs + DIEPCTL(ep));
1771 reg = readl(regs + DOEPCTL(ep));
1772 reg &= ~DxEPCTL_MPS_MASK;
1774 writel(reg, regs + DOEPCTL(ep));
1780 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1784 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1785 * @hsotg: The driver state
1786 * @idx: The index for the endpoint (0..15)
1788 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx)
1793 writel(GRSTCTL_TxFNum(idx) | GRSTCTL_TxFFlsh,
1794 hsotg->regs + GRSTCTL);
1796 /* wait until the fifo is flushed */
1800 val = readl(hsotg->regs + GRSTCTL);
1802 if ((val & (GRSTCTL_TxFFlsh)) == 0)
1805 if (--timeout == 0) {
1807 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1816 * s3c_hsotg_trytx - check to see if anything needs transmitting
1817 * @hsotg: The driver state
1818 * @hs_ep: The driver endpoint to check.
1820 * Check to see if there is a request that has data to send, and if so
1821 * make an attempt to write data into the FIFO.
1823 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1824 struct s3c_hsotg_ep *hs_ep)
1826 struct s3c_hsotg_req *hs_req = hs_ep->req;
1828 if (!hs_ep->dir_in || !hs_req) {
1830 * if request is not enqueued, we disable interrupts
1831 * for endpoints, excepting ep0
1833 if (hs_ep->index != 0)
1834 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index,
1839 if (hs_req->req.actual < hs_req->req.length) {
1840 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1842 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1849 * s3c_hsotg_complete_in - complete IN transfer
1850 * @hsotg: The device state.
1851 * @hs_ep: The endpoint that has just completed.
1853 * An IN transfer has been completed, update the transfer's state and then
1854 * call the relevant completion routines.
1856 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1857 struct s3c_hsotg_ep *hs_ep)
1859 struct s3c_hsotg_req *hs_req = hs_ep->req;
1860 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1861 int size_left, size_done;
1864 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1868 /* Finish ZLP handling for IN EP0 transactions */
1869 if (hsotg->eps[0].sent_zlp) {
1870 dev_dbg(hsotg->dev, "zlp packet received\n");
1871 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1876 * Calculate the size of the transfer by checking how much is left
1877 * in the endpoint size register and then working it out from
1878 * the amount we loaded for the transfer.
1880 * We do this even for DMA, as the transfer may have incremented
1881 * past the end of the buffer (DMA transfers are always 32bit
1885 size_left = DxEPTSIZ_XferSize_GET(epsize);
1887 size_done = hs_ep->size_loaded - size_left;
1888 size_done += hs_ep->last_load;
1890 if (hs_req->req.actual != size_done)
1891 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1892 __func__, hs_req->req.actual, size_done);
1894 hs_req->req.actual = size_done;
1895 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1896 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1899 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1900 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1901 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1902 * inform the host that no more data is available.
1903 * The state of req.zero member is checked to be sure that the value to
1904 * send is smaller than wValue expected from host.
1905 * Check req.length to NOT send another ZLP when the current one is
1906 * under completion (the one for which this completion has been called).
1908 if (hs_req->req.length && hs_ep->index == 0 && hs_req->req.zero &&
1909 hs_req->req.length == hs_req->req.actual &&
1910 !(hs_req->req.length % hs_ep->ep.maxpacket)) {
1912 dev_dbg(hsotg->dev, "ep0 zlp IN packet sent\n");
1913 s3c_hsotg_send_zlp(hsotg, hs_req);
1918 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1919 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1920 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1922 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1926 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1927 * @hsotg: The driver state
1928 * @idx: The index for the endpoint (0..15)
1929 * @dir_in: Set if this is an IN endpoint
1931 * Process and clear any interrupt pending for an individual endpoint
1933 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1936 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1937 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1938 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1939 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1943 ints = readl(hsotg->regs + epint_reg);
1944 ctrl = readl(hsotg->regs + epctl_reg);
1946 /* Clear endpoint interrupts */
1947 writel(ints, hsotg->regs + epint_reg);
1949 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1950 __func__, idx, dir_in ? "in" : "out", ints);
1952 if (ints & DxEPINT_XferCompl) {
1953 if (hs_ep->isochronous && hs_ep->interval == 1) {
1954 if (ctrl & DxEPCTL_EOFrNum)
1955 ctrl |= DxEPCTL_SetEvenFr;
1957 ctrl |= DxEPCTL_SetOddFr;
1958 writel(ctrl, hsotg->regs + epctl_reg);
1962 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1963 __func__, readl(hsotg->regs + epctl_reg),
1964 readl(hsotg->regs + epsiz_reg));
1967 * we get OutDone from the FIFO, so we only need to look
1968 * at completing IN requests here
1971 s3c_hsotg_complete_in(hsotg, hs_ep);
1973 if (idx == 0 && !hs_ep->req)
1974 s3c_hsotg_enqueue_setup(hsotg);
1975 } else if (using_dma(hsotg)) {
1977 * We're using DMA, we need to fire an OutDone here
1978 * as we ignore the RXFIFO.
1981 s3c_hsotg_handle_outdone(hsotg, idx, false);
1985 if (ints & DxEPINT_EPDisbld) {
1986 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1989 int epctl = readl(hsotg->regs + epctl_reg);
1991 s3c_hsotg_txfifo_flush(hsotg, idx);
1993 if ((epctl & DxEPCTL_Stall) &&
1994 (epctl & DxEPCTL_EPType_Bulk)) {
1995 int dctl = readl(hsotg->regs + DCTL);
1997 dctl |= DCTL_CGNPInNAK;
1998 writel(dctl, hsotg->regs + DCTL);
2003 if (ints & DxEPINT_AHBErr)
2004 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2006 if (ints & DxEPINT_Setup) { /* Setup or Timeout */
2007 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2009 if (using_dma(hsotg) && idx == 0) {
2011 * this is the notification we've received a
2012 * setup packet. In non-DMA mode we'd get this
2013 * from the RXFIFO, instead we need to process
2020 s3c_hsotg_handle_outdone(hsotg, 0, true);
2024 if (ints & DxEPINT_Back2BackSetup)
2025 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2027 if (dir_in && !hs_ep->isochronous) {
2028 /* not sure if this is important, but we'll clear it anyway */
2029 if (ints & DIEPMSK_INTknTXFEmpMsk) {
2030 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2034 /* this probably means something bad is happening */
2035 if (ints & DIEPMSK_INTknEPMisMsk) {
2036 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2040 /* FIFO has space or is empty (see GAHBCFG) */
2041 if (hsotg->dedicated_fifos &&
2042 ints & DIEPMSK_TxFIFOEmpty) {
2043 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2045 if (!using_dma(hsotg))
2046 s3c_hsotg_trytx(hsotg, hs_ep);
2052 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2053 * @hsotg: The device state.
2055 * Handle updating the device settings after the enumeration phase has
2058 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
2060 u32 dsts = readl(hsotg->regs + DSTS);
2061 int ep0_mps = 0, ep_mps;
2064 * This should signal the finish of the enumeration phase
2065 * of the USB handshaking, so we should now know what rate
2069 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2072 * note, since we're limited by the size of transfer on EP0, and
2073 * it seems IN transfers must be a even number of packets we do
2074 * not advertise a 64byte MPS on EP0.
2077 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2078 switch (dsts & DSTS_EnumSpd_MASK) {
2079 case DSTS_EnumSpd_FS:
2080 case DSTS_EnumSpd_FS48:
2081 hsotg->gadget.speed = USB_SPEED_FULL;
2082 ep0_mps = EP0_MPS_LIMIT;
2086 case DSTS_EnumSpd_HS:
2087 hsotg->gadget.speed = USB_SPEED_HIGH;
2088 ep0_mps = EP0_MPS_LIMIT;
2092 case DSTS_EnumSpd_LS:
2093 hsotg->gadget.speed = USB_SPEED_LOW;
2095 * note, we don't actually support LS in this driver at the
2096 * moment, and the documentation seems to imply that it isn't
2097 * supported by the PHYs on some of the devices.
2101 dev_info(hsotg->dev, "new device is %s\n",
2102 usb_speed_string(hsotg->gadget.speed));
2105 * we should now know the maximum packet size for an
2106 * endpoint, so set the endpoints to a default value.
2111 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
2112 for (i = 1; i < hsotg->num_of_eps; i++)
2113 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
2116 /* ensure after enumeration our EP0 is active */
2118 s3c_hsotg_enqueue_setup(hsotg);
2120 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2121 readl(hsotg->regs + DIEPCTL0),
2122 readl(hsotg->regs + DOEPCTL0));
2126 * kill_all_requests - remove all requests from the endpoint's queue
2127 * @hsotg: The device state.
2128 * @ep: The endpoint the requests may be on.
2129 * @result: The result code to use.
2130 * @force: Force removal of any current requests
2132 * Go through the requests on the given endpoint and mark them
2133 * completed with the given result code.
2135 static void kill_all_requests(struct s3c_hsotg *hsotg,
2136 struct s3c_hsotg_ep *ep,
2137 int result, bool force)
2139 struct s3c_hsotg_req *req, *treq;
2141 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2143 * currently, we can't do much about an already
2144 * running request on an in endpoint
2147 if (ep->req == req && ep->dir_in && !force)
2150 s3c_hsotg_complete_request(hsotg, ep, req,
2153 if(hsotg->dedicated_fifos)
2154 if ((readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4 < 3072)
2155 s3c_hsotg_txfifo_flush(hsotg, ep->index);
2158 #define call_gadget(_hs, _entry) \
2160 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
2161 (_hs)->driver && (_hs)->driver->_entry) { \
2162 spin_unlock(&_hs->lock); \
2163 (_hs)->driver->_entry(&(_hs)->gadget); \
2164 spin_lock(&_hs->lock); \
2169 * s3c_hsotg_disconnect - disconnect service
2170 * @hsotg: The device state.
2172 * The device has been disconnected. Remove all current
2173 * transactions and signal the gadget driver that this
2176 static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg)
2180 for (ep = 0; ep < hsotg->num_of_eps; ep++)
2181 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
2183 call_gadget(hsotg, disconnect);
2187 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2188 * @hsotg: The device state:
2189 * @periodic: True if this is a periodic FIFO interrupt
2191 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2193 struct s3c_hsotg_ep *ep;
2196 /* look through for any more data to transmit */
2198 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2199 ep = &hsotg->eps[epno];
2204 if ((periodic && !ep->periodic) ||
2205 (!periodic && ep->periodic))
2208 ret = s3c_hsotg_trytx(hsotg, ep);
2214 /* IRQ flags which will trigger a retry around the IRQ loop */
2215 #define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \
2220 * s3c_hsotg_corereset - issue softreset to the core
2221 * @hsotg: The device state
2223 * Issue a soft reset to the core, and await the core finishing it.
2225 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2230 dev_dbg(hsotg->dev, "resetting core\n");
2232 /* issue soft reset */
2233 writel(GRSTCTL_CSftRst, hsotg->regs + GRSTCTL);
2237 grstctl = readl(hsotg->regs + GRSTCTL);
2238 } while ((grstctl & GRSTCTL_CSftRst) && timeout-- > 0);
2240 if (grstctl & GRSTCTL_CSftRst) {
2241 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2248 u32 grstctl = readl(hsotg->regs + GRSTCTL);
2250 if (timeout-- < 0) {
2251 dev_info(hsotg->dev,
2252 "%s: reset failed, GRSTCTL=%08x\n",
2257 if (!(grstctl & GRSTCTL_AHBIdle))
2260 break; /* reset done */
2263 dev_dbg(hsotg->dev, "reset successful\n");
2268 * s3c_hsotg_core_init - issue softreset to the core
2269 * @hsotg: The device state
2271 * Issue a soft reset to the core, and await the core finishing it.
2273 static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2275 s3c_hsotg_corereset(hsotg);
2278 * we must now enable ep0 ready for host detection and then
2279 * set configuration.
2282 /* set the PLL on, remove the HNP/SRP and set the PHY */
2283 writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) |
2284 (0x5 << 10), hsotg->regs + GUSBCFG);
2286 s3c_hsotg_init_fifo(hsotg);
2288 __orr32(hsotg->regs + DCTL, DCTL_SftDiscon);
2290 writel(1 << 18 | DCFG_DevSpd_HS, hsotg->regs + DCFG);
2292 /* Clear any pending OTG interrupts */
2293 writel(0xffffffff, hsotg->regs + GOTGINT);
2295 /* Clear any pending interrupts */
2296 writel(0xffffffff, hsotg->regs + GINTSTS);
2298 writel(GINTSTS_ErlySusp | GINTSTS_SessReqInt |
2299 GINTSTS_GOUTNakEff | GINTSTS_GINNakEff |
2300 GINTSTS_ConIDStsChng | GINTSTS_USBRst |
2301 GINTSTS_EnumDone | GINTSTS_OTGInt |
2302 GINTSTS_USBSusp | GINTSTS_WkUpInt,
2303 hsotg->regs + GINTMSK);
2305 if (using_dma(hsotg))
2306 writel(GAHBCFG_GlblIntrEn | GAHBCFG_DMAEn |
2307 GAHBCFG_HBstLen_Incr4,
2308 hsotg->regs + GAHBCFG);
2310 writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NPTxFEmpLvl |
2311 GAHBCFG_PTxFEmpLvl) : 0) |
2313 hsotg->regs + GAHBCFG);
2316 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2317 * when we have no data to transfer. Otherwise we get being flooded by
2321 writel(((hsotg->dedicated_fifos) ? DIEPMSK_TxFIFOEmpty |
2322 DIEPMSK_INTknTXFEmpMsk : 0) |
2323 DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk |
2324 DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
2325 DIEPMSK_INTknEPMisMsk,
2326 hsotg->regs + DIEPMSK);
2329 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2330 * DMA mode we may need this.
2332 writel((using_dma(hsotg) ? (DIEPMSK_XferComplMsk |
2333 DIEPMSK_TimeOUTMsk) : 0) |
2334 DOEPMSK_EPDisbldMsk | DOEPMSK_AHBErrMsk |
2336 hsotg->regs + DOEPMSK);
2338 writel(0, hsotg->regs + DAINTMSK);
2340 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2341 readl(hsotg->regs + DIEPCTL0),
2342 readl(hsotg->regs + DOEPCTL0));
2344 /* enable in and out endpoint interrupts */
2345 s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPInt | GINTSTS_IEPInt);
2348 * Enable the RXFIFO when in slave mode, as this is how we collect
2349 * the data. In DMA mode, we get events from the FIFO but also
2350 * things we cannot process, so do not use it.
2352 if (!using_dma(hsotg))
2353 s3c_hsotg_en_gsint(hsotg, GINTSTS_RxFLvl);
2355 /* Enable interrupts for EP0 in and out */
2356 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2357 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2359 __orr32(hsotg->regs + DCTL, DCTL_PWROnPrgDone);
2360 udelay(10); /* see openiboot */
2361 __bic32(hsotg->regs + DCTL, DCTL_PWROnPrgDone);
2363 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL));
2366 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2367 * writing to the EPCTL register..
2370 /* set to read 1 8byte packet */
2371 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
2372 DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2374 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2375 DxEPCTL_CNAK | DxEPCTL_EPEna |
2377 hsotg->regs + DOEPCTL0);
2379 /* enable, but don't activate EP0in */
2380 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2381 DxEPCTL_USBActEp, hsotg->regs + DIEPCTL0);
2383 s3c_hsotg_enqueue_setup(hsotg);
2385 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2386 readl(hsotg->regs + DIEPCTL0),
2387 readl(hsotg->regs + DOEPCTL0));
2389 /* clear global NAKs */
2390 writel(DCTL_CGOUTNak | DCTL_CGNPInNAK,
2391 hsotg->regs + DCTL);
2393 /* must be at-least 3ms to allow bus to see disconnect */
2396 /* remove the soft-disconnect and let's go */
2397 __bic32(hsotg->regs + DCTL, DCTL_SftDiscon);
2401 * s3c_hsotg_irq - handle device interrupt
2402 * @irq: The IRQ number triggered
2403 * @pw: The pw value when registered the handler.
2405 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2407 struct s3c_hsotg *hsotg = pw;
2408 int retry_count = 8;
2412 spin_lock(&hsotg->lock);
2414 gintsts = readl(hsotg->regs + GINTSTS);
2415 gintmsk = readl(hsotg->regs + GINTMSK);
2417 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2418 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2422 if (gintsts & GINTSTS_OTGInt) {
2423 u32 otgint = readl(hsotg->regs + GOTGINT);
2425 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2427 writel(otgint, hsotg->regs + GOTGINT);
2430 if (gintsts & GINTSTS_SessReqInt) {
2431 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2432 writel(GINTSTS_SessReqInt, hsotg->regs + GINTSTS);
2435 if (gintsts & GINTSTS_EnumDone) {
2436 writel(GINTSTS_EnumDone, hsotg->regs + GINTSTS);
2438 s3c_hsotg_irq_enumdone(hsotg);
2441 if (gintsts & GINTSTS_ConIDStsChng) {
2442 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2443 readl(hsotg->regs + DSTS),
2444 readl(hsotg->regs + GOTGCTL));
2446 writel(GINTSTS_ConIDStsChng, hsotg->regs + GINTSTS);
2449 if (gintsts & (GINTSTS_OEPInt | GINTSTS_IEPInt)) {
2450 u32 daint = readl(hsotg->regs + DAINT);
2451 u32 daintmsk = readl(hsotg->regs + DAINTMSK);
2452 u32 daint_out, daint_in;
2456 daint_out = daint >> DAINT_OutEP_SHIFT;
2457 daint_in = daint & ~(daint_out << DAINT_OutEP_SHIFT);
2459 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2461 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2463 s3c_hsotg_epint(hsotg, ep, 0);
2466 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2468 s3c_hsotg_epint(hsotg, ep, 1);
2472 if (gintsts & GINTSTS_USBRst) {
2474 u32 usb_status = readl(hsotg->regs + GOTGCTL);
2476 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2477 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2478 readl(hsotg->regs + GNPTXSTS));
2480 writel(GINTSTS_USBRst, hsotg->regs + GINTSTS);
2482 if (usb_status & GOTGCTL_BSESVLD) {
2483 if (time_after(jiffies, hsotg->last_rst +
2484 msecs_to_jiffies(200))) {
2486 kill_all_requests(hsotg, &hsotg->eps[0],
2489 s3c_hsotg_core_init(hsotg);
2490 hsotg->last_rst = jiffies;
2495 /* check both FIFOs */
2497 if (gintsts & GINTSTS_NPTxFEmp) {
2498 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2501 * Disable the interrupt to stop it happening again
2502 * unless one of these endpoint routines decides that
2503 * it needs re-enabling
2506 s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTxFEmp);
2507 s3c_hsotg_irq_fifoempty(hsotg, false);
2510 if (gintsts & GINTSTS_PTxFEmp) {
2511 dev_dbg(hsotg->dev, "PTxFEmp\n");
2513 /* See note in GINTSTS_NPTxFEmp */
2515 s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTxFEmp);
2516 s3c_hsotg_irq_fifoempty(hsotg, true);
2519 if (gintsts & GINTSTS_RxFLvl) {
2521 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2522 * we need to retry s3c_hsotg_handle_rx if this is still
2526 s3c_hsotg_handle_rx(hsotg);
2529 if (gintsts & GINTSTS_ModeMis) {
2530 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2531 writel(GINTSTS_ModeMis, hsotg->regs + GINTSTS);
2534 if (gintsts & GINTSTS_USBSusp) {
2535 dev_info(hsotg->dev, "GINTSTS_USBSusp\n");
2536 writel(GINTSTS_USBSusp, hsotg->regs + GINTSTS);
2538 call_gadget(hsotg, suspend);
2539 s3c_hsotg_disconnect(hsotg);
2542 if (gintsts & GINTSTS_WkUpInt) {
2543 dev_info(hsotg->dev, "GINTSTS_WkUpIn\n");
2544 writel(GINTSTS_WkUpInt, hsotg->regs + GINTSTS);
2546 call_gadget(hsotg, resume);
2549 if (gintsts & GINTSTS_ErlySusp) {
2550 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2551 writel(GINTSTS_ErlySusp, hsotg->regs + GINTSTS);
2555 * these next two seem to crop-up occasionally causing the core
2556 * to shutdown the USB transfer, so try clearing them and logging
2560 if (gintsts & GINTSTS_GOUTNakEff) {
2561 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2563 writel(DCTL_CGOUTNak, hsotg->regs + DCTL);
2565 s3c_hsotg_dump(hsotg);
2568 if (gintsts & GINTSTS_GINNakEff) {
2569 dev_info(hsotg->dev, "GINNakEff triggered\n");
2571 writel(DCTL_CGNPInNAK, hsotg->regs + DCTL);
2573 s3c_hsotg_dump(hsotg);
2577 * if we've had fifo events, we should try and go around the
2578 * loop again to see if there's any point in returning yet.
2581 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2584 spin_unlock(&hsotg->lock);
2590 * s3c_hsotg_ep_enable - enable the given endpoint
2591 * @ep: The USB endpint to configure
2592 * @desc: The USB endpoint descriptor to configure with.
2594 * This is called from the USB gadget code's usb_ep_enable().
2596 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2597 const struct usb_endpoint_descriptor *desc)
2599 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2600 struct s3c_hsotg *hsotg = hs_ep->parent;
2601 unsigned long flags;
2602 int index = hs_ep->index;
2610 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2611 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2612 desc->wMaxPacketSize, desc->bInterval);
2614 /* not to be called for EP0 */
2615 WARN_ON(index == 0);
2617 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2618 if (dir_in != hs_ep->dir_in) {
2619 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2623 mps = usb_endpoint_maxp(desc);
2625 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2627 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2628 epctrl = readl(hsotg->regs + epctrl_reg);
2630 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2631 __func__, epctrl, epctrl_reg);
2633 spin_lock_irqsave(&hsotg->lock, flags);
2635 epctrl &= ~(DxEPCTL_EPType_MASK | DxEPCTL_MPS_MASK);
2636 epctrl |= DxEPCTL_MPS(mps);
2639 * mark the endpoint as active, otherwise the core may ignore
2640 * transactions entirely for this endpoint
2642 epctrl |= DxEPCTL_USBActEp;
2645 * set the NAK status on the endpoint, otherwise we might try and
2646 * do something with data that we've yet got a request to process
2647 * since the RXFIFO will take data for an endpoint even if the
2648 * size register hasn't been set.
2651 epctrl |= DxEPCTL_SNAK;
2653 /* update the endpoint state */
2654 s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps);
2656 /* default, set to non-periodic */
2657 hs_ep->isochronous = 0;
2658 hs_ep->periodic = 0;
2660 hs_ep->interval = desc->bInterval;
2662 if (hs_ep->interval > 1 && hs_ep->mc > 1)
2663 dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
2665 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2666 case USB_ENDPOINT_XFER_ISOC:
2667 epctrl |= DxEPCTL_EPType_Iso;
2668 epctrl |= DxEPCTL_SetEvenFr;
2669 hs_ep->isochronous = 1;
2671 hs_ep->periodic = 1;
2674 case USB_ENDPOINT_XFER_BULK:
2675 epctrl |= DxEPCTL_EPType_Bulk;
2678 case USB_ENDPOINT_XFER_INT:
2681 * Allocate our TxFNum by simply using the index
2682 * of the endpoint for the moment. We could do
2683 * something better if the host indicates how
2684 * many FIFOs we are expecting to use.
2687 hs_ep->periodic = 1;
2688 epctrl |= DxEPCTL_TxFNum(index);
2691 epctrl |= DxEPCTL_EPType_Intterupt;
2694 case USB_ENDPOINT_XFER_CONTROL:
2695 epctrl |= DxEPCTL_EPType_Control;
2700 * if the hardware has dedicated fifos, we must give each IN EP
2701 * a unique tx-fifo even if it is non-periodic.
2703 if (dir_in && hsotg->dedicated_fifos)
2704 epctrl |= DxEPCTL_TxFNum(index);
2706 /* for non control endpoints, set PID to D0 */
2708 epctrl |= DxEPCTL_SetD0PID;
2710 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2713 writel(epctrl, hsotg->regs + epctrl_reg);
2714 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2715 __func__, readl(hsotg->regs + epctrl_reg));
2717 /* enable the endpoint interrupt */
2718 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2720 spin_unlock_irqrestore(&hsotg->lock, flags);
2725 * s3c_hsotg_ep_disable - disable given endpoint
2726 * @ep: The endpoint to disable.
2728 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2730 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2731 struct s3c_hsotg *hsotg = hs_ep->parent;
2732 int dir_in = hs_ep->dir_in;
2733 int index = hs_ep->index;
2734 unsigned long flags;
2738 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2740 if (ep == &hsotg->eps[0].ep) {
2741 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2745 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2747 spin_lock_irqsave(&hsotg->lock, flags);
2748 /* terminate all requests with shutdown */
2749 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2752 ctrl = readl(hsotg->regs + epctrl_reg);
2753 ctrl &= ~DxEPCTL_EPEna;
2754 ctrl &= ~DxEPCTL_USBActEp;
2755 ctrl |= DxEPCTL_SNAK;
2757 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2758 writel(ctrl, hsotg->regs + epctrl_reg);
2760 /* disable endpoint interrupts */
2761 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2763 spin_unlock_irqrestore(&hsotg->lock, flags);
2768 * on_list - check request is on the given endpoint
2769 * @ep: The endpoint to check.
2770 * @test: The request to test if it is on the endpoint.
2772 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2774 struct s3c_hsotg_req *req, *treq;
2776 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2785 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2786 * @ep: The endpoint to dequeue.
2787 * @req: The request to be removed from a queue.
2789 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2791 struct s3c_hsotg_req *hs_req = our_req(req);
2792 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2793 struct s3c_hsotg *hs = hs_ep->parent;
2794 unsigned long flags;
2796 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2798 spin_lock_irqsave(&hs->lock, flags);
2800 if (!on_list(hs_ep, hs_req)) {
2801 spin_unlock_irqrestore(&hs->lock, flags);
2805 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2806 spin_unlock_irqrestore(&hs->lock, flags);
2812 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2813 * @ep: The endpoint to set halt.
2814 * @value: Set or unset the halt.
2816 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2818 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2819 struct s3c_hsotg *hs = hs_ep->parent;
2820 int index = hs_ep->index;
2825 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2827 /* write both IN and OUT control registers */
2829 epreg = DIEPCTL(index);
2830 epctl = readl(hs->regs + epreg);
2833 epctl |= DxEPCTL_Stall + DxEPCTL_SNAK;
2834 if (epctl & DxEPCTL_EPEna)
2835 epctl |= DxEPCTL_EPDis;
2837 epctl &= ~DxEPCTL_Stall;
2838 xfertype = epctl & DxEPCTL_EPType_MASK;
2839 if (xfertype == DxEPCTL_EPType_Bulk ||
2840 xfertype == DxEPCTL_EPType_Intterupt)
2841 epctl |= DxEPCTL_SetD0PID;
2844 writel(epctl, hs->regs + epreg);
2846 epreg = DOEPCTL(index);
2847 epctl = readl(hs->regs + epreg);
2850 epctl |= DxEPCTL_Stall;
2852 epctl &= ~DxEPCTL_Stall;
2853 xfertype = epctl & DxEPCTL_EPType_MASK;
2854 if (xfertype == DxEPCTL_EPType_Bulk ||
2855 xfertype == DxEPCTL_EPType_Intterupt)
2856 epctl |= DxEPCTL_SetD0PID;
2859 writel(epctl, hs->regs + epreg);
2861 hs_ep->halted = value;
2867 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2868 * @ep: The endpoint to set halt.
2869 * @value: Set or unset the halt.
2871 static int s3c_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
2873 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2874 struct s3c_hsotg *hs = hs_ep->parent;
2875 unsigned long flags = 0;
2878 spin_lock_irqsave(&hs->lock, flags);
2879 ret = s3c_hsotg_ep_sethalt(ep, value);
2880 spin_unlock_irqrestore(&hs->lock, flags);
2885 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2886 .enable = s3c_hsotg_ep_enable,
2887 .disable = s3c_hsotg_ep_disable,
2888 .alloc_request = s3c_hsotg_ep_alloc_request,
2889 .free_request = s3c_hsotg_ep_free_request,
2890 .queue = s3c_hsotg_ep_queue_lock,
2891 .dequeue = s3c_hsotg_ep_dequeue,
2892 .set_halt = s3c_hsotg_ep_sethalt_lock,
2893 /* note, don't believe we have any call for the fifo routines */
2897 * s3c_hsotg_phy_enable - enable platform phy dev
2898 * @hsotg: The driver state
2900 * A wrapper for platform code responsible for controlling
2901 * low-level USB code
2903 static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
2905 struct platform_device *pdev = to_platform_device(hsotg->dev);
2907 dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
2910 usb_phy_init(hsotg->phy);
2911 else if (hsotg->plat->phy_init)
2912 hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
2916 * s3c_hsotg_phy_disable - disable platform phy dev
2917 * @hsotg: The driver state
2919 * A wrapper for platform code responsible for controlling
2920 * low-level USB code
2922 static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
2924 struct platform_device *pdev = to_platform_device(hsotg->dev);
2927 usb_phy_shutdown(hsotg->phy);
2928 else if (hsotg->plat->phy_exit)
2929 hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
2933 * s3c_hsotg_init - initalize the usb core
2934 * @hsotg: The driver state
2936 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2938 /* unmask subset of endpoint interrupts */
2940 writel(DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
2941 DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk,
2942 hsotg->regs + DIEPMSK);
2944 writel(DOEPMSK_SetupMsk | DOEPMSK_AHBErrMsk |
2945 DOEPMSK_EPDisbldMsk | DOEPMSK_XferComplMsk,
2946 hsotg->regs + DOEPMSK);
2948 writel(0, hsotg->regs + DAINTMSK);
2950 /* Be in disconnected state until gadget is registered */
2951 __orr32(hsotg->regs + DCTL, DCTL_SftDiscon);
2954 /* post global nak until we're ready */
2955 writel(DCTL_SGNPInNAK | DCTL_SGOUTNak,
2956 hsotg->regs + DCTL);
2961 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2962 readl(hsotg->regs + GRXFSIZ),
2963 readl(hsotg->regs + GNPTXFSIZ));
2965 s3c_hsotg_init_fifo(hsotg);
2967 /* set the PLL on, remove the HNP/SRP and set the PHY */
2968 writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) | (0x5 << 10),
2969 hsotg->regs + GUSBCFG);
2971 writel(using_dma(hsotg) ? GAHBCFG_DMAEn : 0x0,
2972 hsotg->regs + GAHBCFG);
2976 * s3c_hsotg_udc_start - prepare the udc for work
2977 * @gadget: The usb gadget state
2978 * @driver: The usb gadget driver
2980 * Perform initialization to prepare udc device and driver
2983 static int s3c_hsotg_udc_start(struct usb_gadget *gadget,
2984 struct usb_gadget_driver *driver)
2986 struct s3c_hsotg *hsotg = to_hsotg(gadget);
2990 pr_err("%s: called with no device\n", __func__);
2995 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2999 if (driver->max_speed < USB_SPEED_FULL)
3000 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
3002 if (!driver->setup) {
3003 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
3007 WARN_ON(hsotg->driver);
3009 driver->driver.bus = NULL;
3010 hsotg->driver = driver;
3011 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
3012 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3014 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3017 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
3021 hsotg->last_rst = jiffies;
3022 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
3026 hsotg->driver = NULL;
3031 * s3c_hsotg_udc_stop - stop the udc
3032 * @gadget: The usb gadget state
3033 * @driver: The usb gadget driver
3035 * Stop udc hw block and stay tunned for future transmissions
3037 static int s3c_hsotg_udc_stop(struct usb_gadget *gadget,
3038 struct usb_gadget_driver *driver)
3040 struct s3c_hsotg *hsotg = to_hsotg(gadget);
3041 unsigned long flags = 0;
3047 /* all endpoints should be shutdown */
3048 for (ep = 0; ep < hsotg->num_of_eps; ep++)
3049 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
3051 spin_lock_irqsave(&hsotg->lock, flags);
3053 s3c_hsotg_phy_disable(hsotg);
3056 hsotg->driver = NULL;
3058 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3060 spin_unlock_irqrestore(&hsotg->lock, flags);
3062 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
3068 * s3c_hsotg_gadget_getframe - read the frame number
3069 * @gadget: The usb gadget state
3071 * Read the {micro} frame number
3073 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
3075 return s3c_hsotg_read_frameno(to_hsotg(gadget));
3079 * s3c_hsotg_pullup - connect/disconnect the USB PHY
3080 * @gadget: The usb gadget state
3081 * @is_on: Current state of the USB PHY
3083 * Connect/Disconnect the USB PHY pullup
3085 static int s3c_hsotg_pullup(struct usb_gadget *gadget, int is_on)
3087 struct s3c_hsotg *hsotg = to_hsotg(gadget);
3088 unsigned long flags = 0;
3090 dev_dbg(hsotg->dev, "%s: is_in: %d\n", __func__, is_on);
3092 spin_lock_irqsave(&hsotg->lock, flags);
3094 s3c_hsotg_phy_enable(hsotg);
3095 s3c_hsotg_core_init(hsotg);
3097 s3c_hsotg_disconnect(hsotg);
3098 s3c_hsotg_phy_disable(hsotg);
3101 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3102 spin_unlock_irqrestore(&hsotg->lock, flags);
3107 static const struct usb_gadget_ops s3c_hsotg_gadget_ops = {
3108 .get_frame = s3c_hsotg_gadget_getframe,
3109 .udc_start = s3c_hsotg_udc_start,
3110 .udc_stop = s3c_hsotg_udc_stop,
3111 .pullup = s3c_hsotg_pullup,
3115 * s3c_hsotg_initep - initialise a single endpoint
3116 * @hsotg: The device state.
3117 * @hs_ep: The endpoint to be initialised.
3118 * @epnum: The endpoint number
3120 * Initialise the given endpoint (as part of the probe and device state
3121 * creation) to give to the gadget driver. Setup the endpoint name, any
3122 * direction information and other state that may be required.
3124 static void s3c_hsotg_initep(struct s3c_hsotg *hsotg,
3125 struct s3c_hsotg_ep *hs_ep,
3133 else if ((epnum % 2) == 0) {
3140 hs_ep->index = epnum;
3142 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3144 INIT_LIST_HEAD(&hs_ep->queue);
3145 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3147 /* add to the list of endpoints known by the gadget driver */
3149 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3151 hs_ep->parent = hsotg;
3152 hs_ep->ep.name = hs_ep->name;
3153 hs_ep->ep.maxpacket = epnum ? 1024 : EP0_MPS_LIMIT;
3154 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
3157 * Read the FIFO size for the Periodic TX FIFO, even if we're
3158 * an OUT endpoint, we may as well do this if in future the
3159 * code is changed to make each endpoint's direction changeable.
3162 ptxfifo = readl(hsotg->regs + DPTXFSIZn(epnum));
3163 hs_ep->fifo_size = DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
3166 * if we're using dma, we need to set the next-endpoint pointer
3167 * to be something valid.
3170 if (using_dma(hsotg)) {
3171 u32 next = DxEPCTL_NextEp((epnum + 1) % 15);
3172 writel(next, hsotg->regs + DIEPCTL(epnum));
3173 writel(next, hsotg->regs + DOEPCTL(epnum));
3178 * s3c_hsotg_hw_cfg - read HW configuration registers
3179 * @param: The device state
3181 * Read the USB core HW configuration registers
3183 static void s3c_hsotg_hw_cfg(struct s3c_hsotg *hsotg)
3186 /* check hardware configuration */
3188 cfg2 = readl(hsotg->regs + 0x48);
3189 hsotg->num_of_eps = (cfg2 >> 10) & 0xF;
3191 dev_info(hsotg->dev, "EPs:%d\n", hsotg->num_of_eps);
3193 cfg4 = readl(hsotg->regs + 0x50);
3194 hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
3196 dev_info(hsotg->dev, "%s fifos\n",
3197 hsotg->dedicated_fifos ? "dedicated" : "shared");
3201 * s3c_hsotg_dump - dump state of the udc
3202 * @param: The device state
3204 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
3207 struct device *dev = hsotg->dev;
3208 void __iomem *regs = hsotg->regs;
3212 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3213 readl(regs + DCFG), readl(regs + DCTL),
3214 readl(regs + DIEPMSK));
3216 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3217 readl(regs + GAHBCFG), readl(regs + 0x44));
3219 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3220 readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
3222 /* show periodic fifo settings */
3224 for (idx = 1; idx <= 15; idx++) {
3225 val = readl(regs + DPTXFSIZn(idx));
3226 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3227 val >> DPTXFSIZn_DPTxFSize_SHIFT,
3228 val & DPTXFSIZn_DPTxFStAddr_MASK);
3231 for (idx = 0; idx < 15; idx++) {
3233 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3234 readl(regs + DIEPCTL(idx)),
3235 readl(regs + DIEPTSIZ(idx)),
3236 readl(regs + DIEPDMA(idx)));
3238 val = readl(regs + DOEPCTL(idx));
3240 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3241 idx, readl(regs + DOEPCTL(idx)),
3242 readl(regs + DOEPTSIZ(idx)),
3243 readl(regs + DOEPDMA(idx)));
3247 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3248 readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE));
3253 * state_show - debugfs: show overall driver and device state.
3254 * @seq: The seq file to write to.
3255 * @v: Unused parameter.
3257 * This debugfs entry shows the overall state of the hardware and
3258 * some general information about each of the endpoints available
3261 static int state_show(struct seq_file *seq, void *v)
3263 struct s3c_hsotg *hsotg = seq->private;
3264 void __iomem *regs = hsotg->regs;
3267 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3270 readl(regs + DSTS));
3272 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3273 readl(regs + DIEPMSK), readl(regs + DOEPMSK));
3275 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3276 readl(regs + GINTMSK),
3277 readl(regs + GINTSTS));
3279 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3280 readl(regs + DAINTMSK),
3281 readl(regs + DAINT));
3283 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3284 readl(regs + GNPTXSTS),
3285 readl(regs + GRXSTSR));
3287 seq_puts(seq, "\nEndpoint status:\n");
3289 for (idx = 0; idx < 15; idx++) {
3292 in = readl(regs + DIEPCTL(idx));
3293 out = readl(regs + DOEPCTL(idx));
3295 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3298 in = readl(regs + DIEPTSIZ(idx));
3299 out = readl(regs + DOEPTSIZ(idx));
3301 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3304 seq_puts(seq, "\n");
3310 static int state_open(struct inode *inode, struct file *file)
3312 return single_open(file, state_show, inode->i_private);
3315 static const struct file_operations state_fops = {
3316 .owner = THIS_MODULE,
3319 .llseek = seq_lseek,
3320 .release = single_release,
3324 * fifo_show - debugfs: show the fifo information
3325 * @seq: The seq_file to write data to.
3326 * @v: Unused parameter.
3328 * Show the FIFO information for the overall fifo and all the
3329 * periodic transmission FIFOs.
3331 static int fifo_show(struct seq_file *seq, void *v)
3333 struct s3c_hsotg *hsotg = seq->private;
3334 void __iomem *regs = hsotg->regs;
3338 seq_puts(seq, "Non-periodic FIFOs:\n");
3339 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ));
3341 val = readl(regs + GNPTXFSIZ);
3342 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3343 val >> GNPTXFSIZ_NPTxFDep_SHIFT,
3344 val & GNPTXFSIZ_NPTxFStAddr_MASK);
3346 seq_puts(seq, "\nPeriodic TXFIFOs:\n");
3348 for (idx = 1; idx <= 15; idx++) {
3349 val = readl(regs + DPTXFSIZn(idx));
3351 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3352 val >> DPTXFSIZn_DPTxFSize_SHIFT,
3353 val & DPTXFSIZn_DPTxFStAddr_MASK);
3359 static int fifo_open(struct inode *inode, struct file *file)
3361 return single_open(file, fifo_show, inode->i_private);
3364 static const struct file_operations fifo_fops = {
3365 .owner = THIS_MODULE,
3368 .llseek = seq_lseek,
3369 .release = single_release,
3373 static const char *decode_direction(int is_in)
3375 return is_in ? "in" : "out";
3379 * ep_show - debugfs: show the state of an endpoint.
3380 * @seq: The seq_file to write data to.
3381 * @v: Unused parameter.
3383 * This debugfs entry shows the state of the given endpoint (one is
3384 * registered for each available).
3386 static int ep_show(struct seq_file *seq, void *v)
3388 struct s3c_hsotg_ep *ep = seq->private;
3389 struct s3c_hsotg *hsotg = ep->parent;
3390 struct s3c_hsotg_req *req;
3391 void __iomem *regs = hsotg->regs;
3392 int index = ep->index;
3393 int show_limit = 15;
3394 unsigned long flags;
3396 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3397 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3399 /* first show the register state */
3401 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3402 readl(regs + DIEPCTL(index)),
3403 readl(regs + DOEPCTL(index)));
3405 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3406 readl(regs + DIEPDMA(index)),
3407 readl(regs + DOEPDMA(index)));
3409 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3410 readl(regs + DIEPINT(index)),
3411 readl(regs + DOEPINT(index)));
3413 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3414 readl(regs + DIEPTSIZ(index)),
3415 readl(regs + DOEPTSIZ(index)));
3417 seq_puts(seq, "\n");
3418 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3419 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3421 seq_printf(seq, "request list (%p,%p):\n",
3422 ep->queue.next, ep->queue.prev);
3424 spin_lock_irqsave(&hsotg->lock, flags);
3426 list_for_each_entry(req, &ep->queue, queue) {
3427 if (--show_limit < 0) {
3428 seq_puts(seq, "not showing more requests...\n");
3432 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3433 req == ep->req ? '*' : ' ',
3434 req, req->req.length, req->req.buf);
3435 seq_printf(seq, "%d done, res %d\n",
3436 req->req.actual, req->req.status);
3439 spin_unlock_irqrestore(&hsotg->lock, flags);
3444 static int ep_open(struct inode *inode, struct file *file)
3446 return single_open(file, ep_show, inode->i_private);
3449 static const struct file_operations ep_fops = {
3450 .owner = THIS_MODULE,
3453 .llseek = seq_lseek,
3454 .release = single_release,
3458 * s3c_hsotg_create_debug - create debugfs directory and files
3459 * @hsotg: The driver state
3461 * Create the debugfs files to allow the user to get information
3462 * about the state of the system. The directory name is created
3463 * with the same name as the device itself, in case we end up
3464 * with multiple blocks in future systems.
3466 static void s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3468 struct dentry *root;
3471 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3472 hsotg->debug_root = root;
3474 dev_err(hsotg->dev, "cannot create debug root\n");
3478 /* create general state file */
3480 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3481 hsotg, &state_fops);
3483 if (IS_ERR(hsotg->debug_file))
3484 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3486 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3489 if (IS_ERR(hsotg->debug_fifo))
3490 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3492 /* create one file for each endpoint */
3494 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3495 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3497 ep->debugfs = debugfs_create_file(ep->name, 0444,
3498 root, ep, &ep_fops);
3500 if (IS_ERR(ep->debugfs))
3501 dev_err(hsotg->dev, "failed to create %s debug file\n",
3507 * s3c_hsotg_delete_debug - cleanup debugfs entries
3508 * @hsotg: The driver state
3510 * Cleanup (remove) the debugfs files for use on module exit.
3512 static void s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3516 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3517 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3518 debugfs_remove(ep->debugfs);
3521 debugfs_remove(hsotg->debug_file);
3522 debugfs_remove(hsotg->debug_fifo);
3523 debugfs_remove(hsotg->debug_root);
3527 * s3c_hsotg_probe - probe function for hsotg driver
3528 * @pdev: The platform information for the driver
3531 static int s3c_hsotg_probe(struct platform_device *pdev)
3533 struct s3c_hsotg_plat *plat = dev_get_platdata(&pdev->dev);
3534 struct usb_phy *phy;
3535 struct device *dev = &pdev->dev;
3536 struct s3c_hsotg_ep *eps;
3537 struct s3c_hsotg *hsotg;
3538 struct resource *res;
3543 hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL);
3545 dev_err(dev, "cannot get memory\n");
3549 phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
3551 /* Fallback for pdata */
3552 plat = dev_get_platdata(&pdev->dev);
3554 dev_err(&pdev->dev, "no platform data or transceiver defined\n");
3555 return -EPROBE_DEFER;
3565 hsotg->clk = devm_clk_get(&pdev->dev, "otg");
3566 if (IS_ERR(hsotg->clk)) {
3567 dev_err(dev, "cannot get otg clock\n");
3568 return PTR_ERR(hsotg->clk);
3571 platform_set_drvdata(pdev, hsotg);
3573 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3575 hsotg->regs = devm_ioremap_resource(&pdev->dev, res);
3576 if (IS_ERR(hsotg->regs)) {
3577 ret = PTR_ERR(hsotg->regs);
3581 ret = platform_get_irq(pdev, 0);
3583 dev_err(dev, "cannot find IRQ\n");
3587 spin_lock_init(&hsotg->lock);
3591 ret = devm_request_irq(&pdev->dev, hsotg->irq, s3c_hsotg_irq, 0,
3592 dev_name(dev), hsotg);
3594 dev_err(dev, "cannot claim IRQ\n");
3598 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3600 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3601 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3602 hsotg->gadget.name = dev_name(dev);
3604 /* reset the system */
3606 clk_prepare_enable(hsotg->clk);
3610 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
3611 hsotg->supplies[i].supply = s3c_hsotg_supply_names[i];
3613 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies),
3616 dev_err(dev, "failed to request supplies: %d\n", ret);
3620 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3624 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
3628 /* usb phy enable */
3629 s3c_hsotg_phy_enable(hsotg);
3631 s3c_hsotg_corereset(hsotg);
3632 s3c_hsotg_init(hsotg);
3633 s3c_hsotg_hw_cfg(hsotg);
3635 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3637 if (hsotg->num_of_eps == 0) {
3638 dev_err(dev, "wrong number of EPs (zero)\n");
3643 eps = kcalloc(hsotg->num_of_eps + 1, sizeof(struct s3c_hsotg_ep),
3646 dev_err(dev, "cannot get memory\n");
3653 /* setup endpoint information */
3655 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3656 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3658 /* allocate EP0 request */
3660 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3662 if (!hsotg->ctrl_req) {
3663 dev_err(dev, "failed to allocate ctrl req\n");
3668 /* initialise the endpoints now the core has been initialised */
3669 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++)
3670 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3672 /* disable power and clock */
3674 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3677 dev_err(hsotg->dev, "failed to disable supplies: %d\n", ret);
3681 s3c_hsotg_phy_disable(hsotg);
3683 ret = usb_add_gadget_udc(&pdev->dev, &hsotg->gadget);
3687 s3c_hsotg_create_debug(hsotg);
3689 s3c_hsotg_dump(hsotg);
3696 s3c_hsotg_phy_disable(hsotg);
3698 clk_disable_unprepare(hsotg->clk);
3704 * s3c_hsotg_remove - remove function for hsotg driver
3705 * @pdev: The platform information for the driver
3707 static int s3c_hsotg_remove(struct platform_device *pdev)
3709 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3711 usb_del_gadget_udc(&hsotg->gadget);
3713 s3c_hsotg_delete_debug(hsotg);
3715 if (hsotg->driver) {
3716 /* should have been done already by driver model core */
3717 usb_gadget_unregister_driver(hsotg->driver);
3720 s3c_hsotg_phy_disable(hsotg);
3721 clk_disable_unprepare(hsotg->clk);
3727 #define s3c_hsotg_suspend NULL
3728 #define s3c_hsotg_resume NULL
3732 static const struct of_device_id s3c_hsotg_of_ids[] = {
3733 { .compatible = "samsung,s3c6400-hsotg", },
3736 MODULE_DEVICE_TABLE(of, s3c_hsotg_of_ids);
3739 static struct platform_driver s3c_hsotg_driver = {
3741 .name = "s3c-hsotg",
3742 .owner = THIS_MODULE,
3743 .of_match_table = of_match_ptr(s3c_hsotg_of_ids),
3745 .probe = s3c_hsotg_probe,
3746 .remove = s3c_hsotg_remove,
3747 .suspend = s3c_hsotg_suspend,
3748 .resume = s3c_hsotg_resume,
3751 module_platform_driver(s3c_hsotg_driver);
3753 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3754 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3755 MODULE_LICENSE("GPL");
3756 MODULE_ALIAS("platform:s3c-hsotg");