2 * linux/drivers/usb/gadget/s3c-hsotg.c
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Copyright 2008 Openmoko, Inc.
8 * Copyright 2008 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
10 * http://armlinux.simtec.co.uk/
12 * S3C USB2.0 High-speed / OtG driver
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/debugfs.h>
26 #include <linux/seq_file.h>
27 #include <linux/delay.h>
29 #include <linux/slab.h>
30 #include <linux/clk.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/of_platform.h>
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 #include <linux/usb/phy.h>
37 #include <linux/platform_data/s3c-hsotg.h>
41 #include "s3c-hsotg.h"
43 static const char * const s3c_hsotg_supply_names[] = {
44 "vusb_d", /* digital USB supply, 1.2V */
45 "vusb_a", /* analog USB supply, 1.1V */
51 * Unfortunately there seems to be a limit of the amount of data that can
52 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
53 * packets (which practically means 1 packet and 63 bytes of data) when the
56 * This means if we are wanting to move >127 bytes of data, we need to
57 * split the transactions up, but just doing one packet at a time does
58 * not work (this may be an implicit DATA0 PID on first packet of the
59 * transaction) and doing 2 packets is outside the controller's limits.
61 * If we try to lower the MPS size for EP0, then no transfers work properly
62 * for EP0, and the system will fail basic enumeration. As no cause for this
63 * has currently been found, we cannot support any large IN transfers for
66 #define EP0_MPS_LIMIT 64
72 * struct s3c_hsotg_ep - driver endpoint definition.
73 * @ep: The gadget layer representation of the endpoint.
74 * @name: The driver generated name for the endpoint.
75 * @queue: Queue of requests for this endpoint.
76 * @parent: Reference back to the parent device structure.
77 * @req: The current request that the endpoint is processing. This is
78 * used to indicate an request has been loaded onto the endpoint
79 * and has yet to be completed (maybe due to data move, or simply
80 * awaiting an ack from the core all the data has been completed).
81 * @debugfs: File entry for debugfs file for this endpoint.
82 * @lock: State lock to protect contents of endpoint.
83 * @dir_in: Set to true if this endpoint is of the IN direction, which
84 * means that it is sending data to the Host.
85 * @index: The index for the endpoint registers.
86 * @name: The name array passed to the USB core.
87 * @halted: Set if the endpoint has been halted.
88 * @periodic: Set if this is a periodic ep, such as Interrupt
89 * @sent_zlp: Set if we've sent a zero-length packet.
90 * @total_data: The total number of data bytes done.
91 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
92 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
93 * @last_load: The offset of data for the last start of request.
94 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
96 * This is the driver's state for each registered enpoint, allowing it
97 * to keep track of transactions that need doing. Each endpoint has a
98 * lock to protect the state, to try and avoid using an overall lock
99 * for the host controller as much as possible.
101 * For periodic IN endpoints, we have fifo_size and fifo_load to try
102 * and keep track of the amount of data in the periodic FIFO for each
103 * of these as we don't have a status register that tells us how much
104 * is in each of them. (note, this may actually be useless information
105 * as in shared-fifo mode periodic in acts like a single-frame packet
106 * buffer than a fifo)
108 struct s3c_hsotg_ep {
110 struct list_head queue;
111 struct s3c_hsotg *parent;
112 struct s3c_hsotg_req *req;
113 struct dentry *debugfs;
116 unsigned long total_data;
117 unsigned int size_loaded;
118 unsigned int last_load;
119 unsigned int fifo_load;
120 unsigned short fifo_size;
122 unsigned char dir_in;
125 unsigned int halted:1;
126 unsigned int periodic:1;
127 unsigned int sent_zlp:1;
133 * struct s3c_hsotg - driver state.
134 * @dev: The parent device supplied to the probe function
135 * @driver: USB gadget driver
136 * @phy: The otg phy transceiver structure for phy control.
137 * @plat: The platform specific configuration data. This can be removed once
138 * all SoCs support usb transceiver.
139 * @regs: The memory area mapped for accessing registers.
140 * @irq: The IRQ number we are using
141 * @supplies: Definition of USB power supplies
142 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
143 * @num_of_eps: Number of available EPs (excluding EP0)
144 * @debug_root: root directrory for debugfs.
145 * @debug_file: main status file for debugfs.
146 * @debug_fifo: FIFO status file for debugfs.
147 * @ep0_reply: Request used for ep0 reply.
148 * @ep0_buff: Buffer for EP0 reply data, if needed.
149 * @ctrl_buff: Buffer for EP0 control requests.
150 * @ctrl_req: Request for EP0 control packets.
151 * @setup: NAK management for EP0 SETUP
152 * @last_rst: Time of last reset
153 * @eps: The endpoints being supplied to the gadget framework
157 struct usb_gadget_driver *driver;
159 struct s3c_hsotg_plat *plat;
167 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)];
169 unsigned int dedicated_fifos:1;
170 unsigned char num_of_eps;
172 struct dentry *debug_root;
173 struct dentry *debug_file;
174 struct dentry *debug_fifo;
176 struct usb_request *ep0_reply;
177 struct usb_request *ctrl_req;
181 struct usb_gadget gadget;
183 unsigned long last_rst;
184 struct s3c_hsotg_ep *eps;
188 * struct s3c_hsotg_req - data transfer request
189 * @req: The USB gadget request
190 * @queue: The list of requests for the endpoint this is queued for.
191 * @in_progress: Has already had size/packets written to core
192 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
194 struct s3c_hsotg_req {
195 struct usb_request req;
196 struct list_head queue;
197 unsigned char in_progress;
198 unsigned char mapped;
201 /* conversion functions */
202 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
204 return container_of(req, struct s3c_hsotg_req, req);
207 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
209 return container_of(ep, struct s3c_hsotg_ep, ep);
212 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
214 return container_of(gadget, struct s3c_hsotg, gadget);
217 static inline void __orr32(void __iomem *ptr, u32 val)
219 writel(readl(ptr) | val, ptr);
222 static inline void __bic32(void __iomem *ptr, u32 val)
224 writel(readl(ptr) & ~val, ptr);
227 /* forward decleration of functions */
228 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
231 * using_dma - return the DMA status of the driver.
232 * @hsotg: The driver state.
234 * Return true if we're using DMA.
236 * Currently, we have the DMA support code worked into everywhere
237 * that needs it, but the AMBA DMA implementation in the hardware can
238 * only DMA from 32bit aligned addresses. This means that gadgets such
239 * as the CDC Ethernet cannot work as they often pass packets which are
242 * Unfortunately the choice to use DMA or not is global to the controller
243 * and seems to be only settable when the controller is being put through
244 * a core reset. This means we either need to fix the gadgets to take
245 * account of DMA alignment, or add bounce buffers (yuerk).
247 * Until this issue is sorted out, we always return 'false'.
249 static inline bool using_dma(struct s3c_hsotg *hsotg)
251 return false; /* support is not complete */
255 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
256 * @hsotg: The device state
257 * @ints: A bitmask of the interrupts to enable
259 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
261 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
264 new_gsintmsk = gsintmsk | ints;
266 if (new_gsintmsk != gsintmsk) {
267 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
268 writel(new_gsintmsk, hsotg->regs + GINTMSK);
273 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
274 * @hsotg: The device state
275 * @ints: A bitmask of the interrupts to enable
277 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
279 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
282 new_gsintmsk = gsintmsk & ~ints;
284 if (new_gsintmsk != gsintmsk)
285 writel(new_gsintmsk, hsotg->regs + GINTMSK);
289 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
290 * @hsotg: The device state
291 * @ep: The endpoint index
292 * @dir_in: True if direction is in.
293 * @en: The enable value, true to enable
295 * Set or clear the mask for an individual endpoint's interrupt
298 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
299 unsigned int ep, unsigned int dir_in,
309 local_irq_save(flags);
310 daint = readl(hsotg->regs + DAINTMSK);
315 writel(daint, hsotg->regs + DAINTMSK);
316 local_irq_restore(flags);
320 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
321 * @hsotg: The device instance.
323 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
331 /* set FIFO sizes to 2048/1024 */
333 writel(2048, hsotg->regs + GRXFSIZ);
334 writel(GNPTXFSIZ_NPTxFStAddr(2048) |
335 GNPTXFSIZ_NPTxFDep(1024),
336 hsotg->regs + GNPTXFSIZ);
339 * arange all the rest of the TX FIFOs, as some versions of this
340 * block have overlapping default addresses. This also ensures
341 * that if the settings have been changed, then they are set to
345 /* start at the end of the GNPTXFSIZ, rounded up */
350 * currently we allocate TX FIFOs for all possible endpoints,
351 * and assume that they are all the same size.
354 for (ep = 1; ep <= 15; ep++) {
356 val |= size << DPTXFSIZn_DPTxFSize_SHIFT;
359 writel(val, hsotg->regs + DPTXFSIZn(ep));
363 * according to p428 of the design guide, we need to ensure that
364 * all fifos are flushed before continuing
367 writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh |
368 GRSTCTL_RxFFlsh, hsotg->regs + GRSTCTL);
370 /* wait until the fifos are both flushed */
373 val = readl(hsotg->regs + GRSTCTL);
375 if ((val & (GRSTCTL_TxFFlsh | GRSTCTL_RxFFlsh)) == 0)
378 if (--timeout == 0) {
380 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
387 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
391 * @ep: USB endpoint to allocate request for.
392 * @flags: Allocation flags
394 * Allocate a new USB request structure appropriate for the specified endpoint
396 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
399 struct s3c_hsotg_req *req;
401 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
405 INIT_LIST_HEAD(&req->queue);
411 * is_ep_periodic - return true if the endpoint is in periodic mode.
412 * @hs_ep: The endpoint to query.
414 * Returns true if the endpoint is in periodic mode, meaning it is being
415 * used for an Interrupt or ISO transfer.
417 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
419 return hs_ep->periodic;
423 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
424 * @hsotg: The device state.
425 * @hs_ep: The endpoint for the request
426 * @hs_req: The request being processed.
428 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
429 * of a request to ensure the buffer is ready for access by the caller.
431 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
432 struct s3c_hsotg_ep *hs_ep,
433 struct s3c_hsotg_req *hs_req)
435 struct usb_request *req = &hs_req->req;
437 /* ignore this if we're not moving any data */
438 if (hs_req->req.length == 0)
441 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
445 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
446 * @hsotg: The controller state.
447 * @hs_ep: The endpoint we're going to write for.
448 * @hs_req: The request to write data for.
450 * This is called when the TxFIFO has some space in it to hold a new
451 * transmission and we have something to give it. The actual setup of
452 * the data size is done elsewhere, so all we have to do is to actually
455 * The return value is zero if there is more space (or nothing was done)
456 * otherwise -ENOSPC is returned if the FIFO space was used up.
458 * This routine is only needed for PIO
460 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
461 struct s3c_hsotg_ep *hs_ep,
462 struct s3c_hsotg_req *hs_req)
464 bool periodic = is_ep_periodic(hs_ep);
465 u32 gnptxsts = readl(hsotg->regs + GNPTXSTS);
466 int buf_pos = hs_req->req.actual;
467 int to_write = hs_ep->size_loaded;
472 to_write -= (buf_pos - hs_ep->last_load);
474 /* if there's nothing to write, get out early */
478 if (periodic && !hsotg->dedicated_fifos) {
479 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
484 * work out how much data was loaded so we can calculate
485 * how much data is left in the fifo.
488 size_left = DxEPTSIZ_XferSize_GET(epsize);
491 * if shared fifo, we cannot write anything until the
492 * previous data has been completely sent.
494 if (hs_ep->fifo_load != 0) {
495 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp);
499 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
501 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
503 /* how much of the data has moved */
504 size_done = hs_ep->size_loaded - size_left;
506 /* how much data is left in the fifo */
507 can_write = hs_ep->fifo_load - size_done;
508 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
509 __func__, can_write);
511 can_write = hs_ep->fifo_size - can_write;
512 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
513 __func__, can_write);
515 if (can_write <= 0) {
516 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp);
519 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
520 can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index));
525 if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
527 "%s: no queue slots available (0x%08x)\n",
530 s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTxFEmp);
534 can_write = GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
535 can_write *= 4; /* fifo size is in 32bit quantities. */
538 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
539 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
542 * limit to 512 bytes of data, it seems at least on the non-periodic
543 * FIFO, requests of >512 cause the endpoint to get stuck with a
544 * fragment of the end of the transfer in it.
550 * limit the write to one max-packet size worth of data, but allow
551 * the transfer to return that it did not run out of fifo space
554 if (to_write > hs_ep->ep.maxpacket) {
555 to_write = hs_ep->ep.maxpacket;
557 s3c_hsotg_en_gsint(hsotg,
558 periodic ? GINTSTS_PTxFEmp :
562 /* see if we can write data */
564 if (to_write > can_write) {
565 to_write = can_write;
566 pkt_round = to_write % hs_ep->ep.maxpacket;
569 * Round the write down to an
570 * exact number of packets.
572 * Note, we do not currently check to see if we can ever
573 * write a full packet or not to the FIFO.
577 to_write -= pkt_round;
580 * enable correct FIFO interrupt to alert us when there
584 s3c_hsotg_en_gsint(hsotg,
585 periodic ? GINTSTS_PTxFEmp :
589 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
590 to_write, hs_req->req.length, can_write, buf_pos);
595 hs_req->req.actual = buf_pos + to_write;
596 hs_ep->total_data += to_write;
599 hs_ep->fifo_load += to_write;
601 to_write = DIV_ROUND_UP(to_write, 4);
602 data = hs_req->req.buf + buf_pos;
604 writesl(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
606 return (to_write >= can_write) ? -ENOSPC : 0;
610 * get_ep_limit - get the maximum data legnth for this endpoint
611 * @hs_ep: The endpoint
613 * Return the maximum data that can be queued in one go on a given endpoint
614 * so that transfers that are too long can be split.
616 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
618 int index = hs_ep->index;
623 maxsize = DxEPTSIZ_XferSize_LIMIT + 1;
624 maxpkt = DxEPTSIZ_PktCnt_LIMIT + 1;
628 maxpkt = DIEPTSIZ0_PktCnt_LIMIT + 1;
633 /* we made the constant loading easier above by using +1 */
638 * constrain by packet count if maxpkts*pktsize is greater
639 * than the length register size.
642 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
643 maxsize = maxpkt * hs_ep->ep.maxpacket;
649 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
650 * @hsotg: The controller state.
651 * @hs_ep: The endpoint to process a request for
652 * @hs_req: The request to start.
653 * @continuing: True if we are doing more for the current request.
655 * Start the given request running by setting the endpoint registers
656 * appropriately, and writing any data to the FIFOs.
658 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
659 struct s3c_hsotg_ep *hs_ep,
660 struct s3c_hsotg_req *hs_req,
663 struct usb_request *ureq = &hs_req->req;
664 int index = hs_ep->index;
665 int dir_in = hs_ep->dir_in;
675 if (hs_ep->req && !continuing) {
676 dev_err(hsotg->dev, "%s: active request\n", __func__);
679 } else if (hs_ep->req != hs_req && continuing) {
681 "%s: continue different req\n", __func__);
687 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
688 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
690 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
691 __func__, readl(hsotg->regs + epctrl_reg), index,
692 hs_ep->dir_in ? "in" : "out");
694 /* If endpoint is stalled, we will restart request later */
695 ctrl = readl(hsotg->regs + epctrl_reg);
697 if (ctrl & DxEPCTL_Stall) {
698 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
702 length = ureq->length - ureq->actual;
703 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
704 ureq->length, ureq->actual);
707 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
708 ureq->buf, length, ureq->dma,
709 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
711 maxreq = get_ep_limit(hs_ep);
712 if (length > maxreq) {
713 int round = maxreq % hs_ep->ep.maxpacket;
715 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
716 __func__, length, maxreq, round);
718 /* round down to multiple of packets */
726 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
728 packets = 1; /* send one packet if length is zero. */
730 if (dir_in && index != 0)
731 epsize = DxEPTSIZ_MC(1);
735 if (index != 0 && ureq->zero) {
737 * test for the packets being exactly right for the
741 if (length == (packets * hs_ep->ep.maxpacket))
745 epsize |= DxEPTSIZ_PktCnt(packets);
746 epsize |= DxEPTSIZ_XferSize(length);
748 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
749 __func__, packets, length, ureq->length, epsize, epsize_reg);
751 /* store the request as the current one we're doing */
754 /* write size / packets */
755 writel(epsize, hsotg->regs + epsize_reg);
757 if (using_dma(hsotg) && !continuing) {
758 unsigned int dma_reg;
761 * write DMA address to control register, buffer already
762 * synced by s3c_hsotg_ep_queue().
765 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
766 writel(ureq->dma, hsotg->regs + dma_reg);
768 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
769 __func__, ureq->dma, dma_reg);
772 ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */
773 ctrl |= DxEPCTL_USBActEp;
775 dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup);
777 /* For Setup request do not clear NAK */
778 if (hsotg->setup && index == 0)
781 ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */
784 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
785 writel(ctrl, hsotg->regs + epctrl_reg);
788 * set these, it seems that DMA support increments past the end
789 * of the packet buffer so we need to calculate the length from
792 hs_ep->size_loaded = length;
793 hs_ep->last_load = ureq->actual;
795 if (dir_in && !using_dma(hsotg)) {
796 /* set these anyway, we may need them for non-periodic in */
797 hs_ep->fifo_load = 0;
799 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
803 * clear the INTknTXFEmpMsk when we start request, more as a aide
804 * to debugging to see what is going on.
807 writel(DIEPMSK_INTknTXFEmpMsk,
808 hsotg->regs + DIEPINT(index));
811 * Note, trying to clear the NAK here causes problems with transmit
812 * on the S3C6400 ending up with the TXFIFO becoming full.
815 /* check ep is enabled */
816 if (!(readl(hsotg->regs + epctrl_reg) & DxEPCTL_EPEna))
818 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
819 index, readl(hsotg->regs + epctrl_reg));
821 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
822 __func__, readl(hsotg->regs + epctrl_reg));
826 * s3c_hsotg_map_dma - map the DMA memory being used for the request
827 * @hsotg: The device state.
828 * @hs_ep: The endpoint the request is on.
829 * @req: The request being processed.
831 * We've been asked to queue a request, so ensure that the memory buffer
832 * is correctly setup for DMA. If we've been passed an extant DMA address
833 * then ensure the buffer has been synced to memory. If our buffer has no
834 * DMA memory, then we map the memory and mark our request to allow us to
835 * cleanup on completion.
837 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
838 struct s3c_hsotg_ep *hs_ep,
839 struct usb_request *req)
841 struct s3c_hsotg_req *hs_req = our_req(req);
844 /* if the length is zero, ignore the DMA data */
845 if (hs_req->req.length == 0)
848 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
855 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
856 __func__, req->buf, req->length);
861 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
864 struct s3c_hsotg_req *hs_req = our_req(req);
865 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
866 struct s3c_hsotg *hs = hs_ep->parent;
869 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
870 ep->name, req, req->length, req->buf, req->no_interrupt,
871 req->zero, req->short_not_ok);
873 /* initialise status of the request */
874 INIT_LIST_HEAD(&hs_req->queue);
876 req->status = -EINPROGRESS;
878 /* if we're using DMA, sync the buffers as necessary */
880 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
885 first = list_empty(&hs_ep->queue);
886 list_add_tail(&hs_req->queue, &hs_ep->queue);
889 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
894 static int s3c_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
897 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
898 struct s3c_hsotg *hs = hs_ep->parent;
899 unsigned long flags = 0;
902 spin_lock_irqsave(&hs->lock, flags);
903 ret = s3c_hsotg_ep_queue(ep, req, gfp_flags);
904 spin_unlock_irqrestore(&hs->lock, flags);
909 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
910 struct usb_request *req)
912 struct s3c_hsotg_req *hs_req = our_req(req);
918 * s3c_hsotg_complete_oursetup - setup completion callback
919 * @ep: The endpoint the request was on.
920 * @req: The request completed.
922 * Called on completion of any requests the driver itself
923 * submitted that need cleaning up.
925 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
926 struct usb_request *req)
928 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
929 struct s3c_hsotg *hsotg = hs_ep->parent;
931 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
933 s3c_hsotg_ep_free_request(ep, req);
937 * ep_from_windex - convert control wIndex value to endpoint
938 * @hsotg: The driver state.
939 * @windex: The control request wIndex field (in host order).
941 * Convert the given wIndex into a pointer to an driver endpoint
942 * structure, or return NULL if it is not a valid endpoint.
944 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
947 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
948 int dir = (windex & USB_DIR_IN) ? 1 : 0;
949 int idx = windex & 0x7F;
954 if (idx > hsotg->num_of_eps)
957 if (idx && ep->dir_in != dir)
964 * s3c_hsotg_send_reply - send reply to control request
965 * @hsotg: The device state
967 * @buff: Buffer for request
968 * @length: Length of reply.
970 * Create a request and queue it on the given endpoint. This is useful as
971 * an internal method of sending replies to certain control requests, etc.
973 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
974 struct s3c_hsotg_ep *ep,
978 struct usb_request *req;
981 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
983 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
984 hsotg->ep0_reply = req;
986 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
990 req->buf = hsotg->ep0_buff;
991 req->length = length;
992 req->zero = 1; /* always do zero-length final transfer */
993 req->complete = s3c_hsotg_complete_oursetup;
996 memcpy(req->buf, buff, length);
1000 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1002 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1010 * s3c_hsotg_process_req_status - process request GET_STATUS
1011 * @hsotg: The device state
1012 * @ctrl: USB control request
1014 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
1015 struct usb_ctrlrequest *ctrl)
1017 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1018 struct s3c_hsotg_ep *ep;
1022 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1025 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1029 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1030 case USB_RECIP_DEVICE:
1031 reply = cpu_to_le16(0); /* bit 0 => self powered,
1032 * bit 1 => remote wakeup */
1035 case USB_RECIP_INTERFACE:
1036 /* currently, the data result should be zero */
1037 reply = cpu_to_le16(0);
1040 case USB_RECIP_ENDPOINT:
1041 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1045 reply = cpu_to_le16(ep->halted ? 1 : 0);
1052 if (le16_to_cpu(ctrl->wLength) != 2)
1055 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
1057 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1064 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1067 * get_ep_head - return the first request on the endpoint
1068 * @hs_ep: The controller endpoint to get
1070 * Get the first request on the endpoint.
1072 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1074 if (list_empty(&hs_ep->queue))
1077 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1081 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1082 * @hsotg: The device state
1083 * @ctrl: USB control request
1085 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
1086 struct usb_ctrlrequest *ctrl)
1088 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1089 struct s3c_hsotg_req *hs_req;
1091 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1092 struct s3c_hsotg_ep *ep;
1095 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1096 __func__, set ? "SET" : "CLEAR");
1098 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
1099 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1101 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1102 __func__, le16_to_cpu(ctrl->wIndex));
1106 switch (le16_to_cpu(ctrl->wValue)) {
1107 case USB_ENDPOINT_HALT:
1108 s3c_hsotg_ep_sethalt(&ep->ep, set);
1110 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1113 "%s: failed to send reply\n", __func__);
1119 * If we have request in progress,
1125 list_del_init(&hs_req->queue);
1126 hs_req->req.complete(&ep->ep,
1130 /* If we have pending request, then start it */
1131 restart = !list_empty(&ep->queue);
1133 hs_req = get_ep_head(ep);
1134 s3c_hsotg_start_req(hsotg, ep,
1145 return -ENOENT; /* currently only deal with endpoint */
1151 * s3c_hsotg_process_control - process a control request
1152 * @hsotg: The device state
1153 * @ctrl: The control request received
1155 * The controller has received the SETUP phase of a control request, and
1156 * needs to work out what to do next (and whether to pass it on to the
1159 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1160 struct usb_ctrlrequest *ctrl)
1162 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1168 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1169 ctrl->bRequest, ctrl->bRequestType,
1170 ctrl->wValue, ctrl->wLength);
1173 * record the direction of the request, for later use when enquing
1177 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1178 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1181 * if we've no data with this request, then the last part of the
1182 * transaction is going to implicitly be IN.
1184 if (ctrl->wLength == 0)
1187 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1188 switch (ctrl->bRequest) {
1189 case USB_REQ_SET_ADDRESS:
1190 dcfg = readl(hsotg->regs + DCFG);
1191 dcfg &= ~DCFG_DevAddr_MASK;
1192 dcfg |= ctrl->wValue << DCFG_DevAddr_SHIFT;
1193 writel(dcfg, hsotg->regs + DCFG);
1195 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1197 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1200 case USB_REQ_GET_STATUS:
1201 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1204 case USB_REQ_CLEAR_FEATURE:
1205 case USB_REQ_SET_FEATURE:
1206 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1211 /* as a fallback, try delivering it to the driver to deal with */
1213 if (ret == 0 && hsotg->driver) {
1214 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1216 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1220 * the request is either unhandlable, or is not formatted correctly
1221 * so respond with a STALL for the status stage to indicate failure.
1228 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1229 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1232 * DxEPCTL_Stall will be cleared by EP once it has
1233 * taken effect, so no need to clear later.
1236 ctrl = readl(hsotg->regs + reg);
1237 ctrl |= DxEPCTL_Stall;
1238 ctrl |= DxEPCTL_CNAK;
1239 writel(ctrl, hsotg->regs + reg);
1242 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1243 ctrl, reg, readl(hsotg->regs + reg));
1246 * don't believe we need to anything more to get the EP
1247 * to reply with a STALL packet
1252 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1255 * s3c_hsotg_complete_setup - completion of a setup transfer
1256 * @ep: The endpoint the request was on.
1257 * @req: The request completed.
1259 * Called on completion of any requests the driver itself submitted for
1262 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1263 struct usb_request *req)
1265 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1266 struct s3c_hsotg *hsotg = hs_ep->parent;
1268 if (req->status < 0) {
1269 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1273 if (req->actual == 0)
1274 s3c_hsotg_enqueue_setup(hsotg);
1276 s3c_hsotg_process_control(hsotg, req->buf);
1280 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1281 * @hsotg: The device state.
1283 * Enqueue a request on EP0 if necessary to received any SETUP packets
1284 * received from the host.
1286 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1288 struct usb_request *req = hsotg->ctrl_req;
1289 struct s3c_hsotg_req *hs_req = our_req(req);
1292 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1296 req->buf = hsotg->ctrl_buff;
1297 req->complete = s3c_hsotg_complete_setup;
1299 if (!list_empty(&hs_req->queue)) {
1300 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1304 hsotg->eps[0].dir_in = 0;
1306 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1308 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1310 * Don't think there's much we can do other than watch the
1317 * s3c_hsotg_complete_request - complete a request given to us
1318 * @hsotg: The device state.
1319 * @hs_ep: The endpoint the request was on.
1320 * @hs_req: The request to complete.
1321 * @result: The result code (0 => Ok, otherwise errno)
1323 * The given request has finished, so call the necessary completion
1324 * if it has one and then look to see if we can start a new request
1327 * Note, expects the ep to already be locked as appropriate.
1329 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1330 struct s3c_hsotg_ep *hs_ep,
1331 struct s3c_hsotg_req *hs_req,
1337 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1341 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1342 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1345 * only replace the status if we've not already set an error
1346 * from a previous transaction
1349 if (hs_req->req.status == -EINPROGRESS)
1350 hs_req->req.status = result;
1353 list_del_init(&hs_req->queue);
1355 if (using_dma(hsotg))
1356 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1359 * call the complete request with the locks off, just in case the
1360 * request tries to queue more work for this endpoint.
1363 if (hs_req->req.complete) {
1364 spin_unlock(&hsotg->lock);
1365 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1366 spin_lock(&hsotg->lock);
1370 * Look to see if there is anything else to do. Note, the completion
1371 * of the previous request may have caused a new request to be started
1372 * so be careful when doing this.
1375 if (!hs_ep->req && result >= 0) {
1376 restart = !list_empty(&hs_ep->queue);
1378 hs_req = get_ep_head(hs_ep);
1379 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1385 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1386 * @hsotg: The device state.
1387 * @ep_idx: The endpoint index for the data
1388 * @size: The size of data in the fifo, in bytes
1390 * The FIFO status shows there is data to read from the FIFO for a given
1391 * endpoint, so sort out whether we need to read the data into a request
1392 * that has been made for that endpoint.
1394 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1396 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1397 struct s3c_hsotg_req *hs_req = hs_ep->req;
1398 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1405 u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
1408 dev_warn(hsotg->dev,
1409 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1410 __func__, size, ep_idx, epctl);
1412 /* dump the data from the FIFO, we've nothing we can do */
1413 for (ptr = 0; ptr < size; ptr += 4)
1420 read_ptr = hs_req->req.actual;
1421 max_req = hs_req->req.length - read_ptr;
1423 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1424 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1426 if (to_read > max_req) {
1428 * more data appeared than we where willing
1429 * to deal with in this request.
1432 /* currently we don't deal this */
1436 hs_ep->total_data += to_read;
1437 hs_req->req.actual += to_read;
1438 to_read = DIV_ROUND_UP(to_read, 4);
1441 * note, we might over-write the buffer end by 3 bytes depending on
1442 * alignment of the data.
1444 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1448 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1449 * @hsotg: The device instance
1450 * @req: The request currently on this endpoint
1452 * Generate a zero-length IN packet request for terminating a SETUP
1455 * Note, since we don't write any data to the TxFIFO, then it is
1456 * currently believed that we do not need to wait for any space in
1459 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1460 struct s3c_hsotg_req *req)
1465 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1469 if (req->req.length == 0) {
1470 hsotg->eps[0].sent_zlp = 1;
1471 s3c_hsotg_enqueue_setup(hsotg);
1475 hsotg->eps[0].dir_in = 1;
1476 hsotg->eps[0].sent_zlp = 1;
1478 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1480 /* issue a zero-sized packet to terminate this */
1481 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
1482 DxEPTSIZ_XferSize(0), hsotg->regs + DIEPTSIZ(0));
1484 ctrl = readl(hsotg->regs + DIEPCTL0);
1485 ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */
1486 ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */
1487 ctrl |= DxEPCTL_USBActEp;
1488 writel(ctrl, hsotg->regs + DIEPCTL0);
1492 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1493 * @hsotg: The device instance
1494 * @epnum: The endpoint received from
1495 * @was_setup: Set if processing a SetupDone event.
1497 * The RXFIFO has delivered an OutDone event, which means that the data
1498 * transfer for an OUT endpoint has been completed, either by a short
1499 * packet or by the finish of a transfer.
1501 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1502 int epnum, bool was_setup)
1504 u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
1505 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1506 struct s3c_hsotg_req *hs_req = hs_ep->req;
1507 struct usb_request *req = &hs_req->req;
1508 unsigned size_left = DxEPTSIZ_XferSize_GET(epsize);
1512 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1516 if (using_dma(hsotg)) {
1520 * Calculate the size of the transfer by checking how much
1521 * is left in the endpoint size register and then working it
1522 * out from the amount we loaded for the transfer.
1524 * We need to do this as DMA pointers are always 32bit aligned
1525 * so may overshoot/undershoot the transfer.
1528 size_done = hs_ep->size_loaded - size_left;
1529 size_done += hs_ep->last_load;
1531 req->actual = size_done;
1534 /* if there is more request to do, schedule new transfer */
1535 if (req->actual < req->length && size_left == 0) {
1536 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1538 } else if (epnum == 0) {
1540 * After was_setup = 1 =>
1541 * set CNAK for non Setup requests
1543 hsotg->setup = was_setup ? 0 : 1;
1546 if (req->actual < req->length && req->short_not_ok) {
1547 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1548 __func__, req->actual, req->length);
1551 * todo - what should we return here? there's no one else
1552 * even bothering to check the status.
1558 * Condition req->complete != s3c_hsotg_complete_setup says:
1559 * send ZLP when we have an asynchronous request from gadget
1561 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1562 s3c_hsotg_send_zlp(hsotg, hs_req);
1565 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1569 * s3c_hsotg_read_frameno - read current frame number
1570 * @hsotg: The device instance
1572 * Return the current frame number
1574 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1578 dsts = readl(hsotg->regs + DSTS);
1579 dsts &= DSTS_SOFFN_MASK;
1580 dsts >>= DSTS_SOFFN_SHIFT;
1586 * s3c_hsotg_handle_rx - RX FIFO has data
1587 * @hsotg: The device instance
1589 * The IRQ handler has detected that the RX FIFO has some data in it
1590 * that requires processing, so find out what is in there and do the
1593 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1594 * chunks, so if you have x packets received on an endpoint you'll get x
1595 * FIFO events delivered, each with a packet's worth of data in it.
1597 * When using DMA, we should not be processing events from the RXFIFO
1598 * as the actual data should be sent to the memory directly and we turn
1599 * on the completion interrupts to get notifications of transfer completion.
1601 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1603 u32 grxstsr = readl(hsotg->regs + GRXSTSP);
1604 u32 epnum, status, size;
1606 WARN_ON(using_dma(hsotg));
1608 epnum = grxstsr & GRXSTS_EPNum_MASK;
1609 status = grxstsr & GRXSTS_PktSts_MASK;
1611 size = grxstsr & GRXSTS_ByteCnt_MASK;
1612 size >>= GRXSTS_ByteCnt_SHIFT;
1615 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1616 __func__, grxstsr, size, epnum);
1618 #define __status(x) ((x) >> GRXSTS_PktSts_SHIFT)
1620 switch (status >> GRXSTS_PktSts_SHIFT) {
1621 case __status(GRXSTS_PktSts_GlobalOutNAK):
1622 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1625 case __status(GRXSTS_PktSts_OutDone):
1626 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1627 s3c_hsotg_read_frameno(hsotg));
1629 if (!using_dma(hsotg))
1630 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1633 case __status(GRXSTS_PktSts_SetupDone):
1635 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1636 s3c_hsotg_read_frameno(hsotg),
1637 readl(hsotg->regs + DOEPCTL(0)));
1639 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1642 case __status(GRXSTS_PktSts_OutRX):
1643 s3c_hsotg_rx_data(hsotg, epnum, size);
1646 case __status(GRXSTS_PktSts_SetupRX):
1648 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1649 s3c_hsotg_read_frameno(hsotg),
1650 readl(hsotg->regs + DOEPCTL(0)));
1652 s3c_hsotg_rx_data(hsotg, epnum, size);
1656 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1659 s3c_hsotg_dump(hsotg);
1665 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1666 * @mps: The maximum packet size in bytes.
1668 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1672 return D0EPCTL_MPS_64;
1674 return D0EPCTL_MPS_32;
1676 return D0EPCTL_MPS_16;
1678 return D0EPCTL_MPS_8;
1681 /* bad max packet size, warn and return invalid result */
1687 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1688 * @hsotg: The driver state.
1689 * @ep: The index number of the endpoint
1690 * @mps: The maximum packet size in bytes
1692 * Configure the maximum packet size for the given endpoint, updating
1693 * the hardware control registers to reflect this.
1695 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1696 unsigned int ep, unsigned int mps)
1698 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1699 void __iomem *regs = hsotg->regs;
1704 /* EP0 is a special case */
1705 mpsval = s3c_hsotg_ep0_mps(mps);
1709 if (mps >= DxEPCTL_MPS_LIMIT+1)
1715 hs_ep->ep.maxpacket = mps;
1718 * update both the in and out endpoint controldir_ registers, even
1719 * if one of the directions may not be in use.
1722 reg = readl(regs + DIEPCTL(ep));
1723 reg &= ~DxEPCTL_MPS_MASK;
1725 writel(reg, regs + DIEPCTL(ep));
1728 reg = readl(regs + DOEPCTL(ep));
1729 reg &= ~DxEPCTL_MPS_MASK;
1731 writel(reg, regs + DOEPCTL(ep));
1737 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1741 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1742 * @hsotg: The driver state
1743 * @idx: The index for the endpoint (0..15)
1745 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx)
1750 writel(GRSTCTL_TxFNum(idx) | GRSTCTL_TxFFlsh,
1751 hsotg->regs + GRSTCTL);
1753 /* wait until the fifo is flushed */
1757 val = readl(hsotg->regs + GRSTCTL);
1759 if ((val & (GRSTCTL_TxFFlsh)) == 0)
1762 if (--timeout == 0) {
1764 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1773 * s3c_hsotg_trytx - check to see if anything needs transmitting
1774 * @hsotg: The driver state
1775 * @hs_ep: The driver endpoint to check.
1777 * Check to see if there is a request that has data to send, and if so
1778 * make an attempt to write data into the FIFO.
1780 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1781 struct s3c_hsotg_ep *hs_ep)
1783 struct s3c_hsotg_req *hs_req = hs_ep->req;
1785 if (!hs_ep->dir_in || !hs_req)
1788 if (hs_req->req.actual < hs_req->req.length) {
1789 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1791 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1798 * s3c_hsotg_complete_in - complete IN transfer
1799 * @hsotg: The device state.
1800 * @hs_ep: The endpoint that has just completed.
1802 * An IN transfer has been completed, update the transfer's state and then
1803 * call the relevant completion routines.
1805 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1806 struct s3c_hsotg_ep *hs_ep)
1808 struct s3c_hsotg_req *hs_req = hs_ep->req;
1809 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1810 int size_left, size_done;
1813 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1817 /* Finish ZLP handling for IN EP0 transactions */
1818 if (hsotg->eps[0].sent_zlp) {
1819 dev_dbg(hsotg->dev, "zlp packet received\n");
1820 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1825 * Calculate the size of the transfer by checking how much is left
1826 * in the endpoint size register and then working it out from
1827 * the amount we loaded for the transfer.
1829 * We do this even for DMA, as the transfer may have incremented
1830 * past the end of the buffer (DMA transfers are always 32bit
1834 size_left = DxEPTSIZ_XferSize_GET(epsize);
1836 size_done = hs_ep->size_loaded - size_left;
1837 size_done += hs_ep->last_load;
1839 if (hs_req->req.actual != size_done)
1840 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1841 __func__, hs_req->req.actual, size_done);
1843 hs_req->req.actual = size_done;
1844 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1845 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1848 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1849 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1850 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1851 * inform the host that no more data is available.
1852 * The state of req.zero member is checked to be sure that the value to
1853 * send is smaller than wValue expected from host.
1854 * Check req.length to NOT send another ZLP when the current one is
1855 * under completion (the one for which this completion has been called).
1857 if (hs_req->req.length && hs_ep->index == 0 && hs_req->req.zero &&
1858 hs_req->req.length == hs_req->req.actual &&
1859 !(hs_req->req.length % hs_ep->ep.maxpacket)) {
1861 dev_dbg(hsotg->dev, "ep0 zlp IN packet sent\n");
1862 s3c_hsotg_send_zlp(hsotg, hs_req);
1867 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1868 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1869 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1871 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1875 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1876 * @hsotg: The driver state
1877 * @idx: The index for the endpoint (0..15)
1878 * @dir_in: Set if this is an IN endpoint
1880 * Process and clear any interrupt pending for an individual endpoint
1882 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1885 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1886 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1887 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1888 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1891 ints = readl(hsotg->regs + epint_reg);
1893 /* Clear endpoint interrupts */
1894 writel(ints, hsotg->regs + epint_reg);
1896 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1897 __func__, idx, dir_in ? "in" : "out", ints);
1899 if (ints & DxEPINT_XferCompl) {
1901 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1902 __func__, readl(hsotg->regs + epctl_reg),
1903 readl(hsotg->regs + epsiz_reg));
1906 * we get OutDone from the FIFO, so we only need to look
1907 * at completing IN requests here
1910 s3c_hsotg_complete_in(hsotg, hs_ep);
1912 if (idx == 0 && !hs_ep->req)
1913 s3c_hsotg_enqueue_setup(hsotg);
1914 } else if (using_dma(hsotg)) {
1916 * We're using DMA, we need to fire an OutDone here
1917 * as we ignore the RXFIFO.
1920 s3c_hsotg_handle_outdone(hsotg, idx, false);
1924 if (ints & DxEPINT_EPDisbld) {
1925 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1928 int epctl = readl(hsotg->regs + epctl_reg);
1930 s3c_hsotg_txfifo_flush(hsotg, idx);
1932 if ((epctl & DxEPCTL_Stall) &&
1933 (epctl & DxEPCTL_EPType_Bulk)) {
1934 int dctl = readl(hsotg->regs + DCTL);
1936 dctl |= DCTL_CGNPInNAK;
1937 writel(dctl, hsotg->regs + DCTL);
1942 if (ints & DxEPINT_AHBErr)
1943 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1945 if (ints & DxEPINT_Setup) { /* Setup or Timeout */
1946 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1948 if (using_dma(hsotg) && idx == 0) {
1950 * this is the notification we've received a
1951 * setup packet. In non-DMA mode we'd get this
1952 * from the RXFIFO, instead we need to process
1959 s3c_hsotg_handle_outdone(hsotg, 0, true);
1963 if (ints & DxEPINT_Back2BackSetup)
1964 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1967 /* not sure if this is important, but we'll clear it anyway */
1968 if (ints & DIEPMSK_INTknTXFEmpMsk) {
1969 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1973 /* this probably means something bad is happening */
1974 if (ints & DIEPMSK_INTknEPMisMsk) {
1975 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1979 /* FIFO has space or is empty (see GAHBCFG) */
1980 if (hsotg->dedicated_fifos &&
1981 ints & DIEPMSK_TxFIFOEmpty) {
1982 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
1984 if (!using_dma(hsotg))
1985 s3c_hsotg_trytx(hsotg, hs_ep);
1991 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1992 * @hsotg: The device state.
1994 * Handle updating the device settings after the enumeration phase has
1997 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1999 u32 dsts = readl(hsotg->regs + DSTS);
2000 int ep0_mps = 0, ep_mps;
2003 * This should signal the finish of the enumeration phase
2004 * of the USB handshaking, so we should now know what rate
2008 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2011 * note, since we're limited by the size of transfer on EP0, and
2012 * it seems IN transfers must be a even number of packets we do
2013 * not advertise a 64byte MPS on EP0.
2016 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2017 switch (dsts & DSTS_EnumSpd_MASK) {
2018 case DSTS_EnumSpd_FS:
2019 case DSTS_EnumSpd_FS48:
2020 hsotg->gadget.speed = USB_SPEED_FULL;
2021 ep0_mps = EP0_MPS_LIMIT;
2025 case DSTS_EnumSpd_HS:
2026 hsotg->gadget.speed = USB_SPEED_HIGH;
2027 ep0_mps = EP0_MPS_LIMIT;
2031 case DSTS_EnumSpd_LS:
2032 hsotg->gadget.speed = USB_SPEED_LOW;
2034 * note, we don't actually support LS in this driver at the
2035 * moment, and the documentation seems to imply that it isn't
2036 * supported by the PHYs on some of the devices.
2040 dev_info(hsotg->dev, "new device is %s\n",
2041 usb_speed_string(hsotg->gadget.speed));
2044 * we should now know the maximum packet size for an
2045 * endpoint, so set the endpoints to a default value.
2050 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
2051 for (i = 1; i < hsotg->num_of_eps; i++)
2052 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
2055 /* ensure after enumeration our EP0 is active */
2057 s3c_hsotg_enqueue_setup(hsotg);
2059 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2060 readl(hsotg->regs + DIEPCTL0),
2061 readl(hsotg->regs + DOEPCTL0));
2065 * kill_all_requests - remove all requests from the endpoint's queue
2066 * @hsotg: The device state.
2067 * @ep: The endpoint the requests may be on.
2068 * @result: The result code to use.
2069 * @force: Force removal of any current requests
2071 * Go through the requests on the given endpoint and mark them
2072 * completed with the given result code.
2074 static void kill_all_requests(struct s3c_hsotg *hsotg,
2075 struct s3c_hsotg_ep *ep,
2076 int result, bool force)
2078 struct s3c_hsotg_req *req, *treq;
2080 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2082 * currently, we can't do much about an already
2083 * running request on an in endpoint
2086 if (ep->req == req && ep->dir_in && !force)
2089 s3c_hsotg_complete_request(hsotg, ep, req,
2094 #define call_gadget(_hs, _entry) \
2095 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
2096 (_hs)->driver && (_hs)->driver->_entry) { \
2097 spin_unlock(&_hs->lock); \
2098 (_hs)->driver->_entry(&(_hs)->gadget); \
2099 spin_lock(&_hs->lock); \
2103 * s3c_hsotg_disconnect - disconnect service
2104 * @hsotg: The device state.
2106 * The device has been disconnected. Remove all current
2107 * transactions and signal the gadget driver that this
2110 static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg)
2114 for (ep = 0; ep < hsotg->num_of_eps; ep++)
2115 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
2117 call_gadget(hsotg, disconnect);
2121 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2122 * @hsotg: The device state:
2123 * @periodic: True if this is a periodic FIFO interrupt
2125 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2127 struct s3c_hsotg_ep *ep;
2130 /* look through for any more data to transmit */
2132 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2133 ep = &hsotg->eps[epno];
2138 if ((periodic && !ep->periodic) ||
2139 (!periodic && ep->periodic))
2142 ret = s3c_hsotg_trytx(hsotg, ep);
2148 /* IRQ flags which will trigger a retry around the IRQ loop */
2149 #define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \
2154 * s3c_hsotg_corereset - issue softreset to the core
2155 * @hsotg: The device state
2157 * Issue a soft reset to the core, and await the core finishing it.
2159 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2164 dev_dbg(hsotg->dev, "resetting core\n");
2166 /* issue soft reset */
2167 writel(GRSTCTL_CSftRst, hsotg->regs + GRSTCTL);
2171 grstctl = readl(hsotg->regs + GRSTCTL);
2172 } while ((grstctl & GRSTCTL_CSftRst) && timeout-- > 0);
2174 if (grstctl & GRSTCTL_CSftRst) {
2175 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2182 u32 grstctl = readl(hsotg->regs + GRSTCTL);
2184 if (timeout-- < 0) {
2185 dev_info(hsotg->dev,
2186 "%s: reset failed, GRSTCTL=%08x\n",
2191 if (!(grstctl & GRSTCTL_AHBIdle))
2194 break; /* reset done */
2197 dev_dbg(hsotg->dev, "reset successful\n");
2202 * s3c_hsotg_core_init - issue softreset to the core
2203 * @hsotg: The device state
2205 * Issue a soft reset to the core, and await the core finishing it.
2207 static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2209 s3c_hsotg_corereset(hsotg);
2212 * we must now enable ep0 ready for host detection and then
2213 * set configuration.
2216 /* set the PLL on, remove the HNP/SRP and set the PHY */
2217 writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) |
2218 (0x5 << 10), hsotg->regs + GUSBCFG);
2220 s3c_hsotg_init_fifo(hsotg);
2222 __orr32(hsotg->regs + DCTL, DCTL_SftDiscon);
2224 writel(1 << 18 | DCFG_DevSpd_HS, hsotg->regs + DCFG);
2226 /* Clear any pending OTG interrupts */
2227 writel(0xffffffff, hsotg->regs + GOTGINT);
2229 /* Clear any pending interrupts */
2230 writel(0xffffffff, hsotg->regs + GINTSTS);
2232 writel(GINTSTS_ErlySusp | GINTSTS_SessReqInt |
2233 GINTSTS_GOUTNakEff | GINTSTS_GINNakEff |
2234 GINTSTS_ConIDStsChng | GINTSTS_USBRst |
2235 GINTSTS_EnumDone | GINTSTS_OTGInt |
2236 GINTSTS_USBSusp | GINTSTS_WkUpInt,
2237 hsotg->regs + GINTMSK);
2239 if (using_dma(hsotg))
2240 writel(GAHBCFG_GlblIntrEn | GAHBCFG_DMAEn |
2241 GAHBCFG_HBstLen_Incr4,
2242 hsotg->regs + GAHBCFG);
2244 writel(GAHBCFG_GlblIntrEn, hsotg->regs + GAHBCFG);
2247 * Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2248 * up being flooded with interrupts if the host is polling the
2249 * endpoint to try and read data.
2252 writel(((hsotg->dedicated_fifos) ? DIEPMSK_TxFIFOEmpty : 0) |
2253 DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk |
2254 DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
2255 DIEPMSK_INTknEPMisMsk,
2256 hsotg->regs + DIEPMSK);
2259 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2260 * DMA mode we may need this.
2262 writel((using_dma(hsotg) ? (DIEPMSK_XferComplMsk |
2263 DIEPMSK_TimeOUTMsk) : 0) |
2264 DOEPMSK_EPDisbldMsk | DOEPMSK_AHBErrMsk |
2266 hsotg->regs + DOEPMSK);
2268 writel(0, hsotg->regs + DAINTMSK);
2270 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2271 readl(hsotg->regs + DIEPCTL0),
2272 readl(hsotg->regs + DOEPCTL0));
2274 /* enable in and out endpoint interrupts */
2275 s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPInt | GINTSTS_IEPInt);
2278 * Enable the RXFIFO when in slave mode, as this is how we collect
2279 * the data. In DMA mode, we get events from the FIFO but also
2280 * things we cannot process, so do not use it.
2282 if (!using_dma(hsotg))
2283 s3c_hsotg_en_gsint(hsotg, GINTSTS_RxFLvl);
2285 /* Enable interrupts for EP0 in and out */
2286 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2287 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2289 __orr32(hsotg->regs + DCTL, DCTL_PWROnPrgDone);
2290 udelay(10); /* see openiboot */
2291 __bic32(hsotg->regs + DCTL, DCTL_PWROnPrgDone);
2293 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL));
2296 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2297 * writing to the EPCTL register..
2300 /* set to read 1 8byte packet */
2301 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
2302 DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2304 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2305 DxEPCTL_CNAK | DxEPCTL_EPEna |
2307 hsotg->regs + DOEPCTL0);
2309 /* enable, but don't activate EP0in */
2310 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2311 DxEPCTL_USBActEp, hsotg->regs + DIEPCTL0);
2313 s3c_hsotg_enqueue_setup(hsotg);
2315 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2316 readl(hsotg->regs + DIEPCTL0),
2317 readl(hsotg->regs + DOEPCTL0));
2319 /* clear global NAKs */
2320 writel(DCTL_CGOUTNak | DCTL_CGNPInNAK,
2321 hsotg->regs + DCTL);
2323 /* must be at-least 3ms to allow bus to see disconnect */
2326 /* remove the soft-disconnect and let's go */
2327 __bic32(hsotg->regs + DCTL, DCTL_SftDiscon);
2331 * s3c_hsotg_irq - handle device interrupt
2332 * @irq: The IRQ number triggered
2333 * @pw: The pw value when registered the handler.
2335 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2337 struct s3c_hsotg *hsotg = pw;
2338 int retry_count = 8;
2342 spin_lock(&hsotg->lock);
2344 gintsts = readl(hsotg->regs + GINTSTS);
2345 gintmsk = readl(hsotg->regs + GINTMSK);
2347 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2348 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2352 if (gintsts & GINTSTS_OTGInt) {
2353 u32 otgint = readl(hsotg->regs + GOTGINT);
2355 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2357 writel(otgint, hsotg->regs + GOTGINT);
2360 if (gintsts & GINTSTS_SessReqInt) {
2361 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2362 writel(GINTSTS_SessReqInt, hsotg->regs + GINTSTS);
2365 if (gintsts & GINTSTS_EnumDone) {
2366 writel(GINTSTS_EnumDone, hsotg->regs + GINTSTS);
2368 s3c_hsotg_irq_enumdone(hsotg);
2371 if (gintsts & GINTSTS_ConIDStsChng) {
2372 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2373 readl(hsotg->regs + DSTS),
2374 readl(hsotg->regs + GOTGCTL));
2376 writel(GINTSTS_ConIDStsChng, hsotg->regs + GINTSTS);
2379 if (gintsts & (GINTSTS_OEPInt | GINTSTS_IEPInt)) {
2380 u32 daint = readl(hsotg->regs + DAINT);
2381 u32 daint_out = daint >> DAINT_OutEP_SHIFT;
2382 u32 daint_in = daint & ~(daint_out << DAINT_OutEP_SHIFT);
2385 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2387 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2389 s3c_hsotg_epint(hsotg, ep, 0);
2392 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2394 s3c_hsotg_epint(hsotg, ep, 1);
2398 if (gintsts & GINTSTS_USBRst) {
2400 u32 usb_status = readl(hsotg->regs + GOTGCTL);
2402 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2403 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2404 readl(hsotg->regs + GNPTXSTS));
2406 writel(GINTSTS_USBRst, hsotg->regs + GINTSTS);
2408 if (usb_status & GOTGCTL_BSESVLD) {
2409 if (time_after(jiffies, hsotg->last_rst +
2410 msecs_to_jiffies(200))) {
2412 kill_all_requests(hsotg, &hsotg->eps[0],
2415 s3c_hsotg_core_init(hsotg);
2416 hsotg->last_rst = jiffies;
2421 /* check both FIFOs */
2423 if (gintsts & GINTSTS_NPTxFEmp) {
2424 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2427 * Disable the interrupt to stop it happening again
2428 * unless one of these endpoint routines decides that
2429 * it needs re-enabling
2432 s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTxFEmp);
2433 s3c_hsotg_irq_fifoempty(hsotg, false);
2436 if (gintsts & GINTSTS_PTxFEmp) {
2437 dev_dbg(hsotg->dev, "PTxFEmp\n");
2439 /* See note in GINTSTS_NPTxFEmp */
2441 s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTxFEmp);
2442 s3c_hsotg_irq_fifoempty(hsotg, true);
2445 if (gintsts & GINTSTS_RxFLvl) {
2447 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2448 * we need to retry s3c_hsotg_handle_rx if this is still
2452 s3c_hsotg_handle_rx(hsotg);
2455 if (gintsts & GINTSTS_ModeMis) {
2456 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2457 writel(GINTSTS_ModeMis, hsotg->regs + GINTSTS);
2460 if (gintsts & GINTSTS_USBSusp) {
2461 dev_info(hsotg->dev, "GINTSTS_USBSusp\n");
2462 writel(GINTSTS_USBSusp, hsotg->regs + GINTSTS);
2464 call_gadget(hsotg, suspend);
2465 s3c_hsotg_disconnect(hsotg);
2468 if (gintsts & GINTSTS_WkUpInt) {
2469 dev_info(hsotg->dev, "GINTSTS_WkUpIn\n");
2470 writel(GINTSTS_WkUpInt, hsotg->regs + GINTSTS);
2472 call_gadget(hsotg, resume);
2475 if (gintsts & GINTSTS_ErlySusp) {
2476 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2477 writel(GINTSTS_ErlySusp, hsotg->regs + GINTSTS);
2479 s3c_hsotg_disconnect(hsotg);
2483 * these next two seem to crop-up occasionally causing the core
2484 * to shutdown the USB transfer, so try clearing them and logging
2488 if (gintsts & GINTSTS_GOUTNakEff) {
2489 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2491 writel(DCTL_CGOUTNak, hsotg->regs + DCTL);
2493 s3c_hsotg_dump(hsotg);
2496 if (gintsts & GINTSTS_GINNakEff) {
2497 dev_info(hsotg->dev, "GINNakEff triggered\n");
2499 writel(DCTL_CGNPInNAK, hsotg->regs + DCTL);
2501 s3c_hsotg_dump(hsotg);
2505 * if we've had fifo events, we should try and go around the
2506 * loop again to see if there's any point in returning yet.
2509 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2512 spin_unlock(&hsotg->lock);
2518 * s3c_hsotg_ep_enable - enable the given endpoint
2519 * @ep: The USB endpint to configure
2520 * @desc: The USB endpoint descriptor to configure with.
2522 * This is called from the USB gadget code's usb_ep_enable().
2524 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2525 const struct usb_endpoint_descriptor *desc)
2527 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2528 struct s3c_hsotg *hsotg = hs_ep->parent;
2529 unsigned long flags;
2530 int index = hs_ep->index;
2538 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2539 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2540 desc->wMaxPacketSize, desc->bInterval);
2542 /* not to be called for EP0 */
2543 WARN_ON(index == 0);
2545 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2546 if (dir_in != hs_ep->dir_in) {
2547 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2551 mps = usb_endpoint_maxp(desc);
2553 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2555 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2556 epctrl = readl(hsotg->regs + epctrl_reg);
2558 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2559 __func__, epctrl, epctrl_reg);
2561 spin_lock_irqsave(&hsotg->lock, flags);
2563 epctrl &= ~(DxEPCTL_EPType_MASK | DxEPCTL_MPS_MASK);
2564 epctrl |= DxEPCTL_MPS(mps);
2567 * mark the endpoint as active, otherwise the core may ignore
2568 * transactions entirely for this endpoint
2570 epctrl |= DxEPCTL_USBActEp;
2573 * set the NAK status on the endpoint, otherwise we might try and
2574 * do something with data that we've yet got a request to process
2575 * since the RXFIFO will take data for an endpoint even if the
2576 * size register hasn't been set.
2579 epctrl |= DxEPCTL_SNAK;
2581 /* update the endpoint state */
2582 hs_ep->ep.maxpacket = mps;
2584 /* default, set to non-periodic */
2585 hs_ep->periodic = 0;
2587 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2588 case USB_ENDPOINT_XFER_ISOC:
2589 dev_err(hsotg->dev, "no current ISOC support\n");
2593 case USB_ENDPOINT_XFER_BULK:
2594 epctrl |= DxEPCTL_EPType_Bulk;
2597 case USB_ENDPOINT_XFER_INT:
2600 * Allocate our TxFNum by simply using the index
2601 * of the endpoint for the moment. We could do
2602 * something better if the host indicates how
2603 * many FIFOs we are expecting to use.
2606 hs_ep->periodic = 1;
2607 epctrl |= DxEPCTL_TxFNum(index);
2610 epctrl |= DxEPCTL_EPType_Intterupt;
2613 case USB_ENDPOINT_XFER_CONTROL:
2614 epctrl |= DxEPCTL_EPType_Control;
2619 * if the hardware has dedicated fifos, we must give each IN EP
2620 * a unique tx-fifo even if it is non-periodic.
2622 if (dir_in && hsotg->dedicated_fifos)
2623 epctrl |= DxEPCTL_TxFNum(index);
2625 /* for non control endpoints, set PID to D0 */
2627 epctrl |= DxEPCTL_SetD0PID;
2629 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2632 writel(epctrl, hsotg->regs + epctrl_reg);
2633 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2634 __func__, readl(hsotg->regs + epctrl_reg));
2636 /* enable the endpoint interrupt */
2637 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2640 spin_unlock_irqrestore(&hsotg->lock, flags);
2645 * s3c_hsotg_ep_disable - disable given endpoint
2646 * @ep: The endpoint to disable.
2648 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2650 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2651 struct s3c_hsotg *hsotg = hs_ep->parent;
2652 int dir_in = hs_ep->dir_in;
2653 int index = hs_ep->index;
2654 unsigned long flags;
2658 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2660 if (ep == &hsotg->eps[0].ep) {
2661 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2665 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2667 spin_lock_irqsave(&hsotg->lock, flags);
2668 /* terminate all requests with shutdown */
2669 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2672 ctrl = readl(hsotg->regs + epctrl_reg);
2673 ctrl &= ~DxEPCTL_EPEna;
2674 ctrl &= ~DxEPCTL_USBActEp;
2675 ctrl |= DxEPCTL_SNAK;
2677 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2678 writel(ctrl, hsotg->regs + epctrl_reg);
2680 /* disable endpoint interrupts */
2681 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2683 spin_unlock_irqrestore(&hsotg->lock, flags);
2688 * on_list - check request is on the given endpoint
2689 * @ep: The endpoint to check.
2690 * @test: The request to test if it is on the endpoint.
2692 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2694 struct s3c_hsotg_req *req, *treq;
2696 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2705 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2706 * @ep: The endpoint to dequeue.
2707 * @req: The request to be removed from a queue.
2709 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2711 struct s3c_hsotg_req *hs_req = our_req(req);
2712 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2713 struct s3c_hsotg *hs = hs_ep->parent;
2714 unsigned long flags;
2716 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2718 spin_lock_irqsave(&hs->lock, flags);
2720 if (!on_list(hs_ep, hs_req)) {
2721 spin_unlock_irqrestore(&hs->lock, flags);
2725 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2726 spin_unlock_irqrestore(&hs->lock, flags);
2732 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2733 * @ep: The endpoint to set halt.
2734 * @value: Set or unset the halt.
2736 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2738 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2739 struct s3c_hsotg *hs = hs_ep->parent;
2740 int index = hs_ep->index;
2745 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2747 /* write both IN and OUT control registers */
2749 epreg = DIEPCTL(index);
2750 epctl = readl(hs->regs + epreg);
2753 epctl |= DxEPCTL_Stall + DxEPCTL_SNAK;
2754 if (epctl & DxEPCTL_EPEna)
2755 epctl |= DxEPCTL_EPDis;
2757 epctl &= ~DxEPCTL_Stall;
2758 xfertype = epctl & DxEPCTL_EPType_MASK;
2759 if (xfertype == DxEPCTL_EPType_Bulk ||
2760 xfertype == DxEPCTL_EPType_Intterupt)
2761 epctl |= DxEPCTL_SetD0PID;
2764 writel(epctl, hs->regs + epreg);
2766 epreg = DOEPCTL(index);
2767 epctl = readl(hs->regs + epreg);
2770 epctl |= DxEPCTL_Stall;
2772 epctl &= ~DxEPCTL_Stall;
2773 xfertype = epctl & DxEPCTL_EPType_MASK;
2774 if (xfertype == DxEPCTL_EPType_Bulk ||
2775 xfertype == DxEPCTL_EPType_Intterupt)
2776 epctl |= DxEPCTL_SetD0PID;
2779 writel(epctl, hs->regs + epreg);
2785 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2786 * @ep: The endpoint to set halt.
2787 * @value: Set or unset the halt.
2789 static int s3c_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
2791 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2792 struct s3c_hsotg *hs = hs_ep->parent;
2793 unsigned long flags = 0;
2796 spin_lock_irqsave(&hs->lock, flags);
2797 ret = s3c_hsotg_ep_sethalt(ep, value);
2798 spin_unlock_irqrestore(&hs->lock, flags);
2803 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2804 .enable = s3c_hsotg_ep_enable,
2805 .disable = s3c_hsotg_ep_disable,
2806 .alloc_request = s3c_hsotg_ep_alloc_request,
2807 .free_request = s3c_hsotg_ep_free_request,
2808 .queue = s3c_hsotg_ep_queue_lock,
2809 .dequeue = s3c_hsotg_ep_dequeue,
2810 .set_halt = s3c_hsotg_ep_sethalt_lock,
2811 /* note, don't believe we have any call for the fifo routines */
2815 * s3c_hsotg_phy_enable - enable platform phy dev
2816 * @hsotg: The driver state
2818 * A wrapper for platform code responsible for controlling
2819 * low-level USB code
2821 static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
2823 struct platform_device *pdev = to_platform_device(hsotg->dev);
2825 dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
2828 usb_phy_init(hsotg->phy);
2829 else if (hsotg->plat->phy_init)
2830 hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
2834 * s3c_hsotg_phy_disable - disable platform phy dev
2835 * @hsotg: The driver state
2837 * A wrapper for platform code responsible for controlling
2838 * low-level USB code
2840 static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
2842 struct platform_device *pdev = to_platform_device(hsotg->dev);
2845 usb_phy_shutdown(hsotg->phy);
2846 else if (hsotg->plat->phy_exit)
2847 hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
2851 * s3c_hsotg_init - initalize the usb core
2852 * @hsotg: The driver state
2854 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2856 /* unmask subset of endpoint interrupts */
2858 writel(DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
2859 DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk,
2860 hsotg->regs + DIEPMSK);
2862 writel(DOEPMSK_SetupMsk | DOEPMSK_AHBErrMsk |
2863 DOEPMSK_EPDisbldMsk | DOEPMSK_XferComplMsk,
2864 hsotg->regs + DOEPMSK);
2866 writel(0, hsotg->regs + DAINTMSK);
2868 /* Be in disconnected state until gadget is registered */
2869 __orr32(hsotg->regs + DCTL, DCTL_SftDiscon);
2872 /* post global nak until we're ready */
2873 writel(DCTL_SGNPInNAK | DCTL_SGOUTNak,
2874 hsotg->regs + DCTL);
2879 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2880 readl(hsotg->regs + GRXFSIZ),
2881 readl(hsotg->regs + GNPTXFSIZ));
2883 s3c_hsotg_init_fifo(hsotg);
2885 /* set the PLL on, remove the HNP/SRP and set the PHY */
2886 writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) | (0x5 << 10),
2887 hsotg->regs + GUSBCFG);
2889 writel(using_dma(hsotg) ? GAHBCFG_DMAEn : 0x0,
2890 hsotg->regs + GAHBCFG);
2894 * s3c_hsotg_udc_start - prepare the udc for work
2895 * @gadget: The usb gadget state
2896 * @driver: The usb gadget driver
2898 * Perform initialization to prepare udc device and driver
2901 static int s3c_hsotg_udc_start(struct usb_gadget *gadget,
2902 struct usb_gadget_driver *driver)
2904 struct s3c_hsotg *hsotg = to_hsotg(gadget);
2908 printk(KERN_ERR "%s: called with no device\n", __func__);
2913 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2917 if (driver->max_speed < USB_SPEED_FULL)
2918 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2920 if (!driver->setup) {
2921 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2925 WARN_ON(hsotg->driver);
2927 driver->driver.bus = NULL;
2928 hsotg->driver = driver;
2929 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
2930 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2932 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
2935 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
2939 hsotg->last_rst = jiffies;
2940 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2944 hsotg->driver = NULL;
2949 * s3c_hsotg_udc_stop - stop the udc
2950 * @gadget: The usb gadget state
2951 * @driver: The usb gadget driver
2953 * Stop udc hw block and stay tunned for future transmissions
2955 static int s3c_hsotg_udc_stop(struct usb_gadget *gadget,
2956 struct usb_gadget_driver *driver)
2958 struct s3c_hsotg *hsotg = to_hsotg(gadget);
2959 unsigned long flags = 0;
2965 if (!driver || driver != hsotg->driver || !driver->unbind)
2968 /* all endpoints should be shutdown */
2969 for (ep = 0; ep < hsotg->num_of_eps; ep++)
2970 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2972 spin_lock_irqsave(&hsotg->lock, flags);
2974 s3c_hsotg_phy_disable(hsotg);
2975 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
2977 hsotg->driver = NULL;
2978 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2980 spin_unlock_irqrestore(&hsotg->lock, flags);
2982 dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
2983 driver->driver.name);
2989 * s3c_hsotg_gadget_getframe - read the frame number
2990 * @gadget: The usb gadget state
2992 * Read the {micro} frame number
2994 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2996 return s3c_hsotg_read_frameno(to_hsotg(gadget));
3000 * s3c_hsotg_pullup - connect/disconnect the USB PHY
3001 * @gadget: The usb gadget state
3002 * @is_on: Current state of the USB PHY
3004 * Connect/Disconnect the USB PHY pullup
3006 static int s3c_hsotg_pullup(struct usb_gadget *gadget, int is_on)
3008 struct s3c_hsotg *hsotg = to_hsotg(gadget);
3009 unsigned long flags = 0;
3011 dev_dbg(hsotg->dev, "%s: is_in: %d\n", __func__, is_on);
3013 spin_lock_irqsave(&hsotg->lock, flags);
3015 s3c_hsotg_phy_enable(hsotg);
3016 s3c_hsotg_core_init(hsotg);
3018 s3c_hsotg_disconnect(hsotg);
3019 s3c_hsotg_phy_disable(hsotg);
3022 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3023 spin_unlock_irqrestore(&hsotg->lock, flags);
3028 static const struct usb_gadget_ops s3c_hsotg_gadget_ops = {
3029 .get_frame = s3c_hsotg_gadget_getframe,
3030 .udc_start = s3c_hsotg_udc_start,
3031 .udc_stop = s3c_hsotg_udc_stop,
3032 .pullup = s3c_hsotg_pullup,
3036 * s3c_hsotg_initep - initialise a single endpoint
3037 * @hsotg: The device state.
3038 * @hs_ep: The endpoint to be initialised.
3039 * @epnum: The endpoint number
3041 * Initialise the given endpoint (as part of the probe and device state
3042 * creation) to give to the gadget driver. Setup the endpoint name, any
3043 * direction information and other state that may be required.
3045 static void s3c_hsotg_initep(struct s3c_hsotg *hsotg,
3046 struct s3c_hsotg_ep *hs_ep,
3054 else if ((epnum % 2) == 0) {
3061 hs_ep->index = epnum;
3063 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3065 INIT_LIST_HEAD(&hs_ep->queue);
3066 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3068 /* add to the list of endpoints known by the gadget driver */
3070 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3072 hs_ep->parent = hsotg;
3073 hs_ep->ep.name = hs_ep->name;
3074 hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
3075 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
3078 * Read the FIFO size for the Periodic TX FIFO, even if we're
3079 * an OUT endpoint, we may as well do this if in future the
3080 * code is changed to make each endpoint's direction changeable.
3083 ptxfifo = readl(hsotg->regs + DPTXFSIZn(epnum));
3084 hs_ep->fifo_size = DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
3087 * if we're using dma, we need to set the next-endpoint pointer
3088 * to be something valid.
3091 if (using_dma(hsotg)) {
3092 u32 next = DxEPCTL_NextEp((epnum + 1) % 15);
3093 writel(next, hsotg->regs + DIEPCTL(epnum));
3094 writel(next, hsotg->regs + DOEPCTL(epnum));
3099 * s3c_hsotg_hw_cfg - read HW configuration registers
3100 * @param: The device state
3102 * Read the USB core HW configuration registers
3104 static void s3c_hsotg_hw_cfg(struct s3c_hsotg *hsotg)
3107 /* check hardware configuration */
3109 cfg2 = readl(hsotg->regs + 0x48);
3110 hsotg->num_of_eps = (cfg2 >> 10) & 0xF;
3112 dev_info(hsotg->dev, "EPs:%d\n", hsotg->num_of_eps);
3114 cfg4 = readl(hsotg->regs + 0x50);
3115 hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
3117 dev_info(hsotg->dev, "%s fifos\n",
3118 hsotg->dedicated_fifos ? "dedicated" : "shared");
3122 * s3c_hsotg_dump - dump state of the udc
3123 * @param: The device state
3125 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
3128 struct device *dev = hsotg->dev;
3129 void __iomem *regs = hsotg->regs;
3133 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3134 readl(regs + DCFG), readl(regs + DCTL),
3135 readl(regs + DIEPMSK));
3137 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3138 readl(regs + GAHBCFG), readl(regs + 0x44));
3140 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3141 readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
3143 /* show periodic fifo settings */
3145 for (idx = 1; idx <= 15; idx++) {
3146 val = readl(regs + DPTXFSIZn(idx));
3147 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3148 val >> DPTXFSIZn_DPTxFSize_SHIFT,
3149 val & DPTXFSIZn_DPTxFStAddr_MASK);
3152 for (idx = 0; idx < 15; idx++) {
3154 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3155 readl(regs + DIEPCTL(idx)),
3156 readl(regs + DIEPTSIZ(idx)),
3157 readl(regs + DIEPDMA(idx)));
3159 val = readl(regs + DOEPCTL(idx));
3161 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3162 idx, readl(regs + DOEPCTL(idx)),
3163 readl(regs + DOEPTSIZ(idx)),
3164 readl(regs + DOEPDMA(idx)));
3168 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3169 readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE));
3174 * state_show - debugfs: show overall driver and device state.
3175 * @seq: The seq file to write to.
3176 * @v: Unused parameter.
3178 * This debugfs entry shows the overall state of the hardware and
3179 * some general information about each of the endpoints available
3182 static int state_show(struct seq_file *seq, void *v)
3184 struct s3c_hsotg *hsotg = seq->private;
3185 void __iomem *regs = hsotg->regs;
3188 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3191 readl(regs + DSTS));
3193 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3194 readl(regs + DIEPMSK), readl(regs + DOEPMSK));
3196 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3197 readl(regs + GINTMSK),
3198 readl(regs + GINTSTS));
3200 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3201 readl(regs + DAINTMSK),
3202 readl(regs + DAINT));
3204 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3205 readl(regs + GNPTXSTS),
3206 readl(regs + GRXSTSR));
3208 seq_printf(seq, "\nEndpoint status:\n");
3210 for (idx = 0; idx < 15; idx++) {
3213 in = readl(regs + DIEPCTL(idx));
3214 out = readl(regs + DOEPCTL(idx));
3216 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3219 in = readl(regs + DIEPTSIZ(idx));
3220 out = readl(regs + DOEPTSIZ(idx));
3222 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3225 seq_printf(seq, "\n");
3231 static int state_open(struct inode *inode, struct file *file)
3233 return single_open(file, state_show, inode->i_private);
3236 static const struct file_operations state_fops = {
3237 .owner = THIS_MODULE,
3240 .llseek = seq_lseek,
3241 .release = single_release,
3245 * fifo_show - debugfs: show the fifo information
3246 * @seq: The seq_file to write data to.
3247 * @v: Unused parameter.
3249 * Show the FIFO information for the overall fifo and all the
3250 * periodic transmission FIFOs.
3252 static int fifo_show(struct seq_file *seq, void *v)
3254 struct s3c_hsotg *hsotg = seq->private;
3255 void __iomem *regs = hsotg->regs;
3259 seq_printf(seq, "Non-periodic FIFOs:\n");
3260 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ));
3262 val = readl(regs + GNPTXFSIZ);
3263 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3264 val >> GNPTXFSIZ_NPTxFDep_SHIFT,
3265 val & GNPTXFSIZ_NPTxFStAddr_MASK);
3267 seq_printf(seq, "\nPeriodic TXFIFOs:\n");
3269 for (idx = 1; idx <= 15; idx++) {
3270 val = readl(regs + DPTXFSIZn(idx));
3272 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3273 val >> DPTXFSIZn_DPTxFSize_SHIFT,
3274 val & DPTXFSIZn_DPTxFStAddr_MASK);
3280 static int fifo_open(struct inode *inode, struct file *file)
3282 return single_open(file, fifo_show, inode->i_private);
3285 static const struct file_operations fifo_fops = {
3286 .owner = THIS_MODULE,
3289 .llseek = seq_lseek,
3290 .release = single_release,
3294 static const char *decode_direction(int is_in)
3296 return is_in ? "in" : "out";
3300 * ep_show - debugfs: show the state of an endpoint.
3301 * @seq: The seq_file to write data to.
3302 * @v: Unused parameter.
3304 * This debugfs entry shows the state of the given endpoint (one is
3305 * registered for each available).
3307 static int ep_show(struct seq_file *seq, void *v)
3309 struct s3c_hsotg_ep *ep = seq->private;
3310 struct s3c_hsotg *hsotg = ep->parent;
3311 struct s3c_hsotg_req *req;
3312 void __iomem *regs = hsotg->regs;
3313 int index = ep->index;
3314 int show_limit = 15;
3315 unsigned long flags;
3317 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3318 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3320 /* first show the register state */
3322 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3323 readl(regs + DIEPCTL(index)),
3324 readl(regs + DOEPCTL(index)));
3326 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3327 readl(regs + DIEPDMA(index)),
3328 readl(regs + DOEPDMA(index)));
3330 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3331 readl(regs + DIEPINT(index)),
3332 readl(regs + DOEPINT(index)));
3334 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3335 readl(regs + DIEPTSIZ(index)),
3336 readl(regs + DOEPTSIZ(index)));
3338 seq_printf(seq, "\n");
3339 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3340 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3342 seq_printf(seq, "request list (%p,%p):\n",
3343 ep->queue.next, ep->queue.prev);
3345 spin_lock_irqsave(&hsotg->lock, flags);
3347 list_for_each_entry(req, &ep->queue, queue) {
3348 if (--show_limit < 0) {
3349 seq_printf(seq, "not showing more requests...\n");
3353 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3354 req == ep->req ? '*' : ' ',
3355 req, req->req.length, req->req.buf);
3356 seq_printf(seq, "%d done, res %d\n",
3357 req->req.actual, req->req.status);
3360 spin_unlock_irqrestore(&hsotg->lock, flags);
3365 static int ep_open(struct inode *inode, struct file *file)
3367 return single_open(file, ep_show, inode->i_private);
3370 static const struct file_operations ep_fops = {
3371 .owner = THIS_MODULE,
3374 .llseek = seq_lseek,
3375 .release = single_release,
3379 * s3c_hsotg_create_debug - create debugfs directory and files
3380 * @hsotg: The driver state
3382 * Create the debugfs files to allow the user to get information
3383 * about the state of the system. The directory name is created
3384 * with the same name as the device itself, in case we end up
3385 * with multiple blocks in future systems.
3387 static void s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3389 struct dentry *root;
3392 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3393 hsotg->debug_root = root;
3395 dev_err(hsotg->dev, "cannot create debug root\n");
3399 /* create general state file */
3401 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3402 hsotg, &state_fops);
3404 if (IS_ERR(hsotg->debug_file))
3405 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3407 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3410 if (IS_ERR(hsotg->debug_fifo))
3411 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3413 /* create one file for each endpoint */
3415 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3416 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3418 ep->debugfs = debugfs_create_file(ep->name, 0444,
3419 root, ep, &ep_fops);
3421 if (IS_ERR(ep->debugfs))
3422 dev_err(hsotg->dev, "failed to create %s debug file\n",
3428 * s3c_hsotg_delete_debug - cleanup debugfs entries
3429 * @hsotg: The driver state
3431 * Cleanup (remove) the debugfs files for use on module exit.
3433 static void s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3437 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3438 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3439 debugfs_remove(ep->debugfs);
3442 debugfs_remove(hsotg->debug_file);
3443 debugfs_remove(hsotg->debug_fifo);
3444 debugfs_remove(hsotg->debug_root);
3448 * s3c_hsotg_probe - probe function for hsotg driver
3449 * @pdev: The platform information for the driver
3452 static int s3c_hsotg_probe(struct platform_device *pdev)
3454 struct s3c_hsotg_plat *plat = dev_get_platdata(&pdev->dev);
3455 struct usb_phy *phy;
3456 struct device *dev = &pdev->dev;
3457 struct s3c_hsotg_ep *eps;
3458 struct s3c_hsotg *hsotg;
3459 struct resource *res;
3464 hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL);
3466 dev_err(dev, "cannot get memory\n");
3470 phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
3472 /* Fallback for pdata */
3473 plat = dev_get_platdata(&pdev->dev);
3475 dev_err(&pdev->dev, "no platform data or transceiver defined\n");
3476 return -EPROBE_DEFER;
3486 hsotg->clk = devm_clk_get(&pdev->dev, "otg");
3487 if (IS_ERR(hsotg->clk)) {
3488 dev_err(dev, "cannot get otg clock\n");
3489 return PTR_ERR(hsotg->clk);
3492 platform_set_drvdata(pdev, hsotg);
3494 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3496 hsotg->regs = devm_ioremap_resource(&pdev->dev, res);
3497 if (IS_ERR(hsotg->regs)) {
3498 ret = PTR_ERR(hsotg->regs);
3502 ret = platform_get_irq(pdev, 0);
3504 dev_err(dev, "cannot find IRQ\n");
3508 spin_lock_init(&hsotg->lock);
3512 ret = devm_request_irq(&pdev->dev, hsotg->irq, s3c_hsotg_irq, 0,
3513 dev_name(dev), hsotg);
3515 dev_err(dev, "cannot claim IRQ\n");
3519 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3521 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3522 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3523 hsotg->gadget.name = dev_name(dev);
3525 /* reset the system */
3527 clk_prepare_enable(hsotg->clk);
3531 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
3532 hsotg->supplies[i].supply = s3c_hsotg_supply_names[i];
3534 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies),
3537 dev_err(dev, "failed to request supplies: %d\n", ret);
3541 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3545 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
3549 /* usb phy enable */
3550 s3c_hsotg_phy_enable(hsotg);
3552 s3c_hsotg_corereset(hsotg);
3553 s3c_hsotg_init(hsotg);
3554 s3c_hsotg_hw_cfg(hsotg);
3556 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3558 if (hsotg->num_of_eps == 0) {
3559 dev_err(dev, "wrong number of EPs (zero)\n");
3564 eps = kcalloc(hsotg->num_of_eps + 1, sizeof(struct s3c_hsotg_ep),
3567 dev_err(dev, "cannot get memory\n");
3574 /* setup endpoint information */
3576 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3577 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3579 /* allocate EP0 request */
3581 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3583 if (!hsotg->ctrl_req) {
3584 dev_err(dev, "failed to allocate ctrl req\n");
3589 /* initialise the endpoints now the core has been initialised */
3590 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++)
3591 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3593 /* disable power and clock */
3595 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3598 dev_err(hsotg->dev, "failed to disable supplies: %d\n", ret);
3602 s3c_hsotg_phy_disable(hsotg);
3604 ret = usb_add_gadget_udc(&pdev->dev, &hsotg->gadget);
3608 s3c_hsotg_create_debug(hsotg);
3610 s3c_hsotg_dump(hsotg);
3617 s3c_hsotg_phy_disable(hsotg);
3619 clk_disable_unprepare(hsotg->clk);
3625 * s3c_hsotg_remove - remove function for hsotg driver
3626 * @pdev: The platform information for the driver
3628 static int s3c_hsotg_remove(struct platform_device *pdev)
3630 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3632 usb_del_gadget_udc(&hsotg->gadget);
3634 s3c_hsotg_delete_debug(hsotg);
3636 if (hsotg->driver) {
3637 /* should have been done already by driver model core */
3638 usb_gadget_unregister_driver(hsotg->driver);
3641 s3c_hsotg_phy_disable(hsotg);
3642 clk_disable_unprepare(hsotg->clk);
3648 #define s3c_hsotg_suspend NULL
3649 #define s3c_hsotg_resume NULL
3653 static const struct of_device_id s3c_hsotg_of_ids[] = {
3654 { .compatible = "samsung,s3c6400-hsotg", },
3657 MODULE_DEVICE_TABLE(of, s3c_hsotg_of_ids);
3660 static struct platform_driver s3c_hsotg_driver = {
3662 .name = "s3c-hsotg",
3663 .owner = THIS_MODULE,
3664 .of_match_table = of_match_ptr(s3c_hsotg_of_ids),
3666 .probe = s3c_hsotg_probe,
3667 .remove = s3c_hsotg_remove,
3668 .suspend = s3c_hsotg_suspend,
3669 .resume = s3c_hsotg_resume,
3672 module_platform_driver(s3c_hsotg_driver);
3674 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3675 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3676 MODULE_LICENSE("GPL");
3677 MODULE_ALIAS("platform:s3c-hsotg");