4 * Copyright (C) 2007-2009 Renesas Solutions Corp.
6 * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
13 #ifndef __R8A66597_H__
14 #define __R8A66597_H__
16 #include <linux/clk.h>
17 #include <linux/usb/r8a66597.h>
19 #define R8A66597_MAX_SAMPLING 10
21 #define R8A66597_MAX_NUM_PIPE 8
22 #define R8A66597_MAX_NUM_BULK 3
23 #define R8A66597_MAX_NUM_ISOC 2
24 #define R8A66597_MAX_NUM_INT 2
26 #define R8A66597_BASE_PIPENUM_BULK 3
27 #define R8A66597_BASE_PIPENUM_ISOC 1
28 #define R8A66597_BASE_PIPENUM_INT 6
30 #define R8A66597_BASE_BUFNUM 6
31 #define R8A66597_MAX_BUFNUM 0x4F
33 #define is_bulk_pipe(pipenum) \
34 ((pipenum >= R8A66597_BASE_PIPENUM_BULK) && \
35 (pipenum < (R8A66597_BASE_PIPENUM_BULK + R8A66597_MAX_NUM_BULK)))
36 #define is_interrupt_pipe(pipenum) \
37 ((pipenum >= R8A66597_BASE_PIPENUM_INT) && \
38 (pipenum < (R8A66597_BASE_PIPENUM_INT + R8A66597_MAX_NUM_INT)))
39 #define is_isoc_pipe(pipenum) \
40 ((pipenum >= R8A66597_BASE_PIPENUM_ISOC) && \
41 (pipenum < (R8A66597_BASE_PIPENUM_ISOC + R8A66597_MAX_NUM_ISOC)))
43 #define r8a66597_is_sudmac(r8a66597) (r8a66597->pdata->sudmac)
44 struct r8a66597_pipe_info {
53 struct r8a66597_request {
54 struct usb_request req;
55 struct list_head queue;
60 struct r8a66597 *r8a66597;
61 struct r8a66597_dma *dma;
63 struct list_head queue;
66 unsigned internal_ccpl:1; /* use only control */
68 /* this member can able to after r8a66597_enable */
73 /* register address */
74 unsigned char fifoaddr;
75 unsigned char fifosel;
76 unsigned char fifoctr;
77 unsigned char pipectr;
78 unsigned char pipetre;
79 unsigned char pipetrn;
84 unsigned dir:1; /* 1 = IN(write), 0 = OUT(read) */
90 void __iomem *sudmac_reg;
93 struct r8a66597_platdata *pdata;
95 struct usb_gadget gadget;
96 struct usb_gadget_driver *driver;
98 struct r8a66597_ep ep[R8A66597_MAX_NUM_PIPE];
99 struct r8a66597_ep *pipenum2ep[R8A66597_MAX_NUM_PIPE];
100 struct r8a66597_ep *epaddr2ep[16];
101 struct r8a66597_dma dma;
103 struct timer_list timer;
104 struct usb_request *ep0_req; /* for internal request */
105 u16 ep0_data; /* for internal request */
109 u16 device_status; /* for GET_STATUS */
113 unsigned char interrupt;
114 unsigned char isochronous;
115 unsigned char num_dma;
117 unsigned irq_sense_low:1;
120 #define gadget_to_r8a66597(_gadget) \
121 container_of(_gadget, struct r8a66597, gadget)
122 #define r8a66597_to_gadget(r8a66597) (&r8a66597->gadget)
123 #define r8a66597_to_dev(r8a66597) (r8a66597->gadget.dev.parent)
125 static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
127 return ioread16(r8a66597->reg + offset);
130 static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
131 unsigned long offset,
135 void __iomem *fifoaddr = r8a66597->reg + offset;
136 unsigned int data = 0;
139 if (r8a66597->pdata->on_chip) {
140 /* 32-bit accesses for on_chip controllers */
142 /* aligned buf case */
143 if (len >= 4 && !((unsigned long)buf & 0x03)) {
144 ioread32_rep(fifoaddr, buf, len / 4);
149 /* unaligned buf case */
150 for (i = 0; i < len; i++) {
152 data = ioread32(fifoaddr);
154 buf[i] = (data >> ((i & 0x03) * 8)) & 0xff;
157 /* 16-bit accesses for external controllers */
159 /* aligned buf case */
160 if (len >= 2 && !((unsigned long)buf & 0x01)) {
161 ioread16_rep(fifoaddr, buf, len / 2);
166 /* unaligned buf case */
167 for (i = 0; i < len; i++) {
169 data = ioread16(fifoaddr);
171 buf[i] = (data >> ((i & 0x01) * 8)) & 0xff;
176 static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
177 unsigned long offset)
179 iowrite16(val, r8a66597->reg + offset);
182 static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
183 u16 val, u16 pat, unsigned long offset)
186 tmp = r8a66597_read(r8a66597, offset);
189 r8a66597_write(r8a66597, tmp, offset);
192 #define r8a66597_bclr(r8a66597, val, offset) \
193 r8a66597_mdfy(r8a66597, 0, val, offset)
194 #define r8a66597_bset(r8a66597, val, offset) \
195 r8a66597_mdfy(r8a66597, val, 0, offset)
197 static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
198 struct r8a66597_ep *ep,
202 void __iomem *fifoaddr = r8a66597->reg + ep->fifoaddr;
206 if (r8a66597->pdata->on_chip) {
207 /* 32-bit access only if buf is 32-bit aligned */
208 if (len >= 4 && !((unsigned long)buf & 0x03)) {
209 iowrite32_rep(fifoaddr, buf, len / 4);
214 /* 16-bit access only if buf is 16-bit aligned */
215 if (len >= 2 && !((unsigned long)buf & 0x01)) {
216 iowrite16_rep(fifoaddr, buf, len / 2);
222 /* adjust fifo address in the little endian case */
223 if (!(r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)) {
224 if (r8a66597->pdata->on_chip)
225 adj = 0x03; /* 32-bit wide */
227 adj = 0x01; /* 16-bit wide */
230 if (r8a66597->pdata->wr0_shorted_to_wr1)
231 r8a66597_bclr(r8a66597, MBW_16, ep->fifosel);
232 for (i = 0; i < len; i++)
233 iowrite8(buf[i], fifoaddr + adj - (i & adj));
234 if (r8a66597->pdata->wr0_shorted_to_wr1)
235 r8a66597_bclr(r8a66597, MBW_16, ep->fifosel);
238 static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
242 switch (pdata->xtal) {
243 case R8A66597_PLATDATA_XTAL_12MHZ:
246 case R8A66597_PLATDATA_XTAL_24MHZ:
249 case R8A66597_PLATDATA_XTAL_48MHZ:
253 printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
260 static inline u32 r8a66597_sudmac_read(struct r8a66597 *r8a66597,
261 unsigned long offset)
263 return ioread32(r8a66597->sudmac_reg + offset);
266 static inline void r8a66597_sudmac_write(struct r8a66597 *r8a66597, u32 val,
267 unsigned long offset)
269 iowrite32(val, r8a66597->sudmac_reg + offset);
272 #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
273 #define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
274 #define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
276 #define enable_irq_ready(r8a66597, pipenum) \
277 enable_pipe_irq(r8a66597, pipenum, BRDYENB)
278 #define disable_irq_ready(r8a66597, pipenum) \
279 disable_pipe_irq(r8a66597, pipenum, BRDYENB)
280 #define enable_irq_empty(r8a66597, pipenum) \
281 enable_pipe_irq(r8a66597, pipenum, BEMPENB)
282 #define disable_irq_empty(r8a66597, pipenum) \
283 disable_pipe_irq(r8a66597, pipenum, BEMPENB)
284 #define enable_irq_nrdy(r8a66597, pipenum) \
285 enable_pipe_irq(r8a66597, pipenum, NRDYENB)
286 #define disable_irq_nrdy(r8a66597, pipenum) \
287 disable_pipe_irq(r8a66597, pipenum, NRDYENB)
289 #endif /* __R8A66597_H__ */