drivers/usb/host/ehci-fsl.c

   1 /*
   2  * Copyright 2005-2009 MontaVista Software, Inc.
   3  * Copyright 2008,2012,2015      Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software Foundation,
  17  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
  20  * by Hunter Wu.
  21  * Power Management support by Dave Liu <daveliu@freescale.com>,
  22  * Jerry Huang <Chang-Ming.Huang@freescale.com> and
  23  * Anton Vorontsov <avorontsov@ru.mvista.com>.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/types.h>
  29 #include <linux/delay.h>
  30 #include <linux/pm.h>
  31 #include <linux/err.h>
  32 #include <linux/usb.h>
  33 #include <linux/usb/ehci_def.h>
  34 #include <linux/usb/hcd.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/fsl_devices.h>
  38
  39 #include "ehci.h"
  40 #include "ehci-fsl.h"
  41
  42 #define DRIVER_DESC "Freescale EHCI Host controller driver"
  43 #define DRV_NAME "ehci-fsl"
  44
  45 static struct hc_driver __read_mostly fsl_ehci_hc_driver;
  46
  47 /* configure so an HC device and id are always provided */
  48 /* always called with process context; sleeping is OK */
  49
  50 /*
  51  * fsl_ehci_drv_probe - initialize FSL-based HCDs
  52  * @pdev: USB Host Controller being probed
  53  * Context: !in_interrupt()
  54  *
  55  * Allocates basic resources for this USB host controller.
  56  *
  57  */
  58 static int fsl_ehci_drv_probe(struct platform_device *pdev)
  59 {
  60         struct fsl_usb2_platform_data *pdata;
  61         struct usb_hcd *hcd;
  62         struct resource *res;
  63         int irq;
  64         int retval;
  65
  66         pr_debug("initializing FSL-SOC USB Controller\n");
  67
  68         /* Need platform data for setup */
  69         pdata = dev_get_platdata(&pdev->dev);
  70         if (!pdata) {
  71                 dev_err(&pdev->dev,
  72                         "No platform data for %s.\n", dev_name(&pdev->dev));
  73                 return -ENODEV;
  74         }
  75
  76         /*
  77          * This is a host mode driver, verify that we're supposed to be
  78          * in host mode.
  79          */
  80         if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  81               (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
  82               (pdata->operating_mode == FSL_USB2_DR_OTG))) {
  83                 dev_err(&pdev->dev,
  84                         "Non Host Mode configured for %s. Wrong driver linked.\n",
  85                         dev_name(&pdev->dev));
  86                 return -ENODEV;
  87         }
  88
  89         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  90         if (!res) {
  91                 dev_err(&pdev->dev,
  92                         "Found HC with no IRQ. Check %s setup!\n",
  93                         dev_name(&pdev->dev));
  94                 return -ENODEV;
  95         }
  96         irq = res->start;
  97
  98         hcd = usb_create_hcd(&fsl_ehci_hc_driver, &pdev->dev,
  99                                 dev_name(&pdev->dev));
 100         if (!hcd) {
 101                 retval = -ENOMEM;
 102                 goto err1;
 103         }
 104
 105         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 106         hcd->regs = devm_ioremap_resource(&pdev->dev, res);
 107         if (IS_ERR(hcd->regs)) {
 108                 retval = PTR_ERR(hcd->regs);
 109                 goto err2;
 110         }
 111
 112         hcd->rsrc_start = res->start;
 113         hcd->rsrc_len = resource_size(res);
 114
 115         pdata->regs = hcd->regs;
 116
 117         if (pdata->power_budget)
 118                 hcd->power_budget = pdata->power_budget;
 119
 120         /*
 121          * do platform specific init: check the clock, grab/config pins, etc.
 122          */
 123         if (pdata->init && pdata->init(pdev)) {
 124                 retval = -ENODEV;
 125                 goto err2;
 126         }
 127
 128         /* Enable USB controller, 83xx or 8536 */
 129         if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
 130                 setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
 131
 132         /*
 133          * Enable UTMI phy and program PTS field in UTMI mode before asserting
 134          * controller reset for USB Controller version 2.5
 135          */
 136         if (pdata->has_fsl_erratum_a007792) {
 137                 writel_be(CTRL_UTMI_PHY_EN, hcd->regs + FSL_SOC_USB_CTRL);
 138                 writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);
 139         }
 140
 141         /* Don't need to set host mode here. It will be done by tdi_reset() */
 142
 143         retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
 144         if (retval != 0)
 145                 goto err2;
 146         device_wakeup_enable(hcd->self.controller);
 147
 148 #ifdef CONFIG_USB_OTG
 149         if (pdata->operating_mode == FSL_USB2_DR_OTG) {
 150                 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 151
 152                 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
 153                 dev_dbg(&pdev->dev, "hcd=0x%p  ehci=0x%p, phy=0x%p\n",
 154                         hcd, ehci, hcd->usb_phy);
 155
 156                 if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
 157                         retval = otg_set_host(hcd->usb_phy->otg,
 158                                               &ehci_to_hcd(ehci)->self);
 159                         if (retval) {
 160                                 usb_put_phy(hcd->usb_phy);
 161                                 goto err2;
 162                         }
 163                 } else {
 164                         dev_err(&pdev->dev, "can't find phy\n");
 165                         retval = -ENODEV;
 166                         goto err2;
 167                 }
 168         }
 169 #endif
 170         return retval;
 171
 172       err2:
 173         usb_put_hcd(hcd);
 174       err1:
 175         dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
 176         if (pdata->exit)
 177                 pdata->exit(pdev);
 178         return retval;
 179 }
 180
 181 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
 182                                enum fsl_usb2_phy_modes phy_mode,
 183                                unsigned int port_offset)
 184 {
 185         u32 portsc;
 186         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 187         void __iomem *non_ehci = hcd->regs;
 188         struct device *dev = hcd->self.controller;
 189         struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
 190
 191         if (pdata->controller_ver < 0) {
 192                 dev_warn(hcd->self.controller, "Could not get controller version\n");
 193                 return -ENODEV;
 194         }
 195
 196         portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
 197         portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
 198
 199         switch (phy_mode) {
 200         case FSL_USB2_PHY_ULPI:
 201                 if (pdata->have_sysif_regs && pdata->controller_ver) {
 202                         /* controller version 1.6 or above */
 203                         clrbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
 204                         setbits32(non_ehci + FSL_SOC_USB_CTRL,
 205                                 ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
 206                 }
 207                 portsc |= PORT_PTS_ULPI;
 208                 break;
 209         case FSL_USB2_PHY_SERIAL:
 210                 portsc |= PORT_PTS_SERIAL;
 211                 break;
 212         case FSL_USB2_PHY_UTMI_WIDE:
 213                 portsc |= PORT_PTS_PTW;
 214                 /* fall through */
 215         case FSL_USB2_PHY_UTMI:
 216                 if (pdata->have_sysif_regs && pdata->controller_ver) {
 217                         /* controller version 1.6 or above */
 218                         setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
 219                         mdelay(FSL_UTMI_PHY_DLY);  /* Delay for UTMI PHY CLK to
 220                                                 become stable - 10ms*/
 221                 }
 222                 /* enable UTMI PHY */
 223                 if (pdata->have_sysif_regs)
 224                         setbits32(non_ehci + FSL_SOC_USB_CTRL,
 225                                   CTRL_UTMI_PHY_EN);
 226                 portsc |= PORT_PTS_UTMI;
 227                 break;
 228         case FSL_USB2_PHY_NONE:
 229                 break;
 230         }
 231
 232         if (pdata->have_sysif_regs &&
 233             pdata->controller_ver > FSL_USB_VER_1_6 &&
 234             (phy_mode == FSL_USB2_PHY_ULPI)) {
 235                 /* check PHY_CLK_VALID to get phy clk valid */
 236                 if (!(spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
 237                                 PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0) ||
 238                                 in_be32(non_ehci + FSL_SOC_USB_PRICTRL))) {
 239                         dev_warn(hcd->self.controller, "USB PHY clock invalid\n");
 240                         return -EINVAL;
 241                 }
 242         }
 243
 244         ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
 245
 246         if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
 247                 setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN);
 248
 249         return 0;
 250 }
 251
 252 static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
 253 {
 254         struct usb_hcd *hcd = ehci_to_hcd(ehci);
 255         struct fsl_usb2_platform_data *pdata;
 256         void __iomem *non_ehci = hcd->regs;
 257
 258         pdata = dev_get_platdata(hcd->self.controller);
 259
 260         if (pdata->have_sysif_regs) {
 261                 /*
 262                 * Turn on cache snooping hardware, since some PowerPC platforms
 263                 * wholly rely on hardware to deal with cache coherent
 264                 */
 265
 266                 /* Setup Snooping for all the 4GB space */
 267                 /* SNOOP1 starts from 0x0, size 2G */
 268                 out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0 | SNOOP_SIZE_2GB);
 269                 /* SNOOP2 starts from 0x80000000, size 2G */
 270                 out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB);
 271         }
 272
 273         if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
 274                         (pdata->operating_mode == FSL_USB2_DR_OTG))
 275                 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
 276                         return -EINVAL;
 277
 278         if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
 279                 unsigned int chip, rev, svr;
 280
 281                 svr = mfspr(SPRN_SVR);
 282                 chip = svr >> 16;
 283                 rev = (svr >> 4) & 0xf;
 284
 285                 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
 286                 if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
 287                         ehci->has_fsl_port_bug = 1;
 288
 289                 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
 290                         if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
 291                                 return -EINVAL;
 292
 293                 if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
 294                         if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1))
 295                                 return -EINVAL;
 296         }
 297
 298         if (pdata->have_sysif_regs) {
 299 #ifdef CONFIG_FSL_SOC_BOOKE
 300                 out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008);
 301                 out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000080);
 302 #else
 303                 out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c);
 304                 out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040);
 305 #endif
 306                 out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
 307         }
 308
 309         return 0;
 310 }
 311
 312 /* called after powerup, by probe or system-pm "wakeup" */
 313 static int ehci_fsl_reinit(struct ehci_hcd *ehci)
 314 {
 315         if (ehci_fsl_usb_setup(ehci))
 316                 return -EINVAL;
 317
 318         return 0;
 319 }
 320
 321 /* called during probe() after chip reset completes */
 322 static int ehci_fsl_setup(struct usb_hcd *hcd)
 323 {
 324         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 325         int retval;
 326         struct fsl_usb2_platform_data *pdata;
 327         struct device *dev;
 328
 329         dev = hcd->self.controller;
 330         pdata = dev_get_platdata(hcd->self.controller);
 331         ehci->big_endian_desc = pdata->big_endian_desc;
 332         ehci->big_endian_mmio = pdata->big_endian_mmio;
 333
 334         /* EHCI registers start at offset 0x100 */
 335         ehci->caps = hcd->regs + 0x100;
 336
 337 #ifdef CONFIG_PPC_83xx
 338         /*
 339          * Deal with MPC834X that need port power to be cycled after the power
 340          * fault condition is removed. Otherwise the state machine does not
 341          * reflect PORTSC[CSC] correctly.
 342          */
 343         ehci->need_oc_pp_cycle = 1;
 344 #endif
 345
 346         hcd->has_tt = 1;
 347
 348         retval = ehci_setup(hcd);
 349         if (retval)
 350                 return retval;
 351
 352         if (of_device_is_compatible(dev->parent->of_node,
 353                                     "fsl,mpc5121-usb2-dr")) {
 354                 /*
 355                  * set SBUSCFG:AHBBRST so that control msgs don't
 356                  * fail when doing heavy PATA writes.
 357                  */
 358                 ehci_writel(ehci, SBUSCFG_INCR8,
 359                             hcd->regs + FSL_SOC_USB_SBUSCFG);
 360         }
 361
 362         retval = ehci_fsl_reinit(ehci);
 363         return retval;
 364 }
 365
 366 struct ehci_fsl {
 367         struct ehci_hcd ehci;
 368
 369 #ifdef CONFIG_PM
 370         /* Saved USB PHY settings, need to restore after deep sleep. */
 371         u32 usb_ctrl;
 372 #endif
 373 };
 374
 375 #ifdef CONFIG_PM
 376
 377 #ifdef CONFIG_PPC_MPC512x
 378 static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
 379 {
 380         struct usb_hcd *hcd = dev_get_drvdata(dev);
 381         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 382         struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
 383         u32 tmp;
 384
 385 #ifdef CONFIG_DYNAMIC_DEBUG
 386         u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
 387         mode &= USBMODE_CM_MASK;
 388         tmp = ehci_readl(ehci, hcd->regs + 0x140);      /* usbcmd */
 389
 390         dev_dbg(dev, "suspend=%d already_suspended=%d "
 391                 "mode=%d  usbcmd %08x\n", pdata->suspended,
 392                 pdata->already_suspended, mode, tmp);
 393 #endif
 394
 395         /*
 396          * If the controller is already suspended, then this must be a
 397          * PM suspend.  Remember this fact, so that we will leave the
 398          * controller suspended at PM resume time.
 399          */
 400         if (pdata->suspended) {
 401                 dev_dbg(dev, "already suspended, leaving early\n");
 402                 pdata->already_suspended = 1;
 403                 return 0;
 404         }
 405
 406         dev_dbg(dev, "suspending...\n");
 407
 408         ehci->rh_state = EHCI_RH_SUSPENDED;
 409         dev->power.power_state = PMSG_SUSPEND;
 410
 411         /* ignore non-host interrupts */
 412         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 413
 414         /* stop the controller */
 415         tmp = ehci_readl(ehci, &ehci->regs->command);
 416         tmp &= ~CMD_RUN;
 417         ehci_writel(ehci, tmp, &ehci->regs->command);
 418
 419         /* save EHCI registers */
 420         pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
 421         pdata->pm_command &= ~CMD_RUN;
 422         pdata->pm_status  = ehci_readl(ehci, &ehci->regs->status);
 423         pdata->pm_intr_enable  = ehci_readl(ehci, &ehci->regs->intr_enable);
 424         pdata->pm_frame_index  = ehci_readl(ehci, &ehci->regs->frame_index);
 425         pdata->pm_segment  = ehci_readl(ehci, &ehci->regs->segment);
 426         pdata->pm_frame_list  = ehci_readl(ehci, &ehci->regs->frame_list);
 427         pdata->pm_async_next  = ehci_readl(ehci, &ehci->regs->async_next);
 428         pdata->pm_configured_flag  =
 429                 ehci_readl(ehci, &ehci->regs->configured_flag);
 430         pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
 431         pdata->pm_usbgenctrl = ehci_readl(ehci,
 432                                           hcd->regs + FSL_SOC_USB_USBGENCTRL);
 433
 434         /* clear the W1C bits */
 435         pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
 436
 437         pdata->suspended = 1;
 438
 439         /* clear PP to cut power to the port */
 440         tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
 441         tmp &= ~PORT_POWER;
 442         ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
 443
 444         return 0;
 445 }
 446
 447 static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
 448 {
 449         struct usb_hcd *hcd = dev_get_drvdata(dev);
 450         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 451         struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
 452         u32 tmp;
 453
 454         dev_dbg(dev, "suspend=%d already_suspended=%d\n",
 455                 pdata->suspended, pdata->already_suspended);
 456
 457         /*
 458          * If the controller was already suspended at suspend time,
 459          * then don't resume it now.
 460          */
 461         if (pdata->already_suspended) {
 462                 dev_dbg(dev, "already suspended, leaving early\n");
 463                 pdata->already_suspended = 0;
 464                 return 0;
 465         }
 466
 467         if (!pdata->suspended) {
 468                 dev_dbg(dev, "not suspended, leaving early\n");
 469                 return 0;
 470         }
 471
 472         pdata->suspended = 0;
 473
 474         dev_dbg(dev, "resuming...\n");
 475
 476         /* set host mode */
 477         tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
 478         ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
 479
 480         ehci_writel(ehci, pdata->pm_usbgenctrl,
 481                     hcd->regs + FSL_SOC_USB_USBGENCTRL);
 482         ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
 483                     hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
 484
 485         ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
 486
 487         /* restore EHCI registers */
 488         ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
 489         ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
 490         ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
 491         ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
 492         ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
 493         ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
 494         ehci_writel(ehci, pdata->pm_configured_flag,
 495                     &ehci->regs->configured_flag);
 496         ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
 497
 498         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 499         ehci->rh_state = EHCI_RH_RUNNING;
 500         dev->power.power_state = PMSG_ON;
 501
 502         tmp = ehci_readl(ehci, &ehci->regs->command);
 503         tmp |= CMD_RUN;
 504         ehci_writel(ehci, tmp, &ehci->regs->command);
 505
 506         usb_hcd_resume_root_hub(hcd);
 507
 508         return 0;
 509 }
 510 #else
 511 static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
 512 {
 513         return 0;
 514 }
 515
 516 static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
 517 {
 518         return 0;
 519 }
 520 #endif /* CONFIG_PPC_MPC512x */
 521
 522 static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
 523 {
 524         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 525
 526         return container_of(ehci, struct ehci_fsl, ehci);
 527 }
 528
 529 static int ehci_fsl_drv_suspend(struct device *dev)
 530 {
 531         struct usb_hcd *hcd = dev_get_drvdata(dev);
 532         struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
 533         void __iomem *non_ehci = hcd->regs;
 534
 535         if (of_device_is_compatible(dev->parent->of_node,
 536                                     "fsl,mpc5121-usb2-dr")) {
 537                 return ehci_fsl_mpc512x_drv_suspend(dev);
 538         }
 539
 540         ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
 541                         device_may_wakeup(dev));
 542         if (!fsl_deep_sleep())
 543                 return 0;
 544
 545         ehci_fsl->usb_ctrl = in_be32(non_ehci + FSL_SOC_USB_CTRL);
 546         return 0;
 547 }
 548
 549 static int ehci_fsl_drv_resume(struct device *dev)
 550 {
 551         struct usb_hcd *hcd = dev_get_drvdata(dev);
 552         struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
 553         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 554         void __iomem *non_ehci = hcd->regs;
 555
 556         if (of_device_is_compatible(dev->parent->of_node,
 557                                     "fsl,mpc5121-usb2-dr")) {
 558                 return ehci_fsl_mpc512x_drv_resume(dev);
 559         }
 560
 561         ehci_prepare_ports_for_controller_resume(ehci);
 562         if (!fsl_deep_sleep())
 563                 return 0;
 564
 565         usb_root_hub_lost_power(hcd->self.root_hub);
 566
 567         /* Restore USB PHY settings and enable the controller. */
 568         out_be32(non_ehci + FSL_SOC_USB_CTRL, ehci_fsl->usb_ctrl);
 569
 570         ehci_reset(ehci);
 571         ehci_fsl_reinit(ehci);
 572
 573         return 0;
 574 }
 575
 576 static int ehci_fsl_drv_restore(struct device *dev)
 577 {
 578         struct usb_hcd *hcd = dev_get_drvdata(dev);
 579
 580         usb_root_hub_lost_power(hcd->self.root_hub);
 581         return 0;
 582 }
 583
 584 static struct dev_pm_ops ehci_fsl_pm_ops = {
 585         .suspend = ehci_fsl_drv_suspend,
 586         .resume = ehci_fsl_drv_resume,
 587         .restore = ehci_fsl_drv_restore,
 588 };
 589
 590 #define EHCI_FSL_PM_OPS         (&ehci_fsl_pm_ops)
 591 #else
 592 #define EHCI_FSL_PM_OPS         NULL
 593 #endif /* CONFIG_PM */
 594
 595 #ifdef CONFIG_USB_OTG
 596 static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
 597 {
 598         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 599         u32 status;
 600
 601         if (!port)
 602                 return -EINVAL;
 603
 604         port--;
 605
 606         /* start port reset before HNP protocol time out */
 607         status = readl(&ehci->regs->port_status[port]);
 608         if (!(status & PORT_CONNECT))
 609                 return -ENODEV;
 610
 611         /* hub_wq will finish the reset later */
 612         if (ehci_is_TDI(ehci)) {
 613                 writel(PORT_RESET |
 614                        (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
 615                        &ehci->regs->port_status[port]);
 616         } else {
 617                 writel(PORT_RESET, &ehci->regs->port_status[port]);
 618         }
 619
 620         return 0;
 621 }
 622 #else
 623 #define ehci_start_port_reset   NULL
 624 #endif /* CONFIG_USB_OTG */
 625
 626 static struct ehci_driver_overrides ehci_fsl_overrides __initdata = {
 627         .extra_priv_size = sizeof(struct ehci_fsl),
 628         .reset = ehci_fsl_setup,
 629 };
 630
 631 /**
 632  * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs
 633  * @dev: USB Host Controller being removed
 634  * Context: !in_interrupt()
 635  *
 636  * Reverses the effect of usb_hcd_fsl_probe().
 637  *
 638  */
 639
 640 static int fsl_ehci_drv_remove(struct platform_device *pdev)
 641 {
 642         struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
 643         struct usb_hcd *hcd = platform_get_drvdata(pdev);
 644
 645         if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
 646                 otg_set_host(hcd->usb_phy->otg, NULL);
 647                 usb_put_phy(hcd->usb_phy);
 648         }
 649
 650         usb_remove_hcd(hcd);
 651
 652         /*
 653          * do platform specific un-initialization:
 654          * release iomux pins, disable clock, etc.
 655          */
 656         if (pdata->exit)
 657                 pdata->exit(pdev);
 658         usb_put_hcd(hcd);
 659
 660         return 0;
 661 }
 662
 663 static struct platform_driver ehci_fsl_driver = {
 664         .probe = fsl_ehci_drv_probe,
 665         .remove = fsl_ehci_drv_remove,
 666         .shutdown = usb_hcd_platform_shutdown,
 667         .driver = {
 668                 .name = "fsl-ehci",
 669                 .pm = EHCI_FSL_PM_OPS,
 670         },
 671 };
 672
 673 static int __init ehci_fsl_init(void)
 674 {
 675         if (usb_disabled())
 676                 return -ENODEV;
 677
 678         pr_info(DRV_NAME ": " DRIVER_DESC "\n");
 679
 680         ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides);
 681
 682         fsl_ehci_hc_driver.product_desc =
 683                         "Freescale On-Chip EHCI Host Controller";
 684         fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset;
 685
 686
 687         return platform_driver_register(&ehci_fsl_driver);
 688 }
 689 module_init(ehci_fsl_init);
 690
 691 static void __exit ehci_fsl_cleanup(void)
 692 {
 693         platform_driver_unregister(&ehci_fsl_driver);
 694 }
 695 module_exit(ehci_fsl_cleanup);
 696
 697 MODULE_DESCRIPTION(DRIVER_DESC);
 698 MODULE_LICENSE("GPL");
 699 MODULE_ALIAS("platform:" DRV_NAME);