2 * Enhanced Host Controller Interface (EHCI) driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * Copyright (c) 2000-2004 by David Brownell
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/dmapool.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/vmalloc.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/hrtimer.h>
34 #include <linux/list.h>
35 #include <linux/interrupt.h>
36 #include <linux/usb.h>
37 #include <linux/usb/hcd.h>
38 #include <linux/moduleparam.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/debugfs.h>
41 #include <linux/slab.h>
43 #include <asm/byteorder.h>
46 #include <asm/unaligned.h>
48 #if defined(CONFIG_PPC_PS3)
49 #include <asm/firmware.h>
52 /*-------------------------------------------------------------------------*/
55 * EHCI hc_driver implementation ... experimental, incomplete.
56 * Based on the final 1.0 register interface specification.
58 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
59 * First was PCMCIA, like ISA; then CardBus, which is PCI.
60 * Next comes "CardBay", using USB 2.0 signals.
62 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
63 * Special thanks to Intel and VIA for providing host controllers to
64 * test this driver on, and Cypress (including In-System Design) for
65 * providing early devices for those host controllers to talk to!
68 #define DRIVER_AUTHOR "David Brownell"
69 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
71 static const char hcd_name [] = "ehci_hcd";
77 /* magic numbers that can affect system performance */
78 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
79 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
80 #define EHCI_TUNE_RL_TT 0
81 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
82 #define EHCI_TUNE_MULT_TT 1
84 * Some drivers think it's safe to schedule isochronous transfers more than
85 * 256 ms into the future (partly as a result of an old bug in the scheduling
86 * code). In an attempt to avoid trouble, we will use a minimum scheduling
87 * length of 512 frames instead of 256.
89 #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
91 /* Initial IRQ latency: faster than hw default */
92 static int log2_irq_thresh = 0; // 0 to 6
93 module_param (log2_irq_thresh, int, S_IRUGO);
94 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
96 /* initial park setting: slower than hw default */
97 static unsigned park = 0;
98 module_param (park, uint, S_IRUGO);
99 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
101 /* for flakey hardware, ignore overcurrent indicators */
102 static bool ignore_oc = 0;
103 module_param (ignore_oc, bool, S_IRUGO);
104 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
106 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
108 /*-------------------------------------------------------------------------*/
111 #include "pci-quirks.h"
114 * The MosChip MCS9990 controller updates its microframe counter
115 * a little before the frame counter, and occasionally we will read
116 * the invalid intermediate value. Avoid problems by checking the
117 * microframe number (the low-order 3 bits); if they are 0 then
118 * re-read the register to get the correct value.
120 static unsigned ehci_moschip_read_frame_index(struct ehci_hcd *ehci)
124 uf = ehci_readl(ehci, &ehci->regs->frame_index);
125 if (unlikely((uf & 7) == 0))
126 uf = ehci_readl(ehci, &ehci->regs->frame_index);
130 static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
132 if (ehci->frame_index_bug)
133 return ehci_moschip_read_frame_index(ehci);
134 return ehci_readl(ehci, &ehci->regs->frame_index);
137 #include "ehci-dbg.c"
139 /*-------------------------------------------------------------------------*/
142 * handshake - spin reading hc until handshake completes or fails
143 * @ptr: address of hc register to be read
144 * @mask: bits to look at in result of read
145 * @done: value of those bits when handshake succeeds
146 * @usec: timeout in microseconds
148 * Returns negative errno, or zero on success
150 * Success happens when the "mask" bits have the specified value (hardware
151 * handshake done). There are two failure modes: "usec" have passed (major
152 * hardware flakeout), or the register reads as all-ones (hardware removed).
154 * That last failure should_only happen in cases like physical cardbus eject
155 * before driver shutdown. But it also seems to be caused by bugs in cardbus
156 * bridge shutdown: shutting down the bridge before the devices using it.
158 static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
159 u32 mask, u32 done, int usec)
164 result = ehci_readl(ehci, ptr);
165 if (result == ~(u32)0) /* card removed */
176 /* check TDI/ARC silicon is in host mode */
177 static int tdi_in_host_mode (struct ehci_hcd *ehci)
181 tmp = ehci_readl(ehci, &ehci->regs->usbmode);
182 return (tmp & 3) == USBMODE_CM_HC;
186 * Force HC to halt state from unknown (EHCI spec section 2.3).
187 * Must be called with interrupts enabled and the lock not held.
189 static int ehci_halt (struct ehci_hcd *ehci)
193 spin_lock_irq(&ehci->lock);
195 /* disable any irqs left enabled by previous code */
196 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
198 if (ehci_is_TDI(ehci) && !tdi_in_host_mode(ehci)) {
199 spin_unlock_irq(&ehci->lock);
204 * This routine gets called during probe before ehci->command
205 * has been initialized, so we can't rely on its value.
207 ehci->command &= ~CMD_RUN;
208 temp = ehci_readl(ehci, &ehci->regs->command);
209 temp &= ~(CMD_RUN | CMD_IAAD);
210 ehci_writel(ehci, temp, &ehci->regs->command);
212 spin_unlock_irq(&ehci->lock);
213 synchronize_irq(ehci_to_hcd(ehci)->irq);
215 return handshake(ehci, &ehci->regs->status,
216 STS_HALT, STS_HALT, 16 * 125);
219 /* put TDI/ARC silicon into EHCI mode */
220 static void tdi_reset (struct ehci_hcd *ehci)
224 tmp = ehci_readl(ehci, &ehci->regs->usbmode);
225 tmp |= USBMODE_CM_HC;
226 /* The default byte access to MMR space is LE after
227 * controller reset. Set the required endian mode
228 * for transfer buffers to match the host microprocessor
230 if (ehci_big_endian_mmio(ehci))
232 ehci_writel(ehci, tmp, &ehci->regs->usbmode);
236 * Reset a non-running (STS_HALT == 1) controller.
237 * Must be called with interrupts enabled and the lock not held.
239 static int ehci_reset (struct ehci_hcd *ehci)
242 u32 command = ehci_readl(ehci, &ehci->regs->command);
244 /* If the EHCI debug controller is active, special care must be
245 * taken before and after a host controller reset */
246 if (ehci->debug && !dbgp_reset_prep(ehci_to_hcd(ehci)))
249 command |= CMD_RESET;
250 dbg_cmd (ehci, "reset", command);
251 ehci_writel(ehci, command, &ehci->regs->command);
252 ehci->rh_state = EHCI_RH_HALTED;
253 ehci->next_statechange = jiffies;
254 retval = handshake (ehci, &ehci->regs->command,
255 CMD_RESET, 0, 250 * 1000);
257 if (ehci->has_hostpc) {
258 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
259 &ehci->regs->usbmode_ex);
260 ehci_writel(ehci, TXFIFO_DEFAULT, &ehci->regs->txfill_tuning);
265 if (ehci_is_TDI(ehci))
269 dbgp_external_startup(ehci_to_hcd(ehci));
271 ehci->port_c_suspend = ehci->suspended_ports =
272 ehci->resuming_ports = 0;
277 * Idle the controller (turn off the schedules).
278 * Must be called with interrupts enabled and the lock not held.
280 static void ehci_quiesce (struct ehci_hcd *ehci)
284 if (ehci->rh_state != EHCI_RH_RUNNING)
287 /* wait for any schedule enables/disables to take effect */
288 temp = (ehci->command << 10) & (STS_ASS | STS_PSS);
289 handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, temp, 16 * 125);
291 /* then disable anything that's still active */
292 spin_lock_irq(&ehci->lock);
293 ehci->command &= ~(CMD_ASE | CMD_PSE);
294 ehci_writel(ehci, ehci->command, &ehci->regs->command);
295 spin_unlock_irq(&ehci->lock);
297 /* hardware can take 16 microframes to turn off ... */
298 handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, 0, 16 * 125);
301 /*-------------------------------------------------------------------------*/
303 static void end_unlink_async(struct ehci_hcd *ehci);
304 static void unlink_empty_async(struct ehci_hcd *ehci);
305 static void ehci_work(struct ehci_hcd *ehci);
306 static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
307 static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
309 #include "ehci-timer.c"
310 #include "ehci-hub.c"
311 #include "ehci-mem.c"
313 #include "ehci-sched.c"
314 #include "ehci-sysfs.c"
316 /*-------------------------------------------------------------------------*/
318 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
319 * The firmware seems to think that powering off is a wakeup event!
320 * This routine turns off remote wakeup and everything else, on all ports.
322 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
324 int port = HCS_N_PORTS(ehci->hcs_params);
327 ehci_writel(ehci, PORT_RWC_BITS,
328 &ehci->regs->port_status[port]);
332 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
333 * Must be called with interrupts enabled and the lock not held.
335 static void ehci_silence_controller(struct ehci_hcd *ehci)
339 spin_lock_irq(&ehci->lock);
340 ehci->rh_state = EHCI_RH_HALTED;
341 ehci_turn_off_all_ports(ehci);
343 /* make BIOS/etc use companion controller during reboot */
344 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
346 /* unblock posted writes */
347 ehci_readl(ehci, &ehci->regs->configured_flag);
348 spin_unlock_irq(&ehci->lock);
351 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
352 * This forcibly disables dma and IRQs, helping kexec and other cases
353 * where the next system software may expect clean state.
355 static void ehci_shutdown(struct usb_hcd *hcd)
357 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
359 spin_lock_irq(&ehci->lock);
360 ehci->shutdown = true;
361 ehci->rh_state = EHCI_RH_STOPPING;
362 ehci->enabled_hrtimer_events = 0;
363 spin_unlock_irq(&ehci->lock);
365 ehci_silence_controller(ehci);
367 hrtimer_cancel(&ehci->hrtimer);
370 /*-------------------------------------------------------------------------*/
373 * ehci_work is called from some interrupts, timers, and so on.
374 * it calls driver completion functions, after dropping ehci->lock.
376 static void ehci_work (struct ehci_hcd *ehci)
378 /* another CPU may drop ehci->lock during a schedule scan while
379 * it reports urb completions. this flag guards against bogus
380 * attempts at re-entrant schedule scanning.
382 if (ehci->scanning) {
383 ehci->need_rescan = true;
386 ehci->scanning = true;
389 ehci->need_rescan = false;
390 if (ehci->async_count)
392 if (ehci->intr_count > 0)
394 if (ehci->isoc_count > 0)
396 if (ehci->need_rescan)
398 ehci->scanning = false;
400 /* the IO watchdog guards against hardware or driver bugs that
401 * misplace IRQs, and should let us run completely without IRQs.
402 * such lossage has been observed on both VT6202 and VT8235.
404 turn_on_io_watchdog(ehci);
408 * Called when the ehci_hcd module is removed.
410 static void ehci_stop (struct usb_hcd *hcd)
412 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
414 ehci_dbg (ehci, "stop\n");
416 /* no more interrupts ... */
418 spin_lock_irq(&ehci->lock);
419 ehci->enabled_hrtimer_events = 0;
420 spin_unlock_irq(&ehci->lock);
423 ehci_silence_controller(ehci);
426 hrtimer_cancel(&ehci->hrtimer);
427 remove_sysfs_files(ehci);
428 remove_debug_files (ehci);
430 /* root hub is shut down separately (first, when possible) */
431 spin_lock_irq (&ehci->lock);
433 spin_unlock_irq (&ehci->lock);
434 ehci_mem_cleanup (ehci);
436 if (ehci->amd_pll_fix == 1)
440 ehci_dbg(ehci, "irq normal %ld err %ld iaa %ld (lost %ld)\n",
441 ehci->stats.normal, ehci->stats.error, ehci->stats.iaa,
442 ehci->stats.lost_iaa);
443 ehci_dbg (ehci, "complete %ld unlink %ld\n",
444 ehci->stats.complete, ehci->stats.unlink);
447 dbg_status (ehci, "ehci_stop completed",
448 ehci_readl(ehci, &ehci->regs->status));
451 /* one-time init, only for memory state */
452 static int ehci_init(struct usb_hcd *hcd)
454 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
458 struct ehci_qh_hw *hw;
460 spin_lock_init(&ehci->lock);
463 * keep io watchdog by default, those good HCDs could turn off it later
465 ehci->need_io_watchdog = 1;
467 hrtimer_init(&ehci->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
468 ehci->hrtimer.function = ehci_hrtimer_func;
469 ehci->next_hrtimer_event = EHCI_HRTIMER_NO_EVENT;
471 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
474 * by default set standard 80% (== 100 usec/uframe) max periodic
475 * bandwidth as required by USB 2.0
477 ehci->uframe_periodic_max = 100;
480 * hw default: 1K periodic list heads, one per frame.
481 * periodic_size can shrink by USBCMD update if hcc_params allows.
483 ehci->periodic_size = DEFAULT_I_TDPS;
484 INIT_LIST_HEAD(&ehci->intr_qh_list);
485 INIT_LIST_HEAD(&ehci->cached_itd_list);
486 INIT_LIST_HEAD(&ehci->cached_sitd_list);
488 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
489 /* periodic schedule size can be smaller than default */
490 switch (EHCI_TUNE_FLS) {
491 case 0: ehci->periodic_size = 1024; break;
492 case 1: ehci->periodic_size = 512; break;
493 case 2: ehci->periodic_size = 256; break;
497 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
500 /* controllers may cache some of the periodic schedule ... */
501 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
503 else // N microframes cached
504 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
507 * dedicate a qh for the async ring head, since we couldn't unlink
508 * a 'real' qh without stopping the async schedule [4.8]. use it
509 * as the 'reclamation list head' too.
510 * its dummy is used in hw_alt_next of many tds, to prevent the qh
511 * from automatically advancing to the next td after short reads.
513 ehci->async->qh_next.qh = NULL;
514 hw = ehci->async->hw;
515 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
516 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
517 #if defined(CONFIG_PPC_PS3)
518 hw->hw_info1 |= cpu_to_hc32(ehci, QH_INACTIVATE);
520 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
521 hw->hw_qtd_next = EHCI_LIST_END(ehci);
522 ehci->async->qh_state = QH_STATE_LINKED;
523 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
525 /* clear interrupt enables, set irq latency */
526 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
528 temp = 1 << (16 + log2_irq_thresh);
529 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
531 ehci_dbg(ehci, "enable per-port change event\n");
534 if (HCC_CANPARK(hcc_params)) {
535 /* HW default park == 3, on hardware that supports it (like
536 * NVidia and ALI silicon), maximizes throughput on the async
537 * schedule by avoiding QH fetches between transfers.
539 * With fast usb storage devices and NForce2, "park" seems to
540 * make problems: throughput reduction (!), data errors...
543 park = min(park, (unsigned) 3);
547 ehci_dbg(ehci, "park %d\n", park);
549 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
550 /* periodic schedule size can be smaller than default */
552 temp |= (EHCI_TUNE_FLS << 2);
554 ehci->command = temp;
556 /* Accept arbitrarily long scatter-gather lists */
557 if (!(hcd->driver->flags & HCD_LOCAL_MEM))
558 hcd->self.sg_tablesize = ~0;
562 /* start HC running; it's halted, ehci_init() has been run (once) */
563 static int ehci_run (struct usb_hcd *hcd)
565 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
569 hcd->uses_new_polling = 1;
571 /* EHCI spec section 4.1 */
573 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
574 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
577 * hcc_params controls whether ehci->regs->segment must (!!!)
578 * be used; it constrains QH/ITD/SITD and QTD locations.
579 * pci_pool consistent memory always uses segment zero.
580 * streaming mappings for I/O buffers, like pci_map_single(),
581 * can return segments above 4GB, if the device allows.
583 * NOTE: the dma mask is visible through dma_supported(), so
584 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
585 * Scsi_Host.highmem_io, and so forth. It's readonly to all
586 * host side drivers though.
588 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
589 if (HCC_64BIT_ADDR(hcc_params)) {
590 ehci_writel(ehci, 0, &ehci->regs->segment);
592 // this is deeply broken on almost all architectures
593 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
594 ehci_info(ehci, "enabled 64bit DMA\n");
599 // Philips, Intel, and maybe others need CMD_RUN before the
600 // root hub will detect new devices (why?); NEC doesn't
601 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
602 ehci->command |= CMD_RUN;
603 ehci_writel(ehci, ehci->command, &ehci->regs->command);
604 dbg_cmd (ehci, "init", ehci->command);
607 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
608 * are explicitly handed to companion controller(s), so no TT is
609 * involved with the root hub. (Except where one is integrated,
610 * and there's no companion controller unless maybe for USB OTG.)
612 * Turning on the CF flag will transfer ownership of all ports
613 * from the companions to the EHCI controller. If any of the
614 * companions are in the middle of a port reset at the time, it
615 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
616 * guarantees that no resets are in progress. After we set CF,
617 * a short delay lets the hardware catch up; new resets shouldn't
618 * be started before the port switching actions could complete.
620 down_write(&ehci_cf_port_reset_rwsem);
621 ehci->rh_state = EHCI_RH_RUNNING;
622 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
623 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
625 up_write(&ehci_cf_port_reset_rwsem);
626 ehci->last_periodic_enable = ktime_get_real();
628 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
630 "USB %x.%x started, EHCI %x.%02x%s\n",
631 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
632 temp >> 8, temp & 0xff,
633 ignore_oc ? ", overcurrent ignored" : "");
635 ehci_writel(ehci, INTR_MASK,
636 &ehci->regs->intr_enable); /* Turn On Interrupts */
638 /* GRR this is run-once init(), being done every time the HC starts.
639 * So long as they're part of class devices, we can't do it init()
640 * since the class device isn't created that early.
642 create_debug_files(ehci);
643 create_sysfs_files(ehci);
648 int ehci_setup(struct usb_hcd *hcd)
650 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
653 ehci->regs = (void __iomem *)ehci->caps +
654 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
655 dbg_hcs_params(ehci, "reset");
656 dbg_hcc_params(ehci, "reset");
658 /* cache this readonly data; minimize chip reads */
659 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
661 ehci->sbrn = HCD_USB2;
663 /* data structure init */
664 retval = ehci_init(hcd);
668 retval = ehci_halt(ehci);
672 if (ehci_is_TDI(ehci))
679 EXPORT_SYMBOL_GPL(ehci_setup);
681 /*-------------------------------------------------------------------------*/
683 static irqreturn_t ehci_irq (struct usb_hcd *hcd)
685 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
686 u32 status, masked_status, pcd_status = 0, cmd;
689 spin_lock (&ehci->lock);
691 status = ehci_readl(ehci, &ehci->regs->status);
693 /* e.g. cardbus physical eject */
694 if (status == ~(u32) 0) {
695 ehci_dbg (ehci, "device removed\n");
700 * We don't use STS_FLR, but some controllers don't like it to
701 * remain on, so mask it out along with the other status bits.
703 masked_status = status & (INTR_MASK | STS_FLR);
706 if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
707 spin_unlock(&ehci->lock);
711 /* clear (just) interrupts */
712 ehci_writel(ehci, masked_status, &ehci->regs->status);
713 cmd = ehci_readl(ehci, &ehci->regs->command);
717 /* unrequested/ignored: Frame List Rollover */
718 dbg_status (ehci, "irq", status);
721 /* INT, ERR, and IAA interrupt rates can be throttled */
723 /* normal [4.15.1.2] or error [4.15.1.1] completion */
724 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
725 if (likely ((status & STS_ERR) == 0))
726 COUNT (ehci->stats.normal);
728 COUNT (ehci->stats.error);
732 /* complete the unlinking of some qh [4.15.2.3] */
733 if (status & STS_IAA) {
735 /* Turn off the IAA watchdog */
736 ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_IAA_WATCHDOG);
739 * Mild optimization: Allow another IAAD to reset the
740 * hrtimer, if one occurs before the next expiration.
741 * In theory we could always cancel the hrtimer, but
742 * tests show that about half the time it will be reset
743 * for some other event anyway.
745 if (ehci->next_hrtimer_event == EHCI_HRTIMER_IAA_WATCHDOG)
746 ++ehci->next_hrtimer_event;
748 /* guard against (alleged) silicon errata */
750 ehci_dbg(ehci, "IAA with IAAD still set?\n");
751 if (ehci->async_iaa) {
752 COUNT(ehci->stats.iaa);
753 end_unlink_async(ehci);
755 ehci_dbg(ehci, "IAA with nothing unlinked?\n");
758 /* remote wakeup [4.3.1] */
759 if (status & STS_PCD) {
760 unsigned i = HCS_N_PORTS (ehci->hcs_params);
763 /* kick root hub later */
766 /* resume root hub? */
767 if (ehci->rh_state == EHCI_RH_SUSPENDED)
768 usb_hcd_resume_root_hub(hcd);
770 /* get per-port change detect bits */
777 /* leverage per-port change bits feature */
778 if (ehci->has_ppcd && !(ppcd & (1 << i)))
780 pstatus = ehci_readl(ehci,
781 &ehci->regs->port_status[i]);
783 if (pstatus & PORT_OWNER)
785 if (!(test_bit(i, &ehci->suspended_ports) &&
786 ((pstatus & PORT_RESUME) ||
787 !(pstatus & PORT_SUSPEND)) &&
788 (pstatus & PORT_PE) &&
789 ehci->reset_done[i] == 0))
792 /* start 20 msec resume signaling from this port,
793 * and make khubd collect PORT_STAT_C_SUSPEND to
794 * stop that signaling. Use 5 ms extra for safety,
795 * like usb_port_resume() does.
797 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
798 set_bit(i, &ehci->resuming_ports);
799 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
800 usb_hcd_start_port_resume(&hcd->self, i);
801 mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
805 /* PCI errors [4.15.2.4] */
806 if (unlikely ((status & STS_FATAL) != 0)) {
807 ehci_err(ehci, "fatal error\n");
808 dbg_cmd(ehci, "fatal", cmd);
809 dbg_status(ehci, "fatal", status);
813 /* Don't let the controller do anything more */
814 ehci->shutdown = true;
815 ehci->rh_state = EHCI_RH_STOPPING;
816 ehci->command &= ~(CMD_RUN | CMD_ASE | CMD_PSE);
817 ehci_writel(ehci, ehci->command, &ehci->regs->command);
818 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
819 ehci_handle_controller_death(ehci);
821 /* Handle completions when the controller stops */
827 spin_unlock (&ehci->lock);
829 usb_hcd_poll_rh_status(hcd);
833 /*-------------------------------------------------------------------------*/
836 * non-error returns are a promise to giveback() the urb later
837 * we drop ownership so next owner (or urb unlink) can get it
839 * urb + dev is in hcd.self.controller.urb_list
840 * we're queueing TDs onto software and hardware lists
842 * hcd-specific init for hcpriv hasn't been done yet
844 * NOTE: control, bulk, and interrupt share the same code to append TDs
845 * to a (possibly active) QH, and the same QH scanning code.
847 static int ehci_urb_enqueue (
852 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
853 struct list_head qtd_list;
855 INIT_LIST_HEAD (&qtd_list);
857 switch (usb_pipetype (urb->pipe)) {
859 /* qh_completions() code doesn't handle all the fault cases
860 * in multi-TD control transfers. Even 1KB is rare anyway.
862 if (urb->transfer_buffer_length > (16 * 1024))
865 /* case PIPE_BULK: */
867 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
869 return submit_async(ehci, urb, &qtd_list, mem_flags);
872 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
874 return intr_submit(ehci, urb, &qtd_list, mem_flags);
876 case PIPE_ISOCHRONOUS:
877 if (urb->dev->speed == USB_SPEED_HIGH)
878 return itd_submit (ehci, urb, mem_flags);
880 return sitd_submit (ehci, urb, mem_flags);
884 /* remove from hardware lists
885 * completions normally happen asynchronously
888 static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
890 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
895 spin_lock_irqsave (&ehci->lock, flags);
896 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
900 switch (usb_pipetype (urb->pipe)) {
901 // case PIPE_CONTROL:
904 qh = (struct ehci_qh *) urb->hcpriv;
907 switch (qh->qh_state) {
908 case QH_STATE_LINKED:
909 case QH_STATE_COMPLETING:
910 start_unlink_async(ehci, qh);
912 case QH_STATE_UNLINK:
913 case QH_STATE_UNLINK_WAIT:
914 /* already started */
917 /* QH might be waiting for a Clear-TT-Buffer */
918 qh_completions(ehci, qh);
924 qh = (struct ehci_qh *) urb->hcpriv;
927 switch (qh->qh_state) {
928 case QH_STATE_LINKED:
929 case QH_STATE_COMPLETING:
930 start_unlink_intr(ehci, qh);
933 qh_completions (ehci, qh);
936 ehci_dbg (ehci, "bogus qh %p state %d\n",
942 case PIPE_ISOCHRONOUS:
945 // wait till next completion, do it then.
946 // completion irqs can wait up to 1024 msec,
950 spin_unlock_irqrestore (&ehci->lock, flags);
954 /*-------------------------------------------------------------------------*/
956 // bulk qh holds the data toggle
959 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
961 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
963 struct ehci_qh *qh, *tmp;
965 /* ASSERT: any requests/urbs are being unlinked */
966 /* ASSERT: nobody can be submitting urbs for this any more */
969 spin_lock_irqsave (&ehci->lock, flags);
974 /* endpoints can be iso streams. for now, we don't
975 * accelerate iso completions ... so spin a while.
977 if (qh->hw == NULL) {
978 struct ehci_iso_stream *stream = ep->hcpriv;
980 if (!list_empty(&stream->td_list))
983 /* BUG_ON(!list_empty(&stream->free_list)); */
988 if (ehci->rh_state < EHCI_RH_RUNNING)
989 qh->qh_state = QH_STATE_IDLE;
990 switch (qh->qh_state) {
991 case QH_STATE_LINKED:
992 case QH_STATE_COMPLETING:
993 for (tmp = ehci->async->qh_next.qh;
995 tmp = tmp->qh_next.qh)
997 /* periodic qh self-unlinks on empty, and a COMPLETING qh
998 * may already be unlinked.
1001 start_unlink_async(ehci, qh);
1003 case QH_STATE_UNLINK: /* wait for hw to finish? */
1004 case QH_STATE_UNLINK_WAIT:
1006 spin_unlock_irqrestore (&ehci->lock, flags);
1007 schedule_timeout_uninterruptible(1);
1009 case QH_STATE_IDLE: /* fully unlinked */
1010 if (qh->clearing_tt)
1012 if (list_empty (&qh->qtd_list)) {
1013 qh_destroy(ehci, qh);
1016 /* else FALL THROUGH */
1018 /* caller was supposed to have unlinked any requests;
1019 * that's not our job. just leak this memory.
1021 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1022 qh, ep->desc.bEndpointAddress, qh->qh_state,
1023 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1028 spin_unlock_irqrestore (&ehci->lock, flags);
1032 ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1034 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1036 int eptype = usb_endpoint_type(&ep->desc);
1037 int epnum = usb_endpoint_num(&ep->desc);
1038 int is_out = usb_endpoint_dir_out(&ep->desc);
1039 unsigned long flags;
1041 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1044 spin_lock_irqsave(&ehci->lock, flags);
1047 /* For Bulk and Interrupt endpoints we maintain the toggle state
1048 * in the hardware; the toggle bits in udev aren't used at all.
1049 * When an endpoint is reset by usb_clear_halt() we must reset
1050 * the toggle bit in the QH.
1053 usb_settoggle(qh->dev, epnum, is_out, 0);
1054 if (!list_empty(&qh->qtd_list)) {
1055 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1056 } else if (qh->qh_state == QH_STATE_LINKED ||
1057 qh->qh_state == QH_STATE_COMPLETING) {
1059 /* The toggle value in the QH can't be updated
1060 * while the QH is active. Unlink it now;
1061 * re-linking will call qh_refresh().
1063 if (eptype == USB_ENDPOINT_XFER_BULK)
1064 start_unlink_async(ehci, qh);
1066 start_unlink_intr(ehci, qh);
1069 spin_unlock_irqrestore(&ehci->lock, flags);
1072 static int ehci_get_frame (struct usb_hcd *hcd)
1074 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1075 return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size;
1078 /*-------------------------------------------------------------------------*/
1082 /* suspend/resume, section 4.3 */
1084 /* These routines handle the generic parts of controller suspend/resume */
1086 int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1088 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1090 if (time_before(jiffies, ehci->next_statechange))
1094 * Root hub was already suspended. Disable IRQ emission and
1095 * mark HW unaccessible. The PM and USB cores make sure that
1096 * the root hub is either suspended or stopped.
1098 ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
1100 spin_lock_irq(&ehci->lock);
1101 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
1102 (void) ehci_readl(ehci, &ehci->regs->intr_enable);
1104 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1105 spin_unlock_irq(&ehci->lock);
1109 EXPORT_SYMBOL_GPL(ehci_suspend);
1111 /* Returns 0 if power was preserved, 1 if power was lost */
1112 int ehci_resume(struct usb_hcd *hcd, bool hibernated)
1114 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1116 if (time_before(jiffies, ehci->next_statechange))
1119 /* Mark hardware accessible again as we are back to full power by now */
1120 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1123 return 0; /* Controller is dead */
1126 * If CF is still set and we aren't resuming from hibernation
1127 * then we maintained suspend power.
1128 * Just undo the effect of ehci_suspend().
1130 if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
1132 int mask = INTR_MASK;
1134 ehci_prepare_ports_for_controller_resume(ehci);
1136 spin_lock_irq(&ehci->lock);
1140 if (!hcd->self.root_hub->do_remote_wakeup)
1142 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
1143 ehci_readl(ehci, &ehci->regs->intr_enable);
1145 spin_unlock_irq(&ehci->lock);
1150 * Else reset, to cope with power loss or resume from hibernation
1151 * having let the firmware kick in during reboot.
1153 usb_root_hub_lost_power(hcd->self.root_hub);
1154 (void) ehci_halt(ehci);
1155 (void) ehci_reset(ehci);
1157 spin_lock_irq(&ehci->lock);
1161 ehci_writel(ehci, ehci->command, &ehci->regs->command);
1162 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
1163 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
1165 ehci->rh_state = EHCI_RH_SUSPENDED;
1166 spin_unlock_irq(&ehci->lock);
1170 EXPORT_SYMBOL_GPL(ehci_resume);
1174 /*-------------------------------------------------------------------------*/
1177 * Generic structure: This gets copied for platform drivers so that
1178 * individual entries can be overridden as needed.
1181 static const struct hc_driver ehci_hc_driver = {
1182 .description = hcd_name,
1183 .product_desc = "EHCI Host Controller",
1184 .hcd_priv_size = sizeof(struct ehci_hcd),
1187 * generic hardware linkage
1190 .flags = HCD_MEMORY | HCD_USB2,
1193 * basic lifecycle operations
1195 .reset = ehci_setup,
1198 .shutdown = ehci_shutdown,
1201 * managing i/o requests and associated device resources
1203 .urb_enqueue = ehci_urb_enqueue,
1204 .urb_dequeue = ehci_urb_dequeue,
1205 .endpoint_disable = ehci_endpoint_disable,
1206 .endpoint_reset = ehci_endpoint_reset,
1207 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
1210 * scheduling support
1212 .get_frame_number = ehci_get_frame,
1217 .hub_status_data = ehci_hub_status_data,
1218 .hub_control = ehci_hub_control,
1219 .bus_suspend = ehci_bus_suspend,
1220 .bus_resume = ehci_bus_resume,
1221 .relinquish_port = ehci_relinquish_port,
1222 .port_handed_over = ehci_port_handed_over,
1225 void ehci_init_driver(struct hc_driver *drv,
1226 const struct ehci_driver_overrides *over)
1228 /* Copy the generic table to drv and then apply the overrides */
1229 *drv = ehci_hc_driver;
1232 drv->hcd_priv_size += over->extra_priv_size;
1234 drv->reset = over->reset;
1237 EXPORT_SYMBOL_GPL(ehci_init_driver);
1239 /*-------------------------------------------------------------------------*/
1241 MODULE_DESCRIPTION(DRIVER_DESC);
1242 MODULE_AUTHOR (DRIVER_AUTHOR);
1243 MODULE_LICENSE ("GPL");
1245 #ifdef CONFIG_USB_EHCI_FSL
1246 #include "ehci-fsl.c"
1247 #define PLATFORM_DRIVER ehci_fsl_driver
1250 #ifdef CONFIG_USB_EHCI_SH
1251 #include "ehci-sh.c"
1252 #define PLATFORM_DRIVER ehci_hcd_sh_driver
1255 #ifdef CONFIG_USB_EHCI_HCD_OMAP
1256 #include "ehci-omap.c"
1257 #define PLATFORM_DRIVER ehci_hcd_omap_driver
1260 #ifdef CONFIG_PPC_PS3
1261 #include "ehci-ps3.c"
1262 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
1265 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1266 #include "ehci-ppc-of.c"
1267 #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1270 #ifdef CONFIG_XPS_USB_HCD_XILINX
1271 #include "ehci-xilinx-of.c"
1272 #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
1275 #ifdef CONFIG_PLAT_ORION
1276 #include "ehci-orion.c"
1277 #define PLATFORM_DRIVER ehci_orion_driver
1280 #ifdef CONFIG_USB_W90X900_EHCI
1281 #include "ehci-w90x900.c"
1282 #define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1285 #ifdef CONFIG_ARCH_AT91
1286 #include "ehci-atmel.c"
1287 #define PLATFORM_DRIVER ehci_atmel_driver
1290 #ifdef CONFIG_USB_OCTEON_EHCI
1291 #include "ehci-octeon.c"
1292 #define PLATFORM_DRIVER ehci_octeon_driver
1295 #ifdef CONFIG_ARCH_VT8500
1296 #include "ehci-vt8500.c"
1297 #define PLATFORM_DRIVER vt8500_ehci_driver
1300 #ifdef CONFIG_PLAT_SPEAR
1301 #include "ehci-spear.c"
1302 #define PLATFORM_DRIVER spear_ehci_hcd_driver
1305 #ifdef CONFIG_USB_EHCI_MSM
1306 #include "ehci-msm.c"
1307 #define PLATFORM_DRIVER ehci_msm_driver
1310 #ifdef CONFIG_TILE_USB
1311 #include "ehci-tilegx.c"
1312 #define PLATFORM_DRIVER ehci_hcd_tilegx_driver
1315 #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
1316 #include "ehci-pmcmsp.c"
1317 #define PLATFORM_DRIVER ehci_hcd_msp_driver
1320 #ifdef CONFIG_USB_EHCI_TEGRA
1321 #include "ehci-tegra.c"
1322 #define PLATFORM_DRIVER tegra_ehci_driver
1325 #ifdef CONFIG_USB_EHCI_S5P
1326 #include "ehci-s5p.c"
1327 #define PLATFORM_DRIVER s5p_ehci_driver
1330 #ifdef CONFIG_SPARC_LEON
1331 #include "ehci-grlib.c"
1332 #define PLATFORM_DRIVER ehci_grlib_driver
1335 #ifdef CONFIG_USB_EHCI_MV
1336 #include "ehci-mv.c"
1337 #define PLATFORM_DRIVER ehci_mv_driver
1340 #ifdef CONFIG_MIPS_SEAD3
1341 #include "ehci-sead3.c"
1342 #define PLATFORM_DRIVER ehci_hcd_sead3_driver
1345 #if !IS_ENABLED(CONFIG_USB_EHCI_PCI) && \
1346 !IS_ENABLED(CONFIG_USB_EHCI_HCD_PLATFORM) && \
1347 !IS_ENABLED(CONFIG_USB_CHIPIDEA_HOST) && \
1348 !IS_ENABLED(CONFIG_USB_EHCI_MXC) && \
1349 !defined(PLATFORM_DRIVER) && \
1350 !defined(PS3_SYSTEM_BUS_DRIVER) && \
1351 !defined(OF_PLATFORM_DRIVER) && \
1352 !defined(XILINX_OF_PLATFORM_DRIVER)
1353 #error "missing bus glue for ehci-hcd"
1356 static int __init ehci_hcd_init(void)
1363 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1364 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1365 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1366 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1367 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1368 " before uhci_hcd and ohci_hcd, not after\n");
1370 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1372 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1373 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1376 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1377 if (!ehci_debug_root) {
1383 #ifdef PLATFORM_DRIVER
1384 retval = platform_driver_register(&PLATFORM_DRIVER);
1389 #ifdef PS3_SYSTEM_BUS_DRIVER
1390 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1395 #ifdef OF_PLATFORM_DRIVER
1396 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1401 #ifdef XILINX_OF_PLATFORM_DRIVER
1402 retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER);
1408 #ifdef XILINX_OF_PLATFORM_DRIVER
1409 /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */
1412 #ifdef OF_PLATFORM_DRIVER
1413 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1416 #ifdef PS3_SYSTEM_BUS_DRIVER
1417 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1420 #ifdef PLATFORM_DRIVER
1421 platform_driver_unregister(&PLATFORM_DRIVER);
1425 debugfs_remove(ehci_debug_root);
1426 ehci_debug_root = NULL;
1429 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1432 module_init(ehci_hcd_init);
1434 static void __exit ehci_hcd_cleanup(void)
1436 #ifdef XILINX_OF_PLATFORM_DRIVER
1437 platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
1439 #ifdef OF_PLATFORM_DRIVER
1440 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1442 #ifdef PLATFORM_DRIVER
1443 platform_driver_unregister(&PLATFORM_DRIVER);
1445 #ifdef PS3_SYSTEM_BUS_DRIVER
1446 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1449 debugfs_remove(ehci_debug_root);
1451 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1453 module_exit(ehci_hcd_cleanup);