2 * Copyright (c) 2001-2004 by David Brownell
3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 /* this file is part of ehci-hcd.c */
22 /*-------------------------------------------------------------------------*/
25 * EHCI scheduled transaction support: interrupt, iso, split iso
26 * These are called "periodic" transactions in the EHCI spec.
28 * Note that for interrupt transfers, the QH/QTD manipulation is shared
29 * with the "asynchronous" transaction support (control/bulk transfers).
30 * The only real difference is in how interrupt transfers are scheduled.
32 * For ISO, we make an "iso_stream" head to serve the same role as a QH.
33 * It keeps track of every ITD (or SITD) that's linked, and holds enough
34 * pre-calculated schedule data to make appending to the queue be quick.
37 static int ehci_get_frame (struct usb_hcd *hcd);
41 static unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
46 * The MosChip MCS9990 controller updates its microframe counter
47 * a little before the frame counter, and occasionally we will read
48 * the invalid intermediate value. Avoid problems by checking the
49 * microframe number (the low-order 3 bits); if they are 0 then
50 * re-read the register to get the correct value.
52 uf = ehci_readl(ehci, &ehci->regs->frame_index);
53 if (unlikely(ehci->frame_index_bug && ((uf & 7) == 0)))
54 uf = ehci_readl(ehci, &ehci->regs->frame_index);
60 /*-------------------------------------------------------------------------*/
63 * periodic_next_shadow - return "next" pointer on shadow list
64 * @periodic: host pointer to qh/itd/sitd
65 * @tag: hardware tag for type of this record
67 static union ehci_shadow *
68 periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
71 switch (hc32_to_cpu(ehci, tag)) {
73 return &periodic->qh->qh_next;
75 return &periodic->fstn->fstn_next;
77 return &periodic->itd->itd_next;
80 return &periodic->sitd->sitd_next;
85 shadow_next_periodic(struct ehci_hcd *ehci, union ehci_shadow *periodic,
88 switch (hc32_to_cpu(ehci, tag)) {
89 /* our ehci_shadow.qh is actually software part */
91 return &periodic->qh->hw->hw_next;
92 /* others are hw parts */
94 return periodic->hw_next;
98 /* caller must hold ehci->lock */
99 static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
101 union ehci_shadow *prev_p = &ehci->pshadow[frame];
102 __hc32 *hw_p = &ehci->periodic[frame];
103 union ehci_shadow here = *prev_p;
105 /* find predecessor of "ptr"; hw and shadow lists are in sync */
106 while (here.ptr && here.ptr != ptr) {
107 prev_p = periodic_next_shadow(ehci, prev_p,
108 Q_NEXT_TYPE(ehci, *hw_p));
109 hw_p = shadow_next_periodic(ehci, &here,
110 Q_NEXT_TYPE(ehci, *hw_p));
113 /* an interrupt entry (at list end) could have been shared */
117 /* update shadow and hardware lists ... the old "next" pointers
118 * from ptr may still be in use, the caller updates them.
120 *prev_p = *periodic_next_shadow(ehci, &here,
121 Q_NEXT_TYPE(ehci, *hw_p));
123 if (!ehci->use_dummy_qh ||
124 *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p))
125 != EHCI_LIST_END(ehci))
126 *hw_p = *shadow_next_periodic(ehci, &here,
127 Q_NEXT_TYPE(ehci, *hw_p));
129 *hw_p = ehci->dummy->qh_dma;
132 /* how many of the uframe's 125 usecs are allocated? */
133 static unsigned short
134 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
136 __hc32 *hw_p = &ehci->periodic [frame];
137 union ehci_shadow *q = &ehci->pshadow [frame];
139 struct ehci_qh_hw *hw;
142 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
145 /* is it in the S-mask? */
146 if (hw->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
147 usecs += q->qh->usecs;
149 if (hw->hw_info2 & cpu_to_hc32(ehci,
151 usecs += q->qh->c_usecs;
157 /* for "save place" FSTNs, count the relevant INTR
158 * bandwidth from the previous frame
160 if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
161 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
163 hw_p = &q->fstn->hw_next;
164 q = &q->fstn->fstn_next;
167 if (q->itd->hw_transaction[uframe])
168 usecs += q->itd->stream->usecs;
169 hw_p = &q->itd->hw_next;
170 q = &q->itd->itd_next;
173 /* is it in the S-mask? (count SPLIT, DATA) */
174 if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
176 if (q->sitd->hw_fullspeed_ep &
177 cpu_to_hc32(ehci, 1<<31))
178 usecs += q->sitd->stream->usecs;
179 else /* worst case for OUT start-split */
180 usecs += HS_USECS_ISO (188);
183 /* ... C-mask? (count CSPLIT, DATA) */
184 if (q->sitd->hw_uframe &
185 cpu_to_hc32(ehci, 1 << (8 + uframe))) {
186 /* worst case for IN complete-split */
187 usecs += q->sitd->stream->c_usecs;
190 hw_p = &q->sitd->hw_next;
191 q = &q->sitd->sitd_next;
197 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
198 frame * 8 + uframe, usecs);
203 /*-------------------------------------------------------------------------*/
205 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
207 if (!dev1->tt || !dev2->tt)
209 if (dev1->tt != dev2->tt)
212 return dev1->ttport == dev2->ttport;
217 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
219 /* Which uframe does the low/fullspeed transfer start in?
221 * The parameter is the mask of ssplits in "H-frame" terms
222 * and this returns the transfer start uframe in "B-frame" terms,
223 * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
224 * will cause a transfer in "B-frame" uframe 0. "B-frames" lag
225 * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7.
227 static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
229 unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
231 ehci_err(ehci, "invalid empty smask!\n");
232 /* uframe 7 can't have bw so this will indicate failure */
235 return ffs(smask) - 1;
238 static const unsigned char
239 max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
241 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
242 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
245 for (i=0; i<7; i++) {
246 if (max_tt_usecs[i] < tt_usecs[i]) {
247 tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
248 tt_usecs[i] = max_tt_usecs[i];
253 /* How many of the tt's periodic downstream 1000 usecs are allocated?
255 * While this measures the bandwidth in terms of usecs/uframe,
256 * the low/fullspeed bus has no notion of uframes, so any particular
257 * low/fullspeed transfer can "carry over" from one uframe to the next,
258 * since the TT just performs downstream transfers in sequence.
260 * For example two separate 100 usec transfers can start in the same uframe,
261 * and the second one would "carry over" 75 usecs into the next uframe.
265 struct ehci_hcd *ehci,
266 struct usb_device *dev,
268 unsigned short tt_usecs[8]
271 __hc32 *hw_p = &ehci->periodic [frame];
272 union ehci_shadow *q = &ehci->pshadow [frame];
275 memset(tt_usecs, 0, 16);
278 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
280 hw_p = &q->itd->hw_next;
281 q = &q->itd->itd_next;
284 if (same_tt(dev, q->qh->dev)) {
285 uf = tt_start_uframe(ehci, q->qh->hw->hw_info2);
286 tt_usecs[uf] += q->qh->tt_usecs;
288 hw_p = &q->qh->hw->hw_next;
292 if (same_tt(dev, q->sitd->urb->dev)) {
293 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
294 tt_usecs[uf] += q->sitd->stream->tt_usecs;
296 hw_p = &q->sitd->hw_next;
297 q = &q->sitd->sitd_next;
301 ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
303 hw_p = &q->fstn->hw_next;
304 q = &q->fstn->fstn_next;
308 carryover_tt_bandwidth(tt_usecs);
310 if (max_tt_usecs[7] < tt_usecs[7])
311 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
312 frame, tt_usecs[7] - max_tt_usecs[7]);
316 * Return true if the device's tt's downstream bus is available for a
317 * periodic transfer of the specified length (usecs), starting at the
318 * specified frame/uframe. Note that (as summarized in section 11.19
319 * of the usb 2.0 spec) TTs can buffer multiple transactions for each
322 * The uframe parameter is when the fullspeed/lowspeed transfer
323 * should be executed in "B-frame" terms, which is the same as the
324 * highspeed ssplit's uframe (which is in "H-frame" terms). For example
325 * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
326 * See the EHCI spec sec 4.5 and fig 4.7.
328 * This checks if the full/lowspeed bus, at the specified starting uframe,
329 * has the specified bandwidth available, according to rules listed
330 * in USB 2.0 spec section 11.18.1 fig 11-60.
332 * This does not check if the transfer would exceed the max ssplit
333 * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
334 * since proper scheduling limits ssplits to less than 16 per uframe.
336 static int tt_available (
337 struct ehci_hcd *ehci,
339 struct usb_device *dev,
345 if ((period == 0) || (uframe >= 7)) /* error */
348 for (; frame < ehci->periodic_size; frame += period) {
349 unsigned short tt_usecs[8];
351 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
353 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
354 " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
355 frame, usecs, uframe,
356 tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
357 tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
359 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
360 ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
365 /* special case for isoc transfers larger than 125us:
366 * the first and each subsequent fully used uframe
367 * must be empty, so as to not illegally delay
368 * already scheduled transactions
371 int ufs = (usecs / 125);
373 for (i = uframe; i < (uframe + ufs) && i < 8; i++)
374 if (0 < tt_usecs[i]) {
376 "multi-uframe xfer can't fit "
377 "in frame %d uframe %d\n",
383 tt_usecs[uframe] += usecs;
385 carryover_tt_bandwidth(tt_usecs);
387 /* fail if the carryover pushed bw past the last uframe's limit */
388 if (max_tt_usecs[7] < tt_usecs[7]) {
390 "tt unavailable usecs %d frame %d uframe %d\n",
391 usecs, frame, uframe);
401 /* return true iff the device's transaction translator is available
402 * for a periodic transfer starting at the specified frame, using
403 * all the uframes in the mask.
405 static int tt_no_collision (
406 struct ehci_hcd *ehci,
408 struct usb_device *dev,
413 if (period == 0) /* error */
416 /* note bandwidth wastage: split never follows csplit
417 * (different dev or endpoint) until the next uframe.
418 * calling convention doesn't make that distinction.
420 for (; frame < ehci->periodic_size; frame += period) {
421 union ehci_shadow here;
423 struct ehci_qh_hw *hw;
425 here = ehci->pshadow [frame];
426 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
428 switch (hc32_to_cpu(ehci, type)) {
430 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
431 here = here.itd->itd_next;
435 if (same_tt (dev, here.qh->dev)) {
438 mask = hc32_to_cpu(ehci,
440 /* "knows" no gap is needed */
445 type = Q_NEXT_TYPE(ehci, hw->hw_next);
446 here = here.qh->qh_next;
449 if (same_tt (dev, here.sitd->urb->dev)) {
452 mask = hc32_to_cpu(ehci, here.sitd
454 /* FIXME assumes no gap for IN! */
459 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
460 here = here.sitd->sitd_next;
465 "periodic frame %d bogus type %d\n",
469 /* collision or error */
478 #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
480 /*-------------------------------------------------------------------------*/
482 static int enable_periodic (struct ehci_hcd *ehci)
487 if (ehci->periodic_sched++)
490 /* did clearing PSE did take effect yet?
491 * takes effect only at frame boundaries...
493 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
494 STS_PSS, 0, 9 * 125);
496 usb_hc_died(ehci_to_hcd(ehci));
500 cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE;
501 ehci_writel(ehci, cmd, &ehci->regs->command);
502 /* posted write ... PSS happens later */
503 ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
505 /* make sure ehci_work scans these */
506 ehci->next_uframe = ehci_read_frame_index(ehci)
507 % (ehci->periodic_size << 3);
508 if (unlikely(ehci->broken_periodic))
509 ehci->last_periodic_enable = ktime_get_real();
513 static int disable_periodic (struct ehci_hcd *ehci)
518 if (--ehci->periodic_sched)
521 if (unlikely(ehci->broken_periodic)) {
522 /* delay experimentally determined */
523 ktime_t safe = ktime_add_us(ehci->last_periodic_enable, 1000);
524 ktime_t now = ktime_get_real();
525 s64 delay = ktime_us_delta(safe, now);
527 if (unlikely(delay > 0))
531 /* did setting PSE not take effect yet?
532 * takes effect only at frame boundaries...
534 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
535 STS_PSS, STS_PSS, 9 * 125);
537 usb_hc_died(ehci_to_hcd(ehci));
541 cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE;
542 ehci_writel(ehci, cmd, &ehci->regs->command);
543 /* posted write ... */
545 free_cached_lists(ehci);
547 ehci->next_uframe = -1;
551 /*-------------------------------------------------------------------------*/
553 /* periodic schedule slots have iso tds (normal or split) first, then a
554 * sparse tree for active interrupt transfers.
556 * this just links in a qh; caller guarantees uframe masks are set right.
557 * no FSTN support (yet; ehci 0.96+)
559 static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
562 unsigned period = qh->period;
564 dev_dbg (&qh->dev->dev,
565 "link qh%d-%04x/%p start %d [%d/%d us]\n",
566 period, hc32_to_cpup(ehci, &qh->hw->hw_info2)
567 & (QH_CMASK | QH_SMASK),
568 qh, qh->start, qh->usecs, qh->c_usecs);
570 /* high bandwidth, or otherwise every microframe */
574 for (i = qh->start; i < ehci->periodic_size; i += period) {
575 union ehci_shadow *prev = &ehci->pshadow[i];
576 __hc32 *hw_p = &ehci->periodic[i];
577 union ehci_shadow here = *prev;
580 /* skip the iso nodes at list head */
582 type = Q_NEXT_TYPE(ehci, *hw_p);
583 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
585 prev = periodic_next_shadow(ehci, prev, type);
586 hw_p = shadow_next_periodic(ehci, &here, type);
590 /* sorting each branch by period (slow-->fast)
591 * enables sharing interior tree nodes
593 while (here.ptr && qh != here.qh) {
594 if (qh->period > here.qh->period)
596 prev = &here.qh->qh_next;
597 hw_p = &here.qh->hw->hw_next;
600 /* link in this qh, unless some earlier pass did that */
604 qh->hw->hw_next = *hw_p;
607 *hw_p = QH_NEXT (ehci, qh->qh_dma);
610 qh->qh_state = QH_STATE_LINKED;
614 /* update per-qh bandwidth for usbfs */
615 ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
616 ? ((qh->usecs + qh->c_usecs) / qh->period)
619 /* maybe enable periodic schedule processing */
620 return enable_periodic(ehci);
623 static int qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh)
629 // IF this isn't high speed
630 // and this qh is active in the current uframe
631 // (and overlay token SplitXstate is false?)
633 // qh->hw_info1 |= cpu_to_hc32(1 << 7 /* "ignore" */);
635 /* high bandwidth, or otherwise part of every microframe */
636 if ((period = qh->period) == 0)
639 for (i = qh->start; i < ehci->periodic_size; i += period)
640 periodic_unlink (ehci, i, qh);
642 /* update per-qh bandwidth for usbfs */
643 ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
644 ? ((qh->usecs + qh->c_usecs) / qh->period)
647 dev_dbg (&qh->dev->dev,
648 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
650 hc32_to_cpup(ehci, &qh->hw->hw_info2) & (QH_CMASK | QH_SMASK),
651 qh, qh->start, qh->usecs, qh->c_usecs);
653 /* qh->qh_next still "live" to HC */
654 qh->qh_state = QH_STATE_UNLINK;
655 qh->qh_next.ptr = NULL;
658 /* maybe turn off periodic schedule */
659 return disable_periodic(ehci);
662 static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
665 struct ehci_qh_hw *hw = qh->hw;
668 /* If the QH isn't linked then there's nothing we can do
669 * unless we were called during a giveback, in which case
670 * qh_completions() has to deal with it.
672 if (qh->qh_state != QH_STATE_LINKED) {
673 if (qh->qh_state == QH_STATE_COMPLETING)
674 qh->needs_rescan = 1;
678 qh_unlink_periodic (ehci, qh);
680 /* simple/paranoid: always delay, expecting the HC needs to read
681 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
682 * expect khubd to clean up after any CSPLITs we won't issue.
683 * active high speed queues may need bigger delays...
685 if (list_empty (&qh->qtd_list)
686 || (cpu_to_hc32(ehci, QH_CMASK)
687 & hw->hw_info2) != 0)
690 wait = 55; /* worst case: 3 * 1024 */
693 qh->qh_state = QH_STATE_IDLE;
694 hw->hw_next = EHCI_LIST_END(ehci);
697 qh_completions(ehci, qh);
699 /* reschedule QH iff another request is queued */
700 if (!list_empty(&qh->qtd_list) &&
701 HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
702 rc = qh_schedule(ehci, qh);
704 /* An error here likely indicates handshake failure
705 * or no space left in the schedule. Neither fault
706 * should happen often ...
708 * FIXME kill the now-dysfunctional queued urbs
711 ehci_err(ehci, "can't reschedule qh %p, err %d\n",
716 /*-------------------------------------------------------------------------*/
718 static int check_period (
719 struct ehci_hcd *ehci,
727 /* complete split running into next frame?
728 * given FSTN support, we could sometimes check...
734 * 80% periodic == 100 usec/uframe available
735 * convert "usecs we need" to "max already claimed"
739 /* we "know" 2 and 4 uframe intervals were rejected; so
740 * for period 0, check _every_ microframe in the schedule.
742 if (unlikely (period == 0)) {
744 for (uframe = 0; uframe < 7; uframe++) {
745 claimed = periodic_usecs (ehci, frame, uframe);
749 } while ((frame += 1) < ehci->periodic_size);
751 /* just check the specified uframe, at that period */
754 claimed = periodic_usecs (ehci, frame, uframe);
757 } while ((frame += period) < ehci->periodic_size);
764 static int check_intr_schedule (
765 struct ehci_hcd *ehci,
768 const struct ehci_qh *qh,
772 int retval = -ENOSPC;
775 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
778 if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
786 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
787 if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
791 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
792 for (i=uframe+1; i<8 && i<uframe+4; i++)
793 if (!check_period (ehci, frame, i,
794 qh->period, qh->c_usecs))
801 *c_maskp = cpu_to_hc32(ehci, mask << 8);
804 /* Make sure this tt's buffer is also available for CSPLITs.
805 * We pessimize a bit; probably the typical full speed case
806 * doesn't need the second CSPLIT.
808 * NOTE: both SPLIT and CSPLIT could be checked in just
811 mask = 0x03 << (uframe + qh->gap_uf);
812 *c_maskp = cpu_to_hc32(ehci, mask << 8);
815 if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
816 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
817 qh->period, qh->c_usecs))
819 if (!check_period (ehci, frame, uframe + qh->gap_uf,
820 qh->period, qh->c_usecs))
829 /* "first fit" scheduling policy used the first time through,
830 * or when the previous schedule slot can't be re-used.
832 static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
837 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
838 struct ehci_qh_hw *hw = qh->hw;
840 qh_refresh(ehci, qh);
841 hw->hw_next = EHCI_LIST_END(ehci);
844 /* reuse the previous schedule slots, if we can */
845 if (frame < qh->period) {
846 uframe = ffs(hc32_to_cpup(ehci, &hw->hw_info2) & QH_SMASK);
847 status = check_intr_schedule (ehci, frame, --uframe,
855 /* else scan the schedule to find a group of slots such that all
856 * uframes have enough periodic bandwidth available.
859 /* "normal" case, uframing flexible except with splits */
863 for (i = qh->period; status && i > 0; --i) {
864 frame = ++ehci->random_frame % qh->period;
865 for (uframe = 0; uframe < 8; uframe++) {
866 status = check_intr_schedule (ehci,
874 /* qh->period == 0 means every uframe */
877 status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
883 /* reset S-frame and (maybe) C-frame masks */
884 hw->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
885 hw->hw_info2 |= qh->period
886 ? cpu_to_hc32(ehci, 1 << uframe)
887 : cpu_to_hc32(ehci, QH_SMASK);
888 hw->hw_info2 |= c_mask;
890 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
892 /* stuff into the periodic schedule */
893 status = qh_link_periodic (ehci, qh);
898 static int intr_submit (
899 struct ehci_hcd *ehci,
901 struct list_head *qtd_list,
908 struct list_head empty;
910 /* get endpoint and transfer/schedule data */
911 epnum = urb->ep->desc.bEndpointAddress;
913 spin_lock_irqsave (&ehci->lock, flags);
915 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
917 goto done_not_linked;
919 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
920 if (unlikely(status))
921 goto done_not_linked;
923 /* get qh and force any scheduling errors */
924 INIT_LIST_HEAD (&empty);
925 qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv);
930 if (qh->qh_state == QH_STATE_IDLE) {
931 if ((status = qh_schedule (ehci, qh)) != 0)
935 /* then queue the urb's tds to the qh */
936 qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
939 /* ... update usbfs periodic stats */
940 ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
943 if (unlikely(status))
944 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
946 spin_unlock_irqrestore (&ehci->lock, flags);
948 qtd_list_free (ehci, urb, qtd_list);
953 /*-------------------------------------------------------------------------*/
955 /* ehci_iso_stream ops work with both ITD and SITD */
957 static struct ehci_iso_stream *
958 iso_stream_alloc (gfp_t mem_flags)
960 struct ehci_iso_stream *stream;
962 stream = kzalloc(sizeof *stream, mem_flags);
963 if (likely (stream != NULL)) {
964 INIT_LIST_HEAD(&stream->td_list);
965 INIT_LIST_HEAD(&stream->free_list);
966 stream->next_uframe = -1;
967 stream->refcount = 1;
974 struct ehci_hcd *ehci,
975 struct ehci_iso_stream *stream,
976 struct usb_device *dev,
981 static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
984 unsigned epnum, maxp;
989 * this might be a "high bandwidth" highspeed endpoint,
990 * as encoded in the ep descriptor's wMaxPacket field
992 epnum = usb_pipeendpoint (pipe);
993 is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
994 maxp = usb_maxpacket(dev, pipe, !is_input);
1001 /* knows about ITD vs SITD */
1002 if (dev->speed == USB_SPEED_HIGH) {
1003 unsigned multi = hb_mult(maxp);
1005 stream->highspeed = 1;
1007 maxp = max_packet(maxp);
1011 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
1012 stream->buf1 = cpu_to_hc32(ehci, buf1);
1013 stream->buf2 = cpu_to_hc32(ehci, multi);
1015 /* usbfs wants to report the average usecs per frame tied up
1016 * when transfers on this endpoint are scheduled ...
1018 stream->usecs = HS_USECS_ISO (maxp);
1019 bandwidth = stream->usecs * 8;
1020 bandwidth /= interval;
1027 addr = dev->ttport << 24;
1028 if (!ehci_is_TDI(ehci)
1030 ehci_to_hcd(ehci)->self.root_hub))
1031 addr |= dev->tt->hub->devnum << 16;
1033 addr |= dev->devnum;
1034 stream->usecs = HS_USECS_ISO (maxp);
1035 think_time = dev->tt ? dev->tt->think_time : 0;
1036 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
1037 dev->speed, is_input, 1, maxp));
1038 hs_transfers = max (1u, (maxp + 187) / 188);
1043 stream->c_usecs = stream->usecs;
1044 stream->usecs = HS_USECS_ISO (1);
1045 stream->raw_mask = 1;
1047 /* c-mask as specified in USB 2.0 11.18.4 3.c */
1048 tmp = (1 << (hs_transfers + 2)) - 1;
1049 stream->raw_mask |= tmp << (8 + 2);
1051 stream->raw_mask = smask_out [hs_transfers - 1];
1052 bandwidth = stream->usecs + stream->c_usecs;
1053 bandwidth /= interval << 3;
1055 /* stream->splits gets created from raw_mask later */
1056 stream->address = cpu_to_hc32(ehci, addr);
1058 stream->bandwidth = bandwidth;
1062 stream->bEndpointAddress = is_input | epnum;
1063 stream->interval = interval;
1064 stream->maxp = maxp;
1068 iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
1072 /* free whenever just a dev->ep reference remains.
1073 * not like a QH -- no persistent state (toggle, halt)
1075 if (stream->refcount == 1) {
1076 // BUG_ON (!list_empty(&stream->td_list));
1078 while (!list_empty (&stream->free_list)) {
1079 struct list_head *entry;
1081 entry = stream->free_list.next;
1084 /* knows about ITD vs SITD */
1085 if (stream->highspeed) {
1086 struct ehci_itd *itd;
1088 itd = list_entry (entry, struct ehci_itd,
1090 dma_pool_free (ehci->itd_pool, itd,
1093 struct ehci_sitd *sitd;
1095 sitd = list_entry (entry, struct ehci_sitd,
1097 dma_pool_free (ehci->sitd_pool, sitd,
1102 stream->bEndpointAddress &= 0x0f;
1104 stream->ep->hcpriv = NULL;
1110 static inline struct ehci_iso_stream *
1111 iso_stream_get (struct ehci_iso_stream *stream)
1113 if (likely (stream != NULL))
1118 static struct ehci_iso_stream *
1119 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1122 struct ehci_iso_stream *stream;
1123 struct usb_host_endpoint *ep;
1124 unsigned long flags;
1126 epnum = usb_pipeendpoint (urb->pipe);
1127 if (usb_pipein(urb->pipe))
1128 ep = urb->dev->ep_in[epnum];
1130 ep = urb->dev->ep_out[epnum];
1132 spin_lock_irqsave (&ehci->lock, flags);
1133 stream = ep->hcpriv;
1135 if (unlikely (stream == NULL)) {
1136 stream = iso_stream_alloc(GFP_ATOMIC);
1137 if (likely (stream != NULL)) {
1138 /* dev->ep owns the initial refcount */
1139 ep->hcpriv = stream;
1141 iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1145 /* if dev->ep [epnum] is a QH, hw is set */
1146 } else if (unlikely (stream->hw != NULL)) {
1147 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1148 urb->dev->devpath, epnum,
1149 usb_pipein(urb->pipe) ? "in" : "out");
1153 /* caller guarantees an eventual matching iso_stream_put */
1154 stream = iso_stream_get (stream);
1156 spin_unlock_irqrestore (&ehci->lock, flags);
1160 /*-------------------------------------------------------------------------*/
1162 /* ehci_iso_sched ops can be ITD-only or SITD-only */
1164 static struct ehci_iso_sched *
1165 iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1167 struct ehci_iso_sched *iso_sched;
1168 int size = sizeof *iso_sched;
1170 size += packets * sizeof (struct ehci_iso_packet);
1171 iso_sched = kzalloc(size, mem_flags);
1172 if (likely (iso_sched != NULL)) {
1173 INIT_LIST_HEAD (&iso_sched->td_list);
1180 struct ehci_hcd *ehci,
1181 struct ehci_iso_sched *iso_sched,
1182 struct ehci_iso_stream *stream,
1187 dma_addr_t dma = urb->transfer_dma;
1189 /* how many uframes are needed for these transfers */
1190 iso_sched->span = urb->number_of_packets * stream->interval;
1192 /* figure out per-uframe itd fields that we'll need later
1193 * when we fit new itds into the schedule.
1195 for (i = 0; i < urb->number_of_packets; i++) {
1196 struct ehci_iso_packet *uframe = &iso_sched->packet [i];
1201 length = urb->iso_frame_desc [i].length;
1202 buf = dma + urb->iso_frame_desc [i].offset;
1204 trans = EHCI_ISOC_ACTIVE;
1205 trans |= buf & 0x0fff;
1206 if (unlikely (((i + 1) == urb->number_of_packets))
1207 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1208 trans |= EHCI_ITD_IOC;
1209 trans |= length << 16;
1210 uframe->transaction = cpu_to_hc32(ehci, trans);
1212 /* might need to cross a buffer page within a uframe */
1213 uframe->bufp = (buf & ~(u64)0x0fff);
1215 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1222 struct ehci_iso_stream *stream,
1223 struct ehci_iso_sched *iso_sched
1228 // caller must hold ehci->lock!
1229 list_splice (&iso_sched->td_list, &stream->free_list);
1234 itd_urb_transaction (
1235 struct ehci_iso_stream *stream,
1236 struct ehci_hcd *ehci,
1241 struct ehci_itd *itd;
1245 struct ehci_iso_sched *sched;
1246 unsigned long flags;
1248 sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1249 if (unlikely (sched == NULL))
1252 itd_sched_init(ehci, sched, stream, urb);
1254 if (urb->interval < 8)
1255 num_itds = 1 + (sched->span + 7) / 8;
1257 num_itds = urb->number_of_packets;
1259 /* allocate/init ITDs */
1260 spin_lock_irqsave (&ehci->lock, flags);
1261 for (i = 0; i < num_itds; i++) {
1263 /* free_list.next might be cache-hot ... but maybe
1264 * the HC caches it too. avoid that issue for now.
1267 /* prefer previously-allocated itds */
1268 if (likely (!list_empty(&stream->free_list))) {
1269 itd = list_entry (stream->free_list.prev,
1270 struct ehci_itd, itd_list);
1271 list_del (&itd->itd_list);
1272 itd_dma = itd->itd_dma;
1274 spin_unlock_irqrestore (&ehci->lock, flags);
1275 itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1277 spin_lock_irqsave (&ehci->lock, flags);
1279 iso_sched_free(stream, sched);
1280 spin_unlock_irqrestore(&ehci->lock, flags);
1285 memset (itd, 0, sizeof *itd);
1286 itd->itd_dma = itd_dma;
1287 list_add (&itd->itd_list, &sched->td_list);
1289 spin_unlock_irqrestore (&ehci->lock, flags);
1291 /* temporarily store schedule info in hcpriv */
1292 urb->hcpriv = sched;
1293 urb->error_count = 0;
1297 /*-------------------------------------------------------------------------*/
1301 struct ehci_hcd *ehci,
1310 /* can't commit more than 80% periodic == 100 usec */
1311 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1315 /* we know urb->interval is 2^N uframes */
1317 } while (uframe < mod);
1323 struct ehci_hcd *ehci,
1325 struct ehci_iso_stream *stream,
1327 struct ehci_iso_sched *sched,
1334 mask = stream->raw_mask << (uframe & 7);
1336 /* for IN, don't wrap CSPLIT into the next frame */
1340 /* this multi-pass logic is simple, but performance may
1341 * suffer when the schedule data isn't cached.
1344 /* check bandwidth */
1345 uframe %= period_uframes;
1349 frame = uframe >> 3;
1352 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1353 /* The tt's fullspeed bus bandwidth must be available.
1354 * tt_available scheduling guarantees 10+% for control/bulk.
1356 if (!tt_available (ehci, period_uframes << 3,
1357 stream->udev, frame, uf, stream->tt_usecs))
1360 /* tt must be idle for start(s), any gap, and csplit.
1361 * assume scheduling slop leaves 10+% for control/bulk.
1363 if (!tt_no_collision (ehci, period_uframes << 3,
1364 stream->udev, frame, mask))
1368 /* check starts (OUT uses more than one) */
1369 max_used = 100 - stream->usecs;
1370 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1371 if (periodic_usecs (ehci, frame, uf) > max_used)
1375 /* for IN, check CSPLIT */
1376 if (stream->c_usecs) {
1378 max_used = 100 - stream->c_usecs;
1382 if ((stream->raw_mask & tmp) == 0)
1384 if (periodic_usecs (ehci, frame, uf)
1390 /* we know urb->interval is 2^N uframes */
1391 uframe += period_uframes;
1392 } while (uframe < mod);
1394 stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1399 * This scheduler plans almost as far into the future as it has actual
1400 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
1401 * "as small as possible" to be cache-friendlier.) That limits the size
1402 * transfers you can stream reliably; avoid more than 64 msec per urb.
1403 * Also avoid queue depths of less than ehci's worst irq latency (affected
1404 * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1405 * and other factors); or more than about 230 msec total (for portability,
1406 * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler!
1409 #define SCHEDULE_SLOP 80 /* microframes */
1412 iso_stream_schedule (
1413 struct ehci_hcd *ehci,
1415 struct ehci_iso_stream *stream
1418 u32 now, next, start, period, span;
1420 unsigned mod = ehci->periodic_size << 3;
1421 struct ehci_iso_sched *sched = urb->hcpriv;
1423 period = urb->interval;
1425 if (!stream->highspeed) {
1430 if (span > mod - SCHEDULE_SLOP) {
1431 ehci_dbg (ehci, "iso request %p too long\n", urb);
1436 now = ehci_read_frame_index(ehci) & (mod - 1);
1438 /* Typical case: reuse current schedule, stream is still active.
1439 * Hopefully there are no gaps from the host falling behind
1440 * (irq delays etc), but if there are we'll take the next
1441 * slot in the schedule, implicitly assuming URB_ISO_ASAP.
1443 if (likely (!list_empty (&stream->td_list))) {
1446 /* For high speed devices, allow scheduling within the
1447 * isochronous scheduling threshold. For full speed devices
1448 * and Intel PCI-based controllers, don't (work around for
1451 if (!stream->highspeed && ehci->fs_i_thresh)
1452 next = now + ehci->i_thresh;
1456 /* Fell behind (by up to twice the slop amount)?
1457 * We decide based on the time of the last currently-scheduled
1458 * slot, not the time of the next available slot.
1460 excess = (stream->next_uframe - period - next) & (mod - 1);
1461 if (excess >= mod - 2 * SCHEDULE_SLOP)
1462 start = next + excess - mod + period *
1463 DIV_ROUND_UP(mod - excess, period);
1465 start = next + excess + period;
1466 if (start - now >= mod) {
1467 ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n",
1468 urb, start - now - period, period,
1475 /* need to schedule; when's the next (u)frame we could start?
1476 * this is bigger than ehci->i_thresh allows; scheduling itself
1477 * isn't free, the slop should handle reasonably slow cpus. it
1478 * can also help high bandwidth if the dma and irq loads don't
1479 * jump until after the queue is primed.
1483 start = SCHEDULE_SLOP + (now & ~0x07);
1485 /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */
1487 /* find a uframe slot with enough bandwidth.
1488 * Early uframes are more precious because full-speed
1489 * iso IN transfers can't use late uframes,
1490 * and therefore they should be allocated last.
1496 /* check schedule: enough space? */
1497 if (stream->highspeed) {
1498 if (itd_slot_ok(ehci, mod, start,
1499 stream->usecs, period))
1502 if ((start % 8) >= 6)
1504 if (sitd_slot_ok(ehci, mod, stream,
1505 start, sched, period))
1508 } while (start > next && !done);
1510 /* no room in the schedule */
1512 ehci_dbg(ehci, "iso resched full %p (now %d max %d)\n",
1513 urb, now, now + mod);
1519 /* Tried to schedule too far into the future? */
1520 if (unlikely(start - now + span - period
1521 >= mod - 2 * SCHEDULE_SLOP)) {
1522 ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n",
1523 urb, start - now, span - period,
1524 mod - 2 * SCHEDULE_SLOP);
1529 stream->next_uframe = start & (mod - 1);
1531 /* report high speed start in uframes; full speed, in frames */
1532 urb->start_frame = stream->next_uframe;
1533 if (!stream->highspeed)
1534 urb->start_frame >>= 3;
1538 iso_sched_free(stream, sched);
1543 /*-------------------------------------------------------------------------*/
1546 itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1547 struct ehci_itd *itd)
1551 /* it's been recently zeroed */
1552 itd->hw_next = EHCI_LIST_END(ehci);
1553 itd->hw_bufp [0] = stream->buf0;
1554 itd->hw_bufp [1] = stream->buf1;
1555 itd->hw_bufp [2] = stream->buf2;
1557 for (i = 0; i < 8; i++)
1560 /* All other fields are filled when scheduling */
1565 struct ehci_hcd *ehci,
1566 struct ehci_itd *itd,
1567 struct ehci_iso_sched *iso_sched,
1572 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1573 unsigned pg = itd->pg;
1575 // BUG_ON (pg == 6 && uf->cross);
1578 itd->index [uframe] = index;
1580 itd->hw_transaction[uframe] = uf->transaction;
1581 itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1582 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1583 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1585 /* iso_frame_desc[].offset must be strictly increasing */
1586 if (unlikely (uf->cross)) {
1587 u64 bufp = uf->bufp + 4096;
1590 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1591 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1596 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1598 union ehci_shadow *prev = &ehci->pshadow[frame];
1599 __hc32 *hw_p = &ehci->periodic[frame];
1600 union ehci_shadow here = *prev;
1603 /* skip any iso nodes which might belong to previous microframes */
1605 type = Q_NEXT_TYPE(ehci, *hw_p);
1606 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
1608 prev = periodic_next_shadow(ehci, prev, type);
1609 hw_p = shadow_next_periodic(ehci, &here, type);
1613 itd->itd_next = here;
1614 itd->hw_next = *hw_p;
1618 *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1621 /* fit urb's itds into the selected schedule slot; activate as needed */
1624 struct ehci_hcd *ehci,
1627 struct ehci_iso_stream *stream
1631 unsigned next_uframe, uframe, frame;
1632 struct ehci_iso_sched *iso_sched = urb->hcpriv;
1633 struct ehci_itd *itd;
1635 next_uframe = stream->next_uframe & (mod - 1);
1637 if (unlikely (list_empty(&stream->td_list))) {
1638 ehci_to_hcd(ehci)->self.bandwidth_allocated
1639 += stream->bandwidth;
1641 "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1642 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1643 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1645 next_uframe >> 3, next_uframe & 0x7);
1648 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
1649 if (ehci->amd_pll_fix == 1)
1650 usb_amd_quirk_pll_disable();
1653 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1655 /* fill iTDs uframe by uframe */
1656 for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1658 /* ASSERT: we have all necessary itds */
1659 // BUG_ON (list_empty (&iso_sched->td_list));
1661 /* ASSERT: no itds for this endpoint in this uframe */
1663 itd = list_entry (iso_sched->td_list.next,
1664 struct ehci_itd, itd_list);
1665 list_move_tail (&itd->itd_list, &stream->td_list);
1666 itd->stream = iso_stream_get (stream);
1668 itd_init (ehci, stream, itd);
1671 uframe = next_uframe & 0x07;
1672 frame = next_uframe >> 3;
1674 itd_patch(ehci, itd, iso_sched, packet, uframe);
1676 next_uframe += stream->interval;
1677 next_uframe &= mod - 1;
1680 /* link completed itds into the schedule */
1681 if (((next_uframe >> 3) != frame)
1682 || packet == urb->number_of_packets) {
1683 itd_link(ehci, frame & (ehci->periodic_size - 1), itd);
1687 stream->next_uframe = next_uframe;
1689 /* don't need that schedule data any more */
1690 iso_sched_free (stream, iso_sched);
1693 timer_action (ehci, TIMER_IO_WATCHDOG);
1694 return enable_periodic(ehci);
1697 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1699 /* Process and recycle a completed ITD. Return true iff its urb completed,
1700 * and hence its completion callback probably added things to the hardware
1703 * Note that we carefully avoid recycling this descriptor until after any
1704 * completion callback runs, so that it won't be reused quickly. That is,
1705 * assuming (a) no more than two urbs per frame on this endpoint, and also
1706 * (b) only this endpoint's completions submit URBs. It seems some silicon
1707 * corrupts things if you reuse completed descriptors very quickly...
1711 struct ehci_hcd *ehci,
1712 struct ehci_itd *itd
1714 struct urb *urb = itd->urb;
1715 struct usb_iso_packet_descriptor *desc;
1719 struct ehci_iso_stream *stream = itd->stream;
1720 struct usb_device *dev;
1721 unsigned retval = false;
1723 /* for each uframe with a packet */
1724 for (uframe = 0; uframe < 8; uframe++) {
1725 if (likely (itd->index[uframe] == -1))
1727 urb_index = itd->index[uframe];
1728 desc = &urb->iso_frame_desc [urb_index];
1730 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1731 itd->hw_transaction [uframe] = 0;
1733 /* report transfer status */
1734 if (unlikely (t & ISO_ERRS)) {
1736 if (t & EHCI_ISOC_BUF_ERR)
1737 desc->status = usb_pipein (urb->pipe)
1738 ? -ENOSR /* hc couldn't read */
1739 : -ECOMM; /* hc couldn't write */
1740 else if (t & EHCI_ISOC_BABBLE)
1741 desc->status = -EOVERFLOW;
1742 else /* (t & EHCI_ISOC_XACTERR) */
1743 desc->status = -EPROTO;
1745 /* HC need not update length with this error */
1746 if (!(t & EHCI_ISOC_BABBLE)) {
1747 desc->actual_length = EHCI_ITD_LENGTH(t);
1748 urb->actual_length += desc->actual_length;
1750 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1752 desc->actual_length = EHCI_ITD_LENGTH(t);
1753 urb->actual_length += desc->actual_length;
1755 /* URB was too late */
1756 desc->status = -EXDEV;
1760 /* handle completion now? */
1761 if (likely ((urb_index + 1) != urb->number_of_packets))
1764 /* ASSERT: it's really the last itd for this urb
1765 list_for_each_entry (itd, &stream->td_list, itd_list)
1766 BUG_ON (itd->urb == urb);
1769 /* give urb back to the driver; completion often (re)submits */
1771 ehci_urb_done(ehci, urb, 0);
1774 (void) disable_periodic(ehci);
1775 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1777 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
1778 if (ehci->amd_pll_fix == 1)
1779 usb_amd_quirk_pll_enable();
1782 if (unlikely(list_is_singular(&stream->td_list))) {
1783 ehci_to_hcd(ehci)->self.bandwidth_allocated
1784 -= stream->bandwidth;
1786 "deschedule devp %s ep%d%s-iso\n",
1787 dev->devpath, stream->bEndpointAddress & 0x0f,
1788 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1790 iso_stream_put (ehci, stream);
1794 if (ehci->clock_frame != itd->frame || itd->index[7] != -1) {
1795 /* OK to recycle this ITD now. */
1797 list_move(&itd->itd_list, &stream->free_list);
1798 iso_stream_put(ehci, stream);
1800 /* HW might remember this ITD, so we can't recycle it yet.
1801 * Move it to a safe place until a new frame starts.
1803 list_move(&itd->itd_list, &ehci->cached_itd_list);
1804 if (stream->refcount == 2) {
1805 /* If iso_stream_put() were called here, stream
1806 * would be freed. Instead, just prevent reuse.
1808 stream->ep->hcpriv = NULL;
1815 /*-------------------------------------------------------------------------*/
1817 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
1820 int status = -EINVAL;
1821 unsigned long flags;
1822 struct ehci_iso_stream *stream;
1824 /* Get iso_stream head */
1825 stream = iso_stream_find (ehci, urb);
1826 if (unlikely (stream == NULL)) {
1827 ehci_dbg (ehci, "can't get iso stream\n");
1830 if (unlikely (urb->interval != stream->interval)) {
1831 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1832 stream->interval, urb->interval);
1836 #ifdef EHCI_URB_TRACE
1838 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1839 __func__, urb->dev->devpath, urb,
1840 usb_pipeendpoint (urb->pipe),
1841 usb_pipein (urb->pipe) ? "in" : "out",
1842 urb->transfer_buffer_length,
1843 urb->number_of_packets, urb->interval,
1847 /* allocate ITDs w/o locking anything */
1848 status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1849 if (unlikely (status < 0)) {
1850 ehci_dbg (ehci, "can't init itds\n");
1854 /* schedule ... need to lock */
1855 spin_lock_irqsave (&ehci->lock, flags);
1856 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
1857 status = -ESHUTDOWN;
1858 goto done_not_linked;
1860 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
1861 if (unlikely(status))
1862 goto done_not_linked;
1863 status = iso_stream_schedule(ehci, urb, stream);
1864 if (likely (status == 0))
1865 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1867 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
1869 spin_unlock_irqrestore (&ehci->lock, flags);
1872 if (unlikely (status < 0))
1873 iso_stream_put (ehci, stream);
1877 /*-------------------------------------------------------------------------*/
1880 * "Split ISO TDs" ... used for USB 1.1 devices going through the
1881 * TTs in USB 2.0 hubs. These need microframe scheduling.
1886 struct ehci_hcd *ehci,
1887 struct ehci_iso_sched *iso_sched,
1888 struct ehci_iso_stream *stream,
1893 dma_addr_t dma = urb->transfer_dma;
1895 /* how many frames are needed for these transfers */
1896 iso_sched->span = urb->number_of_packets * stream->interval;
1898 /* figure out per-frame sitd fields that we'll need later
1899 * when we fit new sitds into the schedule.
1901 for (i = 0; i < urb->number_of_packets; i++) {
1902 struct ehci_iso_packet *packet = &iso_sched->packet [i];
1907 length = urb->iso_frame_desc [i].length & 0x03ff;
1908 buf = dma + urb->iso_frame_desc [i].offset;
1910 trans = SITD_STS_ACTIVE;
1911 if (((i + 1) == urb->number_of_packets)
1912 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1914 trans |= length << 16;
1915 packet->transaction = cpu_to_hc32(ehci, trans);
1917 /* might need to cross a buffer page within a td */
1919 packet->buf1 = (buf + length) & ~0x0fff;
1920 if (packet->buf1 != (buf & ~(u64)0x0fff))
1923 /* OUT uses multiple start-splits */
1924 if (stream->bEndpointAddress & USB_DIR_IN)
1926 length = (length + 187) / 188;
1927 if (length > 1) /* BEGIN vs ALL */
1929 packet->buf1 |= length;
1934 sitd_urb_transaction (
1935 struct ehci_iso_stream *stream,
1936 struct ehci_hcd *ehci,
1941 struct ehci_sitd *sitd;
1942 dma_addr_t sitd_dma;
1944 struct ehci_iso_sched *iso_sched;
1945 unsigned long flags;
1947 iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1948 if (iso_sched == NULL)
1951 sitd_sched_init(ehci, iso_sched, stream, urb);
1953 /* allocate/init sITDs */
1954 spin_lock_irqsave (&ehci->lock, flags);
1955 for (i = 0; i < urb->number_of_packets; i++) {
1957 /* NOTE: for now, we don't try to handle wraparound cases
1958 * for IN (using sitd->hw_backpointer, like a FSTN), which
1959 * means we never need two sitds for full speed packets.
1962 /* free_list.next might be cache-hot ... but maybe
1963 * the HC caches it too. avoid that issue for now.
1966 /* prefer previously-allocated sitds */
1967 if (!list_empty(&stream->free_list)) {
1968 sitd = list_entry (stream->free_list.prev,
1969 struct ehci_sitd, sitd_list);
1970 list_del (&sitd->sitd_list);
1971 sitd_dma = sitd->sitd_dma;
1973 spin_unlock_irqrestore (&ehci->lock, flags);
1974 sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1976 spin_lock_irqsave (&ehci->lock, flags);
1978 iso_sched_free(stream, iso_sched);
1979 spin_unlock_irqrestore(&ehci->lock, flags);
1984 memset (sitd, 0, sizeof *sitd);
1985 sitd->sitd_dma = sitd_dma;
1986 list_add (&sitd->sitd_list, &iso_sched->td_list);
1989 /* temporarily store schedule info in hcpriv */
1990 urb->hcpriv = iso_sched;
1991 urb->error_count = 0;
1993 spin_unlock_irqrestore (&ehci->lock, flags);
1997 /*-------------------------------------------------------------------------*/
2001 struct ehci_hcd *ehci,
2002 struct ehci_iso_stream *stream,
2003 struct ehci_sitd *sitd,
2004 struct ehci_iso_sched *iso_sched,
2008 struct ehci_iso_packet *uf = &iso_sched->packet [index];
2009 u64 bufp = uf->bufp;
2011 sitd->hw_next = EHCI_LIST_END(ehci);
2012 sitd->hw_fullspeed_ep = stream->address;
2013 sitd->hw_uframe = stream->splits;
2014 sitd->hw_results = uf->transaction;
2015 sitd->hw_backpointer = EHCI_LIST_END(ehci);
2018 sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
2019 sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
2021 sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
2024 sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
2025 sitd->index = index;
2029 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
2031 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
2032 sitd->sitd_next = ehci->pshadow [frame];
2033 sitd->hw_next = ehci->periodic [frame];
2034 ehci->pshadow [frame].sitd = sitd;
2035 sitd->frame = frame;
2037 ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
2040 /* fit urb's sitds into the selected schedule slot; activate as needed */
2043 struct ehci_hcd *ehci,
2046 struct ehci_iso_stream *stream
2050 unsigned next_uframe;
2051 struct ehci_iso_sched *sched = urb->hcpriv;
2052 struct ehci_sitd *sitd;
2054 next_uframe = stream->next_uframe;
2056 if (list_empty(&stream->td_list)) {
2057 /* usbfs ignores TT bandwidth */
2058 ehci_to_hcd(ehci)->self.bandwidth_allocated
2059 += stream->bandwidth;
2061 "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
2062 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
2063 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
2064 (next_uframe >> 3) & (ehci->periodic_size - 1),
2065 stream->interval, hc32_to_cpu(ehci, stream->splits));
2068 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
2069 if (ehci->amd_pll_fix == 1)
2070 usb_amd_quirk_pll_disable();
2073 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
2075 /* fill sITDs frame by frame */
2076 for (packet = 0, sitd = NULL;
2077 packet < urb->number_of_packets;
2080 /* ASSERT: we have all necessary sitds */
2081 BUG_ON (list_empty (&sched->td_list));
2083 /* ASSERT: no itds for this endpoint in this frame */
2085 sitd = list_entry (sched->td_list.next,
2086 struct ehci_sitd, sitd_list);
2087 list_move_tail (&sitd->sitd_list, &stream->td_list);
2088 sitd->stream = iso_stream_get (stream);
2091 sitd_patch(ehci, stream, sitd, sched, packet);
2092 sitd_link(ehci, (next_uframe >> 3) & (ehci->periodic_size - 1),
2095 next_uframe += stream->interval << 3;
2097 stream->next_uframe = next_uframe & (mod - 1);
2099 /* don't need that schedule data any more */
2100 iso_sched_free (stream, sched);
2103 timer_action (ehci, TIMER_IO_WATCHDOG);
2104 return enable_periodic(ehci);
2107 /*-------------------------------------------------------------------------*/
2109 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
2110 | SITD_STS_XACT | SITD_STS_MMF)
2112 /* Process and recycle a completed SITD. Return true iff its urb completed,
2113 * and hence its completion callback probably added things to the hardware
2116 * Note that we carefully avoid recycling this descriptor until after any
2117 * completion callback runs, so that it won't be reused quickly. That is,
2118 * assuming (a) no more than two urbs per frame on this endpoint, and also
2119 * (b) only this endpoint's completions submit URBs. It seems some silicon
2120 * corrupts things if you reuse completed descriptors very quickly...
2124 struct ehci_hcd *ehci,
2125 struct ehci_sitd *sitd
2127 struct urb *urb = sitd->urb;
2128 struct usb_iso_packet_descriptor *desc;
2131 struct ehci_iso_stream *stream = sitd->stream;
2132 struct usb_device *dev;
2133 unsigned retval = false;
2135 urb_index = sitd->index;
2136 desc = &urb->iso_frame_desc [urb_index];
2137 t = hc32_to_cpup(ehci, &sitd->hw_results);
2139 /* report transfer status */
2140 if (t & SITD_ERRS) {
2142 if (t & SITD_STS_DBE)
2143 desc->status = usb_pipein (urb->pipe)
2144 ? -ENOSR /* hc couldn't read */
2145 : -ECOMM; /* hc couldn't write */
2146 else if (t & SITD_STS_BABBLE)
2147 desc->status = -EOVERFLOW;
2148 else /* XACT, MMF, etc */
2149 desc->status = -EPROTO;
2152 desc->actual_length = desc->length - SITD_LENGTH(t);
2153 urb->actual_length += desc->actual_length;
2156 /* handle completion now? */
2157 if ((urb_index + 1) != urb->number_of_packets)
2160 /* ASSERT: it's really the last sitd for this urb
2161 list_for_each_entry (sitd, &stream->td_list, sitd_list)
2162 BUG_ON (sitd->urb == urb);
2165 /* give urb back to the driver; completion often (re)submits */
2167 ehci_urb_done(ehci, urb, 0);
2170 (void) disable_periodic(ehci);
2171 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2173 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
2174 if (ehci->amd_pll_fix == 1)
2175 usb_amd_quirk_pll_enable();
2178 if (list_is_singular(&stream->td_list)) {
2179 ehci_to_hcd(ehci)->self.bandwidth_allocated
2180 -= stream->bandwidth;
2182 "deschedule devp %s ep%d%s-iso\n",
2183 dev->devpath, stream->bEndpointAddress & 0x0f,
2184 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2186 iso_stream_put (ehci, stream);
2190 if (ehci->clock_frame != sitd->frame) {
2191 /* OK to recycle this SITD now. */
2192 sitd->stream = NULL;
2193 list_move(&sitd->sitd_list, &stream->free_list);
2194 iso_stream_put(ehci, stream);
2196 /* HW might remember this SITD, so we can't recycle it yet.
2197 * Move it to a safe place until a new frame starts.
2199 list_move(&sitd->sitd_list, &ehci->cached_sitd_list);
2200 if (stream->refcount == 2) {
2201 /* If iso_stream_put() were called here, stream
2202 * would be freed. Instead, just prevent reuse.
2204 stream->ep->hcpriv = NULL;
2212 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
2215 int status = -EINVAL;
2216 unsigned long flags;
2217 struct ehci_iso_stream *stream;
2219 /* Get iso_stream head */
2220 stream = iso_stream_find (ehci, urb);
2221 if (stream == NULL) {
2222 ehci_dbg (ehci, "can't get iso stream\n");
2225 if (urb->interval != stream->interval) {
2226 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2227 stream->interval, urb->interval);
2231 #ifdef EHCI_URB_TRACE
2233 "submit %p dev%s ep%d%s-iso len %d\n",
2234 urb, urb->dev->devpath,
2235 usb_pipeendpoint (urb->pipe),
2236 usb_pipein (urb->pipe) ? "in" : "out",
2237 urb->transfer_buffer_length);
2240 /* allocate SITDs */
2241 status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2243 ehci_dbg (ehci, "can't init sitds\n");
2247 /* schedule ... need to lock */
2248 spin_lock_irqsave (&ehci->lock, flags);
2249 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
2250 status = -ESHUTDOWN;
2251 goto done_not_linked;
2253 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
2254 if (unlikely(status))
2255 goto done_not_linked;
2256 status = iso_stream_schedule(ehci, urb, stream);
2258 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
2260 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
2262 spin_unlock_irqrestore (&ehci->lock, flags);
2266 iso_stream_put (ehci, stream);
2270 /*-------------------------------------------------------------------------*/
2272 static void free_cached_lists(struct ehci_hcd *ehci)
2274 struct ehci_itd *itd, *n;
2275 struct ehci_sitd *sitd, *sn;
2277 list_for_each_entry_safe(itd, n, &ehci->cached_itd_list, itd_list) {
2278 struct ehci_iso_stream *stream = itd->stream;
2280 list_move(&itd->itd_list, &stream->free_list);
2281 iso_stream_put(ehci, stream);
2284 list_for_each_entry_safe(sitd, sn, &ehci->cached_sitd_list, sitd_list) {
2285 struct ehci_iso_stream *stream = sitd->stream;
2286 sitd->stream = NULL;
2287 list_move(&sitd->sitd_list, &stream->free_list);
2288 iso_stream_put(ehci, stream);
2292 /*-------------------------------------------------------------------------*/
2295 scan_periodic (struct ehci_hcd *ehci)
2297 unsigned now_uframe, frame, clock, clock_frame, mod;
2300 mod = ehci->periodic_size << 3;
2303 * When running, scan from last scan point up to "now"
2304 * else clean up by scanning everything that's left.
2305 * Touches as few pages as possible: cache-friendly.
2307 now_uframe = ehci->next_uframe;
2308 if (HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2309 clock = ehci_read_frame_index(ehci);
2310 clock_frame = (clock >> 3) & (ehci->periodic_size - 1);
2312 clock = now_uframe + mod - 1;
2315 if (ehci->clock_frame != clock_frame) {
2316 free_cached_lists(ehci);
2317 ehci->clock_frame = clock_frame;
2320 clock_frame = clock >> 3;
2321 ++ehci->periodic_stamp;
2324 union ehci_shadow q, *q_p;
2326 unsigned incomplete = false;
2328 frame = now_uframe >> 3;
2331 /* scan each element in frame's queue for completions */
2332 q_p = &ehci->pshadow [frame];
2333 hw_p = &ehci->periodic [frame];
2335 type = Q_NEXT_TYPE(ehci, *hw_p);
2338 while (q.ptr != NULL) {
2340 union ehci_shadow temp;
2343 live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
2344 switch (hc32_to_cpu(ehci, type)) {
2346 /* handle any completions */
2347 temp.qh = qh_get (q.qh);
2348 type = Q_NEXT_TYPE(ehci, q.qh->hw->hw_next);
2350 if (temp.qh->stamp != ehci->periodic_stamp) {
2351 modified = qh_completions(ehci, temp.qh);
2353 temp.qh->stamp = ehci->periodic_stamp;
2354 if (unlikely(list_empty(&temp.qh->qtd_list) ||
2355 temp.qh->needs_rescan))
2356 intr_deschedule(ehci, temp.qh);
2361 /* for "save place" FSTNs, look at QH entries
2362 * in the previous frame for completions.
2364 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
2365 dbg ("ignoring completions from FSTNs");
2367 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
2368 q = q.fstn->fstn_next;
2371 /* If this ITD is still active, leave it for
2372 * later processing ... check the next entry.
2373 * No need to check for activity unless the
2376 if (frame == clock_frame && live) {
2378 for (uf = 0; uf < 8; uf++) {
2379 if (q.itd->hw_transaction[uf] &
2385 q_p = &q.itd->itd_next;
2386 hw_p = &q.itd->hw_next;
2387 type = Q_NEXT_TYPE(ehci,
2394 /* Take finished ITDs out of the schedule
2395 * and process them: recycle, maybe report
2396 * URB completion. HC won't cache the
2397 * pointer for much longer, if at all.
2399 *q_p = q.itd->itd_next;
2400 if (!ehci->use_dummy_qh ||
2401 q.itd->hw_next != EHCI_LIST_END(ehci))
2402 *hw_p = q.itd->hw_next;
2404 *hw_p = ehci->dummy->qh_dma;
2405 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
2407 modified = itd_complete (ehci, q.itd);
2411 /* If this SITD is still active, leave it for
2412 * later processing ... check the next entry.
2413 * No need to check for activity unless the
2416 if (((frame == clock_frame) ||
2417 (((frame + 1) & (ehci->periodic_size - 1))
2420 && (q.sitd->hw_results &
2421 SITD_ACTIVE(ehci))) {
2424 q_p = &q.sitd->sitd_next;
2425 hw_p = &q.sitd->hw_next;
2426 type = Q_NEXT_TYPE(ehci,
2432 /* Take finished SITDs out of the schedule
2433 * and process them: recycle, maybe report
2436 *q_p = q.sitd->sitd_next;
2437 if (!ehci->use_dummy_qh ||
2438 q.sitd->hw_next != EHCI_LIST_END(ehci))
2439 *hw_p = q.sitd->hw_next;
2441 *hw_p = ehci->dummy->qh_dma;
2442 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
2444 modified = sitd_complete (ehci, q.sitd);
2448 dbg ("corrupt type %d frame %d shadow %p",
2449 type, frame, q.ptr);
2454 /* assume completion callbacks modify the queue */
2455 if (unlikely (modified)) {
2456 if (likely(ehci->periodic_sched > 0))
2458 /* short-circuit this scan */
2464 /* If we can tell we caught up to the hardware, stop now.
2465 * We can't advance our scan without collecting the ISO
2466 * transfers that are still pending in this frame.
2468 if (incomplete && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2469 ehci->next_uframe = now_uframe;
2473 // FIXME: this assumes we won't get lapped when
2474 // latencies climb; that should be rare, but...
2475 // detect it, and just go all the way around.
2476 // FLR might help detect this case, so long as latencies
2477 // don't exceed periodic_size msec (default 1.024 sec).
2479 // FIXME: likewise assumes HC doesn't halt mid-scan
2481 if (now_uframe == clock) {
2484 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)
2485 || ehci->periodic_sched == 0)
2487 ehci->next_uframe = now_uframe;
2488 now = ehci_read_frame_index(ehci) & (mod - 1);
2489 if (now_uframe == now)
2492 /* rescan the rest of this frame, then ... */
2494 clock_frame = clock >> 3;
2495 if (ehci->clock_frame != clock_frame) {
2496 free_cached_lists(ehci);
2497 ehci->clock_frame = clock_frame;
2498 ++ehci->periodic_stamp;
2502 now_uframe &= mod - 1;