drivers/usb/host/ehci-sched.c

   1 /*
   2  * Copyright (c) 2001-2004 by David Brownell
   3  * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software Foundation,
  17  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 /* this file is part of ehci-hcd.c */
  21
  22 /*-------------------------------------------------------------------------*/
  23
  24 /*
  25  * EHCI scheduled transaction support:  interrupt, iso, split iso
  26  * These are called "periodic" transactions in the EHCI spec.
  27  *
  28  * Note that for interrupt transfers, the QH/QTD manipulation is shared
  29  * with the "asynchronous" transaction support (control/bulk transfers).
  30  * The only real difference is in how interrupt transfers are scheduled.
  31  *
  32  * For ISO, we make an "iso_stream" head to serve the same role as a QH.
  33  * It keeps track of every ITD (or SITD) that's linked, and holds enough
  34  * pre-calculated schedule data to make appending to the queue be quick.
  35  */
  36
  37 static int ehci_get_frame (struct usb_hcd *hcd);
  38
  39 #ifdef CONFIG_PCI
  40
  41 static unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
  42 {
  43         unsigned uf;
  44
  45         /*
  46          * The MosChip MCS9990 controller updates its microframe counter
  47          * a little before the frame counter, and occasionally we will read
  48          * the invalid intermediate value.  Avoid problems by checking the
  49          * microframe number (the low-order 3 bits); if they are 0 then
  50          * re-read the register to get the correct value.
  51          */
  52         uf = ehci_readl(ehci, &ehci->regs->frame_index);
  53         if (unlikely(ehci->frame_index_bug && ((uf & 7) == 0)))
  54                 uf = ehci_readl(ehci, &ehci->regs->frame_index);
  55         return uf;
  56 }
  57
  58 #endif
  59
  60 /*-------------------------------------------------------------------------*/
  61
  62 /*
  63  * periodic_next_shadow - return "next" pointer on shadow list
  64  * @periodic: host pointer to qh/itd/sitd
  65  * @tag: hardware tag for type of this record
  66  */
  67 static union ehci_shadow *
  68 periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
  69                 __hc32 tag)
  70 {
  71         switch (hc32_to_cpu(ehci, tag)) {
  72         case Q_TYPE_QH:
  73                 return &periodic->qh->qh_next;
  74         case Q_TYPE_FSTN:
  75                 return &periodic->fstn->fstn_next;
  76         case Q_TYPE_ITD:
  77                 return &periodic->itd->itd_next;
  78         // case Q_TYPE_SITD:
  79         default:
  80                 return &periodic->sitd->sitd_next;
  81         }
  82 }
  83
  84 static __hc32 *
  85 shadow_next_periodic(struct ehci_hcd *ehci, union ehci_shadow *periodic,
  86                 __hc32 tag)
  87 {
  88         switch (hc32_to_cpu(ehci, tag)) {
  89         /* our ehci_shadow.qh is actually software part */
  90         case Q_TYPE_QH:
  91                 return &periodic->qh->hw->hw_next;
  92         /* others are hw parts */
  93         default:
  94                 return periodic->hw_next;
  95         }
  96 }
  97
  98 /* caller must hold ehci->lock */
  99 static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
 100 {
 101         union ehci_shadow       *prev_p = &ehci->pshadow[frame];
 102         __hc32                  *hw_p = &ehci->periodic[frame];
 103         union ehci_shadow       here = *prev_p;
 104
 105         /* find predecessor of "ptr"; hw and shadow lists are in sync */
 106         while (here.ptr && here.ptr != ptr) {
 107                 prev_p = periodic_next_shadow(ehci, prev_p,
 108                                 Q_NEXT_TYPE(ehci, *hw_p));
 109                 hw_p = shadow_next_periodic(ehci, &here,
 110                                 Q_NEXT_TYPE(ehci, *hw_p));
 111                 here = *prev_p;
 112         }
 113         /* an interrupt entry (at list end) could have been shared */
 114         if (!here.ptr)
 115                 return;
 116
 117         /* update shadow and hardware lists ... the old "next" pointers
 118          * from ptr may still be in use, the caller updates them.
 119          */
 120         *prev_p = *periodic_next_shadow(ehci, &here,
 121                         Q_NEXT_TYPE(ehci, *hw_p));
 122
 123         if (!ehci->use_dummy_qh ||
 124             *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p))
 125                         != EHCI_LIST_END(ehci))
 126                 *hw_p = *shadow_next_periodic(ehci, &here,
 127                                 Q_NEXT_TYPE(ehci, *hw_p));
 128         else
 129                 *hw_p = ehci->dummy->qh_dma;
 130 }
 131
 132 /* how many of the uframe's 125 usecs are allocated? */
 133 static unsigned short
 134 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
 135 {
 136         __hc32                  *hw_p = &ehci->periodic [frame];
 137         union ehci_shadow       *q = &ehci->pshadow [frame];
 138         unsigned                usecs = 0;
 139         struct ehci_qh_hw       *hw;
 140
 141         while (q->ptr) {
 142                 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
 143                 case Q_TYPE_QH:
 144                         hw = q->qh->hw;
 145                         /* is it in the S-mask? */
 146                         if (hw->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
 147                                 usecs += q->qh->usecs;
 148                         /* ... or C-mask? */
 149                         if (hw->hw_info2 & cpu_to_hc32(ehci,
 150                                         1 << (8 + uframe)))
 151                                 usecs += q->qh->c_usecs;
 152                         hw_p = &hw->hw_next;
 153                         q = &q->qh->qh_next;
 154                         break;
 155                 // case Q_TYPE_FSTN:
 156                 default:
 157                         /* for "save place" FSTNs, count the relevant INTR
 158                          * bandwidth from the previous frame
 159                          */
 160                         if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
 161                                 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
 162                         }
 163                         hw_p = &q->fstn->hw_next;
 164                         q = &q->fstn->fstn_next;
 165                         break;
 166                 case Q_TYPE_ITD:
 167                         if (q->itd->hw_transaction[uframe])
 168                                 usecs += q->itd->stream->usecs;
 169                         hw_p = &q->itd->hw_next;
 170                         q = &q->itd->itd_next;
 171                         break;
 172                 case Q_TYPE_SITD:
 173                         /* is it in the S-mask?  (count SPLIT, DATA) */
 174                         if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
 175                                         1 << uframe)) {
 176                                 if (q->sitd->hw_fullspeed_ep &
 177                                                 cpu_to_hc32(ehci, 1<<31))
 178                                         usecs += q->sitd->stream->usecs;
 179                                 else    /* worst case for OUT start-split */
 180                                         usecs += HS_USECS_ISO (188);
 181                         }
 182
 183                         /* ... C-mask?  (count CSPLIT, DATA) */
 184                         if (q->sitd->hw_uframe &
 185                                         cpu_to_hc32(ehci, 1 << (8 + uframe))) {
 186                                 /* worst case for IN complete-split */
 187                                 usecs += q->sitd->stream->c_usecs;
 188                         }
 189
 190                         hw_p = &q->sitd->hw_next;
 191                         q = &q->sitd->sitd_next;
 192                         break;
 193                 }
 194         }
 195 #ifdef  DEBUG
 196         if (usecs > ehci->uframe_periodic_max)
 197                 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
 198                         frame * 8 + uframe, usecs);
 199 #endif
 200         return usecs;
 201 }
 202
 203 /*-------------------------------------------------------------------------*/
 204
 205 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
 206 {
 207         if (!dev1->tt || !dev2->tt)
 208                 return 0;
 209         if (dev1->tt != dev2->tt)
 210                 return 0;
 211         if (dev1->tt->multi)
 212                 return dev1->ttport == dev2->ttport;
 213         else
 214                 return 1;
 215 }
 216
 217 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
 218
 219 /* Which uframe does the low/fullspeed transfer start in?
 220  *
 221  * The parameter is the mask of ssplits in "H-frame" terms
 222  * and this returns the transfer start uframe in "B-frame" terms,
 223  * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
 224  * will cause a transfer in "B-frame" uframe 0.  "B-frames" lag
 225  * "H-frames" by 1 uframe.  See the EHCI spec sec 4.5 and figure 4.7.
 226  */
 227 static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
 228 {
 229         unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
 230         if (!smask) {
 231                 ehci_err(ehci, "invalid empty smask!\n");
 232                 /* uframe 7 can't have bw so this will indicate failure */
 233                 return 7;
 234         }
 235         return ffs(smask) - 1;
 236 }
 237
 238 static const unsigned char
 239 max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
 240
 241 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
 242 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
 243 {
 244         int i;
 245         for (i=0; i<7; i++) {
 246                 if (max_tt_usecs[i] < tt_usecs[i]) {
 247                         tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
 248                         tt_usecs[i] = max_tt_usecs[i];
 249                 }
 250         }
 251 }
 252
 253 /* How many of the tt's periodic downstream 1000 usecs are allocated?
 254  *
 255  * While this measures the bandwidth in terms of usecs/uframe,
 256  * the low/fullspeed bus has no notion of uframes, so any particular
 257  * low/fullspeed transfer can "carry over" from one uframe to the next,
 258  * since the TT just performs downstream transfers in sequence.
 259  *
 260  * For example two separate 100 usec transfers can start in the same uframe,
 261  * and the second one would "carry over" 75 usecs into the next uframe.
 262  */
 263 static void
 264 periodic_tt_usecs (
 265         struct ehci_hcd *ehci,
 266         struct usb_device *dev,
 267         unsigned frame,
 268         unsigned short tt_usecs[8]
 269 )
 270 {
 271         __hc32                  *hw_p = &ehci->periodic [frame];
 272         union ehci_shadow       *q = &ehci->pshadow [frame];
 273         unsigned char           uf;
 274
 275         memset(tt_usecs, 0, 16);
 276
 277         while (q->ptr) {
 278                 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
 279                 case Q_TYPE_ITD:
 280                         hw_p = &q->itd->hw_next;
 281                         q = &q->itd->itd_next;
 282                         continue;
 283                 case Q_TYPE_QH:
 284                         if (same_tt(dev, q->qh->dev)) {
 285                                 uf = tt_start_uframe(ehci, q->qh->hw->hw_info2);
 286                                 tt_usecs[uf] += q->qh->tt_usecs;
 287                         }
 288                         hw_p = &q->qh->hw->hw_next;
 289                         q = &q->qh->qh_next;
 290                         continue;
 291                 case Q_TYPE_SITD:
 292                         if (same_tt(dev, q->sitd->urb->dev)) {
 293                                 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
 294                                 tt_usecs[uf] += q->sitd->stream->tt_usecs;
 295                         }
 296                         hw_p = &q->sitd->hw_next;
 297                         q = &q->sitd->sitd_next;
 298                         continue;
 299                 // case Q_TYPE_FSTN:
 300                 default:
 301                         ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
 302                                         frame);
 303                         hw_p = &q->fstn->hw_next;
 304                         q = &q->fstn->fstn_next;
 305                 }
 306         }
 307
 308         carryover_tt_bandwidth(tt_usecs);
 309
 310         if (max_tt_usecs[7] < tt_usecs[7])
 311                 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
 312                         frame, tt_usecs[7] - max_tt_usecs[7]);
 313 }
 314
 315 /*
 316  * Return true if the device's tt's downstream bus is available for a
 317  * periodic transfer of the specified length (usecs), starting at the
 318  * specified frame/uframe.  Note that (as summarized in section 11.19
 319  * of the usb 2.0 spec) TTs can buffer multiple transactions for each
 320  * uframe.
 321  *
 322  * The uframe parameter is when the fullspeed/lowspeed transfer
 323  * should be executed in "B-frame" terms, which is the same as the
 324  * highspeed ssplit's uframe (which is in "H-frame" terms).  For example
 325  * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
 326  * See the EHCI spec sec 4.5 and fig 4.7.
 327  *
 328  * This checks if the full/lowspeed bus, at the specified starting uframe,
 329  * has the specified bandwidth available, according to rules listed
 330  * in USB 2.0 spec section 11.18.1 fig 11-60.
 331  *
 332  * This does not check if the transfer would exceed the max ssplit
 333  * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
 334  * since proper scheduling limits ssplits to less than 16 per uframe.
 335  */
 336 static int tt_available (
 337         struct ehci_hcd         *ehci,
 338         unsigned                period,
 339         struct usb_device       *dev,
 340         unsigned                frame,
 341         unsigned                uframe,
 342         u16                     usecs
 343 )
 344 {
 345         if ((period == 0) || (uframe >= 7))     /* error */
 346                 return 0;
 347
 348         for (; frame < ehci->periodic_size; frame += period) {
 349                 unsigned short tt_usecs[8];
 350
 351                 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
 352
 353                 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
 354                         " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
 355                         frame, usecs, uframe,
 356                         tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
 357                         tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
 358
 359                 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
 360                         ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
 361                                 frame, uframe);
 362                         return 0;
 363                 }
 364
 365                 /* special case for isoc transfers larger than 125us:
 366                  * the first and each subsequent fully used uframe
 367                  * must be empty, so as to not illegally delay
 368                  * already scheduled transactions
 369                  */
 370                 if (125 < usecs) {
 371                         int ufs = (usecs / 125);
 372                         int i;
 373                         for (i = uframe; i < (uframe + ufs) && i < 8; i++)
 374                                 if (0 < tt_usecs[i]) {
 375                                         ehci_vdbg(ehci,
 376                                                 "multi-uframe xfer can't fit "
 377                                                 "in frame %d uframe %d\n",
 378                                                 frame, i);
 379                                         return 0;
 380                                 }
 381                 }
 382
 383                 tt_usecs[uframe] += usecs;
 384
 385                 carryover_tt_bandwidth(tt_usecs);
 386
 387                 /* fail if the carryover pushed bw past the last uframe's limit */
 388                 if (max_tt_usecs[7] < tt_usecs[7]) {
 389                         ehci_vdbg(ehci,
 390                                 "tt unavailable usecs %d frame %d uframe %d\n",
 391                                 usecs, frame, uframe);
 392                         return 0;
 393                 }
 394         }
 395
 396         return 1;
 397 }
 398
 399 #else
 400
 401 /* return true iff the device's transaction translator is available
 402  * for a periodic transfer starting at the specified frame, using
 403  * all the uframes in the mask.
 404  */
 405 static int tt_no_collision (
 406         struct ehci_hcd         *ehci,
 407         unsigned                period,
 408         struct usb_device       *dev,
 409         unsigned                frame,
 410         u32                     uf_mask
 411 )
 412 {
 413         if (period == 0)        /* error */
 414                 return 0;
 415
 416         /* note bandwidth wastage:  split never follows csplit
 417          * (different dev or endpoint) until the next uframe.
 418          * calling convention doesn't make that distinction.
 419          */
 420         for (; frame < ehci->periodic_size; frame += period) {
 421                 union ehci_shadow       here;
 422                 __hc32                  type;
 423                 struct ehci_qh_hw       *hw;
 424
 425                 here = ehci->pshadow [frame];
 426                 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
 427                 while (here.ptr) {
 428                         switch (hc32_to_cpu(ehci, type)) {
 429                         case Q_TYPE_ITD:
 430                                 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
 431                                 here = here.itd->itd_next;
 432                                 continue;
 433                         case Q_TYPE_QH:
 434                                 hw = here.qh->hw;
 435                                 if (same_tt (dev, here.qh->dev)) {
 436                                         u32             mask;
 437
 438                                         mask = hc32_to_cpu(ehci,
 439                                                         hw->hw_info2);
 440                                         /* "knows" no gap is needed */
 441                                         mask |= mask >> 8;
 442                                         if (mask & uf_mask)
 443                                                 break;
 444                                 }
 445                                 type = Q_NEXT_TYPE(ehci, hw->hw_next);
 446                                 here = here.qh->qh_next;
 447                                 continue;
 448                         case Q_TYPE_SITD:
 449                                 if (same_tt (dev, here.sitd->urb->dev)) {
 450                                         u16             mask;
 451
 452                                         mask = hc32_to_cpu(ehci, here.sitd
 453                                                                 ->hw_uframe);
 454                                         /* FIXME assumes no gap for IN! */
 455                                         mask |= mask >> 8;
 456                                         if (mask & uf_mask)
 457                                                 break;
 458                                 }
 459                                 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
 460                                 here = here.sitd->sitd_next;
 461                                 continue;
 462                         // case Q_TYPE_FSTN:
 463                         default:
 464                                 ehci_dbg (ehci,
 465                                         "periodic frame %d bogus type %d\n",
 466                                         frame, type);
 467                         }
 468
 469                         /* collision or error */
 470                         return 0;
 471                 }
 472         }
 473
 474         /* no collision */
 475         return 1;
 476 }
 477
 478 #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
 479
 480 /*-------------------------------------------------------------------------*/
 481
 482 static int enable_periodic (struct ehci_hcd *ehci)
 483 {
 484         if (ehci->periodic_count++)
 485                 return 0;
 486
 487         /* Stop waiting to turn off the periodic schedule */
 488         ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_DISABLE_PERIODIC);
 489
 490         /* Don't start the schedule until PSS is 0 */
 491         ehci_poll_PSS(ehci);
 492         return 0;
 493 }
 494
 495 static int disable_periodic (struct ehci_hcd *ehci)
 496 {
 497         if (--ehci->periodic_count)
 498                 return 0;
 499
 500         ehci->next_uframe = -1;         /* the periodic schedule is empty */
 501
 502         /* Don't turn off the schedule until PSS is 1 */
 503         ehci_poll_PSS(ehci);
 504         return 0;
 505 }
 506
 507 /*-------------------------------------------------------------------------*/
 508
 509 /* periodic schedule slots have iso tds (normal or split) first, then a
 510  * sparse tree for active interrupt transfers.
 511  *
 512  * this just links in a qh; caller guarantees uframe masks are set right.
 513  * no FSTN support (yet; ehci 0.96+)
 514  */
 515 static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
 516 {
 517         unsigned        i;
 518         unsigned        period = qh->period;
 519
 520         dev_dbg (&qh->dev->dev,
 521                 "link qh%d-%04x/%p start %d [%d/%d us]\n",
 522                 period, hc32_to_cpup(ehci, &qh->hw->hw_info2)
 523                         & (QH_CMASK | QH_SMASK),
 524                 qh, qh->start, qh->usecs, qh->c_usecs);
 525
 526         /* high bandwidth, or otherwise every microframe */
 527         if (period == 0)
 528                 period = 1;
 529
 530         for (i = qh->start; i < ehci->periodic_size; i += period) {
 531                 union ehci_shadow       *prev = &ehci->pshadow[i];
 532                 __hc32                  *hw_p = &ehci->periodic[i];
 533                 union ehci_shadow       here = *prev;
 534                 __hc32                  type = 0;
 535
 536                 /* skip the iso nodes at list head */
 537                 while (here.ptr) {
 538                         type = Q_NEXT_TYPE(ehci, *hw_p);
 539                         if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
 540                                 break;
 541                         prev = periodic_next_shadow(ehci, prev, type);
 542                         hw_p = shadow_next_periodic(ehci, &here, type);
 543                         here = *prev;
 544                 }
 545
 546                 /* sorting each branch by period (slow-->fast)
 547                  * enables sharing interior tree nodes
 548                  */
 549                 while (here.ptr && qh != here.qh) {
 550                         if (qh->period > here.qh->period)
 551                                 break;
 552                         prev = &here.qh->qh_next;
 553                         hw_p = &here.qh->hw->hw_next;
 554                         here = *prev;
 555                 }
 556                 /* link in this qh, unless some earlier pass did that */
 557                 if (qh != here.qh) {
 558                         qh->qh_next = here;
 559                         if (here.qh)
 560                                 qh->hw->hw_next = *hw_p;
 561                         wmb ();
 562                         prev->qh = qh;
 563                         *hw_p = QH_NEXT (ehci, qh->qh_dma);
 564                 }
 565         }
 566         qh->qh_state = QH_STATE_LINKED;
 567         qh->xacterrs = 0;
 568
 569         /* update per-qh bandwidth for usbfs */
 570         ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
 571                 ? ((qh->usecs + qh->c_usecs) / qh->period)
 572                 : (qh->usecs * 8);
 573
 574         /* maybe enable periodic schedule processing */
 575         return enable_periodic(ehci);
 576 }
 577
 578 static int qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh)
 579 {
 580         unsigned        i;
 581         unsigned        period;
 582
 583         // FIXME:
 584         // IF this isn't high speed
 585         //   and this qh is active in the current uframe
 586         //   (and overlay token SplitXstate is false?)
 587         // THEN
 588         //   qh->hw_info1 |= cpu_to_hc32(1 << 7 /* "ignore" */);
 589
 590         /* high bandwidth, or otherwise part of every microframe */
 591         if ((period = qh->period) == 0)
 592                 period = 1;
 593
 594         for (i = qh->start; i < ehci->periodic_size; i += period)
 595                 periodic_unlink (ehci, i, qh);
 596
 597         /* update per-qh bandwidth for usbfs */
 598         ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
 599                 ? ((qh->usecs + qh->c_usecs) / qh->period)
 600                 : (qh->usecs * 8);
 601
 602         dev_dbg (&qh->dev->dev,
 603                 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
 604                 qh->period,
 605                 hc32_to_cpup(ehci, &qh->hw->hw_info2) & (QH_CMASK | QH_SMASK),
 606                 qh, qh->start, qh->usecs, qh->c_usecs);
 607
 608         /* qh->qh_next still "live" to HC */
 609         qh->qh_state = QH_STATE_UNLINK;
 610         qh->qh_next.ptr = NULL;
 611
 612         return 0;
 613 }
 614
 615 static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
 616 {
 617         unsigned                wait;
 618         struct ehci_qh_hw       *hw = qh->hw;
 619         int                     rc;
 620
 621         /* If the QH isn't linked then there's nothing we can do
 622          * unless we were called during a giveback, in which case
 623          * qh_completions() has to deal with it.
 624          */
 625         if (qh->qh_state != QH_STATE_LINKED) {
 626                 if (qh->qh_state == QH_STATE_COMPLETING)
 627                         qh->needs_rescan = 1;
 628                 return;
 629         }
 630
 631         qh_unlink_periodic (ehci, qh);
 632
 633         /* simple/paranoid:  always delay, expecting the HC needs to read
 634          * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
 635          * expect khubd to clean up after any CSPLITs we won't issue.
 636          * active high speed queues may need bigger delays...
 637          */
 638         if (list_empty (&qh->qtd_list)
 639                         || (cpu_to_hc32(ehci, QH_CMASK)
 640                                         & hw->hw_info2) != 0)
 641                 wait = 2;
 642         else
 643                 wait = 55;      /* worst case: 3 * 1024 */
 644
 645         udelay (wait);
 646         qh->qh_state = QH_STATE_IDLE;
 647         hw->hw_next = EHCI_LIST_END(ehci);
 648         wmb ();
 649
 650         qh_completions(ehci, qh);
 651
 652         /* reschedule QH iff another request is queued */
 653         if (!list_empty(&qh->qtd_list) &&
 654                         ehci->rh_state == EHCI_RH_RUNNING) {
 655                 rc = qh_schedule(ehci, qh);
 656
 657                 /* An error here likely indicates handshake failure
 658                  * or no space left in the schedule.  Neither fault
 659                  * should happen often ...
 660                  *
 661                  * FIXME kill the now-dysfunctional queued urbs
 662                  */
 663                 if (rc != 0)
 664                         ehci_err(ehci, "can't reschedule qh %p, err %d\n",
 665                                         qh, rc);
 666         }
 667
 668         /* maybe turn off periodic schedule */
 669         disable_periodic(ehci);
 670 }
 671
 672 /*-------------------------------------------------------------------------*/
 673
 674 static int check_period (
 675         struct ehci_hcd *ehci,
 676         unsigned        frame,
 677         unsigned        uframe,
 678         unsigned        period,
 679         unsigned        usecs
 680 ) {
 681         int             claimed;
 682
 683         /* complete split running into next frame?
 684          * given FSTN support, we could sometimes check...
 685          */
 686         if (uframe >= 8)
 687                 return 0;
 688
 689         /* convert "usecs we need" to "max already claimed" */
 690         usecs = ehci->uframe_periodic_max - usecs;
 691
 692         /* we "know" 2 and 4 uframe intervals were rejected; so
 693          * for period 0, check _every_ microframe in the schedule.
 694          */
 695         if (unlikely (period == 0)) {
 696                 do {
 697                         for (uframe = 0; uframe < 7; uframe++) {
 698                                 claimed = periodic_usecs (ehci, frame, uframe);
 699                                 if (claimed > usecs)
 700                                         return 0;
 701                         }
 702                 } while ((frame += 1) < ehci->periodic_size);
 703
 704         /* just check the specified uframe, at that period */
 705         } else {
 706                 do {
 707                         claimed = periodic_usecs (ehci, frame, uframe);
 708                         if (claimed > usecs)
 709                                 return 0;
 710                 } while ((frame += period) < ehci->periodic_size);
 711         }
 712
 713         // success!
 714         return 1;
 715 }
 716
 717 static int check_intr_schedule (
 718         struct ehci_hcd         *ehci,
 719         unsigned                frame,
 720         unsigned                uframe,
 721         const struct ehci_qh    *qh,
 722         __hc32                  *c_maskp
 723 )
 724 {
 725         int             retval = -ENOSPC;
 726         u8              mask = 0;
 727
 728         if (qh->c_usecs && uframe >= 6)         /* FSTN territory? */
 729                 goto done;
 730
 731         if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
 732                 goto done;
 733         if (!qh->c_usecs) {
 734                 retval = 0;
 735                 *c_maskp = 0;
 736                 goto done;
 737         }
 738
 739 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
 740         if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
 741                                 qh->tt_usecs)) {
 742                 unsigned i;
 743
 744                 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
 745                 for (i=uframe+1; i<8 && i<uframe+4; i++)
 746                         if (!check_period (ehci, frame, i,
 747                                                 qh->period, qh->c_usecs))
 748                                 goto done;
 749                         else
 750                                 mask |= 1 << i;
 751
 752                 retval = 0;
 753
 754                 *c_maskp = cpu_to_hc32(ehci, mask << 8);
 755         }
 756 #else
 757         /* Make sure this tt's buffer is also available for CSPLITs.
 758          * We pessimize a bit; probably the typical full speed case
 759          * doesn't need the second CSPLIT.
 760          *
 761          * NOTE:  both SPLIT and CSPLIT could be checked in just
 762          * one smart pass...
 763          */
 764         mask = 0x03 << (uframe + qh->gap_uf);
 765         *c_maskp = cpu_to_hc32(ehci, mask << 8);
 766
 767         mask |= 1 << uframe;
 768         if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
 769                 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
 770                                         qh->period, qh->c_usecs))
 771                         goto done;
 772                 if (!check_period (ehci, frame, uframe + qh->gap_uf,
 773                                         qh->period, qh->c_usecs))
 774                         goto done;
 775                 retval = 0;
 776         }
 777 #endif
 778 done:
 779         return retval;
 780 }
 781
 782 /* "first fit" scheduling policy used the first time through,
 783  * or when the previous schedule slot can't be re-used.
 784  */
 785 static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
 786 {
 787         int             status;
 788         unsigned        uframe;
 789         __hc32          c_mask;
 790         unsigned        frame;          /* 0..(qh->period - 1), or NO_FRAME */
 791         struct ehci_qh_hw       *hw = qh->hw;
 792
 793         qh_refresh(ehci, qh);
 794         hw->hw_next = EHCI_LIST_END(ehci);
 795         frame = qh->start;
 796
 797         /* reuse the previous schedule slots, if we can */
 798         if (frame < qh->period) {
 799                 uframe = ffs(hc32_to_cpup(ehci, &hw->hw_info2) & QH_SMASK);
 800                 status = check_intr_schedule (ehci, frame, --uframe,
 801                                 qh, &c_mask);
 802         } else {
 803                 uframe = 0;
 804                 c_mask = 0;
 805                 status = -ENOSPC;
 806         }
 807
 808         /* else scan the schedule to find a group of slots such that all
 809          * uframes have enough periodic bandwidth available.
 810          */
 811         if (status) {
 812                 /* "normal" case, uframing flexible except with splits */
 813                 if (qh->period) {
 814                         int             i;
 815
 816                         for (i = qh->period; status && i > 0; --i) {
 817                                 frame = ++ehci->random_frame % qh->period;
 818                                 for (uframe = 0; uframe < 8; uframe++) {
 819                                         status = check_intr_schedule (ehci,
 820                                                         frame, uframe, qh,
 821                                                         &c_mask);
 822                                         if (status == 0)
 823                                                 break;
 824                                 }
 825                         }
 826
 827                 /* qh->period == 0 means every uframe */
 828                 } else {
 829                         frame = 0;
 830                         status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
 831                 }
 832                 if (status)
 833                         goto done;
 834                 qh->start = frame;
 835
 836                 /* reset S-frame and (maybe) C-frame masks */
 837                 hw->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
 838                 hw->hw_info2 |= qh->period
 839                         ? cpu_to_hc32(ehci, 1 << uframe)
 840                         : cpu_to_hc32(ehci, QH_SMASK);
 841                 hw->hw_info2 |= c_mask;
 842         } else
 843                 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
 844
 845         /* stuff into the periodic schedule */
 846         status = qh_link_periodic (ehci, qh);
 847 done:
 848         return status;
 849 }
 850
 851 static int intr_submit (
 852         struct ehci_hcd         *ehci,
 853         struct urb              *urb,
 854         struct list_head        *qtd_list,
 855         gfp_t                   mem_flags
 856 ) {
 857         unsigned                epnum;
 858         unsigned long           flags;
 859         struct ehci_qh          *qh;
 860         int                     status;
 861         struct list_head        empty;
 862
 863         /* get endpoint and transfer/schedule data */
 864         epnum = urb->ep->desc.bEndpointAddress;
 865
 866         spin_lock_irqsave (&ehci->lock, flags);
 867
 868         if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
 869                 status = -ESHUTDOWN;
 870                 goto done_not_linked;
 871         }
 872         status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
 873         if (unlikely(status))
 874                 goto done_not_linked;
 875
 876         /* get qh and force any scheduling errors */
 877         INIT_LIST_HEAD (&empty);
 878         qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv);
 879         if (qh == NULL) {
 880                 status = -ENOMEM;
 881                 goto done;
 882         }
 883         if (qh->qh_state == QH_STATE_IDLE) {
 884                 if ((status = qh_schedule (ehci, qh)) != 0)
 885                         goto done;
 886         }
 887
 888         /* then queue the urb's tds to the qh */
 889         qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
 890         BUG_ON (qh == NULL);
 891
 892         /* ... update usbfs periodic stats */
 893         ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
 894
 895 done:
 896         if (unlikely(status))
 897                 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
 898 done_not_linked:
 899         spin_unlock_irqrestore (&ehci->lock, flags);
 900         if (status)
 901                 qtd_list_free (ehci, urb, qtd_list);
 902
 903         return status;
 904 }
 905
 906 /*-------------------------------------------------------------------------*/
 907
 908 /* ehci_iso_stream ops work with both ITD and SITD */
 909
 910 static struct ehci_iso_stream *
 911 iso_stream_alloc (gfp_t mem_flags)
 912 {
 913         struct ehci_iso_stream *stream;
 914
 915         stream = kzalloc(sizeof *stream, mem_flags);
 916         if (likely (stream != NULL)) {
 917                 INIT_LIST_HEAD(&stream->td_list);
 918                 INIT_LIST_HEAD(&stream->free_list);
 919                 stream->next_uframe = -1;
 920                 stream->refcount = 1;
 921         }
 922         return stream;
 923 }
 924
 925 static void
 926 iso_stream_init (
 927         struct ehci_hcd         *ehci,
 928         struct ehci_iso_stream  *stream,
 929         struct usb_device       *dev,
 930         int                     pipe,
 931         unsigned                interval
 932 )
 933 {
 934         static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
 935
 936         u32                     buf1;
 937         unsigned                epnum, maxp;
 938         int                     is_input;
 939         long                    bandwidth;
 940
 941         /*
 942          * this might be a "high bandwidth" highspeed endpoint,
 943          * as encoded in the ep descriptor's wMaxPacket field
 944          */
 945         epnum = usb_pipeendpoint (pipe);
 946         is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
 947         maxp = usb_maxpacket(dev, pipe, !is_input);
 948         if (is_input) {
 949                 buf1 = (1 << 11);
 950         } else {
 951                 buf1 = 0;
 952         }
 953
 954         /* knows about ITD vs SITD */
 955         if (dev->speed == USB_SPEED_HIGH) {
 956                 unsigned multi = hb_mult(maxp);
 957
 958                 stream->highspeed = 1;
 959
 960                 maxp = max_packet(maxp);
 961                 buf1 |= maxp;
 962                 maxp *= multi;
 963
 964                 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
 965                 stream->buf1 = cpu_to_hc32(ehci, buf1);
 966                 stream->buf2 = cpu_to_hc32(ehci, multi);
 967
 968                 /* usbfs wants to report the average usecs per frame tied up
 969                  * when transfers on this endpoint are scheduled ...
 970                  */
 971                 stream->usecs = HS_USECS_ISO (maxp);
 972                 bandwidth = stream->usecs * 8;
 973                 bandwidth /= interval;
 974
 975         } else {
 976                 u32             addr;
 977                 int             think_time;
 978                 int             hs_transfers;
 979
 980                 addr = dev->ttport << 24;
 981                 if (!ehci_is_TDI(ehci)
 982                                 || (dev->tt->hub !=
 983                                         ehci_to_hcd(ehci)->self.root_hub))
 984                         addr |= dev->tt->hub->devnum << 16;
 985                 addr |= epnum << 8;
 986                 addr |= dev->devnum;
 987                 stream->usecs = HS_USECS_ISO (maxp);
 988                 think_time = dev->tt ? dev->tt->think_time : 0;
 989                 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
 990                                 dev->speed, is_input, 1, maxp));
 991                 hs_transfers = max (1u, (maxp + 187) / 188);
 992                 if (is_input) {
 993                         u32     tmp;
 994
 995                         addr |= 1 << 31;
 996                         stream->c_usecs = stream->usecs;
 997                         stream->usecs = HS_USECS_ISO (1);
 998                         stream->raw_mask = 1;
 999
1000                         /* c-mask as specified in USB 2.0 11.18.4 3.c */
1001                         tmp = (1 << (hs_transfers + 2)) - 1;
1002                         stream->raw_mask |= tmp << (8 + 2);
1003                 } else
1004                         stream->raw_mask = smask_out [hs_transfers - 1];
1005                 bandwidth = stream->usecs + stream->c_usecs;
1006                 bandwidth /= interval << 3;
1007
1008                 /* stream->splits gets created from raw_mask later */
1009                 stream->address = cpu_to_hc32(ehci, addr);
1010         }
1011         stream->bandwidth = bandwidth;
1012
1013         stream->udev = dev;
1014
1015         stream->bEndpointAddress = is_input | epnum;
1016         stream->interval = interval;
1017         stream->maxp = maxp;
1018 }
1019
1020 static void
1021 iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
1022 {
1023         stream->refcount--;
1024
1025         /* free whenever just a dev->ep reference remains.
1026          * not like a QH -- no persistent state (toggle, halt)
1027          */
1028         if (stream->refcount == 1) {
1029                 // BUG_ON (!list_empty(&stream->td_list));
1030
1031                 while (!list_empty (&stream->free_list)) {
1032                         struct list_head        *entry;
1033
1034                         entry = stream->free_list.next;
1035                         list_del (entry);
1036
1037                         /* knows about ITD vs SITD */
1038                         if (stream->highspeed) {
1039                                 struct ehci_itd         *itd;
1040
1041                                 itd = list_entry (entry, struct ehci_itd,
1042                                                 itd_list);
1043                                 dma_pool_free (ehci->itd_pool, itd,
1044                                                 itd->itd_dma);
1045                         } else {
1046                                 struct ehci_sitd        *sitd;
1047
1048                                 sitd = list_entry (entry, struct ehci_sitd,
1049                                                 sitd_list);
1050                                 dma_pool_free (ehci->sitd_pool, sitd,
1051                                                 sitd->sitd_dma);
1052                         }
1053                 }
1054
1055                 stream->bEndpointAddress &= 0x0f;
1056                 if (stream->ep)
1057                         stream->ep->hcpriv = NULL;
1058
1059                 kfree(stream);
1060         }
1061 }
1062
1063 static inline struct ehci_iso_stream *
1064 iso_stream_get (struct ehci_iso_stream *stream)
1065 {
1066         if (likely (stream != NULL))
1067                 stream->refcount++;
1068         return stream;
1069 }
1070
1071 static struct ehci_iso_stream *
1072 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1073 {
1074         unsigned                epnum;
1075         struct ehci_iso_stream  *stream;
1076         struct usb_host_endpoint *ep;
1077         unsigned long           flags;
1078
1079         epnum = usb_pipeendpoint (urb->pipe);
1080         if (usb_pipein(urb->pipe))
1081                 ep = urb->dev->ep_in[epnum];
1082         else
1083                 ep = urb->dev->ep_out[epnum];
1084
1085         spin_lock_irqsave (&ehci->lock, flags);
1086         stream = ep->hcpriv;
1087
1088         if (unlikely (stream == NULL)) {
1089                 stream = iso_stream_alloc(GFP_ATOMIC);
1090                 if (likely (stream != NULL)) {
1091                         /* dev->ep owns the initial refcount */
1092                         ep->hcpriv = stream;
1093                         stream->ep = ep;
1094                         iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1095                                         urb->interval);
1096                 }
1097
1098         /* if dev->ep [epnum] is a QH, hw is set */
1099         } else if (unlikely (stream->hw != NULL)) {
1100                 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1101                         urb->dev->devpath, epnum,
1102                         usb_pipein(urb->pipe) ? "in" : "out");
1103                 stream = NULL;
1104         }
1105
1106         /* caller guarantees an eventual matching iso_stream_put */
1107         stream = iso_stream_get (stream);
1108
1109         spin_unlock_irqrestore (&ehci->lock, flags);
1110         return stream;
1111 }
1112
1113 /*-------------------------------------------------------------------------*/
1114
1115 /* ehci_iso_sched ops can be ITD-only or SITD-only */
1116
1117 static struct ehci_iso_sched *
1118 iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1119 {
1120         struct ehci_iso_sched   *iso_sched;
1121         int                     size = sizeof *iso_sched;
1122
1123         size += packets * sizeof (struct ehci_iso_packet);
1124         iso_sched = kzalloc(size, mem_flags);
1125         if (likely (iso_sched != NULL)) {
1126                 INIT_LIST_HEAD (&iso_sched->td_list);
1127         }
1128         return iso_sched;
1129 }
1130
1131 static inline void
1132 itd_sched_init(
1133         struct ehci_hcd         *ehci,
1134         struct ehci_iso_sched   *iso_sched,
1135         struct ehci_iso_stream  *stream,
1136         struct urb              *urb
1137 )
1138 {
1139         unsigned        i;
1140         dma_addr_t      dma = urb->transfer_dma;
1141
1142         /* how many uframes are needed for these transfers */
1143         iso_sched->span = urb->number_of_packets * stream->interval;
1144
1145         /* figure out per-uframe itd fields that we'll need later
1146          * when we fit new itds into the schedule.
1147          */
1148         for (i = 0; i < urb->number_of_packets; i++) {
1149                 struct ehci_iso_packet  *uframe = &iso_sched->packet [i];
1150                 unsigned                length;
1151                 dma_addr_t              buf;
1152                 u32                     trans;
1153
1154                 length = urb->iso_frame_desc [i].length;
1155                 buf = dma + urb->iso_frame_desc [i].offset;
1156
1157                 trans = EHCI_ISOC_ACTIVE;
1158                 trans |= buf & 0x0fff;
1159                 if (unlikely (((i + 1) == urb->number_of_packets))
1160                                 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1161                         trans |= EHCI_ITD_IOC;
1162                 trans |= length << 16;
1163                 uframe->transaction = cpu_to_hc32(ehci, trans);
1164
1165                 /* might need to cross a buffer page within a uframe */
1166                 uframe->bufp = (buf & ~(u64)0x0fff);
1167                 buf += length;
1168                 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1169                         uframe->cross = 1;
1170         }
1171 }
1172
1173 static void
1174 iso_sched_free (
1175         struct ehci_iso_stream  *stream,
1176         struct ehci_iso_sched   *iso_sched
1177 )
1178 {
1179         if (!iso_sched)
1180                 return;
1181         // caller must hold ehci->lock!
1182         list_splice (&iso_sched->td_list, &stream->free_list);
1183         kfree (iso_sched);
1184 }
1185
1186 static int
1187 itd_urb_transaction (
1188         struct ehci_iso_stream  *stream,
1189         struct ehci_hcd         *ehci,
1190         struct urb              *urb,
1191         gfp_t                   mem_flags
1192 )
1193 {
1194         struct ehci_itd         *itd;
1195         dma_addr_t              itd_dma;
1196         int                     i;
1197         unsigned                num_itds;
1198         struct ehci_iso_sched   *sched;
1199         unsigned long           flags;
1200
1201         sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1202         if (unlikely (sched == NULL))
1203                 return -ENOMEM;
1204
1205         itd_sched_init(ehci, sched, stream, urb);
1206
1207         if (urb->interval < 8)
1208                 num_itds = 1 + (sched->span + 7) / 8;
1209         else
1210                 num_itds = urb->number_of_packets;
1211
1212         /* allocate/init ITDs */
1213         spin_lock_irqsave (&ehci->lock, flags);
1214         for (i = 0; i < num_itds; i++) {
1215
1216                 /* free_list.next might be cache-hot ... but maybe
1217                  * the HC caches it too. avoid that issue for now.
1218                  */
1219
1220                 /* prefer previously-allocated itds */
1221                 if (likely (!list_empty(&stream->free_list))) {
1222                         itd = list_entry (stream->free_list.prev,
1223                                         struct ehci_itd, itd_list);
1224                         list_del (&itd->itd_list);
1225                         itd_dma = itd->itd_dma;
1226                 } else {
1227                         spin_unlock_irqrestore (&ehci->lock, flags);
1228                         itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1229                                         &itd_dma);
1230                         spin_lock_irqsave (&ehci->lock, flags);
1231                         if (!itd) {
1232                                 iso_sched_free(stream, sched);
1233                                 spin_unlock_irqrestore(&ehci->lock, flags);
1234                                 return -ENOMEM;
1235                         }
1236                 }
1237
1238                 memset (itd, 0, sizeof *itd);
1239                 itd->itd_dma = itd_dma;
1240                 list_add (&itd->itd_list, &sched->td_list);
1241         }
1242         spin_unlock_irqrestore (&ehci->lock, flags);
1243
1244         /* temporarily store schedule info in hcpriv */
1245         urb->hcpriv = sched;
1246         urb->error_count = 0;
1247         return 0;
1248 }
1249
1250 /*-------------------------------------------------------------------------*/
1251
1252 static inline int
1253 itd_slot_ok (
1254         struct ehci_hcd         *ehci,
1255         u32                     mod,
1256         u32                     uframe,
1257         u8                      usecs,
1258         u32                     period
1259 )
1260 {
1261         uframe %= period;
1262         do {
1263                 /* can't commit more than uframe_periodic_max usec */
1264                 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1265                                 > (ehci->uframe_periodic_max - usecs))
1266                         return 0;
1267
1268                 /* we know urb->interval is 2^N uframes */
1269                 uframe += period;
1270         } while (uframe < mod);
1271         return 1;
1272 }
1273
1274 static inline int
1275 sitd_slot_ok (
1276         struct ehci_hcd         *ehci,
1277         u32                     mod,
1278         struct ehci_iso_stream  *stream,
1279         u32                     uframe,
1280         struct ehci_iso_sched   *sched,
1281         u32                     period_uframes
1282 )
1283 {
1284         u32                     mask, tmp;
1285         u32                     frame, uf;
1286
1287         mask = stream->raw_mask << (uframe & 7);
1288
1289         /* for IN, don't wrap CSPLIT into the next frame */
1290         if (mask & ~0xffff)
1291                 return 0;
1292
1293         /* check bandwidth */
1294         uframe %= period_uframes;
1295         frame = uframe >> 3;
1296
1297 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1298         /* The tt's fullspeed bus bandwidth must be available.
1299          * tt_available scheduling guarantees 10+% for control/bulk.
1300          */
1301         uf = uframe & 7;
1302         if (!tt_available(ehci, period_uframes >> 3,
1303                         stream->udev, frame, uf, stream->tt_usecs))
1304                 return 0;
1305 #else
1306         /* tt must be idle for start(s), any gap, and csplit.
1307          * assume scheduling slop leaves 10+% for control/bulk.
1308          */
1309         if (!tt_no_collision(ehci, period_uframes >> 3,
1310                         stream->udev, frame, mask))
1311                 return 0;
1312 #endif
1313
1314         /* this multi-pass logic is simple, but performance may
1315          * suffer when the schedule data isn't cached.
1316          */
1317         do {
1318                 u32             max_used;
1319
1320                 frame = uframe >> 3;
1321                 uf = uframe & 7;
1322
1323                 /* check starts (OUT uses more than one) */
1324                 max_used = ehci->uframe_periodic_max - stream->usecs;
1325                 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1326                         if (periodic_usecs (ehci, frame, uf) > max_used)
1327                                 return 0;
1328                 }
1329
1330                 /* for IN, check CSPLIT */
1331                 if (stream->c_usecs) {
1332                         uf = uframe & 7;
1333                         max_used = ehci->uframe_periodic_max - stream->c_usecs;
1334                         do {
1335                                 tmp = 1 << uf;
1336                                 tmp <<= 8;
1337                                 if ((stream->raw_mask & tmp) == 0)
1338                                         continue;
1339                                 if (periodic_usecs (ehci, frame, uf)
1340                                                 > max_used)
1341                                         return 0;
1342                         } while (++uf < 8);
1343                 }
1344
1345                 /* we know urb->interval is 2^N uframes */
1346                 uframe += period_uframes;
1347         } while (uframe < mod);
1348
1349         stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1350         return 1;
1351 }
1352
1353 /*
1354  * This scheduler plans almost as far into the future as it has actual
1355  * periodic schedule slots.  (Affected by TUNE_FLS, which defaults to
1356  * "as small as possible" to be cache-friendlier.)  That limits the size
1357  * transfers you can stream reliably; avoid more than 64 msec per urb.
1358  * Also avoid queue depths of less than ehci's worst irq latency (affected
1359  * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1360  * and other factors); or more than about 230 msec total (for portability,
1361  * given EHCI_TUNE_FLS and the slop).  Or, write a smarter scheduler!
1362  */
1363
1364 #define SCHEDULE_SLOP   80      /* microframes */
1365
1366 static int
1367 iso_stream_schedule (
1368         struct ehci_hcd         *ehci,
1369         struct urb              *urb,
1370         struct ehci_iso_stream  *stream
1371 )
1372 {
1373         u32                     now, next, start, period, span;
1374         int                     status;
1375         unsigned                mod = ehci->periodic_size << 3;
1376         struct ehci_iso_sched   *sched = urb->hcpriv;
1377
1378         period = urb->interval;
1379         span = sched->span;
1380         if (!stream->highspeed) {
1381                 period <<= 3;
1382                 span <<= 3;
1383         }
1384
1385         if (span > mod - SCHEDULE_SLOP) {
1386                 ehci_dbg (ehci, "iso request %p too long\n", urb);
1387                 status = -EFBIG;
1388                 goto fail;
1389         }
1390
1391         now = ehci_read_frame_index(ehci) & (mod - 1);
1392
1393         /* Typical case: reuse current schedule, stream is still active.
1394          * Hopefully there are no gaps from the host falling behind
1395          * (irq delays etc), but if there are we'll take the next
1396          * slot in the schedule, implicitly assuming URB_ISO_ASAP.
1397          */
1398         if (likely (!list_empty (&stream->td_list))) {
1399                 u32     excess;
1400
1401                 /* For high speed devices, allow scheduling within the
1402                  * isochronous scheduling threshold.  For full speed devices
1403                  * and Intel PCI-based controllers, don't (work around for
1404                  * Intel ICH9 bug).
1405                  */
1406                 if (!stream->highspeed && ehci->fs_i_thresh)
1407                         next = now + ehci->i_thresh;
1408                 else
1409                         next = now;
1410
1411                 /* Fell behind (by up to twice the slop amount)?
1412                  * We decide based on the time of the last currently-scheduled
1413                  * slot, not the time of the next available slot.
1414                  */
1415                 excess = (stream->next_uframe - period - next) & (mod - 1);
1416                 if (excess >= mod - 2 * SCHEDULE_SLOP)
1417                         start = next + excess - mod + period *
1418                                         DIV_ROUND_UP(mod - excess, period);
1419                 else
1420                         start = next + excess + period;
1421                 if (start - now >= mod) {
1422                         ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n",
1423                                         urb, start - now - period, period,
1424                                         mod);
1425                         status = -EFBIG;
1426                         goto fail;
1427                 }
1428         }
1429
1430         /* need to schedule; when's the next (u)frame we could start?
1431          * this is bigger than ehci->i_thresh allows; scheduling itself
1432          * isn't free, the slop should handle reasonably slow cpus.  it
1433          * can also help high bandwidth if the dma and irq loads don't
1434          * jump until after the queue is primed.
1435          */
1436         else {
1437                 int done = 0;
1438                 start = SCHEDULE_SLOP + (now & ~0x07);
1439
1440                 /* NOTE:  assumes URB_ISO_ASAP, to limit complexity/bugs */
1441
1442                 /* find a uframe slot with enough bandwidth.
1443                  * Early uframes are more precious because full-speed
1444                  * iso IN transfers can't use late uframes,
1445                  * and therefore they should be allocated last.
1446                  */
1447                 next = start;
1448                 start += period;
1449                 do {
1450                         start--;
1451                         /* check schedule: enough space? */
1452                         if (stream->highspeed) {
1453                                 if (itd_slot_ok(ehci, mod, start,
1454                                                 stream->usecs, period))
1455                                         done = 1;
1456                         } else {
1457                                 if ((start % 8) >= 6)
1458                                         continue;
1459                                 if (sitd_slot_ok(ehci, mod, stream,
1460                                                 start, sched, period))
1461                                         done = 1;
1462                         }
1463                 } while (start > next && !done);
1464
1465                 /* no room in the schedule */
1466                 if (!done) {
1467                         ehci_dbg(ehci, "iso resched full %p (now %d max %d)\n",
1468                                 urb, now, now + mod);
1469                         status = -ENOSPC;
1470                         goto fail;
1471                 }
1472         }
1473
1474         /* Tried to schedule too far into the future? */
1475         if (unlikely(start - now + span - period
1476                                 >= mod - 2 * SCHEDULE_SLOP)) {
1477                 ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n",
1478                                 urb, start - now, span - period,
1479                                 mod - 2 * SCHEDULE_SLOP);
1480                 status = -EFBIG;
1481                 goto fail;
1482         }
1483
1484         stream->next_uframe = start & (mod - 1);
1485
1486         /* report high speed start in uframes; full speed, in frames */
1487         urb->start_frame = stream->next_uframe;
1488         if (!stream->highspeed)
1489                 urb->start_frame >>= 3;
1490         return 0;
1491
1492  fail:
1493         iso_sched_free(stream, sched);
1494         urb->hcpriv = NULL;
1495         return status;
1496 }
1497
1498 /*-------------------------------------------------------------------------*/
1499
1500 static inline void
1501 itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1502                 struct ehci_itd *itd)
1503 {
1504         int i;
1505
1506         /* it's been recently zeroed */
1507         itd->hw_next = EHCI_LIST_END(ehci);
1508         itd->hw_bufp [0] = stream->buf0;
1509         itd->hw_bufp [1] = stream->buf1;
1510         itd->hw_bufp [2] = stream->buf2;
1511
1512         for (i = 0; i < 8; i++)
1513                 itd->index[i] = -1;
1514
1515         /* All other fields are filled when scheduling */
1516 }
1517
1518 static inline void
1519 itd_patch(
1520         struct ehci_hcd         *ehci,
1521         struct ehci_itd         *itd,
1522         struct ehci_iso_sched   *iso_sched,
1523         unsigned                index,
1524         u16                     uframe
1525 )
1526 {
1527         struct ehci_iso_packet  *uf = &iso_sched->packet [index];
1528         unsigned                pg = itd->pg;
1529
1530         // BUG_ON (pg == 6 && uf->cross);
1531
1532         uframe &= 0x07;
1533         itd->index [uframe] = index;
1534
1535         itd->hw_transaction[uframe] = uf->transaction;
1536         itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1537         itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1538         itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1539
1540         /* iso_frame_desc[].offset must be strictly increasing */
1541         if (unlikely (uf->cross)) {
1542                 u64     bufp = uf->bufp + 4096;
1543
1544                 itd->pg = ++pg;
1545                 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1546                 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1547         }
1548 }
1549
1550 static inline void
1551 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1552 {
1553         union ehci_shadow       *prev = &ehci->pshadow[frame];
1554         __hc32                  *hw_p = &ehci->periodic[frame];
1555         union ehci_shadow       here = *prev;
1556         __hc32                  type = 0;
1557
1558         /* skip any iso nodes which might belong to previous microframes */
1559         while (here.ptr) {
1560                 type = Q_NEXT_TYPE(ehci, *hw_p);
1561                 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
1562                         break;
1563                 prev = periodic_next_shadow(ehci, prev, type);
1564                 hw_p = shadow_next_periodic(ehci, &here, type);
1565                 here = *prev;
1566         }
1567
1568         itd->itd_next = here;
1569         itd->hw_next = *hw_p;
1570         prev->itd = itd;
1571         itd->frame = frame;
1572         wmb ();
1573         *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1574 }
1575
1576 /* fit urb's itds into the selected schedule slot; activate as needed */
1577 static int
1578 itd_link_urb (
1579         struct ehci_hcd         *ehci,
1580         struct urb              *urb,
1581         unsigned                mod,
1582         struct ehci_iso_stream  *stream
1583 )
1584 {
1585         int                     packet;
1586         unsigned                next_uframe, uframe, frame;
1587         struct ehci_iso_sched   *iso_sched = urb->hcpriv;
1588         struct ehci_itd         *itd;
1589
1590         next_uframe = stream->next_uframe & (mod - 1);
1591
1592         if (unlikely (list_empty(&stream->td_list))) {
1593                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1594                                 += stream->bandwidth;
1595                 ehci_vdbg (ehci,
1596                         "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1597                         urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1598                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1599                         urb->interval,
1600                         next_uframe >> 3, next_uframe & 0x7);
1601         }
1602
1603         if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
1604                 if (ehci->amd_pll_fix == 1)
1605                         usb_amd_quirk_pll_disable();
1606         }
1607
1608         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1609
1610         /* fill iTDs uframe by uframe */
1611         for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1612                 if (itd == NULL) {
1613                         /* ASSERT:  we have all necessary itds */
1614                         // BUG_ON (list_empty (&iso_sched->td_list));
1615
1616                         /* ASSERT:  no itds for this endpoint in this uframe */
1617
1618                         itd = list_entry (iso_sched->td_list.next,
1619                                         struct ehci_itd, itd_list);
1620                         list_move_tail (&itd->itd_list, &stream->td_list);
1621                         itd->stream = iso_stream_get (stream);
1622                         itd->urb = urb;
1623                         itd_init (ehci, stream, itd);
1624                 }
1625
1626                 uframe = next_uframe & 0x07;
1627                 frame = next_uframe >> 3;
1628
1629                 itd_patch(ehci, itd, iso_sched, packet, uframe);
1630
1631                 next_uframe += stream->interval;
1632                 next_uframe &= mod - 1;
1633                 packet++;
1634
1635                 /* link completed itds into the schedule */
1636                 if (((next_uframe >> 3) != frame)
1637                                 || packet == urb->number_of_packets) {
1638                         itd_link(ehci, frame & (ehci->periodic_size - 1), itd);
1639                         itd = NULL;
1640                 }
1641         }
1642         stream->next_uframe = next_uframe;
1643
1644         /* don't need that schedule data any more */
1645         iso_sched_free (stream, iso_sched);
1646         urb->hcpriv = NULL;
1647
1648         timer_action (ehci, TIMER_IO_WATCHDOG);
1649         return enable_periodic(ehci);
1650 }
1651
1652 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1653
1654 /* Process and recycle a completed ITD.  Return true iff its urb completed,
1655  * and hence its completion callback probably added things to the hardware
1656  * schedule.
1657  *
1658  * Note that we carefully avoid recycling this descriptor until after any
1659  * completion callback runs, so that it won't be reused quickly.  That is,
1660  * assuming (a) no more than two urbs per frame on this endpoint, and also
1661  * (b) only this endpoint's completions submit URBs.  It seems some silicon
1662  * corrupts things if you reuse completed descriptors very quickly...
1663  */
1664 static unsigned
1665 itd_complete (
1666         struct ehci_hcd *ehci,
1667         struct ehci_itd *itd
1668 ) {
1669         struct urb                              *urb = itd->urb;
1670         struct usb_iso_packet_descriptor        *desc;
1671         u32                                     t;
1672         unsigned                                uframe;
1673         int                                     urb_index = -1;
1674         struct ehci_iso_stream                  *stream = itd->stream;
1675         struct usb_device                       *dev;
1676         unsigned                                retval = false;
1677
1678         /* for each uframe with a packet */
1679         for (uframe = 0; uframe < 8; uframe++) {
1680                 if (likely (itd->index[uframe] == -1))
1681                         continue;
1682                 urb_index = itd->index[uframe];
1683                 desc = &urb->iso_frame_desc [urb_index];
1684
1685                 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1686                 itd->hw_transaction [uframe] = 0;
1687
1688                 /* report transfer status */
1689                 if (unlikely (t & ISO_ERRS)) {
1690                         urb->error_count++;
1691                         if (t & EHCI_ISOC_BUF_ERR)
1692                                 desc->status = usb_pipein (urb->pipe)
1693                                         ? -ENOSR  /* hc couldn't read */
1694                                         : -ECOMM; /* hc couldn't write */
1695                         else if (t & EHCI_ISOC_BABBLE)
1696                                 desc->status = -EOVERFLOW;
1697                         else /* (t & EHCI_ISOC_XACTERR) */
1698                                 desc->status = -EPROTO;
1699
1700                         /* HC need not update length with this error */
1701                         if (!(t & EHCI_ISOC_BABBLE)) {
1702                                 desc->actual_length = EHCI_ITD_LENGTH(t);
1703                                 urb->actual_length += desc->actual_length;
1704                         }
1705                 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1706                         desc->status = 0;
1707                         desc->actual_length = EHCI_ITD_LENGTH(t);
1708                         urb->actual_length += desc->actual_length;
1709                 } else {
1710                         /* URB was too late */
1711                         desc->status = -EXDEV;
1712                 }
1713         }
1714
1715         /* handle completion now? */
1716         if (likely ((urb_index + 1) != urb->number_of_packets))
1717                 goto done;
1718
1719         /* ASSERT: it's really the last itd for this urb
1720         list_for_each_entry (itd, &stream->td_list, itd_list)
1721                 BUG_ON (itd->urb == urb);
1722          */
1723
1724         /* give urb back to the driver; completion often (re)submits */
1725         dev = urb->dev;
1726         ehci_urb_done(ehci, urb, 0);
1727         retval = true;
1728         urb = NULL;
1729         (void) disable_periodic(ehci);
1730         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1731
1732         if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
1733                 if (ehci->amd_pll_fix == 1)
1734                         usb_amd_quirk_pll_enable();
1735         }
1736
1737         if (unlikely(list_is_singular(&stream->td_list))) {
1738                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1739                                 -= stream->bandwidth;
1740                 ehci_vdbg (ehci,
1741                         "deschedule devp %s ep%d%s-iso\n",
1742                         dev->devpath, stream->bEndpointAddress & 0x0f,
1743                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1744         }
1745         iso_stream_put (ehci, stream);
1746
1747 done:
1748         itd->urb = NULL;
1749         if (ehci->clock_frame != itd->frame || itd->index[7] != -1) {
1750                 /* OK to recycle this ITD now. */
1751                 itd->stream = NULL;
1752                 list_move(&itd->itd_list, &stream->free_list);
1753                 iso_stream_put(ehci, stream);
1754         } else {
1755                 /* HW might remember this ITD, so we can't recycle it yet.
1756                  * Move it to a safe place until a new frame starts.
1757                  */
1758                 list_move(&itd->itd_list, &ehci->cached_itd_list);
1759                 if (stream->refcount == 2) {
1760                         /* If iso_stream_put() were called here, stream
1761                          * would be freed.  Instead, just prevent reuse.
1762                          */
1763                         stream->ep->hcpriv = NULL;
1764                         stream->ep = NULL;
1765                 }
1766         }
1767         return retval;
1768 }
1769
1770 /*-------------------------------------------------------------------------*/
1771
1772 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
1773         gfp_t mem_flags)
1774 {
1775         int                     status = -EINVAL;
1776         unsigned long           flags;
1777         struct ehci_iso_stream  *stream;
1778
1779         /* Get iso_stream head */
1780         stream = iso_stream_find (ehci, urb);
1781         if (unlikely (stream == NULL)) {
1782                 ehci_dbg (ehci, "can't get iso stream\n");
1783                 return -ENOMEM;
1784         }
1785         if (unlikely (urb->interval != stream->interval)) {
1786                 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1787                         stream->interval, urb->interval);
1788                 goto done;
1789         }
1790
1791 #ifdef EHCI_URB_TRACE
1792         ehci_dbg (ehci,
1793                 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1794                 __func__, urb->dev->devpath, urb,
1795                 usb_pipeendpoint (urb->pipe),
1796                 usb_pipein (urb->pipe) ? "in" : "out",
1797                 urb->transfer_buffer_length,
1798                 urb->number_of_packets, urb->interval,
1799                 stream);
1800 #endif
1801
1802         /* allocate ITDs w/o locking anything */
1803         status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1804         if (unlikely (status < 0)) {
1805                 ehci_dbg (ehci, "can't init itds\n");
1806                 goto done;
1807         }
1808
1809         /* schedule ... need to lock */
1810         spin_lock_irqsave (&ehci->lock, flags);
1811         if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
1812                 status = -ESHUTDOWN;
1813                 goto done_not_linked;
1814         }
1815         status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
1816         if (unlikely(status))
1817                 goto done_not_linked;
1818         status = iso_stream_schedule(ehci, urb, stream);
1819         if (likely (status == 0))
1820                 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1821         else
1822                 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
1823 done_not_linked:
1824         spin_unlock_irqrestore (&ehci->lock, flags);
1825
1826 done:
1827         if (unlikely (status < 0))
1828                 iso_stream_put (ehci, stream);
1829         return status;
1830 }
1831
1832 /*-------------------------------------------------------------------------*/
1833
1834 /*
1835  * "Split ISO TDs" ... used for USB 1.1 devices going through the
1836  * TTs in USB 2.0 hubs.  These need microframe scheduling.
1837  */
1838
1839 static inline void
1840 sitd_sched_init(
1841         struct ehci_hcd         *ehci,
1842         struct ehci_iso_sched   *iso_sched,
1843         struct ehci_iso_stream  *stream,
1844         struct urb              *urb
1845 )
1846 {
1847         unsigned        i;
1848         dma_addr_t      dma = urb->transfer_dma;
1849
1850         /* how many frames are needed for these transfers */
1851         iso_sched->span = urb->number_of_packets * stream->interval;
1852
1853         /* figure out per-frame sitd fields that we'll need later
1854          * when we fit new sitds into the schedule.
1855          */
1856         for (i = 0; i < urb->number_of_packets; i++) {
1857                 struct ehci_iso_packet  *packet = &iso_sched->packet [i];
1858                 unsigned                length;
1859                 dma_addr_t              buf;
1860                 u32                     trans;
1861
1862                 length = urb->iso_frame_desc [i].length & 0x03ff;
1863                 buf = dma + urb->iso_frame_desc [i].offset;
1864
1865                 trans = SITD_STS_ACTIVE;
1866                 if (((i + 1) == urb->number_of_packets)
1867                                 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1868                         trans |= SITD_IOC;
1869                 trans |= length << 16;
1870                 packet->transaction = cpu_to_hc32(ehci, trans);
1871
1872                 /* might need to cross a buffer page within a td */
1873                 packet->bufp = buf;
1874                 packet->buf1 = (buf + length) & ~0x0fff;
1875                 if (packet->buf1 != (buf & ~(u64)0x0fff))
1876                         packet->cross = 1;
1877
1878                 /* OUT uses multiple start-splits */
1879                 if (stream->bEndpointAddress & USB_DIR_IN)
1880                         continue;
1881                 length = (length + 187) / 188;
1882                 if (length > 1) /* BEGIN vs ALL */
1883                         length |= 1 << 3;
1884                 packet->buf1 |= length;
1885         }
1886 }
1887
1888 static int
1889 sitd_urb_transaction (
1890         struct ehci_iso_stream  *stream,
1891         struct ehci_hcd         *ehci,
1892         struct urb              *urb,
1893         gfp_t                   mem_flags
1894 )
1895 {
1896         struct ehci_sitd        *sitd;
1897         dma_addr_t              sitd_dma;
1898         int                     i;
1899         struct ehci_iso_sched   *iso_sched;
1900         unsigned long           flags;
1901
1902         iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1903         if (iso_sched == NULL)
1904                 return -ENOMEM;
1905
1906         sitd_sched_init(ehci, iso_sched, stream, urb);
1907
1908         /* allocate/init sITDs */
1909         spin_lock_irqsave (&ehci->lock, flags);
1910         for (i = 0; i < urb->number_of_packets; i++) {
1911
1912                 /* NOTE:  for now, we don't try to handle wraparound cases
1913                  * for IN (using sitd->hw_backpointer, like a FSTN), which
1914                  * means we never need two sitds for full speed packets.
1915                  */
1916
1917                 /* free_list.next might be cache-hot ... but maybe
1918                  * the HC caches it too. avoid that issue for now.
1919                  */
1920
1921                 /* prefer previously-allocated sitds */
1922                 if (!list_empty(&stream->free_list)) {
1923                         sitd = list_entry (stream->free_list.prev,
1924                                          struct ehci_sitd, sitd_list);
1925                         list_del (&sitd->sitd_list);
1926                         sitd_dma = sitd->sitd_dma;
1927                 } else {
1928                         spin_unlock_irqrestore (&ehci->lock, flags);
1929                         sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1930                                         &sitd_dma);
1931                         spin_lock_irqsave (&ehci->lock, flags);
1932                         if (!sitd) {
1933                                 iso_sched_free(stream, iso_sched);
1934                                 spin_unlock_irqrestore(&ehci->lock, flags);
1935                                 return -ENOMEM;
1936                         }
1937                 }
1938
1939                 memset (sitd, 0, sizeof *sitd);
1940                 sitd->sitd_dma = sitd_dma;
1941                 list_add (&sitd->sitd_list, &iso_sched->td_list);
1942         }
1943
1944         /* temporarily store schedule info in hcpriv */
1945         urb->hcpriv = iso_sched;
1946         urb->error_count = 0;
1947
1948         spin_unlock_irqrestore (&ehci->lock, flags);
1949         return 0;
1950 }
1951
1952 /*-------------------------------------------------------------------------*/
1953
1954 static inline void
1955 sitd_patch(
1956         struct ehci_hcd         *ehci,
1957         struct ehci_iso_stream  *stream,
1958         struct ehci_sitd        *sitd,
1959         struct ehci_iso_sched   *iso_sched,
1960         unsigned                index
1961 )
1962 {
1963         struct ehci_iso_packet  *uf = &iso_sched->packet [index];
1964         u64                     bufp = uf->bufp;
1965
1966         sitd->hw_next = EHCI_LIST_END(ehci);
1967         sitd->hw_fullspeed_ep = stream->address;
1968         sitd->hw_uframe = stream->splits;
1969         sitd->hw_results = uf->transaction;
1970         sitd->hw_backpointer = EHCI_LIST_END(ehci);
1971
1972         bufp = uf->bufp;
1973         sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
1974         sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
1975
1976         sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
1977         if (uf->cross)
1978                 bufp += 4096;
1979         sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
1980         sitd->index = index;
1981 }
1982
1983 static inline void
1984 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1985 {
1986         /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1987         sitd->sitd_next = ehci->pshadow [frame];
1988         sitd->hw_next = ehci->periodic [frame];
1989         ehci->pshadow [frame].sitd = sitd;
1990         sitd->frame = frame;
1991         wmb ();
1992         ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
1993 }
1994
1995 /* fit urb's sitds into the selected schedule slot; activate as needed */
1996 static int
1997 sitd_link_urb (
1998         struct ehci_hcd         *ehci,
1999         struct urb              *urb,
2000         unsigned                mod,
2001         struct ehci_iso_stream  *stream
2002 )
2003 {
2004         int                     packet;
2005         unsigned                next_uframe;
2006         struct ehci_iso_sched   *sched = urb->hcpriv;
2007         struct ehci_sitd        *sitd;
2008
2009         next_uframe = stream->next_uframe;
2010
2011         if (list_empty(&stream->td_list)) {
2012                 /* usbfs ignores TT bandwidth */
2013                 ehci_to_hcd(ehci)->self.bandwidth_allocated
2014                                 += stream->bandwidth;
2015                 ehci_vdbg (ehci,
2016                         "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
2017                         urb->dev->devpath, stream->bEndpointAddress & 0x0f,
2018                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
2019                         (next_uframe >> 3) & (ehci->periodic_size - 1),
2020                         stream->interval, hc32_to_cpu(ehci, stream->splits));
2021         }
2022
2023         if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
2024                 if (ehci->amd_pll_fix == 1)
2025                         usb_amd_quirk_pll_disable();
2026         }
2027
2028         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
2029
2030         /* fill sITDs frame by frame */
2031         for (packet = 0, sitd = NULL;
2032                         packet < urb->number_of_packets;
2033                         packet++) {
2034
2035                 /* ASSERT:  we have all necessary sitds */
2036                 BUG_ON (list_empty (&sched->td_list));
2037
2038                 /* ASSERT:  no itds for this endpoint in this frame */
2039
2040                 sitd = list_entry (sched->td_list.next,
2041                                 struct ehci_sitd, sitd_list);
2042                 list_move_tail (&sitd->sitd_list, &stream->td_list);
2043                 sitd->stream = iso_stream_get (stream);
2044                 sitd->urb = urb;
2045
2046                 sitd_patch(ehci, stream, sitd, sched, packet);
2047                 sitd_link(ehci, (next_uframe >> 3) & (ehci->periodic_size - 1),
2048                                 sitd);
2049
2050                 next_uframe += stream->interval << 3;
2051         }
2052         stream->next_uframe = next_uframe & (mod - 1);
2053
2054         /* don't need that schedule data any more */
2055         iso_sched_free (stream, sched);
2056         urb->hcpriv = NULL;
2057
2058         timer_action (ehci, TIMER_IO_WATCHDOG);
2059         return enable_periodic(ehci);
2060 }
2061
2062 /*-------------------------------------------------------------------------*/
2063
2064 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
2065                                 | SITD_STS_XACT | SITD_STS_MMF)
2066
2067 /* Process and recycle a completed SITD.  Return true iff its urb completed,
2068  * and hence its completion callback probably added things to the hardware
2069  * schedule.
2070  *
2071  * Note that we carefully avoid recycling this descriptor until after any
2072  * completion callback runs, so that it won't be reused quickly.  That is,
2073  * assuming (a) no more than two urbs per frame on this endpoint, and also
2074  * (b) only this endpoint's completions submit URBs.  It seems some silicon
2075  * corrupts things if you reuse completed descriptors very quickly...
2076  */
2077 static unsigned
2078 sitd_complete (
2079         struct ehci_hcd         *ehci,
2080         struct ehci_sitd        *sitd
2081 ) {
2082         struct urb                              *urb = sitd->urb;
2083         struct usb_iso_packet_descriptor        *desc;
2084         u32                                     t;
2085         int                                     urb_index = -1;
2086         struct ehci_iso_stream                  *stream = sitd->stream;
2087         struct usb_device                       *dev;
2088         unsigned                                retval = false;
2089
2090         urb_index = sitd->index;
2091         desc = &urb->iso_frame_desc [urb_index];
2092         t = hc32_to_cpup(ehci, &sitd->hw_results);
2093
2094         /* report transfer status */
2095         if (t & SITD_ERRS) {
2096                 urb->error_count++;
2097                 if (t & SITD_STS_DBE)
2098                         desc->status = usb_pipein (urb->pipe)
2099                                 ? -ENOSR  /* hc couldn't read */
2100                                 : -ECOMM; /* hc couldn't write */
2101                 else if (t & SITD_STS_BABBLE)
2102                         desc->status = -EOVERFLOW;
2103                 else /* XACT, MMF, etc */
2104                         desc->status = -EPROTO;
2105         } else {
2106                 desc->status = 0;
2107                 desc->actual_length = desc->length - SITD_LENGTH(t);
2108                 urb->actual_length += desc->actual_length;
2109         }
2110
2111         /* handle completion now? */
2112         if ((urb_index + 1) != urb->number_of_packets)
2113                 goto done;
2114
2115         /* ASSERT: it's really the last sitd for this urb
2116         list_for_each_entry (sitd, &stream->td_list, sitd_list)
2117                 BUG_ON (sitd->urb == urb);
2118          */
2119
2120         /* give urb back to the driver; completion often (re)submits */
2121         dev = urb->dev;
2122         ehci_urb_done(ehci, urb, 0);
2123         retval = true;
2124         urb = NULL;
2125         (void) disable_periodic(ehci);
2126         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2127
2128         if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
2129                 if (ehci->amd_pll_fix == 1)
2130                         usb_amd_quirk_pll_enable();
2131         }
2132
2133         if (list_is_singular(&stream->td_list)) {
2134                 ehci_to_hcd(ehci)->self.bandwidth_allocated
2135                                 -= stream->bandwidth;
2136                 ehci_vdbg (ehci,
2137                         "deschedule devp %s ep%d%s-iso\n",
2138                         dev->devpath, stream->bEndpointAddress & 0x0f,
2139                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2140         }
2141         iso_stream_put (ehci, stream);
2142
2143 done:
2144         sitd->urb = NULL;
2145         if (ehci->clock_frame != sitd->frame) {
2146                 /* OK to recycle this SITD now. */
2147                 sitd->stream = NULL;
2148                 list_move(&sitd->sitd_list, &stream->free_list);
2149                 iso_stream_put(ehci, stream);
2150         } else {
2151                 /* HW might remember this SITD, so we can't recycle it yet.
2152                  * Move it to a safe place until a new frame starts.
2153                  */
2154                 list_move(&sitd->sitd_list, &ehci->cached_sitd_list);
2155                 if (stream->refcount == 2) {
2156                         /* If iso_stream_put() were called here, stream
2157                          * would be freed.  Instead, just prevent reuse.
2158                          */
2159                         stream->ep->hcpriv = NULL;
2160                         stream->ep = NULL;
2161                 }
2162         }
2163         return retval;
2164 }
2165
2166
2167 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
2168         gfp_t mem_flags)
2169 {
2170         int                     status = -EINVAL;
2171         unsigned long           flags;
2172         struct ehci_iso_stream  *stream;
2173
2174         /* Get iso_stream head */
2175         stream = iso_stream_find (ehci, urb);
2176         if (stream == NULL) {
2177                 ehci_dbg (ehci, "can't get iso stream\n");
2178                 return -ENOMEM;
2179         }
2180         if (urb->interval != stream->interval) {
2181                 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2182                         stream->interval, urb->interval);
2183                 goto done;
2184         }
2185
2186 #ifdef EHCI_URB_TRACE
2187         ehci_dbg (ehci,
2188                 "submit %p dev%s ep%d%s-iso len %d\n",
2189                 urb, urb->dev->devpath,
2190                 usb_pipeendpoint (urb->pipe),
2191                 usb_pipein (urb->pipe) ? "in" : "out",
2192                 urb->transfer_buffer_length);
2193 #endif
2194
2195         /* allocate SITDs */
2196         status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2197         if (status < 0) {
2198                 ehci_dbg (ehci, "can't init sitds\n");
2199                 goto done;
2200         }
2201
2202         /* schedule ... need to lock */
2203         spin_lock_irqsave (&ehci->lock, flags);
2204         if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
2205                 status = -ESHUTDOWN;
2206                 goto done_not_linked;
2207         }
2208         status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
2209         if (unlikely(status))
2210                 goto done_not_linked;
2211         status = iso_stream_schedule(ehci, urb, stream);
2212         if (status == 0)
2213                 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
2214         else
2215                 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
2216 done_not_linked:
2217         spin_unlock_irqrestore (&ehci->lock, flags);
2218
2219 done:
2220         if (status < 0)
2221                 iso_stream_put (ehci, stream);
2222         return status;
2223 }
2224
2225 /*-------------------------------------------------------------------------*/
2226
2227 static void free_cached_lists(struct ehci_hcd *ehci)
2228 {
2229         struct ehci_itd *itd, *n;
2230         struct ehci_sitd *sitd, *sn;
2231
2232         list_for_each_entry_safe(itd, n, &ehci->cached_itd_list, itd_list) {
2233                 struct ehci_iso_stream  *stream = itd->stream;
2234                 itd->stream = NULL;
2235                 list_move(&itd->itd_list, &stream->free_list);
2236                 iso_stream_put(ehci, stream);
2237         }
2238
2239         list_for_each_entry_safe(sitd, sn, &ehci->cached_sitd_list, sitd_list) {
2240                 struct ehci_iso_stream  *stream = sitd->stream;
2241                 sitd->stream = NULL;
2242                 list_move(&sitd->sitd_list, &stream->free_list);
2243                 iso_stream_put(ehci, stream);
2244         }
2245 }
2246
2247 /*-------------------------------------------------------------------------*/
2248
2249 static void
2250 scan_periodic (struct ehci_hcd *ehci)
2251 {
2252         unsigned        now_uframe, frame, clock, clock_frame, mod;
2253         unsigned        modified;
2254
2255         mod = ehci->periodic_size << 3;
2256
2257         /*
2258          * When running, scan from last scan point up to "now"
2259          * else clean up by scanning everything that's left.
2260          * Touches as few pages as possible:  cache-friendly.
2261          */
2262         now_uframe = ehci->next_uframe;
2263         if (ehci->rh_state >= EHCI_RH_RUNNING) {
2264                 clock = ehci_read_frame_index(ehci);
2265                 clock_frame = (clock >> 3) & (ehci->periodic_size - 1);
2266         } else  {
2267                 clock = now_uframe + mod - 1;
2268                 clock_frame = -1;
2269         }
2270         if (ehci->clock_frame != clock_frame) {
2271                 free_cached_lists(ehci);
2272                 ehci->clock_frame = clock_frame;
2273         }
2274         clock &= mod - 1;
2275         clock_frame = clock >> 3;
2276         ++ehci->periodic_stamp;
2277
2278         for (;;) {
2279                 union ehci_shadow       q, *q_p;
2280                 __hc32                  type, *hw_p;
2281                 unsigned                incomplete = false;
2282
2283                 frame = now_uframe >> 3;
2284
2285 restart:
2286                 /* scan each element in frame's queue for completions */
2287                 q_p = &ehci->pshadow [frame];
2288                 hw_p = &ehci->periodic [frame];
2289                 q.ptr = q_p->ptr;
2290                 type = Q_NEXT_TYPE(ehci, *hw_p);
2291                 modified = 0;
2292
2293                 while (q.ptr != NULL) {
2294                         unsigned                uf;
2295                         union ehci_shadow       temp;
2296                         int                     live;
2297
2298                         live = (ehci->rh_state >= EHCI_RH_RUNNING);
2299                         switch (hc32_to_cpu(ehci, type)) {
2300                         case Q_TYPE_QH:
2301                                 /* handle any completions */
2302                                 temp.qh = q.qh;
2303                                 type = Q_NEXT_TYPE(ehci, q.qh->hw->hw_next);
2304                                 q = q.qh->qh_next;
2305                                 if (temp.qh->stamp != ehci->periodic_stamp) {
2306                                         modified = qh_completions(ehci, temp.qh);
2307                                         if (!modified)
2308                                                 temp.qh->stamp = ehci->periodic_stamp;
2309                                         if (unlikely(list_empty(&temp.qh->qtd_list) ||
2310                                                         temp.qh->needs_rescan))
2311                                                 intr_deschedule(ehci, temp.qh);
2312                                 }
2313                                 break;
2314                         case Q_TYPE_FSTN:
2315                                 /* for "save place" FSTNs, look at QH entries
2316                                  * in the previous frame for completions.
2317                                  */
2318                                 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
2319                                         ehci_dbg(ehci,
2320                                                 "ignoring completions from FSTNs\n");
2321                                 }
2322                                 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
2323                                 q = q.fstn->fstn_next;
2324                                 break;
2325                         case Q_TYPE_ITD:
2326                                 /* If this ITD is still active, leave it for
2327                                  * later processing ... check the next entry.
2328                                  * No need to check for activity unless the
2329                                  * frame is current.
2330                                  */
2331                                 if (frame == clock_frame && live) {
2332                                         rmb();
2333                                         for (uf = 0; uf < 8; uf++) {
2334                                                 if (q.itd->hw_transaction[uf] &
2335                                                             ITD_ACTIVE(ehci))
2336                                                         break;
2337                                         }
2338                                         if (uf < 8) {
2339                                                 incomplete = true;
2340                                                 q_p = &q.itd->itd_next;
2341                                                 hw_p = &q.itd->hw_next;
2342                                                 type = Q_NEXT_TYPE(ehci,
2343                                                         q.itd->hw_next);
2344                                                 q = *q_p;
2345                                                 break;
2346                                         }
2347                                 }
2348
2349                                 /* Take finished ITDs out of the schedule
2350                                  * and process them:  recycle, maybe report
2351                                  * URB completion.  HC won't cache the
2352                                  * pointer for much longer, if at all.
2353                                  */
2354                                 *q_p = q.itd->itd_next;
2355                                 if (!ehci->use_dummy_qh ||
2356                                     q.itd->hw_next != EHCI_LIST_END(ehci))
2357                                         *hw_p = q.itd->hw_next;
2358                                 else
2359                                         *hw_p = ehci->dummy->qh_dma;
2360                                 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
2361                                 wmb();
2362                                 modified = itd_complete (ehci, q.itd);
2363                                 q = *q_p;
2364                                 break;
2365                         case Q_TYPE_SITD:
2366                                 /* If this SITD is still active, leave it for
2367                                  * later processing ... check the next entry.
2368                                  * No need to check for activity unless the
2369                                  * frame is current.
2370                                  */
2371                                 if (((frame == clock_frame) ||
2372                                      (((frame + 1) & (ehci->periodic_size - 1))
2373                                       == clock_frame))
2374                                     && live
2375                                     && (q.sitd->hw_results &
2376                                         SITD_ACTIVE(ehci))) {
2377
2378                                         incomplete = true;
2379                                         q_p = &q.sitd->sitd_next;
2380                                         hw_p = &q.sitd->hw_next;
2381                                         type = Q_NEXT_TYPE(ehci,
2382                                                         q.sitd->hw_next);
2383                                         q = *q_p;
2384                                         break;
2385                                 }
2386
2387                                 /* Take finished SITDs out of the schedule
2388                                  * and process them:  recycle, maybe report
2389                                  * URB completion.
2390                                  */
2391                                 *q_p = q.sitd->sitd_next;
2392                                 if (!ehci->use_dummy_qh ||
2393                                     q.sitd->hw_next != EHCI_LIST_END(ehci))
2394                                         *hw_p = q.sitd->hw_next;
2395                                 else
2396                                         *hw_p = ehci->dummy->qh_dma;
2397                                 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
2398                                 wmb();
2399                                 modified = sitd_complete (ehci, q.sitd);
2400                                 q = *q_p;
2401                                 break;
2402                         default:
2403                                 ehci_dbg(ehci, "corrupt type %d frame %d shadow %p\n",
2404                                         type, frame, q.ptr);
2405                                 // BUG ();
2406                                 q.ptr = NULL;
2407                         }
2408
2409                         /* assume completion callbacks modify the queue */
2410                         if (unlikely (modified)) {
2411                                 if (likely(ehci->periodic_count > 0))
2412                                         goto restart;
2413                                 /* short-circuit this scan */
2414                                 now_uframe = clock;
2415                                 break;
2416                         }
2417                 }
2418
2419                 /* If we can tell we caught up to the hardware, stop now.
2420                  * We can't advance our scan without collecting the ISO
2421                  * transfers that are still pending in this frame.
2422                  */
2423                 if (incomplete && ehci->rh_state >= EHCI_RH_RUNNING) {
2424                         ehci->next_uframe = now_uframe;
2425                         break;
2426                 }
2427
2428                 // FIXME:  this assumes we won't get lapped when
2429                 // latencies climb; that should be rare, but...
2430                 // detect it, and just go all the way around.
2431                 // FLR might help detect this case, so long as latencies
2432                 // don't exceed periodic_size msec (default 1.024 sec).
2433
2434                 // FIXME:  likewise assumes HC doesn't halt mid-scan
2435
2436                 if (now_uframe == clock) {
2437                         unsigned        now;
2438
2439                         if (ehci->rh_state < EHCI_RH_RUNNING
2440                                         || ehci->periodic_count == 0)
2441                                 break;
2442                         ehci->next_uframe = now_uframe;
2443                         now = ehci_read_frame_index(ehci) & (mod - 1);
2444                         if (now_uframe == now)
2445                                 break;
2446
2447                         /* rescan the rest of this frame, then ... */
2448                         clock = now;
2449                         clock_frame = clock >> 3;
2450                         if (ehci->clock_frame != clock_frame) {
2451                                 free_cached_lists(ehci);
2452                                 ehci->clock_frame = clock_frame;
2453                                 ++ehci->periodic_stamp;
2454                         }
2455                 } else {
2456                         now_uframe++;
2457                         now_uframe &= mod - 1;
2458                 }
2459         }
2460 }