drivers/usb/host/ehci-tegra.c

   1 /*
   2  * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Copyright (C) 2009 NVIDIA Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/err.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/platform_data/tegra_usb.h>
  23 #include <linux/irq.h>
  24 #include <linux/usb/otg.h>
  25 #include <linux/gpio.h>
  26 #include <linux/of.h>
  27 #include <linux/of_gpio.h>
  28 #include <linux/pm_runtime.h>
  29
  30 #include <linux/usb/tegra_usb_phy.h>
  31
  32 #define TEGRA_USB_BASE                  0xC5000000
  33 #define TEGRA_USB2_BASE                 0xC5004000
  34 #define TEGRA_USB3_BASE                 0xC5008000
  35
  36 #define TEGRA_USB_DMA_ALIGN 32
  37
  38 struct tegra_ehci_hcd {
  39         struct ehci_hcd *ehci;
  40         struct tegra_usb_phy *phy;
  41         struct clk *clk;
  42         struct clk *emc_clk;
  43         struct usb_phy *transceiver;
  44         int host_resumed;
  45         int port_resuming;
  46         enum tegra_usb_phy_port_speed port_speed;
  47 };
  48
  49 static void tegra_ehci_power_up(struct usb_hcd *hcd)
  50 {
  51         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
  52
  53         clk_prepare_enable(tegra->emc_clk);
  54         clk_prepare_enable(tegra->clk);
  55         usb_phy_set_suspend(&tegra->phy->u_phy, 0);
  56         tegra->host_resumed = 1;
  57 }
  58
  59 static void tegra_ehci_power_down(struct usb_hcd *hcd)
  60 {
  61         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
  62
  63         tegra->host_resumed = 0;
  64         usb_phy_set_suspend(&tegra->phy->u_phy, 1);
  65         clk_disable_unprepare(tegra->clk);
  66         clk_disable_unprepare(tegra->emc_clk);
  67 }
  68
  69 static int tegra_ehci_internal_port_reset(
  70         struct ehci_hcd *ehci,
  71         u32 __iomem     *portsc_reg
  72 )
  73 {
  74         u32             temp;
  75         unsigned long   flags;
  76         int             retval = 0;
  77         int             i, tries;
  78         u32             saved_usbintr;
  79
  80         spin_lock_irqsave(&ehci->lock, flags);
  81         saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
  82         /* disable USB interrupt */
  83         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
  84         spin_unlock_irqrestore(&ehci->lock, flags);
  85
  86         /*
  87          * Here we have to do Port Reset at most twice for
  88          * Port Enable bit to be set.
  89          */
  90         for (i = 0; i < 2; i++) {
  91                 temp = ehci_readl(ehci, portsc_reg);
  92                 temp |= PORT_RESET;
  93                 ehci_writel(ehci, temp, portsc_reg);
  94                 mdelay(10);
  95                 temp &= ~PORT_RESET;
  96                 ehci_writel(ehci, temp, portsc_reg);
  97                 mdelay(1);
  98                 tries = 100;
  99                 do {
 100                         mdelay(1);
 101                         /*
 102                          * Up to this point, Port Enable bit is
 103                          * expected to be set after 2 ms waiting.
 104                          * USB1 usually takes extra 45 ms, for safety,
 105                          * we take 100 ms as timeout.
 106                          */
 107                         temp = ehci_readl(ehci, portsc_reg);
 108                 } while (!(temp & PORT_PE) && tries--);
 109                 if (temp & PORT_PE)
 110                         break;
 111         }
 112         if (i == 2)
 113                 retval = -ETIMEDOUT;
 114
 115         /*
 116          * Clear Connect Status Change bit if it's set.
 117          * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
 118          */
 119         if (temp & PORT_CSC)
 120                 ehci_writel(ehci, PORT_CSC, portsc_reg);
 121
 122         /*
 123          * Write to clear any interrupt status bits that might be set
 124          * during port reset.
 125          */
 126         temp = ehci_readl(ehci, &ehci->regs->status);
 127         ehci_writel(ehci, temp, &ehci->regs->status);
 128
 129         /* restore original interrupt enable bits */
 130         ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
 131         return retval;
 132 }
 133
 134 static int tegra_ehci_hub_control(
 135         struct usb_hcd  *hcd,
 136         u16             typeReq,
 137         u16             wValue,
 138         u16             wIndex,
 139         char            *buf,
 140         u16             wLength
 141 )
 142 {
 143         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 144         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 145         u32 __iomem     *status_reg;
 146         u32             temp;
 147         unsigned long   flags;
 148         int             retval = 0;
 149
 150         status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
 151
 152         spin_lock_irqsave(&ehci->lock, flags);
 153
 154         if (typeReq == GetPortStatus) {
 155                 temp = ehci_readl(ehci, status_reg);
 156                 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
 157                         /* Resume completed, re-enable disconnect detection */
 158                         tegra->port_resuming = 0;
 159                         tegra_usb_phy_postresume(tegra->phy);
 160                 }
 161         }
 162
 163         else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
 164                 temp = ehci_readl(ehci, status_reg);
 165                 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
 166                         retval = -EPIPE;
 167                         goto done;
 168                 }
 169
 170                 temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
 171                 temp |= PORT_WKDISC_E | PORT_WKOC_E;
 172                 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
 173
 174                 /*
 175                  * If a transaction is in progress, there may be a delay in
 176                  * suspending the port. Poll until the port is suspended.
 177                  */
 178                 if (handshake(ehci, status_reg, PORT_SUSPEND,
 179                                                 PORT_SUSPEND, 5000))
 180                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
 181
 182                 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
 183                 goto done;
 184         }
 185
 186         /* For USB1 port we need to issue Port Reset twice internally */
 187         if (tegra->phy->instance == 0 &&
 188            (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
 189                 spin_unlock_irqrestore(&ehci->lock, flags);
 190                 return tegra_ehci_internal_port_reset(ehci, status_reg);
 191         }
 192
 193         /*
 194          * Tegra host controller will time the resume operation to clear the bit
 195          * when the port control state switches to HS or FS Idle. This behavior
 196          * is different from EHCI where the host controller driver is required
 197          * to set this bit to a zero after the resume duration is timed in the
 198          * driver.
 199          */
 200         else if (typeReq == ClearPortFeature &&
 201                                         wValue == USB_PORT_FEAT_SUSPEND) {
 202                 temp = ehci_readl(ehci, status_reg);
 203                 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
 204                         retval = -EPIPE;
 205                         goto done;
 206                 }
 207
 208                 if (!(temp & PORT_SUSPEND))
 209                         goto done;
 210
 211                 /* Disable disconnect detection during port resume */
 212                 tegra_usb_phy_preresume(tegra->phy);
 213
 214                 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
 215
 216                 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
 217                 /* start resume signalling */
 218                 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
 219                 set_bit(wIndex-1, &ehci->resuming_ports);
 220
 221                 spin_unlock_irqrestore(&ehci->lock, flags);
 222                 msleep(20);
 223                 spin_lock_irqsave(&ehci->lock, flags);
 224
 225                 /* Poll until the controller clears RESUME and SUSPEND */
 226                 if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
 227                         pr_err("%s: timeout waiting for RESUME\n", __func__);
 228                 if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
 229                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
 230
 231                 ehci->reset_done[wIndex-1] = 0;
 232                 clear_bit(wIndex-1, &ehci->resuming_ports);
 233
 234                 tegra->port_resuming = 1;
 235                 goto done;
 236         }
 237
 238         spin_unlock_irqrestore(&ehci->lock, flags);
 239
 240         /* Handle the hub control events here */
 241         return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
 242 done:
 243         spin_unlock_irqrestore(&ehci->lock, flags);
 244         return retval;
 245 }
 246
 247 static void tegra_ehci_restart(struct usb_hcd *hcd)
 248 {
 249         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 250
 251         ehci_reset(ehci);
 252
 253         /* setup the frame list and Async q heads */
 254         ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
 255         ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
 256         /* setup the command register and set the controller in RUN mode */
 257         ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
 258         ehci->command |= CMD_RUN;
 259         ehci_writel(ehci, ehci->command, &ehci->regs->command);
 260
 261         down_write(&ehci_cf_port_reset_rwsem);
 262         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 263         /* flush posted writes */
 264         ehci_readl(ehci, &ehci->regs->command);
 265         up_write(&ehci_cf_port_reset_rwsem);
 266 }
 267
 268 static void tegra_ehci_shutdown(struct usb_hcd *hcd)
 269 {
 270         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 271
 272         /* ehci_shutdown touches the USB controller registers, make sure
 273          * controller has clocks to it */
 274         if (!tegra->host_resumed)
 275                 tegra_ehci_power_up(hcd);
 276
 277         ehci_shutdown(hcd);
 278 }
 279
 280 static int tegra_ehci_setup(struct usb_hcd *hcd)
 281 {
 282         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 283
 284         /* EHCI registers start at offset 0x100 */
 285         ehci->caps = hcd->regs + 0x100;
 286
 287         /* switch to host mode */
 288         hcd->has_tt = 1;
 289
 290         return ehci_setup(hcd);
 291 }
 292
 293 struct dma_aligned_buffer {
 294         void *kmalloc_ptr;
 295         void *old_xfer_buffer;
 296         u8 data[0];
 297 };
 298
 299 static void free_dma_aligned_buffer(struct urb *urb)
 300 {
 301         struct dma_aligned_buffer *temp;
 302
 303         if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
 304                 return;
 305
 306         temp = container_of(urb->transfer_buffer,
 307                 struct dma_aligned_buffer, data);
 308
 309         if (usb_urb_dir_in(urb))
 310                 memcpy(temp->old_xfer_buffer, temp->data,
 311                        urb->transfer_buffer_length);
 312         urb->transfer_buffer = temp->old_xfer_buffer;
 313         kfree(temp->kmalloc_ptr);
 314
 315         urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
 316 }
 317
 318 static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
 319 {
 320         struct dma_aligned_buffer *temp, *kmalloc_ptr;
 321         size_t kmalloc_size;
 322
 323         if (urb->num_sgs || urb->sg ||
 324             urb->transfer_buffer_length == 0 ||
 325             !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
 326                 return 0;
 327
 328         /* Allocate a buffer with enough padding for alignment */
 329         kmalloc_size = urb->transfer_buffer_length +
 330                 sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
 331
 332         kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
 333         if (!kmalloc_ptr)
 334                 return -ENOMEM;
 335
 336         /* Position our struct dma_aligned_buffer such that data is aligned */
 337         temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
 338         temp->kmalloc_ptr = kmalloc_ptr;
 339         temp->old_xfer_buffer = urb->transfer_buffer;
 340         if (usb_urb_dir_out(urb))
 341                 memcpy(temp->data, urb->transfer_buffer,
 342                        urb->transfer_buffer_length);
 343         urb->transfer_buffer = temp->data;
 344
 345         urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
 346
 347         return 0;
 348 }
 349
 350 static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
 351                                       gfp_t mem_flags)
 352 {
 353         int ret;
 354
 355         ret = alloc_dma_aligned_buffer(urb, mem_flags);
 356         if (ret)
 357                 return ret;
 358
 359         ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
 360         if (ret)
 361                 free_dma_aligned_buffer(urb);
 362
 363         return ret;
 364 }
 365
 366 static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
 367 {
 368         usb_hcd_unmap_urb_for_dma(hcd, urb);
 369         free_dma_aligned_buffer(urb);
 370 }
 371
 372 static const struct hc_driver tegra_ehci_hc_driver = {
 373         .description            = hcd_name,
 374         .product_desc           = "Tegra EHCI Host Controller",
 375         .hcd_priv_size          = sizeof(struct ehci_hcd),
 376         .flags                  = HCD_USB2 | HCD_MEMORY,
 377
 378         /* standard ehci functions */
 379         .irq                    = ehci_irq,
 380         .start                  = ehci_run,
 381         .stop                   = ehci_stop,
 382         .urb_enqueue            = ehci_urb_enqueue,
 383         .urb_dequeue            = ehci_urb_dequeue,
 384         .endpoint_disable       = ehci_endpoint_disable,
 385         .endpoint_reset         = ehci_endpoint_reset,
 386         .get_frame_number       = ehci_get_frame,
 387         .hub_status_data        = ehci_hub_status_data,
 388         .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
 389         .relinquish_port        = ehci_relinquish_port,
 390         .port_handed_over       = ehci_port_handed_over,
 391
 392         /* modified ehci functions for tegra */
 393         .reset                  = tegra_ehci_setup,
 394         .shutdown               = tegra_ehci_shutdown,
 395         .map_urb_for_dma        = tegra_ehci_map_urb_for_dma,
 396         .unmap_urb_for_dma      = tegra_ehci_unmap_urb_for_dma,
 397         .hub_control            = tegra_ehci_hub_control,
 398 #ifdef CONFIG_PM
 399         .bus_suspend            = ehci_bus_suspend,
 400         .bus_resume             = ehci_bus_resume,
 401 #endif
 402 };
 403
 404 static int setup_vbus_gpio(struct platform_device *pdev,
 405                            struct tegra_ehci_platform_data *pdata)
 406 {
 407         int err = 0;
 408         int gpio;
 409
 410         gpio = pdata->vbus_gpio;
 411         if (!gpio_is_valid(gpio))
 412                 gpio = of_get_named_gpio(pdev->dev.of_node,
 413                                          "nvidia,vbus-gpio", 0);
 414         if (!gpio_is_valid(gpio))
 415                 return 0;
 416
 417         err = gpio_request(gpio, "vbus_gpio");
 418         if (err) {
 419                 dev_err(&pdev->dev, "can't request vbus gpio %d", gpio);
 420                 return err;
 421         }
 422         err = gpio_direction_output(gpio, 1);
 423         if (err) {
 424                 dev_err(&pdev->dev, "can't enable vbus\n");
 425                 return err;
 426         }
 427
 428         return err;
 429 }
 430
 431 #ifdef CONFIG_PM
 432
 433 static int controller_suspend(struct device *dev)
 434 {
 435         struct tegra_ehci_hcd *tegra =
 436                         platform_get_drvdata(to_platform_device(dev));
 437         struct ehci_hcd *ehci = tegra->ehci;
 438         struct usb_hcd *hcd = ehci_to_hcd(ehci);
 439         struct ehci_regs __iomem *hw = ehci->regs;
 440         unsigned long flags;
 441
 442         if (time_before(jiffies, ehci->next_statechange))
 443                 msleep(10);
 444
 445         ehci_halt(ehci);
 446
 447         spin_lock_irqsave(&ehci->lock, flags);
 448         tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
 449         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 450         spin_unlock_irqrestore(&ehci->lock, flags);
 451
 452         tegra_ehci_power_down(hcd);
 453         return 0;
 454 }
 455
 456 static int controller_resume(struct device *dev)
 457 {
 458         struct tegra_ehci_hcd *tegra =
 459                         platform_get_drvdata(to_platform_device(dev));
 460         struct ehci_hcd *ehci = tegra->ehci;
 461         struct usb_hcd *hcd = ehci_to_hcd(ehci);
 462         struct ehci_regs __iomem *hw = ehci->regs;
 463         unsigned long val;
 464
 465         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 466         tegra_ehci_power_up(hcd);
 467
 468         if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) {
 469                 /* Wait for the phy to detect new devices
 470                  * before we restart the controller */
 471                 msleep(10);
 472                 goto restart;
 473         }
 474
 475         /* Force the phy to keep data lines in suspend state */
 476         tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
 477
 478         /* Enable host mode */
 479         tdi_reset(ehci);
 480
 481         /* Enable Port Power */
 482         val = readl(&hw->port_status[0]);
 483         val |= PORT_POWER;
 484         writel(val, &hw->port_status[0]);
 485         udelay(10);
 486
 487         /* Check if the phy resume from LP0. When the phy resume from LP0
 488          * USB register will be reset. */
 489         if (!readl(&hw->async_next)) {
 490                 /* Program the field PTC based on the saved speed mode */
 491                 val = readl(&hw->port_status[0]);
 492                 val &= ~PORT_TEST(~0);
 493                 if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
 494                         val |= PORT_TEST_FORCE;
 495                 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
 496                         val |= PORT_TEST(6);
 497                 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
 498                         val |= PORT_TEST(7);
 499                 writel(val, &hw->port_status[0]);
 500                 udelay(10);
 501
 502                 /* Disable test mode by setting PTC field to NORMAL_OP */
 503                 val = readl(&hw->port_status[0]);
 504                 val &= ~PORT_TEST(~0);
 505                 writel(val, &hw->port_status[0]);
 506                 udelay(10);
 507         }
 508
 509         /* Poll until CCS is enabled */
 510         if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
 511                                                  PORT_CONNECT, 2000)) {
 512                 pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
 513                 goto restart;
 514         }
 515
 516         /* Poll until PE is enabled */
 517         if (handshake(ehci, &hw->port_status[0], PORT_PE,
 518                                                  PORT_PE, 2000)) {
 519                 pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
 520                 goto restart;
 521         }
 522
 523         /* Clear the PCI status, to avoid an interrupt taken upon resume */
 524         val = readl(&hw->status);
 525         val |= STS_PCD;
 526         writel(val, &hw->status);
 527
 528         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
 529         val = readl(&hw->port_status[0]);
 530         if ((val & PORT_POWER) && (val & PORT_PE)) {
 531                 val |= PORT_SUSPEND;
 532                 writel(val, &hw->port_status[0]);
 533
 534                 /* Wait until port suspend completes */
 535                 if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
 536                                                          PORT_SUSPEND, 1000)) {
 537                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
 538                                                                 __func__);
 539                         goto restart;
 540                 }
 541         }
 542
 543         tegra_ehci_phy_restore_end(tegra->phy);
 544         goto done;
 545
 546  restart:
 547         if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH)
 548                 tegra_ehci_phy_restore_end(tegra->phy);
 549
 550         tegra_ehci_restart(hcd);
 551
 552  done:
 553         tegra_usb_phy_preresume(tegra->phy);
 554         tegra->port_resuming = 1;
 555         return 0;
 556 }
 557
 558 static int tegra_ehci_suspend(struct device *dev)
 559 {
 560         struct tegra_ehci_hcd *tegra =
 561                         platform_get_drvdata(to_platform_device(dev));
 562         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
 563         int rc = 0;
 564
 565         /*
 566          * When system sleep is supported and USB controller wakeup is
 567          * implemented: If the controller is runtime-suspended and the
 568          * wakeup setting needs to be changed, call pm_runtime_resume().
 569          */
 570         if (HCD_HW_ACCESSIBLE(hcd))
 571                 rc = controller_suspend(dev);
 572         return rc;
 573 }
 574
 575 static int tegra_ehci_resume(struct device *dev)
 576 {
 577         int rc;
 578
 579         rc = controller_resume(dev);
 580         if (rc == 0) {
 581                 pm_runtime_disable(dev);
 582                 pm_runtime_set_active(dev);
 583                 pm_runtime_enable(dev);
 584         }
 585         return rc;
 586 }
 587
 588 static int tegra_ehci_runtime_suspend(struct device *dev)
 589 {
 590         return controller_suspend(dev);
 591 }
 592
 593 static int tegra_ehci_runtime_resume(struct device *dev)
 594 {
 595         return controller_resume(dev);
 596 }
 597
 598 static const struct dev_pm_ops tegra_ehci_pm_ops = {
 599         .suspend        = tegra_ehci_suspend,
 600         .resume         = tegra_ehci_resume,
 601         .runtime_suspend = tegra_ehci_runtime_suspend,
 602         .runtime_resume = tegra_ehci_runtime_resume,
 603 };
 604
 605 #endif
 606
 607 static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32);
 608
 609 static int tegra_ehci_probe(struct platform_device *pdev)
 610 {
 611         struct resource *res;
 612         struct usb_hcd *hcd;
 613         struct tegra_ehci_hcd *tegra;
 614         struct tegra_ehci_platform_data *pdata;
 615         int err = 0;
 616         int irq;
 617         int instance = pdev->id;
 618
 619         pdata = pdev->dev.platform_data;
 620         if (!pdata) {
 621                 dev_err(&pdev->dev, "Platform data missing\n");
 622                 return -EINVAL;
 623         }
 624
 625         /* Right now device-tree probed devices don't get dma_mask set.
 626          * Since shared usb code relies on it, set it here for now.
 627          * Once we have dma capability bindings this can go away.
 628          */
 629         if (!pdev->dev.dma_mask)
 630                 pdev->dev.dma_mask = &tegra_ehci_dma_mask;
 631
 632         setup_vbus_gpio(pdev, pdata);
 633
 634         tegra = devm_kzalloc(&pdev->dev, sizeof(struct tegra_ehci_hcd),
 635                              GFP_KERNEL);
 636         if (!tegra)
 637                 return -ENOMEM;
 638
 639         hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
 640                                         dev_name(&pdev->dev));
 641         if (!hcd) {
 642                 dev_err(&pdev->dev, "Unable to create HCD\n");
 643                 return -ENOMEM;
 644         }
 645
 646         platform_set_drvdata(pdev, tegra);
 647
 648         tegra->clk = devm_clk_get(&pdev->dev, NULL);
 649         if (IS_ERR(tegra->clk)) {
 650                 dev_err(&pdev->dev, "Can't get ehci clock\n");
 651                 err = PTR_ERR(tegra->clk);
 652                 goto fail_clk;
 653         }
 654
 655         err = clk_prepare_enable(tegra->clk);
 656         if (err)
 657                 goto fail_clk;
 658
 659         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
 660         if (IS_ERR(tegra->emc_clk)) {
 661                 dev_err(&pdev->dev, "Can't get emc clock\n");
 662                 err = PTR_ERR(tegra->emc_clk);
 663                 goto fail_emc_clk;
 664         }
 665
 666         clk_prepare_enable(tegra->emc_clk);
 667         clk_set_rate(tegra->emc_clk, 400000000);
 668
 669         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 670         if (!res) {
 671                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
 672                 err = -ENXIO;
 673                 goto fail_io;
 674         }
 675         hcd->rsrc_start = res->start;
 676         hcd->rsrc_len = resource_size(res);
 677         hcd->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
 678         if (!hcd->regs) {
 679                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
 680                 err = -ENOMEM;
 681                 goto fail_io;
 682         }
 683
 684         /* This is pretty ugly and needs to be fixed when we do only
 685          * device-tree probing. Old code relies on the platform_device
 686          * numbering that we lack for device-tree-instantiated devices.
 687          */
 688         if (instance < 0) {
 689                 switch (res->start) {
 690                 case TEGRA_USB_BASE:
 691                         instance = 0;
 692                         break;
 693                 case TEGRA_USB2_BASE:
 694                         instance = 1;
 695                         break;
 696                 case TEGRA_USB3_BASE:
 697                         instance = 2;
 698                         break;
 699                 default:
 700                         err = -ENODEV;
 701                         dev_err(&pdev->dev, "unknown usb instance\n");
 702                         goto fail_io;
 703                 }
 704         }
 705
 706         tegra->phy = tegra_usb_phy_open(&pdev->dev, instance, hcd->regs,
 707                                         pdata->phy_config,
 708                                         TEGRA_USB_PHY_MODE_HOST);
 709         if (IS_ERR(tegra->phy)) {
 710                 dev_err(&pdev->dev, "Failed to open USB phy\n");
 711                 err = -ENXIO;
 712                 goto fail_io;
 713         }
 714
 715         usb_phy_init(&tegra->phy->u_phy);
 716
 717         err = usb_phy_set_suspend(&tegra->phy->u_phy, 0);
 718         if (err) {
 719                 dev_err(&pdev->dev, "Failed to power on the phy\n");
 720                 goto fail;
 721         }
 722
 723         tegra->host_resumed = 1;
 724         tegra->ehci = hcd_to_ehci(hcd);
 725
 726         irq = platform_get_irq(pdev, 0);
 727         if (!irq) {
 728                 dev_err(&pdev->dev, "Failed to get IRQ\n");
 729                 err = -ENODEV;
 730                 goto fail;
 731         }
 732
 733 #ifdef CONFIG_USB_OTG_UTILS
 734         if (pdata->operating_mode == TEGRA_USB_OTG) {
 735                 tegra->transceiver =
 736                         devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
 737                 if (!IS_ERR_OR_NULL(tegra->transceiver))
 738                         otg_set_host(tegra->transceiver->otg, &hcd->self);
 739         }
 740 #endif
 741
 742         err = usb_add_hcd(hcd, irq, IRQF_SHARED);
 743         if (err) {
 744                 dev_err(&pdev->dev, "Failed to add USB HCD\n");
 745                 goto fail;
 746         }
 747
 748         pm_runtime_set_active(&pdev->dev);
 749         pm_runtime_get_noresume(&pdev->dev);
 750
 751         /* Don't skip the pm_runtime_forbid call if wakeup isn't working */
 752         /* if (!pdata->power_down_on_bus_suspend) */
 753                 pm_runtime_forbid(&pdev->dev);
 754         pm_runtime_enable(&pdev->dev);
 755         pm_runtime_put_sync(&pdev->dev);
 756         return err;
 757
 758 fail:
 759 #ifdef CONFIG_USB_OTG_UTILS
 760         if (!IS_ERR_OR_NULL(tegra->transceiver))
 761                 otg_set_host(tegra->transceiver->otg, NULL);
 762 #endif
 763         usb_phy_shutdown(&tegra->phy->u_phy);
 764 fail_io:
 765         clk_disable_unprepare(tegra->emc_clk);
 766 fail_emc_clk:
 767         clk_disable_unprepare(tegra->clk);
 768 fail_clk:
 769         usb_put_hcd(hcd);
 770         return err;
 771 }
 772
 773 static int tegra_ehci_remove(struct platform_device *pdev)
 774 {
 775         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
 776         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
 777
 778         pm_runtime_get_sync(&pdev->dev);
 779         pm_runtime_disable(&pdev->dev);
 780         pm_runtime_put_noidle(&pdev->dev);
 781
 782 #ifdef CONFIG_USB_OTG_UTILS
 783         if (!IS_ERR_OR_NULL(tegra->transceiver))
 784                 otg_set_host(tegra->transceiver->otg, NULL);
 785 #endif
 786
 787         usb_remove_hcd(hcd);
 788         usb_put_hcd(hcd);
 789
 790         usb_phy_shutdown(&tegra->phy->u_phy);
 791
 792         clk_disable_unprepare(tegra->clk);
 793
 794         clk_disable_unprepare(tegra->emc_clk);
 795
 796         return 0;
 797 }
 798
 799 static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
 800 {
 801         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
 802         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
 803
 804         if (hcd->driver->shutdown)
 805                 hcd->driver->shutdown(hcd);
 806 }
 807
 808 static struct of_device_id tegra_ehci_of_match[] = {
 809         { .compatible = "nvidia,tegra20-ehci", },
 810         { },
 811 };
 812
 813 static struct platform_driver tegra_ehci_driver = {
 814         .probe          = tegra_ehci_probe,
 815         .remove         = tegra_ehci_remove,
 816         .shutdown       = tegra_ehci_hcd_shutdown,
 817         .driver         = {
 818                 .name   = "tegra-ehci",
 819                 .of_match_table = tegra_ehci_of_match,
 820 #ifdef CONFIG_PM
 821                 .pm     = &tegra_ehci_pm_ops,
 822 #endif
 823         }
 824 };