2 * Copyright (c) 2001-2002 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
22 /* definitions used for the EHCI driver */
25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
27 * the host controller implementation.
29 * To facilitate the strongest possible byte-order checking from "sparse"
30 * and so on, we use __leXX unless that's not practical.
32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33 typedef __u32 __bitwise __hc32;
34 typedef __u16 __bitwise __hc16;
40 /* statistics can be kept for tuning/monitoring */
46 unsigned long lost_iaa;
48 /* termination of urbs from core */
49 unsigned long complete;
53 /* ehci_hcd->lock guards shared data against other CPUs:
54 * ehci_hcd: async, unlink, periodic (and shadow), ...
55 * usb_host_endpoint: hcpriv
56 * ehci_qh: qh_next, qtd_list
59 * Also, hold this lock when talking to HC registers or
60 * when updating hw_* fields in shared qh/qtd/... structures.
63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
66 * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
67 * controller may be doing DMA. Lower values mean there's no DMA.
77 * Timer events, ordered by increasing delay length.
78 * Always update event_delays_ns[] and event_handlers[] (defined in
79 * ehci-timer.c) in parallel with this list.
81 enum ehci_hrtimer_event {
82 EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */
83 EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
84 EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
85 EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
86 EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
87 EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
88 EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
89 EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
90 EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
91 EHCI_HRTIMER_NUM_EVENTS /* Must come last */
93 #define EHCI_HRTIMER_NO_EVENT 99
95 struct ehci_hcd { /* one per controller */
97 enum ehci_hrtimer_event next_hrtimer_event;
98 unsigned enabled_hrtimer_events;
99 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
100 struct hrtimer hrtimer;
106 /* glue to PCI and HCD framework */
107 struct ehci_caps __iomem *caps;
108 struct ehci_regs __iomem *regs;
109 struct ehci_dbg_port __iomem *debug;
111 __u32 hcs_params; /* cached register copy */
113 enum ehci_rh_state rh_state;
115 /* general schedule support */
118 bool intr_unlinking:1;
119 bool async_unlinking:1;
120 struct ehci_qh *qh_scan_next;
122 /* async schedule support */
123 struct ehci_qh *async;
124 struct ehci_qh *dummy; /* For AMD quirk use */
125 struct ehci_qh *async_unlink;
126 struct ehci_qh *async_unlink_last;
127 struct ehci_qh *async_iaa;
128 unsigned async_unlink_cycle;
129 unsigned async_count; /* async activity count */
131 /* periodic schedule support */
132 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
133 unsigned periodic_size;
134 __hc32 *periodic; /* hw periodic table */
135 dma_addr_t periodic_dma;
136 struct list_head intr_qh_list;
137 unsigned i_thresh; /* uframes HC might cache */
139 union ehci_shadow *pshadow; /* mirror hw periodic table */
140 struct ehci_qh *intr_unlink;
141 struct ehci_qh *intr_unlink_last;
142 unsigned intr_unlink_cycle;
143 int next_uframe; /* scan periodic, start here */
144 unsigned intr_count; /* intr activity count */
145 unsigned isoc_count; /* isoc activity count */
146 unsigned periodic_count; /* periodic activity count */
147 unsigned uframe_periodic_max; /* max periodic time per uframe */
150 /* list of itds & sitds completed while clock_frame was still active */
151 struct list_head cached_itd_list;
152 struct ehci_itd *last_itd_to_free;
153 struct list_head cached_sitd_list;
154 struct ehci_sitd *last_sitd_to_free;
155 unsigned clock_frame;
157 /* per root hub port */
158 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
160 /* bit vectors (one bit per port) */
161 unsigned long bus_suspended; /* which ports were
162 already suspended at the start of a bus suspend */
163 unsigned long companion_ports; /* which ports are
164 dedicated to the companion controller */
165 unsigned long owned_ports; /* which ports are
166 owned by the companion during a bus suspend */
167 unsigned long port_c_suspend; /* which ports have
168 the change-suspend feature turned on */
169 unsigned long suspended_ports; /* which ports are
171 unsigned long resuming_ports; /* which ports have
174 /* per-HC memory pools (could be per-bus, but ...) */
175 struct dma_pool *qh_pool; /* qh per active urb */
176 struct dma_pool *qtd_pool; /* one or more per qh */
177 struct dma_pool *itd_pool; /* itd per iso urb */
178 struct dma_pool *sitd_pool; /* sitd per split iso urb */
180 struct timer_list watchdog;
181 unsigned long actions;
182 unsigned random_frame;
183 unsigned long next_statechange;
184 ktime_t last_periodic_enable;
188 unsigned no_selective_suspend:1;
189 unsigned has_fsl_port_bug:1; /* FreeScale */
190 unsigned big_endian_mmio:1;
191 unsigned big_endian_desc:1;
192 unsigned big_endian_capbase:1;
193 unsigned has_amcc_usb23:1;
194 unsigned need_io_watchdog:1;
195 unsigned amd_pll_fix:1;
196 unsigned fs_i_thresh:1; /* Intel iso scheduling */
197 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/
198 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */
199 unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */
201 /* required for usb32 quirk */
202 #define OHCI_CTRL_HCFS (3 << 6)
203 #define OHCI_USB_OPER (2 << 6)
204 #define OHCI_USB_SUSPEND (3 << 6)
206 #define OHCI_HCCTRL_OFFSET 0x4
207 #define OHCI_HCCTRL_LEN 0x4
208 __hc32 *ohci_hcctrl_reg;
209 unsigned has_hostpc:1;
210 unsigned has_lpm:1; /* support link power management */
211 unsigned has_ppcd:1; /* support per-port change bits */
212 u8 sbrn; /* packed release number */
216 struct ehci_stats stats;
217 # define COUNT(x) do { (x)++; } while (0)
219 # define COUNT(x) do {} while (0)
224 struct dentry *debug_dir;
228 /* convert between an HCD pointer and the corresponding EHCI_HCD */
229 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
231 return (struct ehci_hcd *) (hcd->hcd_priv);
233 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
235 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
238 enum ehci_timer_action {
243 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
245 clear_bit (action, &ehci->actions);
248 /*-------------------------------------------------------------------------*/
250 #include <linux/usb/ehci_def.h>
252 /*-------------------------------------------------------------------------*/
254 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
257 * EHCI Specification 0.95 Section 3.5
258 * QTD: describe data transfer components (buffer, direction, ...)
259 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
261 * These are associated only with "QH" (Queue Head) structures,
262 * used with control, bulk, and interrupt transfers.
265 /* first part defined by EHCI spec */
266 __hc32 hw_next; /* see EHCI 3.5.1 */
267 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
268 __hc32 hw_token; /* see EHCI 3.5.3 */
269 #define QTD_TOGGLE (1 << 31) /* data toggle */
270 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
271 #define QTD_IOC (1 << 15) /* interrupt on complete */
272 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
273 #define QTD_PID(tok) (((tok)>>8) & 0x3)
274 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
275 #define QTD_STS_HALT (1 << 6) /* halted on error */
276 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
277 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
278 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
279 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
280 #define QTD_STS_STS (1 << 1) /* split transaction state */
281 #define QTD_STS_PING (1 << 0) /* issue PING? */
283 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
284 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
285 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
287 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */
288 __hc32 hw_buf_hi [5]; /* Appendix B */
290 /* the rest is HCD-private */
291 dma_addr_t qtd_dma; /* qtd address */
292 struct list_head qtd_list; /* sw qtd list */
293 struct urb *urb; /* qtd's urb */
294 size_t length; /* length of buffer */
295 } __attribute__ ((aligned (32)));
297 /* mask NakCnt+T in qh->hw_alt_next */
298 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
300 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
302 /*-------------------------------------------------------------------------*/
304 /* type tag from {qh,itd,sitd,fstn}->hw_next */
305 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
308 * Now the following defines are not converted using the
309 * cpu_to_le32() macro anymore, since we have to support
310 * "dynamic" switching between be and le support, so that the driver
311 * can be used on one system with SoC EHCI controller using big-endian
312 * descriptors as well as a normal little-endian PCI EHCI controller.
314 /* values for that type tag */
315 #define Q_TYPE_ITD (0 << 1)
316 #define Q_TYPE_QH (1 << 1)
317 #define Q_TYPE_SITD (2 << 1)
318 #define Q_TYPE_FSTN (3 << 1)
320 /* next async queue entry, or pointer to interrupt/periodic QH */
321 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
323 /* for periodic/async schedules and qtd lists, mark end of list */
324 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
327 * Entries in periodic shadow table are pointers to one of four kinds
328 * of data structure. That's dictated by the hardware; a type tag is
329 * encoded in the low bits of the hardware's periodic schedule. Use
330 * Q_NEXT_TYPE to get the tag.
332 * For entries in the async schedule, the type tag always says "qh".
335 struct ehci_qh *qh; /* Q_TYPE_QH */
336 struct ehci_itd *itd; /* Q_TYPE_ITD */
337 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
338 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
339 __hc32 *hw_next; /* (all types) */
343 /*-------------------------------------------------------------------------*/
346 * EHCI Specification 0.95 Section 3.6
347 * QH: describes control/bulk/interrupt endpoints
348 * See Fig 3-7 "Queue Head Structure Layout".
350 * These appear in both the async and (for interrupt) periodic schedules.
353 /* first part defined by EHCI spec */
355 __hc32 hw_next; /* see EHCI 3.6.1 */
356 __hc32 hw_info1; /* see EHCI 3.6.2 */
357 #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
358 #define QH_HEAD (1 << 15) /* Head of async reclamation list */
359 #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
360 #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
361 #define QH_LOW_SPEED (1 << 12)
362 #define QH_FULL_SPEED (0 << 12)
363 #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
364 __hc32 hw_info2; /* see EHCI 3.6.2 */
365 #define QH_SMASK 0x000000ff
366 #define QH_CMASK 0x0000ff00
367 #define QH_HUBADDR 0x007f0000
368 #define QH_HUBPORT 0x3f800000
369 #define QH_MULT 0xc0000000
370 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
372 /* qtd overlay (hardware parts of a struct ehci_qtd) */
377 __hc32 hw_buf_hi [5];
378 } __attribute__ ((aligned(32)));
381 struct ehci_qh_hw *hw; /* Must come first */
382 /* the rest is HCD-private */
383 dma_addr_t qh_dma; /* address of qh */
384 union ehci_shadow qh_next; /* ptr to qh; or periodic */
385 struct list_head qtd_list; /* sw qtd list */
386 struct list_head intr_node; /* list of intr QHs */
387 struct ehci_qtd *dummy;
388 struct ehci_qh *unlink_next; /* next on unlink list */
390 unsigned unlink_cycle;
392 u8 needs_rescan; /* Dequeue during giveback */
394 #define QH_STATE_LINKED 1 /* HC sees this */
395 #define QH_STATE_UNLINK 2 /* HC may still see this */
396 #define QH_STATE_IDLE 3 /* HC doesn't see this */
397 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
398 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
400 u8 xacterrs; /* XactErr retry counter */
401 #define QH_XACTERR_MAX 32 /* XactErr retry limit */
403 /* periodic schedule info */
404 u8 usecs; /* intr bandwidth */
405 u8 gap_uf; /* uframes split/csplit gap */
406 u8 c_usecs; /* ... split completion bw */
407 u16 tt_usecs; /* tt downstream bandwidth */
408 unsigned short period; /* polling interval */
409 unsigned short start; /* where polling starts */
410 #define NO_FRAME ((unsigned short)~0) /* pick new start */
412 struct usb_device *dev; /* access to TT */
413 unsigned is_out:1; /* bulk or intr OUT */
414 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
417 /*-------------------------------------------------------------------------*/
419 /* description of one iso transaction (up to 3 KB data if highspeed) */
420 struct ehci_iso_packet {
421 /* These will be copied to iTD when scheduling */
422 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
423 __hc32 transaction; /* itd->hw_transaction[i] |= */
424 u8 cross; /* buf crosses pages */
425 /* for full speed OUT splits */
429 /* temporary schedule data for packets from iso urbs (both speeds)
430 * each packet is one logical usb transaction to the device (not TT),
431 * beginning at stream->next_uframe
433 struct ehci_iso_sched {
434 struct list_head td_list;
436 struct ehci_iso_packet packet [0];
440 * ehci_iso_stream - groups all (s)itds for this endpoint.
441 * acts like a qh would, if EHCI had them for ISO.
443 struct ehci_iso_stream {
444 /* first field matches ehci_hq, but is NULL */
445 struct ehci_qh_hw *hw;
449 struct list_head td_list; /* queued itds/sitds */
450 struct list_head free_list; /* list of unused itds/sitds */
451 struct usb_device *udev;
452 struct usb_host_endpoint *ep;
454 /* output of (re)scheduling */
458 /* the rest is derived from the endpoint descriptor,
459 * trusting urb->interval == f(epdesc->bInterval) and
460 * including the extra info for hw_bufp[0..2]
469 /* This is used to initialize iTD's hw_bufp fields */
474 /* this is used to initialize sITD's tt info */
478 /*-------------------------------------------------------------------------*/
481 * EHCI Specification 0.95 Section 3.3
482 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
484 * Schedule records for high speed iso xfers
487 /* first part defined by EHCI spec */
488 __hc32 hw_next; /* see EHCI 3.3.1 */
489 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
490 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
491 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
492 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
493 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
494 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
495 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
497 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
499 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
500 __hc32 hw_bufp_hi [7]; /* Appendix B */
502 /* the rest is HCD-private */
503 dma_addr_t itd_dma; /* for this itd */
504 union ehci_shadow itd_next; /* ptr to periodic q entry */
507 struct ehci_iso_stream *stream; /* endpoint's queue */
508 struct list_head itd_list; /* list of stream's itds */
510 /* any/all hw_transactions here may be used by that urb */
511 unsigned frame; /* where scheduled */
513 unsigned index[8]; /* in urb->iso_frame_desc */
514 } __attribute__ ((aligned (32)));
516 /*-------------------------------------------------------------------------*/
519 * EHCI Specification 0.95 Section 3.4
520 * siTD, aka split-transaction isochronous Transfer Descriptor
521 * ... describe full speed iso xfers through TT in hubs
522 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
525 /* first part defined by EHCI spec */
527 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
528 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
529 __hc32 hw_uframe; /* EHCI table 3-10 */
530 __hc32 hw_results; /* EHCI table 3-11 */
531 #define SITD_IOC (1 << 31) /* interrupt on completion */
532 #define SITD_PAGE (1 << 30) /* buffer 0/1 */
533 #define SITD_LENGTH(x) (0x3ff & ((x)>>16))
534 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
535 #define SITD_STS_ERR (1 << 6) /* error from TT */
536 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
537 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
538 #define SITD_STS_XACT (1 << 3) /* illegal IN response */
539 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
540 #define SITD_STS_STS (1 << 1) /* split transaction state */
542 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
544 __hc32 hw_buf [2]; /* EHCI table 3-12 */
545 __hc32 hw_backpointer; /* EHCI table 3-13 */
546 __hc32 hw_buf_hi [2]; /* Appendix B */
548 /* the rest is HCD-private */
550 union ehci_shadow sitd_next; /* ptr to periodic q entry */
553 struct ehci_iso_stream *stream; /* endpoint's queue */
554 struct list_head sitd_list; /* list of stream's sitds */
557 } __attribute__ ((aligned (32)));
559 /*-------------------------------------------------------------------------*/
562 * EHCI Specification 0.96 Section 3.7
563 * Periodic Frame Span Traversal Node (FSTN)
565 * Manages split interrupt transactions (using TT) that span frame boundaries
566 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
567 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
568 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
571 __hc32 hw_next; /* any periodic q entry */
572 __hc32 hw_prev; /* qh or EHCI_LIST_END */
574 /* the rest is HCD-private */
576 union ehci_shadow fstn_next; /* ptr to periodic q entry */
577 } __attribute__ ((aligned (32)));
579 /*-------------------------------------------------------------------------*/
581 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
583 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
584 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
586 #define ehci_prepare_ports_for_controller_resume(ehci) \
587 ehci_adjust_port_wakeup_flags(ehci, false, false);
589 /*-------------------------------------------------------------------------*/
591 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
594 * Some EHCI controllers have a Transaction Translator built into the
595 * root hub. This is a non-standard feature. Each controller will need
596 * to add code to the following inline functions, and call them as
597 * needed (mostly in root hub code).
600 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
602 /* Returns the speed of a device attached to a port on the root hub. */
603 static inline unsigned int
604 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
606 if (ehci_is_TDI(ehci)) {
607 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
611 return USB_PORT_STAT_LOW_SPEED;
614 return USB_PORT_STAT_HIGH_SPEED;
617 return USB_PORT_STAT_HIGH_SPEED;
622 #define ehci_is_TDI(e) (0)
624 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
627 /*-------------------------------------------------------------------------*/
629 #ifdef CONFIG_PPC_83xx
630 /* Some Freescale processors have an erratum in which the TT
631 * port number in the queue head was 0..N-1 instead of 1..N.
633 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
635 #define ehci_has_fsl_portno_bug(e) (0)
639 * While most USB host controllers implement their registers in
640 * little-endian format, a minority (celleb companion chip) implement
641 * them in big endian format.
643 * This attempts to support either format at compile time without a
644 * runtime penalty, or both formats with the additional overhead
645 * of checking a flag bit.
647 * ehci_big_endian_capbase is a special quirk for controllers that
648 * implement the HC capability registers as separate registers and not
649 * as fields of a 32-bit register.
652 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
653 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
654 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
656 #define ehci_big_endian_mmio(e) 0
657 #define ehci_big_endian_capbase(e) 0
661 * Big-endian read/write functions are arch-specific.
662 * Other arches can be added if/when they're needed.
664 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
665 #define readl_be(addr) __raw_readl((__force unsigned *)addr)
666 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
669 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
670 __u32 __iomem * regs)
672 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
673 return ehci_big_endian_mmio(ehci) ?
681 static inline void ehci_writel(const struct ehci_hcd *ehci,
682 const unsigned int val, __u32 __iomem *regs)
684 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
685 ehci_big_endian_mmio(ehci) ?
686 writel_be(val, regs) :
694 * On certain ppc-44x SoC there is a HW issue, that could only worked around with
695 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
696 * Other common bits are dependent on has_amcc_usb23 quirk flag.
699 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
703 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
705 hc_control |= OHCI_USB_OPER;
707 hc_control |= OHCI_USB_SUSPEND;
709 writel_be(hc_control, ehci->ohci_hcctrl_reg);
710 (void) readl_be(ehci->ohci_hcctrl_reg);
713 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
717 /*-------------------------------------------------------------------------*/
720 * The AMCC 440EPx not only implements its EHCI registers in big-endian
721 * format, but also its DMA data structures (descriptors).
723 * EHCI controllers accessed through PCI work normally (little-endian
724 * everywhere), so we won't bother supporting a BE-only mode for now.
726 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
727 #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
730 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
732 return ehci_big_endian_desc(ehci)
733 ? (__force __hc32)cpu_to_be32(x)
734 : (__force __hc32)cpu_to_le32(x);
738 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
740 return ehci_big_endian_desc(ehci)
741 ? be32_to_cpu((__force __be32)x)
742 : le32_to_cpu((__force __le32)x);
745 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
747 return ehci_big_endian_desc(ehci)
748 ? be32_to_cpup((__force __be32 *)x)
749 : le32_to_cpup((__force __le32 *)x);
755 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
757 return cpu_to_le32(x);
761 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
763 return le32_to_cpu(x);
766 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
768 return le32_to_cpup(x);
773 /*-------------------------------------------------------------------------*/
777 /* For working around the MosChip frame-index-register bug */
778 static unsigned ehci_read_frame_index(struct ehci_hcd *ehci);
782 static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
784 return ehci_readl(ehci, &ehci->regs->frame_index);
789 /*-------------------------------------------------------------------------*/
792 #define STUB_DEBUG_FILES
795 /*-------------------------------------------------------------------------*/
797 #endif /* __LINUX_EHCI_HCD_H */