2 * Copyright (c) 2001-2002 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
22 /* definitions used for the EHCI driver */
25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
27 * the host controller implementation.
29 * To facilitate the strongest possible byte-order checking from "sparse"
30 * and so on, we use __leXX unless that's not practical.
32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33 typedef __u32 __bitwise __hc32;
34 typedef __u16 __bitwise __hc16;
40 /* statistics can be kept for tuning/monitoring */
46 unsigned long lost_iaa;
48 /* termination of urbs from core */
49 unsigned long complete;
53 /* ehci_hcd->lock guards shared data against other CPUs:
54 * ehci_hcd: async, unlink, periodic (and shadow), ...
55 * usb_host_endpoint: hcpriv
56 * ehci_qh: qh_next, qtd_list
59 * Also, hold this lock when talking to HC registers or
60 * when updating hw_* fields in shared qh/qtd/... structures.
63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
66 * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
67 * controller may be doing DMA. Lower values mean there's no DMA.
77 * Timer events, ordered by increasing delay length.
78 * Always update event_delays_ns[] and event_handlers[] (defined in
79 * ehci-timer.c) in parallel with this list.
81 enum ehci_hrtimer_event {
82 EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */
83 EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
84 EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
85 EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
86 EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
87 EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
88 EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
89 EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
90 EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
91 EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
92 EHCI_HRTIMER_NUM_EVENTS /* Must come last */
94 #define EHCI_HRTIMER_NO_EVENT 99
96 struct ehci_hcd { /* one per controller */
98 enum ehci_hrtimer_event next_hrtimer_event;
99 unsigned enabled_hrtimer_events;
100 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
101 struct hrtimer hrtimer;
107 /* glue to PCI and HCD framework */
108 struct ehci_caps __iomem *caps;
109 struct ehci_regs __iomem *regs;
110 struct ehci_dbg_port __iomem *debug;
112 __u32 hcs_params; /* cached register copy */
114 enum ehci_rh_state rh_state;
116 /* general schedule support */
119 bool intr_unlinking:1;
120 bool async_unlinking:1;
122 struct ehci_qh *qh_scan_next;
124 /* async schedule support */
125 struct ehci_qh *async;
126 struct ehci_qh *dummy; /* For AMD quirk use */
127 struct ehci_qh *async_unlink;
128 struct ehci_qh *async_unlink_last;
129 struct ehci_qh *async_iaa;
130 unsigned async_unlink_cycle;
131 unsigned async_count; /* async activity count */
133 /* periodic schedule support */
134 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
135 unsigned periodic_size;
136 __hc32 *periodic; /* hw periodic table */
137 dma_addr_t periodic_dma;
138 struct list_head intr_qh_list;
139 unsigned i_thresh; /* uframes HC might cache */
141 union ehci_shadow *pshadow; /* mirror hw periodic table */
142 struct ehci_qh *intr_unlink;
143 struct ehci_qh *intr_unlink_last;
144 unsigned intr_unlink_cycle;
145 unsigned now_frame; /* frame from HC hardware */
146 unsigned last_iso_frame; /* last frame scanned for iso */
147 unsigned intr_count; /* intr activity count */
148 unsigned isoc_count; /* isoc activity count */
149 unsigned periodic_count; /* periodic activity count */
150 unsigned uframe_periodic_max; /* max periodic time per uframe */
153 /* list of itds & sitds completed while now_frame was still active */
154 struct list_head cached_itd_list;
155 struct ehci_itd *last_itd_to_free;
156 struct list_head cached_sitd_list;
157 struct ehci_sitd *last_sitd_to_free;
159 /* per root hub port */
160 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
162 /* bit vectors (one bit per port) */
163 unsigned long bus_suspended; /* which ports were
164 already suspended at the start of a bus suspend */
165 unsigned long companion_ports; /* which ports are
166 dedicated to the companion controller */
167 unsigned long owned_ports; /* which ports are
168 owned by the companion during a bus suspend */
169 unsigned long port_c_suspend; /* which ports have
170 the change-suspend feature turned on */
171 unsigned long suspended_ports; /* which ports are
173 unsigned long resuming_ports; /* which ports have
176 /* per-HC memory pools (could be per-bus, but ...) */
177 struct dma_pool *qh_pool; /* qh per active urb */
178 struct dma_pool *qtd_pool; /* one or more per qh */
179 struct dma_pool *itd_pool; /* itd per iso urb */
180 struct dma_pool *sitd_pool; /* sitd per split iso urb */
182 unsigned random_frame;
183 unsigned long next_statechange;
184 ktime_t last_periodic_enable;
188 unsigned no_selective_suspend:1;
189 unsigned has_fsl_port_bug:1; /* FreeScale */
190 unsigned big_endian_mmio:1;
191 unsigned big_endian_desc:1;
192 unsigned big_endian_capbase:1;
193 unsigned has_amcc_usb23:1;
194 unsigned need_io_watchdog:1;
195 unsigned amd_pll_fix:1;
196 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/
197 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */
198 unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */
200 /* required for usb32 quirk */
201 #define OHCI_CTRL_HCFS (3 << 6)
202 #define OHCI_USB_OPER (2 << 6)
203 #define OHCI_USB_SUSPEND (3 << 6)
205 #define OHCI_HCCTRL_OFFSET 0x4
206 #define OHCI_HCCTRL_LEN 0x4
207 __hc32 *ohci_hcctrl_reg;
208 unsigned has_hostpc:1;
209 unsigned has_lpm:1; /* support link power management */
210 unsigned has_ppcd:1; /* support per-port change bits */
211 u8 sbrn; /* packed release number */
215 struct ehci_stats stats;
216 # define COUNT(x) do { (x)++; } while (0)
218 # define COUNT(x) do {} while (0)
223 struct dentry *debug_dir;
227 /* convert between an HCD pointer and the corresponding EHCI_HCD */
228 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
230 return (struct ehci_hcd *) (hcd->hcd_priv);
232 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
234 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
237 /*-------------------------------------------------------------------------*/
239 #include <linux/usb/ehci_def.h>
241 /*-------------------------------------------------------------------------*/
243 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
246 * EHCI Specification 0.95 Section 3.5
247 * QTD: describe data transfer components (buffer, direction, ...)
248 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
250 * These are associated only with "QH" (Queue Head) structures,
251 * used with control, bulk, and interrupt transfers.
254 /* first part defined by EHCI spec */
255 __hc32 hw_next; /* see EHCI 3.5.1 */
256 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
257 __hc32 hw_token; /* see EHCI 3.5.3 */
258 #define QTD_TOGGLE (1 << 31) /* data toggle */
259 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
260 #define QTD_IOC (1 << 15) /* interrupt on complete */
261 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
262 #define QTD_PID(tok) (((tok)>>8) & 0x3)
263 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
264 #define QTD_STS_HALT (1 << 6) /* halted on error */
265 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
266 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
267 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
268 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
269 #define QTD_STS_STS (1 << 1) /* split transaction state */
270 #define QTD_STS_PING (1 << 0) /* issue PING? */
272 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
273 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
274 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
276 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */
277 __hc32 hw_buf_hi [5]; /* Appendix B */
279 /* the rest is HCD-private */
280 dma_addr_t qtd_dma; /* qtd address */
281 struct list_head qtd_list; /* sw qtd list */
282 struct urb *urb; /* qtd's urb */
283 size_t length; /* length of buffer */
284 } __attribute__ ((aligned (32)));
286 /* mask NakCnt+T in qh->hw_alt_next */
287 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
289 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
291 /*-------------------------------------------------------------------------*/
293 /* type tag from {qh,itd,sitd,fstn}->hw_next */
294 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
297 * Now the following defines are not converted using the
298 * cpu_to_le32() macro anymore, since we have to support
299 * "dynamic" switching between be and le support, so that the driver
300 * can be used on one system with SoC EHCI controller using big-endian
301 * descriptors as well as a normal little-endian PCI EHCI controller.
303 /* values for that type tag */
304 #define Q_TYPE_ITD (0 << 1)
305 #define Q_TYPE_QH (1 << 1)
306 #define Q_TYPE_SITD (2 << 1)
307 #define Q_TYPE_FSTN (3 << 1)
309 /* next async queue entry, or pointer to interrupt/periodic QH */
310 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
312 /* for periodic/async schedules and qtd lists, mark end of list */
313 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
316 * Entries in periodic shadow table are pointers to one of four kinds
317 * of data structure. That's dictated by the hardware; a type tag is
318 * encoded in the low bits of the hardware's periodic schedule. Use
319 * Q_NEXT_TYPE to get the tag.
321 * For entries in the async schedule, the type tag always says "qh".
324 struct ehci_qh *qh; /* Q_TYPE_QH */
325 struct ehci_itd *itd; /* Q_TYPE_ITD */
326 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
327 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
328 __hc32 *hw_next; /* (all types) */
332 /*-------------------------------------------------------------------------*/
335 * EHCI Specification 0.95 Section 3.6
336 * QH: describes control/bulk/interrupt endpoints
337 * See Fig 3-7 "Queue Head Structure Layout".
339 * These appear in both the async and (for interrupt) periodic schedules.
342 /* first part defined by EHCI spec */
344 __hc32 hw_next; /* see EHCI 3.6.1 */
345 __hc32 hw_info1; /* see EHCI 3.6.2 */
346 #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
347 #define QH_HEAD (1 << 15) /* Head of async reclamation list */
348 #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
349 #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
350 #define QH_LOW_SPEED (1 << 12)
351 #define QH_FULL_SPEED (0 << 12)
352 #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
353 __hc32 hw_info2; /* see EHCI 3.6.2 */
354 #define QH_SMASK 0x000000ff
355 #define QH_CMASK 0x0000ff00
356 #define QH_HUBADDR 0x007f0000
357 #define QH_HUBPORT 0x3f800000
358 #define QH_MULT 0xc0000000
359 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
361 /* qtd overlay (hardware parts of a struct ehci_qtd) */
366 __hc32 hw_buf_hi [5];
367 } __attribute__ ((aligned(32)));
370 struct ehci_qh_hw *hw; /* Must come first */
371 /* the rest is HCD-private */
372 dma_addr_t qh_dma; /* address of qh */
373 union ehci_shadow qh_next; /* ptr to qh; or periodic */
374 struct list_head qtd_list; /* sw qtd list */
375 struct list_head intr_node; /* list of intr QHs */
376 struct ehci_qtd *dummy;
377 struct ehci_qh *unlink_next; /* next on unlink list */
379 unsigned unlink_cycle;
381 u8 needs_rescan; /* Dequeue during giveback */
383 #define QH_STATE_LINKED 1 /* HC sees this */
384 #define QH_STATE_UNLINK 2 /* HC may still see this */
385 #define QH_STATE_IDLE 3 /* HC doesn't see this */
386 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
387 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
389 u8 xacterrs; /* XactErr retry counter */
390 #define QH_XACTERR_MAX 32 /* XactErr retry limit */
392 /* periodic schedule info */
393 u8 usecs; /* intr bandwidth */
394 u8 gap_uf; /* uframes split/csplit gap */
395 u8 c_usecs; /* ... split completion bw */
396 u16 tt_usecs; /* tt downstream bandwidth */
397 unsigned short period; /* polling interval */
398 unsigned short start; /* where polling starts */
399 #define NO_FRAME ((unsigned short)~0) /* pick new start */
401 struct usb_device *dev; /* access to TT */
402 unsigned is_out:1; /* bulk or intr OUT */
403 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
406 /*-------------------------------------------------------------------------*/
408 /* description of one iso transaction (up to 3 KB data if highspeed) */
409 struct ehci_iso_packet {
410 /* These will be copied to iTD when scheduling */
411 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
412 __hc32 transaction; /* itd->hw_transaction[i] |= */
413 u8 cross; /* buf crosses pages */
414 /* for full speed OUT splits */
418 /* temporary schedule data for packets from iso urbs (both speeds)
419 * each packet is one logical usb transaction to the device (not TT),
420 * beginning at stream->next_uframe
422 struct ehci_iso_sched {
423 struct list_head td_list;
425 struct ehci_iso_packet packet [0];
429 * ehci_iso_stream - groups all (s)itds for this endpoint.
430 * acts like a qh would, if EHCI had them for ISO.
432 struct ehci_iso_stream {
433 /* first field matches ehci_hq, but is NULL */
434 struct ehci_qh_hw *hw;
438 struct list_head td_list; /* queued itds/sitds */
439 struct list_head free_list; /* list of unused itds/sitds */
440 struct usb_device *udev;
441 struct usb_host_endpoint *ep;
443 /* output of (re)scheduling */
447 /* the rest is derived from the endpoint descriptor,
448 * trusting urb->interval == f(epdesc->bInterval) and
449 * including the extra info for hw_bufp[0..2]
458 /* This is used to initialize iTD's hw_bufp fields */
463 /* this is used to initialize sITD's tt info */
467 /*-------------------------------------------------------------------------*/
470 * EHCI Specification 0.95 Section 3.3
471 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
473 * Schedule records for high speed iso xfers
476 /* first part defined by EHCI spec */
477 __hc32 hw_next; /* see EHCI 3.3.1 */
478 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
479 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
480 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
481 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
482 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
483 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
484 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
486 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
488 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
489 __hc32 hw_bufp_hi [7]; /* Appendix B */
491 /* the rest is HCD-private */
492 dma_addr_t itd_dma; /* for this itd */
493 union ehci_shadow itd_next; /* ptr to periodic q entry */
496 struct ehci_iso_stream *stream; /* endpoint's queue */
497 struct list_head itd_list; /* list of stream's itds */
499 /* any/all hw_transactions here may be used by that urb */
500 unsigned frame; /* where scheduled */
502 unsigned index[8]; /* in urb->iso_frame_desc */
503 } __attribute__ ((aligned (32)));
505 /*-------------------------------------------------------------------------*/
508 * EHCI Specification 0.95 Section 3.4
509 * siTD, aka split-transaction isochronous Transfer Descriptor
510 * ... describe full speed iso xfers through TT in hubs
511 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
514 /* first part defined by EHCI spec */
516 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
517 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
518 __hc32 hw_uframe; /* EHCI table 3-10 */
519 __hc32 hw_results; /* EHCI table 3-11 */
520 #define SITD_IOC (1 << 31) /* interrupt on completion */
521 #define SITD_PAGE (1 << 30) /* buffer 0/1 */
522 #define SITD_LENGTH(x) (0x3ff & ((x)>>16))
523 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
524 #define SITD_STS_ERR (1 << 6) /* error from TT */
525 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
526 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
527 #define SITD_STS_XACT (1 << 3) /* illegal IN response */
528 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
529 #define SITD_STS_STS (1 << 1) /* split transaction state */
531 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
533 __hc32 hw_buf [2]; /* EHCI table 3-12 */
534 __hc32 hw_backpointer; /* EHCI table 3-13 */
535 __hc32 hw_buf_hi [2]; /* Appendix B */
537 /* the rest is HCD-private */
539 union ehci_shadow sitd_next; /* ptr to periodic q entry */
542 struct ehci_iso_stream *stream; /* endpoint's queue */
543 struct list_head sitd_list; /* list of stream's sitds */
546 } __attribute__ ((aligned (32)));
548 /*-------------------------------------------------------------------------*/
551 * EHCI Specification 0.96 Section 3.7
552 * Periodic Frame Span Traversal Node (FSTN)
554 * Manages split interrupt transactions (using TT) that span frame boundaries
555 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
556 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
557 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
560 __hc32 hw_next; /* any periodic q entry */
561 __hc32 hw_prev; /* qh or EHCI_LIST_END */
563 /* the rest is HCD-private */
565 union ehci_shadow fstn_next; /* ptr to periodic q entry */
566 } __attribute__ ((aligned (32)));
568 /*-------------------------------------------------------------------------*/
570 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
572 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
573 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
575 #define ehci_prepare_ports_for_controller_resume(ehci) \
576 ehci_adjust_port_wakeup_flags(ehci, false, false);
578 /*-------------------------------------------------------------------------*/
580 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
583 * Some EHCI controllers have a Transaction Translator built into the
584 * root hub. This is a non-standard feature. Each controller will need
585 * to add code to the following inline functions, and call them as
586 * needed (mostly in root hub code).
589 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
591 /* Returns the speed of a device attached to a port on the root hub. */
592 static inline unsigned int
593 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
595 if (ehci_is_TDI(ehci)) {
596 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
600 return USB_PORT_STAT_LOW_SPEED;
603 return USB_PORT_STAT_HIGH_SPEED;
606 return USB_PORT_STAT_HIGH_SPEED;
611 #define ehci_is_TDI(e) (0)
613 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
616 /*-------------------------------------------------------------------------*/
618 #ifdef CONFIG_PPC_83xx
619 /* Some Freescale processors have an erratum in which the TT
620 * port number in the queue head was 0..N-1 instead of 1..N.
622 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
624 #define ehci_has_fsl_portno_bug(e) (0)
628 * While most USB host controllers implement their registers in
629 * little-endian format, a minority (celleb companion chip) implement
630 * them in big endian format.
632 * This attempts to support either format at compile time without a
633 * runtime penalty, or both formats with the additional overhead
634 * of checking a flag bit.
636 * ehci_big_endian_capbase is a special quirk for controllers that
637 * implement the HC capability registers as separate registers and not
638 * as fields of a 32-bit register.
641 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
642 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
643 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
645 #define ehci_big_endian_mmio(e) 0
646 #define ehci_big_endian_capbase(e) 0
650 * Big-endian read/write functions are arch-specific.
651 * Other arches can be added if/when they're needed.
653 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
654 #define readl_be(addr) __raw_readl((__force unsigned *)addr)
655 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
658 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
659 __u32 __iomem * regs)
661 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
662 return ehci_big_endian_mmio(ehci) ?
670 static inline void ehci_writel(const struct ehci_hcd *ehci,
671 const unsigned int val, __u32 __iomem *regs)
673 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
674 ehci_big_endian_mmio(ehci) ?
675 writel_be(val, regs) :
683 * On certain ppc-44x SoC there is a HW issue, that could only worked around with
684 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
685 * Other common bits are dependent on has_amcc_usb23 quirk flag.
688 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
692 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
694 hc_control |= OHCI_USB_OPER;
696 hc_control |= OHCI_USB_SUSPEND;
698 writel_be(hc_control, ehci->ohci_hcctrl_reg);
699 (void) readl_be(ehci->ohci_hcctrl_reg);
702 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
706 /*-------------------------------------------------------------------------*/
709 * The AMCC 440EPx not only implements its EHCI registers in big-endian
710 * format, but also its DMA data structures (descriptors).
712 * EHCI controllers accessed through PCI work normally (little-endian
713 * everywhere), so we won't bother supporting a BE-only mode for now.
715 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
716 #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
719 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
721 return ehci_big_endian_desc(ehci)
722 ? (__force __hc32)cpu_to_be32(x)
723 : (__force __hc32)cpu_to_le32(x);
727 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
729 return ehci_big_endian_desc(ehci)
730 ? be32_to_cpu((__force __be32)x)
731 : le32_to_cpu((__force __le32)x);
734 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
736 return ehci_big_endian_desc(ehci)
737 ? be32_to_cpup((__force __be32 *)x)
738 : le32_to_cpup((__force __le32 *)x);
744 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
746 return cpu_to_le32(x);
750 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
752 return le32_to_cpu(x);
755 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
757 return le32_to_cpup(x);
762 /*-------------------------------------------------------------------------*/
764 #define ehci_dbg(ehci, fmt, args...) \
765 dev_dbg(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
766 #define ehci_err(ehci, fmt, args...) \
767 dev_err(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
768 #define ehci_info(ehci, fmt, args...) \
769 dev_info(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
770 #define ehci_warn(ehci, fmt, args...) \
771 dev_warn(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
774 # define ehci_vdbg ehci_dbg
776 static inline void ehci_vdbg(struct ehci_hcd *ehci, ...) {}
781 /* For working around the MosChip frame-index-register bug */
782 static unsigned ehci_read_frame_index(struct ehci_hcd *ehci);
786 static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
788 return ehci_readl(ehci, &ehci->regs->frame_index);
793 /*-------------------------------------------------------------------------*/
796 #define STUB_DEBUG_FILES
799 /*-------------------------------------------------------------------------*/
801 #endif /* __LINUX_EHCI_HCD_H */