2 * OHCI HCD (Host Controller Driver) for USB.
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
7 * [ Initialisation is based on Linus' ]
8 * [ uhci code and gregs ohci fragments ]
9 * [ (C) Copyright 1999 Linus Torvalds ]
10 * [ (C) Copyright 1999 Gregory P. Smith]
13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
14 * interfaces (though some non-x86 Intel chips use it). It supports
15 * smarter hardware than UHCI. A download link for the spec available
16 * through the http://www.usb.org website.
18 * This file is licenced under the GPL.
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/timer.h>
32 #include <linux/list.h>
33 #include <linux/usb.h>
34 #include <linux/usb/otg.h>
35 #include <linux/usb/hcd.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/dmapool.h>
38 #include <linux/workqueue.h>
39 #include <linux/debugfs.h>
43 #include <asm/system.h>
44 #include <asm/unaligned.h>
45 #include <asm/byteorder.h>
48 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
49 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
51 /*-------------------------------------------------------------------------*/
53 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
55 /* For initializing controller (mask in an HCFS mode too) */
56 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
57 #define OHCI_INTR_INIT \
58 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
59 | OHCI_INTR_RD | OHCI_INTR_WDH)
62 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
66 #ifdef CONFIG_ARCH_OMAP
67 /* OMAP doesn't support IR (no SMM; not needed) */
71 /*-------------------------------------------------------------------------*/
73 static const char hcd_name [] = "ohci_hcd";
75 #define STATECHANGE_DELAY msecs_to_jiffies(300)
79 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
80 static int ohci_init (struct ohci_hcd *ohci);
81 static void ohci_stop (struct usb_hcd *hcd);
83 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
84 static int ohci_restart (struct ohci_hcd *ohci);
88 static void quirk_amd_pll(int state);
89 static void amd_iso_dev_put(void);
90 static void sb800_prefetch(struct ohci_hcd *ohci, int on);
92 static inline void quirk_amd_pll(int state)
96 static inline void amd_iso_dev_put(void)
100 static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
107 #include "ohci-hub.c"
108 #include "ohci-dbg.c"
109 #include "ohci-mem.c"
114 * On architectures with edge-triggered interrupts we must never return
117 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
118 #define IRQ_NOTMINE IRQ_HANDLED
120 #define IRQ_NOTMINE IRQ_NONE
124 /* Some boards misreport power switching/overcurrent */
125 static int distrust_firmware = 1;
126 module_param (distrust_firmware, bool, 0);
127 MODULE_PARM_DESC (distrust_firmware,
128 "true to distrust firmware power/overcurrent setup");
130 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
131 static int no_handshake = 0;
132 module_param (no_handshake, bool, 0);
133 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
135 /*-------------------------------------------------------------------------*/
138 * queue up an urb for anything except the root hub
140 static int ohci_urb_enqueue (
145 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
147 urb_priv_t *urb_priv;
148 unsigned int pipe = urb->pipe;
153 #ifdef OHCI_VERBOSE_DEBUG
154 urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS);
157 /* every endpoint has a ed, locate and maybe (re)initialize it */
158 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
161 /* for the private part of the URB we need the number of TDs (size) */
164 /* td_submit_urb() doesn't yet handle these */
165 if (urb->transfer_buffer_length > 4096)
168 /* 1 TD for setup, 1 for ACK, plus ... */
171 // case PIPE_INTERRUPT:
174 /* one TD for every 4096 Bytes (can be upto 8K) */
175 size += urb->transfer_buffer_length / 4096;
176 /* ... and for any remaining bytes ... */
177 if ((urb->transfer_buffer_length % 4096) != 0)
179 /* ... and maybe a zero length packet to wrap it up */
182 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
183 && (urb->transfer_buffer_length
184 % usb_maxpacket (urb->dev, pipe,
185 usb_pipeout (pipe))) == 0)
188 case PIPE_ISOCHRONOUS: /* number of packets from URB */
189 size = urb->number_of_packets;
193 /* allocate the private part of the URB */
194 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
198 INIT_LIST_HEAD (&urb_priv->pending);
199 urb_priv->length = size;
202 /* allocate the TDs (deferring hash chain updates) */
203 for (i = 0; i < size; i++) {
204 urb_priv->td [i] = td_alloc (ohci, mem_flags);
205 if (!urb_priv->td [i]) {
206 urb_priv->length = i;
207 urb_free_priv (ohci, urb_priv);
212 spin_lock_irqsave (&ohci->lock, flags);
214 /* don't submit to a dead HC */
215 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
219 if (!HC_IS_RUNNING(hcd->state)) {
223 retval = usb_hcd_link_urb_to_ep(hcd, urb);
227 /* schedule the ed if needed */
228 if (ed->state == ED_IDLE) {
229 retval = ed_schedule (ohci, ed);
231 usb_hcd_unlink_urb_from_ep(hcd, urb);
234 if (ed->type == PIPE_ISOCHRONOUS) {
235 u16 frame = ohci_frame_no(ohci);
237 /* delay a few frames before the first TD */
238 frame += max_t (u16, 8, ed->interval);
239 frame &= ~(ed->interval - 1);
241 urb->start_frame = frame;
243 /* yes, only URB_ISO_ASAP is supported, and
244 * urb->start_frame is never used as input.
247 } else if (ed->type == PIPE_ISOCHRONOUS)
248 urb->start_frame = ed->last_iso + ed->interval;
250 /* fill the TDs and link them to the ed; and
251 * enable that part of the schedule, if needed
252 * and update count of queued periodic urbs
254 urb->hcpriv = urb_priv;
255 td_submit_urb (ohci, urb);
259 urb_free_priv (ohci, urb_priv);
260 spin_unlock_irqrestore (&ohci->lock, flags);
265 * decouple the URB from the HC queues (TDs, urb_priv).
266 * reporting is always done
267 * asynchronously, and we might be dealing with an urb that's
268 * partially transferred, or an ED with other urbs being unlinked.
270 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
272 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
276 #ifdef OHCI_VERBOSE_DEBUG
277 urb_print(urb, "UNLINK", 1, status);
280 spin_lock_irqsave (&ohci->lock, flags);
281 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
284 } else if (HC_IS_RUNNING(hcd->state)) {
285 urb_priv_t *urb_priv;
287 /* Unless an IRQ completed the unlink while it was being
288 * handed to us, flag it for unlink and giveback, and force
289 * some upcoming INTR_SF to call finish_unlinks()
291 urb_priv = urb->hcpriv;
293 if (urb_priv->ed->state == ED_OPER)
294 start_ed_unlink (ohci, urb_priv->ed);
298 * with HC dead, we won't respect hc queue pointers
299 * any more ... just clean up every urb's memory.
302 finish_urb(ohci, urb, status);
304 spin_unlock_irqrestore (&ohci->lock, flags);
308 /*-------------------------------------------------------------------------*/
310 /* frees config/altsetting state for endpoints,
311 * including ED memory, dummy TD, and bulk/intr data toggle
315 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
317 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
319 struct ed *ed = ep->hcpriv;
320 unsigned limit = 1000;
322 /* ASSERT: any requests/urbs are being unlinked */
323 /* ASSERT: nobody can be submitting urbs for this any more */
329 spin_lock_irqsave (&ohci->lock, flags);
331 if (!HC_IS_RUNNING (hcd->state)) {
334 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
335 ohci->eds_scheduled--;
336 finish_unlinks (ohci, 0);
340 case ED_UNLINK: /* wait for hw to finish? */
341 /* major IRQ delivery trouble loses INTR_SF too... */
343 ohci_warn(ohci, "ED unlink timeout\n");
344 if (quirk_zfmicro(ohci)) {
345 ohci_warn(ohci, "Attempting ZF TD recovery\n");
346 ohci->ed_to_check = ed;
351 spin_unlock_irqrestore (&ohci->lock, flags);
352 schedule_timeout_uninterruptible(1);
354 case ED_IDLE: /* fully unlinked */
355 if (list_empty (&ed->td_list)) {
356 td_free (ohci, ed->dummy);
360 /* else FALL THROUGH */
362 /* caller was supposed to have unlinked any requests;
363 * that's not our job. can't recover; must leak ed.
365 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
366 ed, ep->desc.bEndpointAddress, ed->state,
367 list_empty (&ed->td_list) ? "" : " (has tds)");
368 td_free (ohci, ed->dummy);
372 spin_unlock_irqrestore (&ohci->lock, flags);
375 static int ohci_get_frame (struct usb_hcd *hcd)
377 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
379 return ohci_frame_no(ohci);
382 static void ohci_usb_reset (struct ohci_hcd *ohci)
384 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
385 ohci->hc_control &= OHCI_CTRL_RWC;
386 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
389 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
390 * other cases where the next software may expect clean state from the
391 * "firmware". this is bus-neutral, unlike shutdown() methods.
394 ohci_shutdown (struct usb_hcd *hcd)
396 struct ohci_hcd *ohci;
398 ohci = hcd_to_ohci (hcd);
399 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
400 ohci_usb_reset (ohci);
401 /* flush the writes */
402 (void) ohci_readl (ohci, &ohci->regs->control);
405 static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
407 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
408 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
409 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
410 && !list_empty(&ed->td_list);
413 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
414 * an interrupt TD but neglects to add it to the donelist. On systems with
415 * this chipset, we need to periodically check the state of the queues to look
416 * for such "lost" TDs.
418 static void unlink_watchdog_func(unsigned long _ohci)
422 unsigned seen_count = 0;
424 struct ed **seen = NULL;
425 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
427 spin_lock_irqsave(&ohci->lock, flags);
428 max = ohci->eds_scheduled;
432 if (ohci->ed_to_check)
435 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
439 for (i = 0; i < NUM_INTS; i++) {
440 struct ed *ed = ohci->periodic[i];
445 /* scan this branch of the periodic schedule tree */
446 for (temp = 0; temp < seen_count; temp++) {
447 if (seen[temp] == ed) {
448 /* we've checked it and what's after */
455 seen[seen_count++] = ed;
456 if (!check_ed(ohci, ed)) {
461 /* HC's TD list is empty, but HCD sees at least one
462 * TD that's not been sent through the donelist.
464 ohci->ed_to_check = ed;
467 /* The HC may wait until the next frame to report the
468 * TD as done through the donelist and INTR_WDH. (We
469 * just *assume* it's not a multi-TD interrupt URB;
470 * those could defer the IRQ more than one frame, using
471 * DI...) Check again after the next INTR_SF.
473 ohci_writel(ohci, OHCI_INTR_SF,
474 &ohci->regs->intrstatus);
475 ohci_writel(ohci, OHCI_INTR_SF,
476 &ohci->regs->intrenable);
478 /* flush those writes */
479 (void) ohci_readl(ohci, &ohci->regs->control);
486 if (ohci->eds_scheduled)
487 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
489 spin_unlock_irqrestore(&ohci->lock, flags);
492 /*-------------------------------------------------------------------------*
494 *-------------------------------------------------------------------------*/
496 /* init memory, and kick BIOS/SMM off */
498 static int ohci_init (struct ohci_hcd *ohci)
501 struct usb_hcd *hcd = ohci_to_hcd(ohci);
503 if (distrust_firmware)
504 ohci->flags |= OHCI_QUIRK_HUB_POWER;
507 ohci->regs = hcd->regs;
509 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
510 * was never needed for most non-PCI systems ... remove the code?
514 /* SMM owns the HC? not for long! */
515 if (!no_handshake && ohci_readl (ohci,
516 &ohci->regs->control) & OHCI_CTRL_IR) {
519 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
521 /* this timeout is arbitrary. we make it long, so systems
522 * depending on usb keyboards may be usable even if the
523 * BIOS/SMM code seems pretty broken.
525 temp = 500; /* arbitrary: five seconds */
527 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
528 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
529 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
532 ohci_err (ohci, "USB HC takeover failed!"
533 " (BIOS/SMM bug)\n");
537 ohci_usb_reset (ohci);
541 /* Disable HC interrupts */
542 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
544 /* flush the writes, and save key bits like RWC */
545 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
546 ohci->hc_control |= OHCI_CTRL_RWC;
548 /* Read the number of ports unless overridden */
549 if (ohci->num_ports == 0)
550 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
555 ohci->hcca = dma_alloc_coherent (hcd->self.controller,
556 sizeof *ohci->hcca, &ohci->hcca_dma, 0);
560 if ((ret = ohci_mem_init (ohci)) < 0)
563 create_debug_files (ohci);
569 /*-------------------------------------------------------------------------*/
571 /* Start an OHCI controller, set the BUS operational
572 * resets USB and controller
575 static int ohci_run (struct ohci_hcd *ohci)
578 int first = ohci->fminterval == 0;
579 struct usb_hcd *hcd = ohci_to_hcd(ohci);
583 /* boot firmware should have set this up (5.1.1.3.1) */
586 val = ohci_readl (ohci, &ohci->regs->fminterval);
587 ohci->fminterval = val & 0x3fff;
588 if (ohci->fminterval != FI)
589 ohci_dbg (ohci, "fminterval delta %d\n",
590 ohci->fminterval - FI);
591 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
592 /* also: power/overcurrent flags in roothub.a */
595 /* Reset USB nearly "by the book". RemoteWakeupConnected has
596 * to be checked in case boot firmware (BIOS/SMM/...) has set up
597 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
598 * If the bus glue detected wakeup capability then it should
599 * already be enabled; if so we'll just enable it again.
601 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
602 device_set_wakeup_capable(hcd->self.controller, 1);
604 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
608 case OHCI_USB_SUSPEND:
609 case OHCI_USB_RESUME:
610 ohci->hc_control &= OHCI_CTRL_RWC;
611 ohci->hc_control |= OHCI_USB_RESUME;
612 val = 10 /* msec wait */;
614 // case OHCI_USB_RESET:
616 ohci->hc_control &= OHCI_CTRL_RWC;
617 ohci->hc_control |= OHCI_USB_RESET;
618 val = 50 /* msec wait */;
621 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
623 (void) ohci_readl (ohci, &ohci->regs->control);
626 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
628 /* 2msec timelimit here means no irqs/preempt */
629 spin_lock_irq (&ohci->lock);
632 /* HC Reset requires max 10 us delay */
633 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
634 val = 30; /* ... allow extra time */
635 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
637 spin_unlock_irq (&ohci->lock);
638 ohci_err (ohci, "USB HC reset timed out!\n");
644 /* now we're in the SUSPEND state ... must go OPERATIONAL
645 * within 2msec else HC enters RESUME
647 * ... but some hardware won't init fmInterval "by the book"
648 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
649 * this if we write fmInterval after we're OPERATIONAL.
650 * Unclear about ALi, ServerWorks, and others ... this could
651 * easily be a longstanding bug in chip init on Linux.
653 if (ohci->flags & OHCI_QUIRK_INITRESET) {
654 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
655 // flush those writes
656 (void) ohci_readl (ohci, &ohci->regs->control);
659 /* Tell the controller where the control and bulk lists are
660 * The lists are empty now. */
661 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
662 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
664 /* a reset clears this */
665 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
667 periodic_reinit (ohci);
669 /* some OHCI implementations are finicky about how they init.
670 * bogus values here mean not even enumeration could work.
672 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
673 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
674 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
675 ohci->flags |= OHCI_QUIRK_INITRESET;
676 ohci_dbg (ohci, "enabling initreset quirk\n");
679 spin_unlock_irq (&ohci->lock);
680 ohci_err (ohci, "init err (%08x %04x)\n",
681 ohci_readl (ohci, &ohci->regs->fminterval),
682 ohci_readl (ohci, &ohci->regs->periodicstart));
686 /* use rhsc irqs after khubd is fully initialized */
688 hcd->uses_new_polling = 1;
690 /* start controller operations */
691 ohci->hc_control &= OHCI_CTRL_RWC;
692 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
693 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
694 hcd->state = HC_STATE_RUNNING;
696 /* wake on ConnectStatusChange, matching external hubs */
697 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
699 /* Choose the interrupts we care about now, others later on demand */
700 mask = OHCI_INTR_INIT;
701 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
702 ohci_writel (ohci, mask, &ohci->regs->intrenable);
704 /* handle root hub init quirks ... */
705 val = roothub_a (ohci);
706 val &= ~(RH_A_PSM | RH_A_OCPM);
707 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
708 /* NSC 87560 and maybe others */
710 val &= ~(RH_A_POTPGT | RH_A_NPS);
711 ohci_writel (ohci, val, &ohci->regs->roothub.a);
712 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
713 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
714 /* hub power always on; required for AMD-756 and some
715 * Mac platforms. ganged overcurrent reporting, if any.
718 ohci_writel (ohci, val, &ohci->regs->roothub.a);
720 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
721 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
722 &ohci->regs->roothub.b);
723 // flush those writes
724 (void) ohci_readl (ohci, &ohci->regs->control);
726 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
727 spin_unlock_irq (&ohci->lock);
729 // POTPGT delay is bits 24-31, in 2 ms units.
730 mdelay ((val >> 23) & 0x1fe);
731 hcd->state = HC_STATE_RUNNING;
733 if (quirk_zfmicro(ohci)) {
734 /* Create timer to watch for bad queue state on ZF Micro */
735 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
736 (unsigned long) ohci);
738 ohci->eds_scheduled = 0;
739 ohci->ed_to_check = NULL;
747 /*-------------------------------------------------------------------------*/
749 /* an interrupt happens */
751 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
753 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
754 struct ohci_regs __iomem *regs = ohci->regs;
757 /* Read interrupt status (and flush pending writes). We ignore the
758 * optimization of checking the LSB of hcca->done_head; it doesn't
759 * work on all systems (edge triggering for OHCI can be a factor).
761 ints = ohci_readl(ohci, ®s->intrstatus);
763 /* Check for an all 1's result which is a typical consequence
764 * of dead, unclocked, or unplugged (CardBus...) devices
766 if (ints == ~(u32)0) {
768 ohci_dbg (ohci, "device removed!\n");
772 /* We only care about interrupts that are enabled */
773 ints &= ohci_readl(ohci, ®s->intrenable);
775 /* interrupt for some other device? */
779 if (ints & OHCI_INTR_UE) {
780 // e.g. due to PCI Master/Target Abort
781 if (quirk_nec(ohci)) {
782 /* Workaround for a silicon bug in some NEC chips used
783 * in Apple's PowerBooks. Adapted from Darwin code.
785 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
787 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable);
789 schedule_work (&ohci->nec_work);
792 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
796 ohci_usb_reset (ohci);
799 if (ints & OHCI_INTR_RHSC) {
800 ohci_vdbg(ohci, "rhsc\n");
801 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
802 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
805 /* NOTE: Vendors didn't always make the same implementation
806 * choices for RHSC. Many followed the spec; RHSC triggers
807 * on an edge, like setting and maybe clearing a port status
808 * change bit. With others it's level-triggered, active
809 * until khubd clears all the port status change bits. We'll
810 * always disable it here and rely on polling until khubd
813 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable);
814 usb_hcd_poll_rh_status(hcd);
817 /* For connect and disconnect events, we expect the controller
818 * to turn on RHSC along with RD. But for remote wakeup events
819 * this might not happen.
821 else if (ints & OHCI_INTR_RD) {
822 ohci_vdbg(ohci, "resume detect\n");
823 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus);
825 if (ohci->autostop) {
826 spin_lock (&ohci->lock);
827 ohci_rh_resume (ohci);
828 spin_unlock (&ohci->lock);
830 usb_hcd_resume_root_hub(hcd);
833 if (ints & OHCI_INTR_WDH) {
834 spin_lock (&ohci->lock);
836 spin_unlock (&ohci->lock);
839 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
840 spin_lock(&ohci->lock);
841 if (ohci->ed_to_check) {
842 struct ed *ed = ohci->ed_to_check;
844 if (check_ed(ohci, ed)) {
845 /* HC thinks the TD list is empty; HCD knows
846 * at least one TD is outstanding
848 if (--ohci->zf_delay == 0) {
849 struct td *td = list_entry(
853 "Reclaiming orphan TD %p\n",
855 takeback_td(ohci, td);
856 ohci->ed_to_check = NULL;
859 ohci->ed_to_check = NULL;
861 spin_unlock(&ohci->lock);
864 /* could track INTR_SO to reduce available PCI/... bandwidth */
866 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
867 * when there's still unlinking to be done (next frame).
869 spin_lock (&ohci->lock);
870 if (ohci->ed_rm_list)
871 finish_unlinks (ohci, ohci_frame_no(ohci));
872 if ((ints & OHCI_INTR_SF) != 0
874 && !ohci->ed_to_check
875 && HC_IS_RUNNING(hcd->state))
876 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable);
877 spin_unlock (&ohci->lock);
879 if (HC_IS_RUNNING(hcd->state)) {
880 ohci_writel (ohci, ints, ®s->intrstatus);
881 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable);
882 // flush those writes
883 (void) ohci_readl (ohci, &ohci->regs->control);
889 /*-------------------------------------------------------------------------*/
891 static void ohci_stop (struct usb_hcd *hcd)
893 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
897 flush_scheduled_work();
899 ohci_usb_reset (ohci);
900 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
901 free_irq(hcd->irq, hcd);
904 if (quirk_zfmicro(ohci))
905 del_timer(&ohci->unlink_watchdog);
906 if (quirk_amdiso(ohci))
909 remove_debug_files (ohci);
910 ohci_mem_cleanup (ohci);
912 dma_free_coherent (hcd->self.controller,
914 ohci->hcca, ohci->hcca_dma);
920 /*-------------------------------------------------------------------------*/
922 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
924 /* must not be called from interrupt context */
925 static int ohci_restart (struct ohci_hcd *ohci)
929 struct urb_priv *priv;
931 spin_lock_irq(&ohci->lock);
934 /* Recycle any "live" eds/tds (and urbs). */
935 if (!list_empty (&ohci->pending))
936 ohci_dbg(ohci, "abort schedule...\n");
937 list_for_each_entry (priv, &ohci->pending, pending) {
938 struct urb *urb = priv->td[0]->urb;
939 struct ed *ed = priv->ed;
943 ed->state = ED_UNLINK;
944 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
945 ed_deschedule (ohci, ed);
947 ed->ed_next = ohci->ed_rm_list;
949 ohci->ed_rm_list = ed;
954 ohci_dbg(ohci, "bogus ed %p state %d\n",
959 urb->unlinked = -ESHUTDOWN;
961 finish_unlinks (ohci, 0);
962 spin_unlock_irq(&ohci->lock);
964 /* paranoia, in case that didn't work: */
966 /* empty the interrupt branches */
967 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
968 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
970 /* no EDs to remove */
971 ohci->ed_rm_list = NULL;
973 /* empty control and bulk lists */
974 ohci->ed_controltail = NULL;
975 ohci->ed_bulktail = NULL;
977 if ((temp = ohci_run (ohci)) < 0) {
978 ohci_err (ohci, "can't restart, %d\n", temp);
981 ohci_dbg(ohci, "restart complete\n");
987 /*-------------------------------------------------------------------------*/
989 MODULE_AUTHOR (DRIVER_AUTHOR);
990 MODULE_DESCRIPTION(DRIVER_DESC);
991 MODULE_LICENSE ("GPL");
994 #include "ohci-pci.c"
995 #define PCI_DRIVER ohci_pci_driver
998 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
999 #include "ohci-sa1111.c"
1000 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1003 #if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX)
1004 #include "ohci-s3c2410.c"
1005 #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver
1008 #ifdef CONFIG_USB_OHCI_HCD_OMAP1
1009 #include "ohci-omap.c"
1010 #define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver
1013 #ifdef CONFIG_USB_OHCI_HCD_OMAP3
1014 #include "ohci-omap3.c"
1015 #define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver
1018 #ifdef CONFIG_ARCH_LH7A404
1019 #include "ohci-lh7a404.c"
1020 #define PLATFORM_DRIVER ohci_hcd_lh7a404_driver
1023 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1024 #include "ohci-pxa27x.c"
1025 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
1028 #ifdef CONFIG_ARCH_EP93XX
1029 #include "ohci-ep93xx.c"
1030 #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver
1033 #ifdef CONFIG_MIPS_ALCHEMY
1034 #include "ohci-au1xxx.c"
1035 #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver
1038 #ifdef CONFIG_PNX8550
1039 #include "ohci-pnx8550.c"
1040 #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver
1043 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
1044 #include "ohci-ppc-soc.c"
1045 #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver
1048 #ifdef CONFIG_ARCH_AT91
1049 #include "ohci-at91.c"
1050 #define PLATFORM_DRIVER ohci_hcd_at91_driver
1053 #ifdef CONFIG_ARCH_PNX4008
1054 #include "ohci-pnx4008.c"
1055 #define PLATFORM_DRIVER usb_hcd_pnx4008_driver
1058 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
1059 #include "ohci-da8xx.c"
1060 #define PLATFORM_DRIVER ohci_hcd_da8xx_driver
1063 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
1064 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
1065 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1066 defined(CONFIG_CPU_SUBTYPE_SH7786)
1067 #include "ohci-sh.c"
1068 #define PLATFORM_DRIVER ohci_hcd_sh_driver
1072 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1073 #include "ohci-ppc-of.c"
1074 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1077 #ifdef CONFIG_PPC_PS3
1078 #include "ohci-ps3.c"
1079 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1082 #ifdef CONFIG_USB_OHCI_HCD_SSB
1083 #include "ohci-ssb.c"
1084 #define SSB_OHCI_DRIVER ssb_ohci_driver
1087 #ifdef CONFIG_MFD_SM501
1088 #include "ohci-sm501.c"
1089 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1092 #ifdef CONFIG_MFD_TC6393XB
1093 #include "ohci-tmio.c"
1094 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1097 #ifdef CONFIG_MACH_JZ4740
1098 #include "ohci-jz4740.c"
1099 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1102 #if !defined(PCI_DRIVER) && \
1103 !defined(PLATFORM_DRIVER) && \
1104 !defined(OMAP1_PLATFORM_DRIVER) && \
1105 !defined(OMAP3_PLATFORM_DRIVER) && \
1106 !defined(OF_PLATFORM_DRIVER) && \
1107 !defined(SA1111_DRIVER) && \
1108 !defined(PS3_SYSTEM_BUS_DRIVER) && \
1109 !defined(SM501_OHCI_DRIVER) && \
1110 !defined(TMIO_OHCI_DRIVER) && \
1111 !defined(SSB_OHCI_DRIVER)
1112 #error "missing bus glue for ohci-hcd"
1115 static int __init ohci_hcd_mod_init(void)
1122 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1123 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1124 sizeof (struct ed), sizeof (struct td));
1125 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1128 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1129 if (!ohci_debug_root) {
1135 #ifdef PS3_SYSTEM_BUS_DRIVER
1136 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1141 #ifdef PLATFORM_DRIVER
1142 retval = platform_driver_register(&PLATFORM_DRIVER);
1144 goto error_platform;
1147 #ifdef OMAP1_PLATFORM_DRIVER
1148 retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER);
1150 goto error_omap1_platform;
1153 #ifdef OMAP3_PLATFORM_DRIVER
1154 retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER);
1156 goto error_omap3_platform;
1159 #ifdef OF_PLATFORM_DRIVER
1160 retval = of_register_platform_driver(&OF_PLATFORM_DRIVER);
1162 goto error_of_platform;
1165 #ifdef SA1111_DRIVER
1166 retval = sa1111_driver_register(&SA1111_DRIVER);
1172 retval = pci_register_driver(&PCI_DRIVER);
1177 #ifdef SSB_OHCI_DRIVER
1178 retval = ssb_driver_register(&SSB_OHCI_DRIVER);
1183 #ifdef SM501_OHCI_DRIVER
1184 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1189 #ifdef TMIO_OHCI_DRIVER
1190 retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1198 #ifdef TMIO_OHCI_DRIVER
1199 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1202 #ifdef SM501_OHCI_DRIVER
1203 platform_driver_unregister(&SM501_OHCI_DRIVER);
1206 #ifdef SSB_OHCI_DRIVER
1207 ssb_driver_unregister(&SSB_OHCI_DRIVER);
1211 pci_unregister_driver(&PCI_DRIVER);
1214 #ifdef SA1111_DRIVER
1215 sa1111_driver_unregister(&SA1111_DRIVER);
1218 #ifdef OF_PLATFORM_DRIVER
1219 of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1222 #ifdef PLATFORM_DRIVER
1223 platform_driver_unregister(&PLATFORM_DRIVER);
1226 #ifdef OMAP1_PLATFORM_DRIVER
1227 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1228 error_omap1_platform:
1230 #ifdef OMAP3_PLATFORM_DRIVER
1231 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1232 error_omap3_platform:
1234 #ifdef PS3_SYSTEM_BUS_DRIVER
1235 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1239 debugfs_remove(ohci_debug_root);
1240 ohci_debug_root = NULL;
1244 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1247 module_init(ohci_hcd_mod_init);
1249 static void __exit ohci_hcd_mod_exit(void)
1251 #ifdef TMIO_OHCI_DRIVER
1252 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1254 #ifdef SM501_OHCI_DRIVER
1255 platform_driver_unregister(&SM501_OHCI_DRIVER);
1257 #ifdef SSB_OHCI_DRIVER
1258 ssb_driver_unregister(&SSB_OHCI_DRIVER);
1261 pci_unregister_driver(&PCI_DRIVER);
1263 #ifdef SA1111_DRIVER
1264 sa1111_driver_unregister(&SA1111_DRIVER);
1266 #ifdef OF_PLATFORM_DRIVER
1267 of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1269 #ifdef PLATFORM_DRIVER
1270 platform_driver_unregister(&PLATFORM_DRIVER);
1272 #ifdef PS3_SYSTEM_BUS_DRIVER
1273 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1276 debugfs_remove(ohci_debug_root);
1278 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1280 module_exit(ohci_hcd_mod_exit);