drivers/usb/host/xhci-hub.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/gfp.h>
  24 #include <asm/unaligned.h>
  25
  26 #include "xhci.h"
  27
  28 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  29 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  30                          PORT_RC | PORT_PLC | PORT_PE)
  31
  32 /* USB 3.0 BOS descriptor and a capability descriptor, combined */
  33 static u8 usb_bos_descriptor [] = {
  34         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  35         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  36         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  37         0x1,                            /*  __u8 bNumDeviceCaps */
  38         /* First device capability */
  39         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  40         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  41         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  42         0x00,                           /* bmAttributes, LTM off by default */
  43         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  44         0x03,                           /* bFunctionalitySupport,
  45                                            USB 3.0 speed only */
  46         0x00,                           /* bU1DevExitLat, set later. */
  47         0x00, 0x00                      /* __le16 bU2DevExitLat, set later. */
  48 };
  49
  50
  51 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
  52                 struct usb_hub_descriptor *desc, int ports)
  53 {
  54         u16 temp;
  55
  56         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
  57         desc->bHubContrCurrent = 0;
  58
  59         desc->bNbrPorts = ports;
  60         temp = 0;
  61         /* Bits 1:0 - support per-port power switching, or power always on */
  62         if (HCC_PPC(xhci->hcc_params))
  63                 temp |= HUB_CHAR_INDV_PORT_LPSM;
  64         else
  65                 temp |= HUB_CHAR_NO_LPSM;
  66         /* Bit  2 - root hubs are not part of a compound device */
  67         /* Bits 4:3 - individual port over current protection */
  68         temp |= HUB_CHAR_INDV_PORT_OCPM;
  69         /* Bits 6:5 - no TTs in root ports */
  70         /* Bit  7 - no port indicators */
  71         desc->wHubCharacteristics = cpu_to_le16(temp);
  72 }
  73
  74 /* Fill in the USB 2.0 roothub descriptor */
  75 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  76                 struct usb_hub_descriptor *desc)
  77 {
  78         int ports;
  79         u16 temp;
  80         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
  81         u32 portsc;
  82         unsigned int i;
  83
  84         ports = xhci->num_usb2_ports;
  85
  86         xhci_common_hub_descriptor(xhci, desc, ports);
  87         desc->bDescriptorType = USB_DT_HUB;
  88         temp = 1 + (ports / 8);
  89         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
  90
  91         /* The Device Removable bits are reported on a byte granularity.
  92          * If the port doesn't exist within that byte, the bit is set to 0.
  93          */
  94         memset(port_removable, 0, sizeof(port_removable));
  95         for (i = 0; i < ports; i++) {
  96                 portsc = xhci_readl(xhci, xhci->usb2_ports[i]);
  97                 /* If a device is removable, PORTSC reports a 0, same as in the
  98                  * hub descriptor DeviceRemovable bits.
  99                  */
 100                 if (portsc & PORT_DEV_REMOVE)
 101                         /* This math is hairy because bit 0 of DeviceRemovable
 102                          * is reserved, and bit 1 is for port 1, etc.
 103                          */
 104                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 105         }
 106
 107         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 108          * ports on it.  The USB 2.0 specification says that there are two
 109          * variable length fields at the end of the hub descriptor:
 110          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 111          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 112          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 113          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 114          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 115          * set of ports that actually exist.
 116          */
 117         memset(desc->u.hs.DeviceRemovable, 0xff,
 118                         sizeof(desc->u.hs.DeviceRemovable));
 119         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 120                         sizeof(desc->u.hs.PortPwrCtrlMask));
 121
 122         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 123                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 124                                 sizeof(__u8));
 125 }
 126
 127 /* Fill in the USB 3.0 roothub descriptor */
 128 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 129                 struct usb_hub_descriptor *desc)
 130 {
 131         int ports;
 132         u16 port_removable;
 133         u32 portsc;
 134         unsigned int i;
 135
 136         ports = xhci->num_usb3_ports;
 137         xhci_common_hub_descriptor(xhci, desc, ports);
 138         desc->bDescriptorType = USB_DT_SS_HUB;
 139         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 140
 141         /* header decode latency should be zero for roothubs,
 142          * see section 4.23.5.2.
 143          */
 144         desc->u.ss.bHubHdrDecLat = 0;
 145         desc->u.ss.wHubDelay = 0;
 146
 147         port_removable = 0;
 148         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 149         for (i = 0; i < ports; i++) {
 150                 portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
 151                 if (portsc & PORT_DEV_REMOVE)
 152                         port_removable |= 1 << (i + 1);
 153         }
 154
 155         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 156 }
 157
 158 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 159                 struct usb_hub_descriptor *desc)
 160 {
 161
 162         if (hcd->speed == HCD_USB3)
 163                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 164         else
 165                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 166
 167 }
 168
 169 static unsigned int xhci_port_speed(unsigned int port_status)
 170 {
 171         if (DEV_LOWSPEED(port_status))
 172                 return USB_PORT_STAT_LOW_SPEED;
 173         if (DEV_HIGHSPEED(port_status))
 174                 return USB_PORT_STAT_HIGH_SPEED;
 175         /*
 176          * FIXME: Yes, we should check for full speed, but the core uses that as
 177          * a default in portspeed() in usb/core/hub.c (which is the only place
 178          * USB_PORT_STAT_*_SPEED is used).
 179          */
 180         return 0;
 181 }
 182
 183 /*
 184  * These bits are Read Only (RO) and should be saved and written to the
 185  * registers: 0, 3, 10:13, 30
 186  * connect status, over-current status, port speed, and device removable.
 187  * connect status and port speed are also sticky - meaning they're in
 188  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 189  */
 190 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 191 /*
 192  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 193  * bits 5:8, 9, 14:15, 25:27
 194  * link state, port power, port indicator state, "wake on" enable state
 195  */
 196 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 197 /*
 198  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 199  * bit 4 (port reset)
 200  */
 201 #define XHCI_PORT_RW1S  ((1<<4))
 202 /*
 203  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 204  * bits 1, 17, 18, 19, 20, 21, 22, 23
 205  * port enable/disable, and
 206  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 207  * over-current, reset, link state, and L1 change
 208  */
 209 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 210 /*
 211  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 212  * latched in
 213  */
 214 #define XHCI_PORT_RW    ((1<<16))
 215 /*
 216  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 217  * bits 2, 24, 28:31
 218  */
 219 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 220
 221 /*
 222  * Given a port state, this function returns a value that would result in the
 223  * port being in the same state, if the value was written to the port status
 224  * control register.
 225  * Save Read Only (RO) bits and save read/write bits where
 226  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 227  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 228  */
 229 u32 xhci_port_state_to_neutral(u32 state)
 230 {
 231         /* Save read-only status and port state */
 232         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 233 }
 234
 235 /*
 236  * find slot id based on port number.
 237  * @port: The one-based port number from one of the two split roothubs.
 238  */
 239 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 240                 u16 port)
 241 {
 242         int slot_id;
 243         int i;
 244         enum usb_device_speed speed;
 245
 246         slot_id = 0;
 247         for (i = 0; i < MAX_HC_SLOTS; i++) {
 248                 if (!xhci->devs[i])
 249                         continue;
 250                 speed = xhci->devs[i]->udev->speed;
 251                 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
 252                                 && xhci->devs[i]->fake_port == port) {
 253                         slot_id = i;
 254                         break;
 255                 }
 256         }
 257
 258         return slot_id;
 259 }
 260
 261 /*
 262  * Stop device
 263  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 264  * to complete.
 265  * suspend will set to 1, if suspend bit need to set in command.
 266  */
 267 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 268 {
 269         struct xhci_virt_device *virt_dev;
 270         struct xhci_command *cmd;
 271         unsigned long flags;
 272         int timeleft;
 273         int ret;
 274         int i;
 275
 276         ret = 0;
 277         virt_dev = xhci->devs[slot_id];
 278         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 279         if (!cmd) {
 280                 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
 281                 return -ENOMEM;
 282         }
 283
 284         spin_lock_irqsave(&xhci->lock, flags);
 285         for (i = LAST_EP_INDEX; i > 0; i--) {
 286                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
 287                         xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
 288         }
 289         cmd->command_trb = xhci_find_next_enqueue(xhci->cmd_ring);
 290         list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
 291         xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
 292         xhci_ring_cmd_db(xhci);
 293         spin_unlock_irqrestore(&xhci->lock, flags);
 294
 295         /* Wait for last stop endpoint command to finish */
 296         timeleft = wait_for_completion_interruptible_timeout(
 297                         cmd->completion,
 298                         USB_CTRL_SET_TIMEOUT);
 299         if (timeleft <= 0) {
 300                 xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
 301                                 timeleft == 0 ? "Timeout" : "Signal");
 302                 spin_lock_irqsave(&xhci->lock, flags);
 303                 /* The timeout might have raced with the event ring handler, so
 304                  * only delete from the list if the item isn't poisoned.
 305                  */
 306                 if (cmd->cmd_list.next != LIST_POISON1)
 307                         list_del(&cmd->cmd_list);
 308                 spin_unlock_irqrestore(&xhci->lock, flags);
 309                 ret = -ETIME;
 310                 goto command_cleanup;
 311         }
 312
 313 command_cleanup:
 314         xhci_free_command(xhci, cmd);
 315         return ret;
 316 }
 317
 318 /*
 319  * Ring device, it rings the all doorbells unconditionally.
 320  */
 321 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 322 {
 323         int i;
 324
 325         for (i = 0; i < LAST_EP_INDEX + 1; i++)
 326                 if (xhci->devs[slot_id]->eps[i].ring &&
 327                     xhci->devs[slot_id]->eps[i].ring->dequeue)
 328                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 329
 330         return;
 331 }
 332
 333 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 334                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 335 {
 336         /* Don't allow the USB core to disable SuperSpeed ports. */
 337         if (hcd->speed == HCD_USB3) {
 338                 xhci_dbg(xhci, "Ignoring request to disable "
 339                                 "SuperSpeed port.\n");
 340                 return;
 341         }
 342
 343         /* Write 1 to disable the port */
 344         xhci_writel(xhci, port_status | PORT_PE, addr);
 345         port_status = xhci_readl(xhci, addr);
 346         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 347                         wIndex, port_status);
 348 }
 349
 350 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 351                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 352 {
 353         char *port_change_bit;
 354         u32 status;
 355
 356         switch (wValue) {
 357         case USB_PORT_FEAT_C_RESET:
 358                 status = PORT_RC;
 359                 port_change_bit = "reset";
 360                 break;
 361         case USB_PORT_FEAT_C_BH_PORT_RESET:
 362                 status = PORT_WRC;
 363                 port_change_bit = "warm(BH) reset";
 364                 break;
 365         case USB_PORT_FEAT_C_CONNECTION:
 366                 status = PORT_CSC;
 367                 port_change_bit = "connect";
 368                 break;
 369         case USB_PORT_FEAT_C_OVER_CURRENT:
 370                 status = PORT_OCC;
 371                 port_change_bit = "over-current";
 372                 break;
 373         case USB_PORT_FEAT_C_ENABLE:
 374                 status = PORT_PEC;
 375                 port_change_bit = "enable/disable";
 376                 break;
 377         case USB_PORT_FEAT_C_SUSPEND:
 378                 status = PORT_PLC;
 379                 port_change_bit = "suspend/resume";
 380                 break;
 381         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 382                 status = PORT_PLC;
 383                 port_change_bit = "link state";
 384                 break;
 385         default:
 386                 /* Should never happen */
 387                 return;
 388         }
 389         /* Change bits are all write 1 to clear */
 390         xhci_writel(xhci, port_status | status, addr);
 391         port_status = xhci_readl(xhci, addr);
 392         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 393                         port_change_bit, wIndex, port_status);
 394 }
 395
 396 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 397 {
 398         int max_ports;
 399         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 400
 401         if (hcd->speed == HCD_USB3) {
 402                 max_ports = xhci->num_usb3_ports;
 403                 *port_array = xhci->usb3_ports;
 404         } else {
 405                 max_ports = xhci->num_usb2_ports;
 406                 *port_array = xhci->usb2_ports;
 407         }
 408
 409         return max_ports;
 410 }
 411
 412 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 413                                 int port_id, u32 link_state)
 414 {
 415         u32 temp;
 416
 417         temp = xhci_readl(xhci, port_array[port_id]);
 418         temp = xhci_port_state_to_neutral(temp);
 419         temp &= ~PORT_PLS_MASK;
 420         temp |= PORT_LINK_STROBE | link_state;
 421         xhci_writel(xhci, temp, port_array[port_id]);
 422 }
 423
 424 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 425                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 426 {
 427         u32 temp;
 428
 429         temp = xhci_readl(xhci, port_array[port_id]);
 430         temp = xhci_port_state_to_neutral(temp);
 431
 432         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 433                 temp |= PORT_WKCONN_E;
 434         else
 435                 temp &= ~PORT_WKCONN_E;
 436
 437         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 438                 temp |= PORT_WKDISC_E;
 439         else
 440                 temp &= ~PORT_WKDISC_E;
 441
 442         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 443                 temp |= PORT_WKOC_E;
 444         else
 445                 temp &= ~PORT_WKOC_E;
 446
 447         xhci_writel(xhci, temp, port_array[port_id]);
 448 }
 449
 450 /* Test and clear port RWC bit */
 451 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 452                                 int port_id, u32 port_bit)
 453 {
 454         u32 temp;
 455
 456         temp = xhci_readl(xhci, port_array[port_id]);
 457         if (temp & port_bit) {
 458                 temp = xhci_port_state_to_neutral(temp);
 459                 temp |= port_bit;
 460                 xhci_writel(xhci, temp, port_array[port_id]);
 461         }
 462 }
 463
 464 /* Updates Link Status for super Speed port */
 465 static void xhci_hub_report_link_state(struct xhci_hcd *xhci,
 466                 u32 *status, u32 status_reg)
 467 {
 468         u32 pls = status_reg & PORT_PLS_MASK;
 469
 470         /* resume state is a xHCI internal state.
 471          * Do not report it to usb core.
 472          */
 473         if (pls == XDEV_RESUME)
 474                 return;
 475
 476         /* When the CAS bit is set then warm reset
 477          * should be performed on port
 478          */
 479         if (status_reg & PORT_CAS) {
 480                 /* The CAS bit can be set while the port is
 481                  * in any link state.
 482                  * Only roothubs have CAS bit, so we
 483                  * pretend to be in compliance mode
 484                  * unless we're already in compliance
 485                  * or the inactive state.
 486                  */
 487                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 488                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 489                         pls = USB_SS_PORT_LS_COMP_MOD;
 490                 }
 491                 /* Return also connection bit -
 492                  * hub state machine resets port
 493                  * when this bit is set.
 494                  */
 495                 pls |= USB_PORT_STAT_CONNECTION;
 496         } else {
 497                 /*
 498                  * If CAS bit isn't set but the Port is already at
 499                  * Compliance Mode, fake a connection so the USB core
 500                  * notices the Compliance state and resets the port.
 501                  * This resolves an issue generated by the SN65LVPE502CP
 502                  * in which sometimes the port enters compliance mode
 503                  * caused by a delay on the host-device negotiation.
 504                  */
 505                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 506                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 507                         pls |= USB_PORT_STAT_CONNECTION;
 508         }
 509
 510         /* update status field */
 511         *status |= pls;
 512 }
 513
 514 /*
 515  * Function for Compliance Mode Quirk.
 516  *
 517  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 518  * the compliance mode timer is deleted. A port won't enter
 519  * compliance mode if it has previously entered U0.
 520  */
 521 void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, u16 wIndex)
 522 {
 523         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 524         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 525
 526         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 527                 return;
 528
 529         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 530                 xhci->port_status_u0 |= 1 << wIndex;
 531                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 532                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 533                         xhci_dbg(xhci, "All USB3 ports have entered U0 already!\n");
 534                         xhci_dbg(xhci, "Compliance Mode Recovery Timer Deleted.\n");
 535                 }
 536         }
 537 }
 538
 539 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 540                 u16 wIndex, char *buf, u16 wLength)
 541 {
 542         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 543         int max_ports;
 544         unsigned long flags;
 545         u32 temp, status;
 546         int retval = 0;
 547         __le32 __iomem **port_array;
 548         int slot_id;
 549         struct xhci_bus_state *bus_state;
 550         u16 link_state = 0;
 551         u16 wake_mask = 0;
 552         u16 timeout = 0;
 553
 554         max_ports = xhci_get_ports(hcd, &port_array);
 555         bus_state = &xhci->bus_state[hcd_index(hcd)];
 556
 557         spin_lock_irqsave(&xhci->lock, flags);
 558         switch (typeReq) {
 559         case GetHubStatus:
 560                 /* No power source, over-current reported per port */
 561                 memset(buf, 0, 4);
 562                 break;
 563         case GetHubDescriptor:
 564                 /* Check to make sure userspace is asking for the USB 3.0 hub
 565                  * descriptor for the USB 3.0 roothub.  If not, we stall the
 566                  * endpoint, like external hubs do.
 567                  */
 568                 if (hcd->speed == HCD_USB3 &&
 569                                 (wLength < USB_DT_SS_HUB_SIZE ||
 570                                  wValue != (USB_DT_SS_HUB << 8))) {
 571                         xhci_dbg(xhci, "Wrong hub descriptor type for "
 572                                         "USB 3.0 roothub.\n");
 573                         goto error;
 574                 }
 575                 xhci_hub_descriptor(hcd, xhci,
 576                                 (struct usb_hub_descriptor *) buf);
 577                 break;
 578         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
 579                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
 580                         goto error;
 581
 582                 if (hcd->speed != HCD_USB3)
 583                         goto error;
 584
 585                 /* Set the U1 and U2 exit latencies. */
 586                 memcpy(buf, &usb_bos_descriptor,
 587                                 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
 588                 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
 589                 buf[12] = HCS_U1_LATENCY(temp);
 590                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 591
 592                 /* Indicate whether the host has LTM support. */
 593                 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
 594                 if (HCC_LTC(temp))
 595                         buf[8] |= USB_LTM_SUPPORT;
 596
 597                 spin_unlock_irqrestore(&xhci->lock, flags);
 598                 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 599         case GetPortStatus:
 600                 if (!wIndex || wIndex > max_ports)
 601                         goto error;
 602                 wIndex--;
 603                 status = 0;
 604                 temp = xhci_readl(xhci, port_array[wIndex]);
 605                 if (temp == 0xffffffff) {
 606                         retval = -ENODEV;
 607                         break;
 608                 }
 609                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n", wIndex, temp);
 610
 611                 /* wPortChange bits */
 612                 if (temp & PORT_CSC)
 613                         status |= USB_PORT_STAT_C_CONNECTION << 16;
 614                 if (temp & PORT_PEC)
 615                         status |= USB_PORT_STAT_C_ENABLE << 16;
 616                 if ((temp & PORT_OCC))
 617                         status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 618                 if ((temp & PORT_RC))
 619                         status |= USB_PORT_STAT_C_RESET << 16;
 620                 /* USB3.0 only */
 621                 if (hcd->speed == HCD_USB3) {
 622                         if ((temp & PORT_PLC))
 623                                 status |= USB_PORT_STAT_C_LINK_STATE << 16;
 624                         if ((temp & PORT_WRC))
 625                                 status |= USB_PORT_STAT_C_BH_RESET << 16;
 626                 }
 627
 628                 if (hcd->speed != HCD_USB3) {
 629                         if ((temp & PORT_PLS_MASK) == XDEV_U3
 630                                         && (temp & PORT_POWER))
 631                                 status |= USB_PORT_STAT_SUSPEND;
 632                 }
 633                 if ((temp & PORT_PLS_MASK) == XDEV_RESUME &&
 634                                 !DEV_SUPERSPEED(temp)) {
 635                         if ((temp & PORT_RESET) || !(temp & PORT_PE))
 636                                 goto error;
 637                         if (time_after_eq(jiffies,
 638                                         bus_state->resume_done[wIndex])) {
 639                                 xhci_dbg(xhci, "Resume USB2 port %d\n",
 640                                         wIndex + 1);
 641                                 bus_state->resume_done[wIndex] = 0;
 642                                 clear_bit(wIndex, &bus_state->resuming_ports);
 643                                 xhci_set_link_state(xhci, port_array, wIndex,
 644                                                         XDEV_U0);
 645                                 xhci_dbg(xhci, "set port %d resume\n",
 646                                         wIndex + 1);
 647                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 648                                                                  wIndex + 1);
 649                                 if (!slot_id) {
 650                                         xhci_dbg(xhci, "slot_id is zero\n");
 651                                         goto error;
 652                                 }
 653                                 xhci_ring_device(xhci, slot_id);
 654                                 bus_state->port_c_suspend |= 1 << wIndex;
 655                                 bus_state->suspended_ports &= ~(1 << wIndex);
 656                         } else {
 657                                 /*
 658                                  * The resume has been signaling for less than
 659                                  * 20ms. Report the port status as SUSPEND,
 660                                  * let the usbcore check port status again
 661                                  * and clear resume signaling later.
 662                                  */
 663                                 status |= USB_PORT_STAT_SUSPEND;
 664                         }
 665                 }
 666                 if ((temp & PORT_PLS_MASK) == XDEV_U0
 667                         && (temp & PORT_POWER)
 668                         && (bus_state->suspended_ports & (1 << wIndex))) {
 669                         bus_state->suspended_ports &= ~(1 << wIndex);
 670                         if (hcd->speed != HCD_USB3)
 671                                 bus_state->port_c_suspend |= 1 << wIndex;
 672                 }
 673                 if (temp & PORT_CONNECT) {
 674                         status |= USB_PORT_STAT_CONNECTION;
 675                         status |= xhci_port_speed(temp);
 676                 }
 677                 if (temp & PORT_PE)
 678                         status |= USB_PORT_STAT_ENABLE;
 679                 if (temp & PORT_OC)
 680                         status |= USB_PORT_STAT_OVERCURRENT;
 681                 if (temp & PORT_RESET)
 682                         status |= USB_PORT_STAT_RESET;
 683                 if (temp & PORT_POWER) {
 684                         if (hcd->speed == HCD_USB3)
 685                                 status |= USB_SS_PORT_STAT_POWER;
 686                         else
 687                                 status |= USB_PORT_STAT_POWER;
 688                 }
 689                 /* Update Port Link State for super speed ports*/
 690                 if (hcd->speed == HCD_USB3) {
 691                         xhci_hub_report_link_state(xhci, &status, temp);
 692                         /*
 693                          * Verify if all USB3 Ports Have entered U0 already.
 694                          * Delete Compliance Mode Timer if so.
 695                          */
 696                         xhci_del_comp_mod_timer(xhci, temp, wIndex);
 697                 }
 698                 if (bus_state->port_c_suspend & (1 << wIndex))
 699                         status |= 1 << USB_PORT_FEAT_C_SUSPEND;
 700                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
 701                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
 702                 break;
 703         case SetPortFeature:
 704                 if (wValue == USB_PORT_FEAT_LINK_STATE)
 705                         link_state = (wIndex & 0xff00) >> 3;
 706                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
 707                         wake_mask = wIndex & 0xff00;
 708                 /* The MSB of wIndex is the U1/U2 timeout */
 709                 timeout = (wIndex & 0xff00) >> 8;
 710                 wIndex &= 0xff;
 711                 if (!wIndex || wIndex > max_ports)
 712                         goto error;
 713                 wIndex--;
 714                 temp = xhci_readl(xhci, port_array[wIndex]);
 715                 if (temp == 0xffffffff) {
 716                         retval = -ENODEV;
 717                         break;
 718                 }
 719                 temp = xhci_port_state_to_neutral(temp);
 720                 /* FIXME: What new port features do we need to support? */
 721                 switch (wValue) {
 722                 case USB_PORT_FEAT_SUSPEND:
 723                         temp = xhci_readl(xhci, port_array[wIndex]);
 724                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
 725                                 /* Resume the port to U0 first */
 726                                 xhci_set_link_state(xhci, port_array, wIndex,
 727                                                         XDEV_U0);
 728                                 spin_unlock_irqrestore(&xhci->lock, flags);
 729                                 msleep(10);
 730                                 spin_lock_irqsave(&xhci->lock, flags);
 731                         }
 732                         /* In spec software should not attempt to suspend
 733                          * a port unless the port reports that it is in the
 734                          * enabled (PED = ‘1’,PLS < ‘3’) state.
 735                          */
 736                         temp = xhci_readl(xhci, port_array[wIndex]);
 737                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
 738                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
 739                                 xhci_warn(xhci, "USB core suspending device "
 740                                           "not in U0/U1/U2.\n");
 741                                 goto error;
 742                         }
 743
 744                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 745                                         wIndex + 1);
 746                         if (!slot_id) {
 747                                 xhci_warn(xhci, "slot_id is zero\n");
 748                                 goto error;
 749                         }
 750                         /* unlock to execute stop endpoint commands */
 751                         spin_unlock_irqrestore(&xhci->lock, flags);
 752                         xhci_stop_device(xhci, slot_id, 1);
 753                         spin_lock_irqsave(&xhci->lock, flags);
 754
 755                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
 756
 757                         spin_unlock_irqrestore(&xhci->lock, flags);
 758                         msleep(10); /* wait device to enter */
 759                         spin_lock_irqsave(&xhci->lock, flags);
 760
 761                         temp = xhci_readl(xhci, port_array[wIndex]);
 762                         bus_state->suspended_ports |= 1 << wIndex;
 763                         break;
 764                 case USB_PORT_FEAT_LINK_STATE:
 765                         temp = xhci_readl(xhci, port_array[wIndex]);
 766
 767                         /* Disable port */
 768                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
 769                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
 770                                 temp = xhci_port_state_to_neutral(temp);
 771                                 /*
 772                                  * Clear all change bits, so that we get a new
 773                                  * connection event.
 774                                  */
 775                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
 776                                         PORT_OCC | PORT_RC | PORT_PLC |
 777                                         PORT_CEC;
 778                                 xhci_writel(xhci, temp | PORT_PE,
 779                                         port_array[wIndex]);
 780                                 temp = xhci_readl(xhci, port_array[wIndex]);
 781                                 break;
 782                         }
 783
 784                         /* Put link in RxDetect (enable port) */
 785                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
 786                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
 787                                 xhci_set_link_state(xhci, port_array, wIndex,
 788                                                 link_state);
 789                                 temp = xhci_readl(xhci, port_array[wIndex]);
 790                                 break;
 791                         }
 792
 793                         /* Software should not attempt to set
 794                          * port link state above '3' (U3) and the port
 795                          * must be enabled.
 796                          */
 797                         if ((temp & PORT_PE) == 0 ||
 798                                 (link_state > USB_SS_PORT_LS_U3)) {
 799                                 xhci_warn(xhci, "Cannot set link state.\n");
 800                                 goto error;
 801                         }
 802
 803                         if (link_state == USB_SS_PORT_LS_U3) {
 804                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 805                                                 wIndex + 1);
 806                                 if (slot_id) {
 807                                         /* unlock to execute stop endpoint
 808                                          * commands */
 809                                         spin_unlock_irqrestore(&xhci->lock,
 810                                                                 flags);
 811                                         xhci_stop_device(xhci, slot_id, 1);
 812                                         spin_lock_irqsave(&xhci->lock, flags);
 813                                 }
 814                         }
 815
 816                         xhci_set_link_state(xhci, port_array, wIndex,
 817                                                 link_state);
 818
 819                         spin_unlock_irqrestore(&xhci->lock, flags);
 820                         msleep(20); /* wait device to enter */
 821                         spin_lock_irqsave(&xhci->lock, flags);
 822
 823                         temp = xhci_readl(xhci, port_array[wIndex]);
 824                         if (link_state == USB_SS_PORT_LS_U3)
 825                                 bus_state->suspended_ports |= 1 << wIndex;
 826                         break;
 827                 case USB_PORT_FEAT_POWER:
 828                         /*
 829                          * Turn on ports, even if there isn't per-port switching.
 830                          * HC will report connect events even before this is set.
 831                          * However, khubd will ignore the roothub events until
 832                          * the roothub is registered.
 833                          */
 834                         xhci_writel(xhci, temp | PORT_POWER,
 835                                         port_array[wIndex]);
 836
 837                         temp = xhci_readl(xhci, port_array[wIndex]);
 838                         xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n", wIndex, temp);
 839
 840                         spin_unlock_irqrestore(&xhci->lock, flags);
 841                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 842                                         wIndex);
 843                         if (temp)
 844                                 usb_acpi_set_power_state(hcd->self.root_hub,
 845                                                 wIndex, true);
 846                         spin_lock_irqsave(&xhci->lock, flags);
 847                         break;
 848                 case USB_PORT_FEAT_RESET:
 849                         temp = (temp | PORT_RESET);
 850                         xhci_writel(xhci, temp, port_array[wIndex]);
 851
 852                         temp = xhci_readl(xhci, port_array[wIndex]);
 853                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
 854                         break;
 855                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
 856                         xhci_set_remote_wake_mask(xhci, port_array,
 857                                         wIndex, wake_mask);
 858                         temp = xhci_readl(xhci, port_array[wIndex]);
 859                         xhci_dbg(xhci, "set port remote wake mask, "
 860                                         "actual port %d status  = 0x%x\n",
 861                                         wIndex, temp);
 862                         break;
 863                 case USB_PORT_FEAT_BH_PORT_RESET:
 864                         temp |= PORT_WR;
 865                         xhci_writel(xhci, temp, port_array[wIndex]);
 866
 867                         temp = xhci_readl(xhci, port_array[wIndex]);
 868                         break;
 869                 case USB_PORT_FEAT_U1_TIMEOUT:
 870                         if (hcd->speed != HCD_USB3)
 871                                 goto error;
 872                         temp = xhci_readl(xhci, port_array[wIndex] + 1);
 873                         temp &= ~PORT_U1_TIMEOUT_MASK;
 874                         temp |= PORT_U1_TIMEOUT(timeout);
 875                         xhci_writel(xhci, temp, port_array[wIndex] + 1);
 876                         break;
 877                 case USB_PORT_FEAT_U2_TIMEOUT:
 878                         if (hcd->speed != HCD_USB3)
 879                                 goto error;
 880                         temp = xhci_readl(xhci, port_array[wIndex] + 1);
 881                         temp &= ~PORT_U2_TIMEOUT_MASK;
 882                         temp |= PORT_U2_TIMEOUT(timeout);
 883                         xhci_writel(xhci, temp, port_array[wIndex] + 1);
 884                         break;
 885                 default:
 886                         goto error;
 887                 }
 888                 /* unblock any posted writes */
 889                 temp = xhci_readl(xhci, port_array[wIndex]);
 890                 break;
 891         case ClearPortFeature:
 892                 if (!wIndex || wIndex > max_ports)
 893                         goto error;
 894                 wIndex--;
 895                 temp = xhci_readl(xhci, port_array[wIndex]);
 896                 if (temp == 0xffffffff) {
 897                         retval = -ENODEV;
 898                         break;
 899                 }
 900                 /* FIXME: What new port features do we need to support? */
 901                 temp = xhci_port_state_to_neutral(temp);
 902                 switch (wValue) {
 903                 case USB_PORT_FEAT_SUSPEND:
 904                         temp = xhci_readl(xhci, port_array[wIndex]);
 905                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
 906                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
 907                         if (temp & PORT_RESET)
 908                                 goto error;
 909                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
 910                                 if ((temp & PORT_PE) == 0)
 911                                         goto error;
 912
 913                                 xhci_set_link_state(xhci, port_array, wIndex,
 914                                                         XDEV_RESUME);
 915                                 spin_unlock_irqrestore(&xhci->lock, flags);
 916                                 msleep(20);
 917                                 spin_lock_irqsave(&xhci->lock, flags);
 918                                 xhci_set_link_state(xhci, port_array, wIndex,
 919                                                         XDEV_U0);
 920                         }
 921                         bus_state->port_c_suspend |= 1 << wIndex;
 922
 923                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 924                                         wIndex + 1);
 925                         if (!slot_id) {
 926                                 xhci_dbg(xhci, "slot_id is zero\n");
 927                                 goto error;
 928                         }
 929                         xhci_ring_device(xhci, slot_id);
 930                         break;
 931                 case USB_PORT_FEAT_C_SUSPEND:
 932                         bus_state->port_c_suspend &= ~(1 << wIndex);
 933                 case USB_PORT_FEAT_C_RESET:
 934                 case USB_PORT_FEAT_C_BH_PORT_RESET:
 935                 case USB_PORT_FEAT_C_CONNECTION:
 936                 case USB_PORT_FEAT_C_OVER_CURRENT:
 937                 case USB_PORT_FEAT_C_ENABLE:
 938                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
 939                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
 940                                         port_array[wIndex], temp);
 941                         break;
 942                 case USB_PORT_FEAT_ENABLE:
 943                         xhci_disable_port(hcd, xhci, wIndex,
 944                                         port_array[wIndex], temp);
 945                         break;
 946                 case USB_PORT_FEAT_POWER:
 947                         xhci_writel(xhci, temp & ~PORT_POWER,
 948                                 port_array[wIndex]);
 949
 950                         spin_unlock_irqrestore(&xhci->lock, flags);
 951                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 952                                         wIndex);
 953                         if (temp)
 954                                 usb_acpi_set_power_state(hcd->self.root_hub,
 955                                                 wIndex, false);
 956                         spin_lock_irqsave(&xhci->lock, flags);
 957                         break;
 958                 default:
 959                         goto error;
 960                 }
 961                 break;
 962         default:
 963 error:
 964                 /* "stall" on error */
 965                 retval = -EPIPE;
 966         }
 967         spin_unlock_irqrestore(&xhci->lock, flags);
 968         return retval;
 969 }
 970
 971 /*
 972  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
 973  * Ports are 0-indexed from the HCD point of view,
 974  * and 1-indexed from the USB core pointer of view.
 975  *
 976  * Note that the status change bits will be cleared as soon as a port status
 977  * change event is generated, so we use the saved status from that event.
 978  */
 979 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
 980 {
 981         unsigned long flags;
 982         u32 temp, status;
 983         u32 mask;
 984         int i, retval;
 985         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 986         int max_ports;
 987         __le32 __iomem **port_array;
 988         struct xhci_bus_state *bus_state;
 989         bool reset_change = false;
 990
 991         max_ports = xhci_get_ports(hcd, &port_array);
 992         bus_state = &xhci->bus_state[hcd_index(hcd)];
 993
 994         /* Initial status is no changes */
 995         retval = (max_ports + 8) / 8;
 996         memset(buf, 0, retval);
 997
 998         /*
 999          * Inform the usbcore about resume-in-progress by returning
1000          * a non-zero value even if there are no status changes.
1001          */
1002         status = bus_state->resuming_ports;
1003
1004         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
1005
1006         spin_lock_irqsave(&xhci->lock, flags);
1007         /* For each port, did anything change?  If so, set that bit in buf. */
1008         for (i = 0; i < max_ports; i++) {
1009                 temp = xhci_readl(xhci, port_array[i]);
1010                 if (temp == 0xffffffff) {
1011                         retval = -ENODEV;
1012                         break;
1013                 }
1014                 if ((temp & mask) != 0 ||
1015                         (bus_state->port_c_suspend & 1 << i) ||
1016                         (bus_state->resume_done[i] && time_after_eq(
1017                             jiffies, bus_state->resume_done[i]))) {
1018                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1019                         status = 1;
1020                 }
1021                 if ((temp & PORT_RC))
1022                         reset_change = true;
1023         }
1024         if (!status && !reset_change) {
1025                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1026                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1027         }
1028         spin_unlock_irqrestore(&xhci->lock, flags);
1029         return status ? retval : 0;
1030 }
1031
1032 #ifdef CONFIG_PM
1033
1034 int xhci_bus_suspend(struct usb_hcd *hcd)
1035 {
1036         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1037         int max_ports, port_index;
1038         __le32 __iomem **port_array;
1039         struct xhci_bus_state *bus_state;
1040         unsigned long flags;
1041
1042         max_ports = xhci_get_ports(hcd, &port_array);
1043         bus_state = &xhci->bus_state[hcd_index(hcd)];
1044
1045         spin_lock_irqsave(&xhci->lock, flags);
1046
1047         if (hcd->self.root_hub->do_remote_wakeup) {
1048                 if (bus_state->resuming_ports) {
1049                         spin_unlock_irqrestore(&xhci->lock, flags);
1050                         xhci_dbg(xhci, "suspend failed because "
1051                                                 "a port is resuming\n");
1052                         return -EBUSY;
1053                 }
1054         }
1055
1056         port_index = max_ports;
1057         bus_state->bus_suspended = 0;
1058         while (port_index--) {
1059                 /* suspend the port if the port is not suspended */
1060                 u32 t1, t2;
1061                 int slot_id;
1062
1063                 t1 = xhci_readl(xhci, port_array[port_index]);
1064                 t2 = xhci_port_state_to_neutral(t1);
1065
1066                 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1067                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1068                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1069                                         port_index + 1);
1070                         if (slot_id) {
1071                                 spin_unlock_irqrestore(&xhci->lock, flags);
1072                                 xhci_stop_device(xhci, slot_id, 1);
1073                                 spin_lock_irqsave(&xhci->lock, flags);
1074                         }
1075                         t2 &= ~PORT_PLS_MASK;
1076                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1077                         set_bit(port_index, &bus_state->bus_suspended);
1078                 }
1079                 /* USB core sets remote wake mask for USB 3.0 hubs,
1080                  * including the USB 3.0 roothub, but only if CONFIG_PM_RUNTIME
1081                  * is enabled, so also enable remote wake here.
1082                  */
1083                 if (hcd->self.root_hub->do_remote_wakeup) {
1084                         if (t1 & PORT_CONNECT) {
1085                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1086                                 t2 &= ~PORT_WKCONN_E;
1087                         } else {
1088                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1089                                 t2 &= ~PORT_WKDISC_E;
1090                         }
1091                 } else
1092                         t2 &= ~PORT_WAKE_BITS;
1093
1094                 t1 = xhci_port_state_to_neutral(t1);
1095                 if (t1 != t2)
1096                         xhci_writel(xhci, t2, port_array[port_index]);
1097
1098                 if (hcd->speed != HCD_USB3) {
1099                         /* enable remote wake up for USB 2.0 */
1100                         __le32 __iomem *addr;
1101                         u32 tmp;
1102
1103                         /* Add one to the port status register address to get
1104                          * the port power control register address.
1105                          */
1106                         addr = port_array[port_index] + 1;
1107                         tmp = xhci_readl(xhci, addr);
1108                         tmp |= PORT_RWE;
1109                         xhci_writel(xhci, tmp, addr);
1110                 }
1111         }
1112         hcd->state = HC_STATE_SUSPENDED;
1113         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1114         spin_unlock_irqrestore(&xhci->lock, flags);
1115         return 0;
1116 }
1117
1118 int xhci_bus_resume(struct usb_hcd *hcd)
1119 {
1120         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1121         int max_ports, port_index;
1122         __le32 __iomem **port_array;
1123         struct xhci_bus_state *bus_state;
1124         u32 temp;
1125         unsigned long flags;
1126
1127         max_ports = xhci_get_ports(hcd, &port_array);
1128         bus_state = &xhci->bus_state[hcd_index(hcd)];
1129
1130         if (time_before(jiffies, bus_state->next_statechange))
1131                 msleep(5);
1132
1133         spin_lock_irqsave(&xhci->lock, flags);
1134         if (!HCD_HW_ACCESSIBLE(hcd)) {
1135                 spin_unlock_irqrestore(&xhci->lock, flags);
1136                 return -ESHUTDOWN;
1137         }
1138
1139         /* delay the irqs */
1140         temp = xhci_readl(xhci, &xhci->op_regs->command);
1141         temp &= ~CMD_EIE;
1142         xhci_writel(xhci, temp, &xhci->op_regs->command);
1143
1144         port_index = max_ports;
1145         while (port_index--) {
1146                 /* Check whether need resume ports. If needed
1147                    resume port and disable remote wakeup */
1148                 u32 temp;
1149                 int slot_id;
1150
1151                 temp = xhci_readl(xhci, port_array[port_index]);
1152                 if (DEV_SUPERSPEED(temp))
1153                         temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1154                 else
1155                         temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1156                 if (test_bit(port_index, &bus_state->bus_suspended) &&
1157                     (temp & PORT_PLS_MASK)) {
1158                         if (DEV_SUPERSPEED(temp)) {
1159                                 xhci_set_link_state(xhci, port_array,
1160                                                         port_index, XDEV_U0);
1161                         } else {
1162                                 xhci_set_link_state(xhci, port_array,
1163                                                 port_index, XDEV_RESUME);
1164
1165                                 spin_unlock_irqrestore(&xhci->lock, flags);
1166                                 msleep(20);
1167                                 spin_lock_irqsave(&xhci->lock, flags);
1168
1169                                 xhci_set_link_state(xhci, port_array,
1170                                                         port_index, XDEV_U0);
1171                         }
1172                         /* wait for the port to enter U0 and report port link
1173                          * state change.
1174                          */
1175                         spin_unlock_irqrestore(&xhci->lock, flags);
1176                         msleep(20);
1177                         spin_lock_irqsave(&xhci->lock, flags);
1178
1179                         /* Clear PLC */
1180                         xhci_test_and_clear_bit(xhci, port_array, port_index,
1181                                                 PORT_PLC);
1182
1183                         slot_id = xhci_find_slot_id_by_port(hcd,
1184                                         xhci, port_index + 1);
1185                         if (slot_id)
1186                                 xhci_ring_device(xhci, slot_id);
1187                 } else
1188                         xhci_writel(xhci, temp, port_array[port_index]);
1189
1190                 if (hcd->speed != HCD_USB3) {
1191                         /* disable remote wake up for USB 2.0 */
1192                         __le32 __iomem *addr;
1193                         u32 tmp;
1194
1195                         /* Add one to the port status register address to get
1196                          * the port power control register address.
1197                          */
1198                         addr = port_array[port_index] + 1;
1199                         tmp = xhci_readl(xhci, addr);
1200                         tmp &= ~PORT_RWE;
1201                         xhci_writel(xhci, tmp, addr);
1202                 }
1203         }
1204
1205         (void) xhci_readl(xhci, &xhci->op_regs->command);
1206
1207         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1208         /* re-enable irqs */
1209         temp = xhci_readl(xhci, &xhci->op_regs->command);
1210         temp |= CMD_EIE;
1211         xhci_writel(xhci, temp, &xhci->op_regs->command);
1212         temp = xhci_readl(xhci, &xhci->op_regs->command);
1213
1214         spin_unlock_irqrestore(&xhci->lock, flags);
1215         return 0;
1216 }
1217
1218 #endif  /* CONFIG_PM */