drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include "xhci.h"
  69
  70 /*
  71  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  72  * address of the TRB.
  73  */
  74 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  75                 union xhci_trb *trb)
  76 {
  77         unsigned long segment_offset;
  78
  79         if (!seg || !trb || trb < seg->trbs)
  80                 return 0;
  81         /* offset in TRBs */
  82         segment_offset = trb - seg->trbs;
  83         if (segment_offset > TRBS_PER_SEGMENT)
  84                 return 0;
  85         return seg->dma + (segment_offset * sizeof(*trb));
  86 }
  87
  88 /* Does this link TRB point to the first segment in a ring,
  89  * or was the previous TRB the last TRB on the last segment in the ERST?
  90  */
  91 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  92                 struct xhci_segment *seg, union xhci_trb *trb)
  93 {
  94         if (ring == xhci->event_ring)
  95                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
  96                         (seg->next == xhci->event_ring->first_seg);
  97         else
  98                 return trb->link.control & LINK_TOGGLE;
  99 }
 100
 101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 102  * segment?  I.e. would the updated event TRB pointer step off the end of the
 103  * event seg?
 104  */
 105 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 106                 struct xhci_segment *seg, union xhci_trb *trb)
 107 {
 108         if (ring == xhci->event_ring)
 109                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 110         else
 111                 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
 112 }
 113
 114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 115  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 116  * effect the ring dequeue or enqueue pointers.
 117  */
 118 static void next_trb(struct xhci_hcd *xhci,
 119                 struct xhci_ring *ring,
 120                 struct xhci_segment **seg,
 121                 union xhci_trb **trb)
 122 {
 123         if (last_trb(xhci, ring, *seg, *trb)) {
 124                 *seg = (*seg)->next;
 125                 *trb = ((*seg)->trbs);
 126         } else {
 127                 (*trb)++;
 128         }
 129 }
 130
 131 /*
 132  * See Cycle bit rules. SW is the consumer for the event ring only.
 133  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 134  */
 135 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 136 {
 137         union xhci_trb *next = ++(ring->dequeue);
 138         unsigned long long addr;
 139
 140         ring->deq_updates++;
 141         /* Update the dequeue pointer further if that was a link TRB or we're at
 142          * the end of an event ring segment (which doesn't have link TRBS)
 143          */
 144         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 145                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 146                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 147                         if (!in_interrupt())
 148                                 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 149                                                 ring,
 150                                                 (unsigned int) ring->cycle_state);
 151                 }
 152                 ring->deq_seg = ring->deq_seg->next;
 153                 ring->dequeue = ring->deq_seg->trbs;
 154                 next = ring->dequeue;
 155         }
 156         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 157         if (ring == xhci->event_ring)
 158                 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
 159         else if (ring == xhci->cmd_ring)
 160                 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
 161         else
 162                 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
 163 }
 164
 165 /*
 166  * See Cycle bit rules. SW is the consumer for the event ring only.
 167  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 168  *
 169  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 170  * chain bit is set), then set the chain bit in all the following link TRBs.
 171  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 172  * have their chain bit cleared (so that each Link TRB is a separate TD).
 173  *
 174  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 175  * set, but other sections talk about dealing with the chain bit set.  This was
 176  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 177  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 178  */
 179 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 180 {
 181         u32 chain;
 182         union xhci_trb *next;
 183         unsigned long long addr;
 184
 185         chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
 186         next = ++(ring->enqueue);
 187
 188         ring->enq_updates++;
 189         /* Update the dequeue pointer further if that was a link TRB or we're at
 190          * the end of an event ring segment (which doesn't have link TRBS)
 191          */
 192         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 193                 if (!consumer) {
 194                         if (ring != xhci->event_ring) {
 195                                 /* If we're not dealing with 0.95 hardware,
 196                                  * carry over the chain bit of the previous TRB
 197                                  * (which may mean the chain bit is cleared).
 198                                  */
 199                                 if (!xhci_link_trb_quirk(xhci)) {
 200                                         next->link.control &= ~TRB_CHAIN;
 201                                         next->link.control |= chain;
 202                                 }
 203                                 /* Give this link TRB to the hardware */
 204                                 wmb();
 205                                 if (next->link.control & TRB_CYCLE)
 206                                         next->link.control &= (u32) ~TRB_CYCLE;
 207                                 else
 208                                         next->link.control |= (u32) TRB_CYCLE;
 209                         }
 210                         /* Toggle the cycle bit after the last ring segment. */
 211                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 212                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 213                                 if (!in_interrupt())
 214                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 215                                                         ring,
 216                                                         (unsigned int) ring->cycle_state);
 217                         }
 218                 }
 219                 ring->enq_seg = ring->enq_seg->next;
 220                 ring->enqueue = ring->enq_seg->trbs;
 221                 next = ring->enqueue;
 222         }
 223         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 224         if (ring == xhci->event_ring)
 225                 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
 226         else if (ring == xhci->cmd_ring)
 227                 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
 228         else
 229                 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
 230 }
 231
 232 /*
 233  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 234  * above.
 235  * FIXME: this would be simpler and faster if we just kept track of the number
 236  * of free TRBs in a ring.
 237  */
 238 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 239                 unsigned int num_trbs)
 240 {
 241         int i;
 242         union xhci_trb *enq = ring->enqueue;
 243         struct xhci_segment *enq_seg = ring->enq_seg;
 244         struct xhci_segment *cur_seg;
 245         unsigned int left_on_ring;
 246
 247         /* Check if ring is empty */
 248         if (enq == ring->dequeue) {
 249                 /* Can't use link trbs */
 250                 left_on_ring = TRBS_PER_SEGMENT - 1;
 251                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 252                                 cur_seg = cur_seg->next)
 253                         left_on_ring += TRBS_PER_SEGMENT - 1;
 254
 255                 /* Always need one TRB free in the ring. */
 256                 left_on_ring -= 1;
 257                 if (num_trbs > left_on_ring) {
 258                         xhci_warn(xhci, "Not enough room on ring; "
 259                                         "need %u TRBs, %u TRBs left\n",
 260                                         num_trbs, left_on_ring);
 261                         return 0;
 262                 }
 263                 return 1;
 264         }
 265         /* Make sure there's an extra empty TRB available */
 266         for (i = 0; i <= num_trbs; ++i) {
 267                 if (enq == ring->dequeue)
 268                         return 0;
 269                 enq++;
 270                 while (last_trb(xhci, ring, enq_seg, enq)) {
 271                         enq_seg = enq_seg->next;
 272                         enq = enq_seg->trbs;
 273                 }
 274         }
 275         return 1;
 276 }
 277
 278 void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
 279 {
 280         u64 temp;
 281         dma_addr_t deq;
 282
 283         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
 284                         xhci->event_ring->dequeue);
 285         if (deq == 0 && !in_interrupt())
 286                 xhci_warn(xhci, "WARN something wrong with SW event ring "
 287                                 "dequeue ptr.\n");
 288         /* Update HC event ring dequeue pointer */
 289         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
 290         temp &= ERST_PTR_MASK;
 291         /* Don't clear the EHB bit (which is RW1C) because
 292          * there might be more events to service.
 293          */
 294         temp &= ~ERST_EHB;
 295         xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");
 296         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
 297                         &xhci->ir_set->erst_dequeue);
 298 }
 299
 300 /* Ring the host controller doorbell after placing a command on the ring */
 301 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 302 {
 303         u32 temp;
 304
 305         xhci_dbg(xhci, "// Ding dong!\n");
 306         temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
 307         xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
 308         /* Flush PCI posted writes */
 309         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 310 }
 311
 312 static void ring_ep_doorbell(struct xhci_hcd *xhci,
 313                 unsigned int slot_id,
 314                 unsigned int ep_index)
 315 {
 316         struct xhci_virt_ep *ep;
 317         unsigned int ep_state;
 318         u32 field;
 319         __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 320
 321         ep = &xhci->devs[slot_id]->eps[ep_index];
 322         ep_state = ep->ep_state;
 323         /* Don't ring the doorbell for this endpoint if there are pending
 324          * cancellations because the we don't want to interrupt processing.
 325          */
 326         if (!ep->cancels_pending && !(ep_state & SET_DEQ_PENDING)
 327                         && !(ep_state & EP_HALTED)) {
 328                 field = xhci_readl(xhci, db_addr) & DB_MASK;
 329                 xhci_writel(xhci, field | EPI_TO_DB(ep_index), db_addr);
 330                 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
 331                  * isn't time-critical and we shouldn't make the CPU wait for
 332                  * the flush.
 333                  */
 334                 xhci_readl(xhci, db_addr);
 335         }
 336 }
 337
 338 /*
 339  * Find the segment that trb is in.  Start searching in start_seg.
 340  * If we must move past a segment that has a link TRB with a toggle cycle state
 341  * bit set, then we will toggle the value pointed at by cycle_state.
 342  */
 343 static struct xhci_segment *find_trb_seg(
 344                 struct xhci_segment *start_seg,
 345                 union xhci_trb  *trb, int *cycle_state)
 346 {
 347         struct xhci_segment *cur_seg = start_seg;
 348         struct xhci_generic_trb *generic_trb;
 349
 350         while (cur_seg->trbs > trb ||
 351                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 352                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 353                 if ((generic_trb->field[3] & TRB_TYPE_BITMASK) ==
 354                                 TRB_TYPE(TRB_LINK) &&
 355                                 (generic_trb->field[3] & LINK_TOGGLE))
 356                         *cycle_state = ~(*cycle_state) & 0x1;
 357                 cur_seg = cur_seg->next;
 358                 if (cur_seg == start_seg)
 359                         /* Looped over the entire list.  Oops! */
 360                         return 0;
 361         }
 362         return cur_seg;
 363 }
 364
 365 /*
 366  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 367  * Record the new state of the xHC's endpoint ring dequeue segment,
 368  * dequeue pointer, and new consumer cycle state in state.
 369  * Update our internal representation of the ring's dequeue pointer.
 370  *
 371  * We do this in three jumps:
 372  *  - First we update our new ring state to be the same as when the xHC stopped.
 373  *  - Then we traverse the ring to find the segment that contains
 374  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 375  *    any link TRBs with the toggle cycle bit set.
 376  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 377  *    if we've moved it past a link TRB with the toggle cycle bit set.
 378  */
 379 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 380                 unsigned int slot_id, unsigned int ep_index,
 381                 struct xhci_td *cur_td, struct xhci_dequeue_state *state)
 382 {
 383         struct xhci_virt_device *dev = xhci->devs[slot_id];
 384         struct xhci_ring *ep_ring = dev->eps[ep_index].ring;
 385         struct xhci_generic_trb *trb;
 386         struct xhci_ep_ctx *ep_ctx;
 387         dma_addr_t addr;
 388
 389         state->new_cycle_state = 0;
 390         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 391         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 392                         dev->eps[ep_index].stopped_trb,
 393                         &state->new_cycle_state);
 394         if (!state->new_deq_seg) {
 395                 WARN_ON(1);
 396                 return;
 397         }
 398
 399         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 400         xhci_dbg(xhci, "Finding endpoint context\n");
 401         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 402         state->new_cycle_state = 0x1 & ep_ctx->deq;
 403
 404         state->new_deq_ptr = cur_td->last_trb;
 405         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 406         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 407                         state->new_deq_ptr,
 408                         &state->new_cycle_state);
 409         if (!state->new_deq_seg) {
 410                 WARN_ON(1);
 411                 return;
 412         }
 413
 414         trb = &state->new_deq_ptr->generic;
 415         if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) &&
 416                                 (trb->field[3] & LINK_TOGGLE))
 417                 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
 418         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 419
 420         /* Don't update the ring cycle state for the producer (us). */
 421         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 422                         state->new_deq_seg);
 423         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 424         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 425                         (unsigned long long) addr);
 426         xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
 427         ep_ring->dequeue = state->new_deq_ptr;
 428         ep_ring->deq_seg = state->new_deq_seg;
 429 }
 430
 431 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 432                 struct xhci_td *cur_td)
 433 {
 434         struct xhci_segment *cur_seg;
 435         union xhci_trb *cur_trb;
 436
 437         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 438                         true;
 439                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 440                 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
 441                                 TRB_TYPE(TRB_LINK)) {
 442                         /* Unchain any chained Link TRBs, but
 443                          * leave the pointers intact.
 444                          */
 445                         cur_trb->generic.field[3] &= ~TRB_CHAIN;
 446                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 447                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 448                                         "in seg %p (0x%llx dma)\n",
 449                                         cur_trb,
 450                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 451                                         cur_seg,
 452                                         (unsigned long long)cur_seg->dma);
 453                 } else {
 454                         cur_trb->generic.field[0] = 0;
 455                         cur_trb->generic.field[1] = 0;
 456                         cur_trb->generic.field[2] = 0;
 457                         /* Preserve only the cycle bit of this TRB */
 458                         cur_trb->generic.field[3] &= TRB_CYCLE;
 459                         cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
 460                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 461                                         "in seg %p (0x%llx dma)\n",
 462                                         cur_trb,
 463                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 464                                         cur_seg,
 465                                         (unsigned long long)cur_seg->dma);
 466                 }
 467                 if (cur_trb == cur_td->last_trb)
 468                         break;
 469         }
 470 }
 471
 472 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 473                 unsigned int ep_index, struct xhci_segment *deq_seg,
 474                 union xhci_trb *deq_ptr, u32 cycle_state);
 475
 476 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 477                 unsigned int slot_id, unsigned int ep_index,
 478                 struct xhci_dequeue_state *deq_state)
 479 {
 480         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 481
 482         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 483                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 484                         deq_state->new_deq_seg,
 485                         (unsigned long long)deq_state->new_deq_seg->dma,
 486                         deq_state->new_deq_ptr,
 487                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 488                         deq_state->new_cycle_state);
 489         queue_set_tr_deq(xhci, slot_id, ep_index,
 490                         deq_state->new_deq_seg,
 491                         deq_state->new_deq_ptr,
 492                         (u32) deq_state->new_cycle_state);
 493         /* Stop the TD queueing code from ringing the doorbell until
 494          * this command completes.  The HC won't set the dequeue pointer
 495          * if the ring is running, and ringing the doorbell starts the
 496          * ring running.
 497          */
 498         ep->ep_state |= SET_DEQ_PENDING;
 499 }
 500
 501 /*
 502  * When we get a command completion for a Stop Endpoint Command, we need to
 503  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 504  *
 505  *  1. If the HW was in the middle of processing the TD that needs to be
 506  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 507  *     in the TD with a Set Dequeue Pointer Command.
 508  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 509  *     bit cleared) so that the HW will skip over them.
 510  */
 511 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 512                 union xhci_trb *trb)
 513 {
 514         unsigned int slot_id;
 515         unsigned int ep_index;
 516         struct xhci_ring *ep_ring;
 517         struct xhci_virt_ep *ep;
 518         struct list_head *entry;
 519         struct xhci_td *cur_td = 0;
 520         struct xhci_td *last_unlinked_td;
 521
 522         struct xhci_dequeue_state deq_state;
 523 #ifdef CONFIG_USB_HCD_STAT
 524         ktime_t stop_time = ktime_get();
 525 #endif
 526
 527         memset(&deq_state, 0, sizeof(deq_state));
 528         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 529         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 530         ep = &xhci->devs[slot_id]->eps[ep_index];
 531         ep_ring = ep->ring;
 532
 533         if (list_empty(&ep->cancelled_td_list))
 534                 return;
 535
 536         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 537          * We have the xHCI lock, so nothing can modify this list until we drop
 538          * it.  We're also in the event handler, so we can't get re-interrupted
 539          * if another Stop Endpoint command completes
 540          */
 541         list_for_each(entry, &ep->cancelled_td_list) {
 542                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 543                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 544                                 cur_td->first_trb,
 545                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 546                 /*
 547                  * If we stopped on the TD we need to cancel, then we have to
 548                  * move the xHC endpoint ring dequeue pointer past this TD.
 549                  */
 550                 if (cur_td == ep->stopped_td)
 551                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index, cur_td,
 552                                         &deq_state);
 553                 else
 554                         td_to_noop(xhci, ep_ring, cur_td);
 555                 /*
 556                  * The event handler won't see a completion for this TD anymore,
 557                  * so remove it from the endpoint ring's TD list.  Keep it in
 558                  * the cancelled TD list for URB completion later.
 559                  */
 560                 list_del(&cur_td->td_list);
 561                 ep->cancels_pending--;
 562         }
 563         last_unlinked_td = cur_td;
 564
 565         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 566         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 567                 xhci_queue_new_dequeue_state(xhci,
 568                                 slot_id, ep_index, &deq_state);
 569                 xhci_ring_cmd_db(xhci);
 570         } else {
 571                 /* Otherwise just ring the doorbell to restart the ring */
 572                 ring_ep_doorbell(xhci, slot_id, ep_index);
 573         }
 574         ep->stopped_td = NULL;
 575         ep->stopped_trb = NULL;
 576
 577         /*
 578          * Drop the lock and complete the URBs in the cancelled TD list.
 579          * New TDs to be cancelled might be added to the end of the list before
 580          * we can complete all the URBs for the TDs we already unlinked.
 581          * So stop when we've completed the URB for the last TD we unlinked.
 582          */
 583         do {
 584                 cur_td = list_entry(ep->cancelled_td_list.next,
 585                                 struct xhci_td, cancelled_td_list);
 586                 list_del(&cur_td->cancelled_td_list);
 587
 588                 /* Clean up the cancelled URB */
 589 #ifdef CONFIG_USB_HCD_STAT
 590                 hcd_stat_update(xhci->tp_stat, cur_td->urb->actual_length,
 591                                 ktime_sub(stop_time, cur_td->start_time));
 592 #endif
 593                 cur_td->urb->hcpriv = NULL;
 594                 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), cur_td->urb);
 595
 596                 xhci_dbg(xhci, "Giveback cancelled URB %p\n", cur_td->urb);
 597                 spin_unlock(&xhci->lock);
 598                 /* Doesn't matter what we pass for status, since the core will
 599                  * just overwrite it (because the URB has been unlinked).
 600                  */
 601                 usb_hcd_giveback_urb(xhci_to_hcd(xhci), cur_td->urb, 0);
 602                 kfree(cur_td);
 603
 604                 spin_lock(&xhci->lock);
 605         } while (cur_td != last_unlinked_td);
 606
 607         /* Return to the event handler with xhci->lock re-acquired */
 608 }
 609
 610 /*
 611  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 612  * we need to clear the set deq pending flag in the endpoint ring state, so that
 613  * the TD queueing code can ring the doorbell again.  We also need to ring the
 614  * endpoint doorbell to restart the ring, but only if there aren't more
 615  * cancellations pending.
 616  */
 617 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 618                 struct xhci_event_cmd *event,
 619                 union xhci_trb *trb)
 620 {
 621         unsigned int slot_id;
 622         unsigned int ep_index;
 623         struct xhci_ring *ep_ring;
 624         struct xhci_virt_device *dev;
 625         struct xhci_ep_ctx *ep_ctx;
 626         struct xhci_slot_ctx *slot_ctx;
 627
 628         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 629         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 630         dev = xhci->devs[slot_id];
 631         ep_ring = dev->eps[ep_index].ring;
 632         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 633         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 634
 635         if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
 636                 unsigned int ep_state;
 637                 unsigned int slot_state;
 638
 639                 switch (GET_COMP_CODE(event->status)) {
 640                 case COMP_TRB_ERR:
 641                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 642                                         "of stream ID configuration\n");
 643                         break;
 644                 case COMP_CTX_STATE:
 645                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 646                                         "to incorrect slot or ep state.\n");
 647                         ep_state = ep_ctx->ep_info;
 648                         ep_state &= EP_STATE_MASK;
 649                         slot_state = slot_ctx->dev_state;
 650                         slot_state = GET_SLOT_STATE(slot_state);
 651                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 652                                         slot_state, ep_state);
 653                         break;
 654                 case COMP_EBADSLT:
 655                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 656                                         "slot %u was not enabled.\n", slot_id);
 657                         break;
 658                 default:
 659                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 660                                         "completion code of %u.\n",
 661                                         GET_COMP_CODE(event->status));
 662                         break;
 663                 }
 664                 /* OK what do we do now?  The endpoint state is hosed, and we
 665                  * should never get to this point if the synchronization between
 666                  * queueing, and endpoint state are correct.  This might happen
 667                  * if the device gets disconnected after we've finished
 668                  * cancelling URBs, which might not be an error...
 669                  */
 670         } else {
 671                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 672                                 ep_ctx->deq);
 673         }
 674
 675         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 676         ring_ep_doorbell(xhci, slot_id, ep_index);
 677 }
 678
 679 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
 680                 struct xhci_event_cmd *event,
 681                 union xhci_trb *trb)
 682 {
 683         int slot_id;
 684         unsigned int ep_index;
 685         struct xhci_ring *ep_ring;
 686
 687         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 688         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 689         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
 690         /* This command will only fail if the endpoint wasn't halted,
 691          * but we don't care.
 692          */
 693         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
 694                         (unsigned int) GET_COMP_CODE(event->status));
 695
 696         /* HW with the reset endpoint quirk needs to have a configure endpoint
 697          * command complete before the endpoint can be used.  Queue that here
 698          * because the HW can't handle two commands being queued in a row.
 699          */
 700         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
 701                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
 702                 xhci_queue_configure_endpoint(xhci,
 703                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
 704                                 false);
 705                 xhci_ring_cmd_db(xhci);
 706         } else {
 707                 /* Clear our internal halted state and restart the ring */
 708                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
 709                 ring_ep_doorbell(xhci, slot_id, ep_index);
 710         }
 711 }
 712
 713 /* Check to see if a command in the device's command queue matches this one.
 714  * Signal the completion or free the command, and return 1.  Return 0 if the
 715  * completed command isn't at the head of the command list.
 716  */
 717 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
 718                 struct xhci_virt_device *virt_dev,
 719                 struct xhci_event_cmd *event)
 720 {
 721         struct xhci_command *command;
 722
 723         if (list_empty(&virt_dev->cmd_list))
 724                 return 0;
 725
 726         command = list_entry(virt_dev->cmd_list.next,
 727                         struct xhci_command, cmd_list);
 728         if (xhci->cmd_ring->dequeue != command->command_trb)
 729                 return 0;
 730
 731         command->status =
 732                 GET_COMP_CODE(event->status);
 733         list_del(&command->cmd_list);
 734         if (command->completion)
 735                 complete(command->completion);
 736         else
 737                 xhci_free_command(xhci, command);
 738         return 1;
 739 }
 740
 741 static void handle_cmd_completion(struct xhci_hcd *xhci,
 742                 struct xhci_event_cmd *event)
 743 {
 744         int slot_id = TRB_TO_SLOT_ID(event->flags);
 745         u64 cmd_dma;
 746         dma_addr_t cmd_dequeue_dma;
 747         struct xhci_input_control_ctx *ctrl_ctx;
 748         struct xhci_virt_device *virt_dev;
 749         unsigned int ep_index;
 750         struct xhci_ring *ep_ring;
 751         unsigned int ep_state;
 752
 753         cmd_dma = event->cmd_trb;
 754         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
 755                         xhci->cmd_ring->dequeue);
 756         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
 757         if (cmd_dequeue_dma == 0) {
 758                 xhci->error_bitmask |= 1 << 4;
 759                 return;
 760         }
 761         /* Does the DMA address match our internal dequeue pointer address? */
 762         if (cmd_dma != (u64) cmd_dequeue_dma) {
 763                 xhci->error_bitmask |= 1 << 5;
 764                 return;
 765         }
 766         switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
 767         case TRB_TYPE(TRB_ENABLE_SLOT):
 768                 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
 769                         xhci->slot_id = slot_id;
 770                 else
 771                         xhci->slot_id = 0;
 772                 complete(&xhci->addr_dev);
 773                 break;
 774         case TRB_TYPE(TRB_DISABLE_SLOT):
 775                 if (xhci->devs[slot_id])
 776                         xhci_free_virt_device(xhci, slot_id);
 777                 break;
 778         case TRB_TYPE(TRB_CONFIG_EP):
 779                 virt_dev = xhci->devs[slot_id];
 780                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
 781                         break;
 782                 /*
 783                  * Configure endpoint commands can come from the USB core
 784                  * configuration or alt setting changes, or because the HW
 785                  * needed an extra configure endpoint command after a reset
 786                  * endpoint command.  In the latter case, the xHCI driver is
 787                  * not waiting on the configure endpoint command.
 788                  */
 789                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
 790                                 virt_dev->in_ctx);
 791                 /* Input ctx add_flags are the endpoint index plus one */
 792                 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
 793                 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
 794                 if (!ep_ring) {
 795                         /* This must have been an initial configure endpoint */
 796                         xhci->devs[slot_id]->cmd_status =
 797                                 GET_COMP_CODE(event->status);
 798                         complete(&xhci->devs[slot_id]->cmd_completion);
 799                         break;
 800                 }
 801                 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
 802                 xhci_dbg(xhci, "Completed config ep cmd - last ep index = %d, "
 803                                 "state = %d\n", ep_index, ep_state);
 804                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
 805                                 ep_state & EP_HALTED) {
 806                         /* Clear our internal halted state and restart ring */
 807                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
 808                                 ~EP_HALTED;
 809                         ring_ep_doorbell(xhci, slot_id, ep_index);
 810                 } else {
 811                         xhci->devs[slot_id]->cmd_status =
 812                                 GET_COMP_CODE(event->status);
 813                         complete(&xhci->devs[slot_id]->cmd_completion);
 814                 }
 815                 break;
 816         case TRB_TYPE(TRB_EVAL_CONTEXT):
 817                 virt_dev = xhci->devs[slot_id];
 818                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
 819                         break;
 820                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
 821                 complete(&xhci->devs[slot_id]->cmd_completion);
 822                 break;
 823         case TRB_TYPE(TRB_ADDR_DEV):
 824                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
 825                 complete(&xhci->addr_dev);
 826                 break;
 827         case TRB_TYPE(TRB_STOP_RING):
 828                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
 829                 break;
 830         case TRB_TYPE(TRB_SET_DEQ):
 831                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
 832                 break;
 833         case TRB_TYPE(TRB_CMD_NOOP):
 834                 ++xhci->noops_handled;
 835                 break;
 836         case TRB_TYPE(TRB_RESET_EP):
 837                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
 838                 break;
 839         default:
 840                 /* Skip over unknown commands on the event ring */
 841                 xhci->error_bitmask |= 1 << 6;
 842                 break;
 843         }
 844         inc_deq(xhci, xhci->cmd_ring, false);
 845 }
 846
 847 static void handle_port_status(struct xhci_hcd *xhci,
 848                 union xhci_trb *event)
 849 {
 850         u32 port_id;
 851
 852         /* Port status change events always have a successful completion code */
 853         if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
 854                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
 855                 xhci->error_bitmask |= 1 << 8;
 856         }
 857         /* FIXME: core doesn't care about all port link state changes yet */
 858         port_id = GET_PORT_ID(event->generic.field[0]);
 859         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
 860
 861         /* Update event ring dequeue pointer before dropping the lock */
 862         inc_deq(xhci, xhci->event_ring, true);
 863         xhci_set_hc_event_deq(xhci);
 864
 865         spin_unlock(&xhci->lock);
 866         /* Pass this up to the core */
 867         usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
 868         spin_lock(&xhci->lock);
 869 }
 870
 871 /*
 872  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
 873  * at end_trb, which may be in another segment.  If the suspect DMA address is a
 874  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
 875  * returns 0.
 876  */
 877 static struct xhci_segment *trb_in_td(
 878                 struct xhci_segment *start_seg,
 879                 union xhci_trb  *start_trb,
 880                 union xhci_trb  *end_trb,
 881                 dma_addr_t      suspect_dma)
 882 {
 883         dma_addr_t start_dma;
 884         dma_addr_t end_seg_dma;
 885         dma_addr_t end_trb_dma;
 886         struct xhci_segment *cur_seg;
 887
 888         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
 889         cur_seg = start_seg;
 890
 891         do {
 892                 if (start_dma == 0)
 893                         return 0;
 894                 /* We may get an event for a Link TRB in the middle of a TD */
 895                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
 896                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
 897                 /* If the end TRB isn't in this segment, this is set to 0 */
 898                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
 899
 900                 if (end_trb_dma > 0) {
 901                         /* The end TRB is in this segment, so suspect should be here */
 902                         if (start_dma <= end_trb_dma) {
 903                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
 904                                         return cur_seg;
 905                         } else {
 906                                 /* Case for one segment with
 907                                  * a TD wrapped around to the top
 908                                  */
 909                                 if ((suspect_dma >= start_dma &&
 910                                                         suspect_dma <= end_seg_dma) ||
 911                                                 (suspect_dma >= cur_seg->dma &&
 912                                                  suspect_dma <= end_trb_dma))
 913                                         return cur_seg;
 914                         }
 915                         return 0;
 916                 } else {
 917                         /* Might still be somewhere in this segment */
 918                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
 919                                 return cur_seg;
 920                 }
 921                 cur_seg = cur_seg->next;
 922                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
 923         } while (cur_seg != start_seg);
 924
 925         return 0;
 926 }
 927
 928 /*
 929  * If this function returns an error condition, it means it got a Transfer
 930  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
 931  * At this point, the host controller is probably hosed and should be reset.
 932  */
 933 static int handle_tx_event(struct xhci_hcd *xhci,
 934                 struct xhci_transfer_event *event)
 935 {
 936         struct xhci_virt_device *xdev;
 937         struct xhci_virt_ep *ep;
 938         struct xhci_ring *ep_ring;
 939         unsigned int slot_id;
 940         int ep_index;
 941         struct xhci_td *td = 0;
 942         dma_addr_t event_dma;
 943         struct xhci_segment *event_seg;
 944         union xhci_trb *event_trb;
 945         struct urb *urb = 0;
 946         int status = -EINPROGRESS;
 947         struct xhci_ep_ctx *ep_ctx;
 948         u32 trb_comp_code;
 949
 950         xhci_dbg(xhci, "In %s\n", __func__);
 951         slot_id = TRB_TO_SLOT_ID(event->flags);
 952         xdev = xhci->devs[slot_id];
 953         if (!xdev) {
 954                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
 955                 return -ENODEV;
 956         }
 957
 958         /* Endpoint ID is 1 based, our index is zero based */
 959         ep_index = TRB_TO_EP_ID(event->flags) - 1;
 960         xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
 961         ep = &xdev->eps[ep_index];
 962         ep_ring = ep->ring;
 963         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
 964         if (!ep_ring || (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
 965                 xhci_err(xhci, "ERROR Transfer event pointed to disabled endpoint\n");
 966                 return -ENODEV;
 967         }
 968
 969         event_dma = event->buffer;
 970         /* This TRB should be in the TD at the head of this ring's TD list */
 971         xhci_dbg(xhci, "%s - checking for list empty\n", __func__);
 972         if (list_empty(&ep_ring->td_list)) {
 973                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
 974                                 TRB_TO_SLOT_ID(event->flags), ep_index);
 975                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
 976                                 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
 977                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
 978                 urb = NULL;
 979                 goto cleanup;
 980         }
 981         xhci_dbg(xhci, "%s - getting list entry\n", __func__);
 982         td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
 983
 984         /* Is this a TRB in the currently executing TD? */
 985         xhci_dbg(xhci, "%s - looking for TD\n", __func__);
 986         event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
 987                         td->last_trb, event_dma);
 988         xhci_dbg(xhci, "%s - found event_seg = %p\n", __func__, event_seg);
 989         if (!event_seg) {
 990                 /* HC is busted, give up! */
 991                 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
 992                 return -ESHUTDOWN;
 993         }
 994         event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / sizeof(*event_trb)];
 995         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
 996                         (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
 997         xhci_dbg(xhci, "Offset 0x00 (buffer lo) = 0x%x\n",
 998                         lower_32_bits(event->buffer));
 999         xhci_dbg(xhci, "Offset 0x04 (buffer hi) = 0x%x\n",
1000                         upper_32_bits(event->buffer));
1001         xhci_dbg(xhci, "Offset 0x08 (transfer length) = 0x%x\n",
1002                         (unsigned int) event->transfer_len);
1003         xhci_dbg(xhci, "Offset 0x0C (flags) = 0x%x\n",
1004                         (unsigned int) event->flags);
1005
1006         /* Look for common error cases */
1007         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1008         switch (trb_comp_code) {
1009         /* Skip codes that require special handling depending on
1010          * transfer type
1011          */
1012         case COMP_SUCCESS:
1013         case COMP_SHORT_TX:
1014                 break;
1015         case COMP_STOP:
1016                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1017                 break;
1018         case COMP_STOP_INVAL:
1019                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1020                 break;
1021         case COMP_STALL:
1022                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1023                 ep->ep_state |= EP_HALTED;
1024                 status = -EPIPE;
1025                 break;
1026         case COMP_TRB_ERR:
1027                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1028                 status = -EILSEQ;
1029                 break;
1030         case COMP_TX_ERR:
1031                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1032                 status = -EPROTO;
1033                 break;
1034         case COMP_BABBLE:
1035                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1036                 status = -EOVERFLOW;
1037                 break;
1038         case COMP_DB_ERR:
1039                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1040                 status = -ENOSR;
1041                 break;
1042         default:
1043                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably busted\n");
1044                 urb = NULL;
1045                 goto cleanup;
1046         }
1047         /* Now update the urb's actual_length and give back to the core */
1048         /* Was this a control transfer? */
1049         if (usb_endpoint_xfer_control(&td->urb->ep->desc)) {
1050                 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1051                 switch (trb_comp_code) {
1052                 case COMP_SUCCESS:
1053                         if (event_trb == ep_ring->dequeue) {
1054                                 xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n");
1055                                 status = -ESHUTDOWN;
1056                         } else if (event_trb != td->last_trb) {
1057                                 xhci_warn(xhci, "WARN: Success on ctrl data TRB without IOC set??\n");
1058                                 status = -ESHUTDOWN;
1059                         } else {
1060                                 xhci_dbg(xhci, "Successful control transfer!\n");
1061                                 status = 0;
1062                         }
1063                         break;
1064                 case COMP_SHORT_TX:
1065                         xhci_warn(xhci, "WARN: short transfer on control ep\n");
1066                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1067                                 status = -EREMOTEIO;
1068                         else
1069                                 status = 0;
1070                         break;
1071                 case COMP_BABBLE:
1072                         /* The 0.96 spec says a babbling control endpoint
1073                          * is not halted. The 0.96 spec says it is.  Some HW
1074                          * claims to be 0.95 compliant, but it halts the control
1075                          * endpoint anyway.  Check if a babble halted the
1076                          * endpoint.
1077                          */
1078                         if (ep_ctx->ep_info != EP_STATE_HALTED)
1079                                 break;
1080                         /* else fall through */
1081                 case COMP_STALL:
1082                         /* Did we transfer part of the data (middle) phase? */
1083                         if (event_trb != ep_ring->dequeue &&
1084                                         event_trb != td->last_trb)
1085                                 td->urb->actual_length =
1086                                         td->urb->transfer_buffer_length
1087                                         - TRB_LEN(event->transfer_len);
1088                         else
1089                                 td->urb->actual_length = 0;
1090
1091                         ep->stopped_td = td;
1092                         ep->stopped_trb = event_trb;
1093
1094                         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1095                         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1096
1097                         ep->stopped_td = NULL;
1098                         ep->stopped_trb = NULL;
1099
1100                         xhci_ring_cmd_db(xhci);
1101                         goto td_cleanup;
1102                 default:
1103                         /* Others already handled above */
1104                         break;
1105                 }
1106                 /*
1107                  * Did we transfer any data, despite the errors that might have
1108                  * happened?  I.e. did we get past the setup stage?
1109                  */
1110                 if (event_trb != ep_ring->dequeue) {
1111                         /* The event was for the status stage */
1112                         if (event_trb == td->last_trb) {
1113                                 if (td->urb->actual_length != 0) {
1114                                         /* Don't overwrite a previously set error code */
1115                                         if ((status == -EINPROGRESS ||
1116                                                                 status == 0) &&
1117                                                         (td->urb->transfer_flags
1118                                                          & URB_SHORT_NOT_OK))
1119                                                 /* Did we already see a short data stage? */
1120                                                 status = -EREMOTEIO;
1121                                 } else {
1122                                         td->urb->actual_length =
1123                                                 td->urb->transfer_buffer_length;
1124                                 }
1125                         } else {
1126                         /* Maybe the event was for the data stage? */
1127                                 if (trb_comp_code != COMP_STOP_INVAL) {
1128                                         /* We didn't stop on a link TRB in the middle */
1129                                         td->urb->actual_length =
1130                                                 td->urb->transfer_buffer_length -
1131                                                 TRB_LEN(event->transfer_len);
1132                                         xhci_dbg(xhci, "Waiting for status stage event\n");
1133                                         urb = NULL;
1134                                         goto cleanup;
1135                                 }
1136                         }
1137                 }
1138         } else {
1139                 switch (trb_comp_code) {
1140                 case COMP_SUCCESS:
1141                         /* Double check that the HW transferred everything. */
1142                         if (event_trb != td->last_trb) {
1143                                 xhci_warn(xhci, "WARN Successful completion "
1144                                                 "on short TX\n");
1145                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1146                                         status = -EREMOTEIO;
1147                                 else
1148                                         status = 0;
1149                         } else {
1150                                 if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1151                                         xhci_dbg(xhci, "Successful bulk "
1152                                                         "transfer!\n");
1153                                 else
1154                                         xhci_dbg(xhci, "Successful interrupt "
1155                                                         "transfer!\n");
1156                                 status = 0;
1157                         }
1158                         break;
1159                 case COMP_SHORT_TX:
1160                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1161                                 status = -EREMOTEIO;
1162                         else
1163                                 status = 0;
1164                         break;
1165                 default:
1166                         /* Others already handled above */
1167                         break;
1168                 }
1169                 dev_dbg(&td->urb->dev->dev,
1170                                 "ep %#x - asked for %d bytes, "
1171                                 "%d bytes untransferred\n",
1172                                 td->urb->ep->desc.bEndpointAddress,
1173                                 td->urb->transfer_buffer_length,
1174                                 TRB_LEN(event->transfer_len));
1175                 /* Fast path - was this the last TRB in the TD for this URB? */
1176                 if (event_trb == td->last_trb) {
1177                         if (TRB_LEN(event->transfer_len) != 0) {
1178                                 td->urb->actual_length =
1179                                         td->urb->transfer_buffer_length -
1180                                         TRB_LEN(event->transfer_len);
1181                                 if (td->urb->transfer_buffer_length <
1182                                                 td->urb->actual_length) {
1183                                         xhci_warn(xhci, "HC gave bad length "
1184                                                         "of %d bytes left\n",
1185                                                         TRB_LEN(event->transfer_len));
1186                                         td->urb->actual_length = 0;
1187                                         if (td->urb->transfer_flags &
1188                                                         URB_SHORT_NOT_OK)
1189                                                 status = -EREMOTEIO;
1190                                         else
1191                                                 status = 0;
1192                                 }
1193                                 /* Don't overwrite a previously set error code */
1194                                 if (status == -EINPROGRESS) {
1195                                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1196                                                 status = -EREMOTEIO;
1197                                         else
1198                                                 status = 0;
1199                                 }
1200                         } else {
1201                                 td->urb->actual_length = td->urb->transfer_buffer_length;
1202                                 /* Ignore a short packet completion if the
1203                                  * untransferred length was zero.
1204                                  */
1205                                 if (status == -EREMOTEIO)
1206                                         status = 0;
1207                         }
1208                 } else {
1209                         /* Slow path - walk the list, starting from the dequeue
1210                          * pointer, to get the actual length transferred.
1211                          */
1212                         union xhci_trb *cur_trb;
1213                         struct xhci_segment *cur_seg;
1214
1215                         td->urb->actual_length = 0;
1216                         for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1217                                         cur_trb != event_trb;
1218                                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1219                                 if ((cur_trb->generic.field[3] &
1220                                  TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1221                                     (cur_trb->generic.field[3] &
1222                                  TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1223                                         td->urb->actual_length +=
1224                                                 TRB_LEN(cur_trb->generic.field[2]);
1225                         }
1226                         /* If the ring didn't stop on a Link or No-op TRB, add
1227                          * in the actual bytes transferred from the Normal TRB
1228                          */
1229                         if (trb_comp_code != COMP_STOP_INVAL)
1230                                 td->urb->actual_length +=
1231                                         TRB_LEN(cur_trb->generic.field[2]) -
1232                                         TRB_LEN(event->transfer_len);
1233                 }
1234         }
1235         if (trb_comp_code == COMP_STOP_INVAL ||
1236                         trb_comp_code == COMP_STOP) {
1237                 /* The Endpoint Stop Command completion will take care of any
1238                  * stopped TDs.  A stopped TD may be restarted, so don't update
1239                  * the ring dequeue pointer or take this TD off any lists yet.
1240                  */
1241                 ep->stopped_td = td;
1242                 ep->stopped_trb = event_trb;
1243         } else {
1244                 if (trb_comp_code == COMP_STALL ||
1245                                 trb_comp_code == COMP_BABBLE) {
1246                         /* The transfer is completed from the driver's
1247                          * perspective, but we need to issue a set dequeue
1248                          * command for this stalled endpoint to move the dequeue
1249                          * pointer past the TD.  We can't do that here because
1250                          * the halt condition must be cleared first.
1251                          */
1252                         ep->stopped_td = td;
1253                         ep->stopped_trb = event_trb;
1254                 } else {
1255                         /* Update ring dequeue pointer */
1256                         while (ep_ring->dequeue != td->last_trb)
1257                                 inc_deq(xhci, ep_ring, false);
1258                         inc_deq(xhci, ep_ring, false);
1259                 }
1260
1261 td_cleanup:
1262                 /* Clean up the endpoint's TD list */
1263                 urb = td->urb;
1264                 /* Do one last check of the actual transfer length.
1265                  * If the host controller said we transferred more data than
1266                  * the buffer length, urb->actual_length will be a very big
1267                  * number (since it's unsigned).  Play it safe and say we didn't
1268                  * transfer anything.
1269                  */
1270                 if (urb->actual_length > urb->transfer_buffer_length) {
1271                         xhci_warn(xhci, "URB transfer length is wrong, "
1272                                         "xHC issue? req. len = %u, "
1273                                         "act. len = %u\n",
1274                                         urb->transfer_buffer_length,
1275                                         urb->actual_length);
1276                         urb->actual_length = 0;
1277                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1278                                 status = -EREMOTEIO;
1279                         else
1280                                 status = 0;
1281                 }
1282                 list_del(&td->td_list);
1283                 /* Was this TD slated to be cancelled but completed anyway? */
1284                 if (!list_empty(&td->cancelled_td_list)) {
1285                         list_del(&td->cancelled_td_list);
1286                         ep->cancels_pending--;
1287                 }
1288                 /* Leave the TD around for the reset endpoint function to use
1289                  * (but only if it's not a control endpoint, since we already
1290                  * queued the Set TR dequeue pointer command for stalled
1291                  * control endpoints).
1292                  */
1293                 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1294                         (trb_comp_code != COMP_STALL &&
1295                                 trb_comp_code != COMP_BABBLE)) {
1296                         kfree(td);
1297                 }
1298                 urb->hcpriv = NULL;
1299         }
1300 cleanup:
1301         inc_deq(xhci, xhci->event_ring, true);
1302         xhci_set_hc_event_deq(xhci);
1303
1304         /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1305         if (urb) {
1306                 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1307                 xhci_dbg(xhci, "Giveback URB %p, len = %d, status = %d\n",
1308                                 urb, urb->actual_length, status);
1309                 spin_unlock(&xhci->lock);
1310                 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1311                 spin_lock(&xhci->lock);
1312         }
1313         return 0;
1314 }
1315
1316 /*
1317  * This function handles all OS-owned events on the event ring.  It may drop
1318  * xhci->lock between event processing (e.g. to pass up port status changes).
1319  */
1320 void xhci_handle_event(struct xhci_hcd *xhci)
1321 {
1322         union xhci_trb *event;
1323         int update_ptrs = 1;
1324         int ret;
1325
1326         xhci_dbg(xhci, "In %s\n", __func__);
1327         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1328                 xhci->error_bitmask |= 1 << 1;
1329                 return;
1330         }
1331
1332         event = xhci->event_ring->dequeue;
1333         /* Does the HC or OS own the TRB? */
1334         if ((event->event_cmd.flags & TRB_CYCLE) !=
1335                         xhci->event_ring->cycle_state) {
1336                 xhci->error_bitmask |= 1 << 2;
1337                 return;
1338         }
1339         xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1340
1341         /* FIXME: Handle more event types. */
1342         switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1343         case TRB_TYPE(TRB_COMPLETION):
1344                 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1345                 handle_cmd_completion(xhci, &event->event_cmd);
1346                 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1347                 break;
1348         case TRB_TYPE(TRB_PORT_STATUS):
1349                 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1350                 handle_port_status(xhci, event);
1351                 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1352                 update_ptrs = 0;
1353                 break;
1354         case TRB_TYPE(TRB_TRANSFER):
1355                 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
1356                 ret = handle_tx_event(xhci, &event->trans_event);
1357                 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
1358                 if (ret < 0)
1359                         xhci->error_bitmask |= 1 << 9;
1360                 else
1361                         update_ptrs = 0;
1362                 break;
1363         default:
1364                 xhci->error_bitmask |= 1 << 3;
1365         }
1366
1367         if (update_ptrs) {
1368                 /* Update SW and HC event ring dequeue pointer */
1369                 inc_deq(xhci, xhci->event_ring, true);
1370                 xhci_set_hc_event_deq(xhci);
1371         }
1372         /* Are there more items on the event ring? */
1373         xhci_handle_event(xhci);
1374 }
1375
1376 /****           Endpoint Ring Operations        ****/
1377
1378 /*
1379  * Generic function for queueing a TRB on a ring.
1380  * The caller must have checked to make sure there's room on the ring.
1381  */
1382 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
1383                 bool consumer,
1384                 u32 field1, u32 field2, u32 field3, u32 field4)
1385 {
1386         struct xhci_generic_trb *trb;
1387
1388         trb = &ring->enqueue->generic;
1389         trb->field[0] = field1;
1390         trb->field[1] = field2;
1391         trb->field[2] = field3;
1392         trb->field[3] = field4;
1393         inc_enq(xhci, ring, consumer);
1394 }
1395
1396 /*
1397  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1398  * FIXME allocate segments if the ring is full.
1399  */
1400 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
1401                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
1402 {
1403         /* Make sure the endpoint has been added to xHC schedule */
1404         xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
1405         switch (ep_state) {
1406         case EP_STATE_DISABLED:
1407                 /*
1408                  * USB core changed config/interfaces without notifying us,
1409                  * or hardware is reporting the wrong state.
1410                  */
1411                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
1412                 return -ENOENT;
1413         case EP_STATE_ERROR:
1414                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
1415                 /* FIXME event handling code for error needs to clear it */
1416                 /* XXX not sure if this should be -ENOENT or not */
1417                 return -EINVAL;
1418         case EP_STATE_HALTED:
1419                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
1420         case EP_STATE_STOPPED:
1421         case EP_STATE_RUNNING:
1422                 break;
1423         default:
1424                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
1425                 /*
1426                  * FIXME issue Configure Endpoint command to try to get the HC
1427                  * back into a known state.
1428                  */
1429                 return -EINVAL;
1430         }
1431         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
1432                 /* FIXME allocate more room */
1433                 xhci_err(xhci, "ERROR no room on ep ring\n");
1434                 return -ENOMEM;
1435         }
1436         return 0;
1437 }
1438
1439 static int prepare_transfer(struct xhci_hcd *xhci,
1440                 struct xhci_virt_device *xdev,
1441                 unsigned int ep_index,
1442                 unsigned int num_trbs,
1443                 struct urb *urb,
1444                 struct xhci_td **td,
1445                 gfp_t mem_flags)
1446 {
1447         int ret;
1448         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1449         ret = prepare_ring(xhci, xdev->eps[ep_index].ring,
1450                         ep_ctx->ep_info & EP_STATE_MASK,
1451                         num_trbs, mem_flags);
1452         if (ret)
1453                 return ret;
1454         *td = kzalloc(sizeof(struct xhci_td), mem_flags);
1455         if (!*td)
1456                 return -ENOMEM;
1457         INIT_LIST_HEAD(&(*td)->td_list);
1458         INIT_LIST_HEAD(&(*td)->cancelled_td_list);
1459
1460         ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
1461         if (unlikely(ret)) {
1462                 kfree(*td);
1463                 return ret;
1464         }
1465
1466         (*td)->urb = urb;
1467         urb->hcpriv = (void *) (*td);
1468         /* Add this TD to the tail of the endpoint ring's TD list */
1469         list_add_tail(&(*td)->td_list, &xdev->eps[ep_index].ring->td_list);
1470         (*td)->start_seg = xdev->eps[ep_index].ring->enq_seg;
1471         (*td)->first_trb = xdev->eps[ep_index].ring->enqueue;
1472
1473         return 0;
1474 }
1475
1476 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
1477 {
1478         int num_sgs, num_trbs, running_total, temp, i;
1479         struct scatterlist *sg;
1480
1481         sg = NULL;
1482         num_sgs = urb->num_sgs;
1483         temp = urb->transfer_buffer_length;
1484
1485         xhci_dbg(xhci, "count sg list trbs: \n");
1486         num_trbs = 0;
1487         for_each_sg(urb->sg->sg, sg, num_sgs, i) {
1488                 unsigned int previous_total_trbs = num_trbs;
1489                 unsigned int len = sg_dma_len(sg);
1490
1491                 /* Scatter gather list entries may cross 64KB boundaries */
1492                 running_total = TRB_MAX_BUFF_SIZE -
1493                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
1494                 running_total &= TRB_MAX_BUFF_SIZE - 1;
1495                 if (running_total != 0)
1496                         num_trbs++;
1497
1498                 /* How many more 64KB chunks to transfer, how many more TRBs? */
1499                 while (running_total < sg_dma_len(sg)) {
1500                         num_trbs++;
1501                         running_total += TRB_MAX_BUFF_SIZE;
1502                 }
1503                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1504                                 i, (unsigned long long)sg_dma_address(sg),
1505                                 len, len, num_trbs - previous_total_trbs);
1506
1507                 len = min_t(int, len, temp);
1508                 temp -= len;
1509                 if (temp == 0)
1510                         break;
1511         }
1512         xhci_dbg(xhci, "\n");
1513         if (!in_interrupt())
1514                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1515                                 urb->ep->desc.bEndpointAddress,
1516                                 urb->transfer_buffer_length,
1517                                 num_trbs);
1518         return num_trbs;
1519 }
1520
1521 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
1522 {
1523         if (num_trbs != 0)
1524                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
1525                                 "TRBs, %d left\n", __func__,
1526                                 urb->ep->desc.bEndpointAddress, num_trbs);
1527         if (running_total != urb->transfer_buffer_length)
1528                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
1529                                 "queued %#x (%d), asked for %#x (%d)\n",
1530                                 __func__,
1531                                 urb->ep->desc.bEndpointAddress,
1532                                 running_total, running_total,
1533                                 urb->transfer_buffer_length,
1534                                 urb->transfer_buffer_length);
1535 }
1536
1537 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
1538                 unsigned int ep_index, int start_cycle,
1539                 struct xhci_generic_trb *start_trb, struct xhci_td *td)
1540 {
1541         /*
1542          * Pass all the TRBs to the hardware at once and make sure this write
1543          * isn't reordered.
1544          */
1545         wmb();
1546         start_trb->field[3] |= start_cycle;
1547         ring_ep_doorbell(xhci, slot_id, ep_index);
1548 }
1549
1550 /*
1551  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
1552  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
1553  * (comprised of sg list entries) can take several service intervals to
1554  * transmit.
1555  */
1556 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1557                 struct urb *urb, int slot_id, unsigned int ep_index)
1558 {
1559         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
1560                         xhci->devs[slot_id]->out_ctx, ep_index);
1561         int xhci_interval;
1562         int ep_interval;
1563
1564         xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
1565         ep_interval = urb->interval;
1566         /* Convert to microframes */
1567         if (urb->dev->speed == USB_SPEED_LOW ||
1568                         urb->dev->speed == USB_SPEED_FULL)
1569                 ep_interval *= 8;
1570         /* FIXME change this to a warning and a suggestion to use the new API
1571          * to set the polling interval (once the API is added).
1572          */
1573         if (xhci_interval != ep_interval) {
1574                 if (!printk_ratelimit())
1575                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
1576                                         " (%d microframe%s) than xHCI "
1577                                         "(%d microframe%s)\n",
1578                                         ep_interval,
1579                                         ep_interval == 1 ? "" : "s",
1580                                         xhci_interval,
1581                                         xhci_interval == 1 ? "" : "s");
1582                 urb->interval = xhci_interval;
1583                 /* Convert back to frames for LS/FS devices */
1584                 if (urb->dev->speed == USB_SPEED_LOW ||
1585                                 urb->dev->speed == USB_SPEED_FULL)
1586                         urb->interval /= 8;
1587         }
1588         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
1589 }
1590
1591 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1592                 struct urb *urb, int slot_id, unsigned int ep_index)
1593 {
1594         struct xhci_ring *ep_ring;
1595         unsigned int num_trbs;
1596         struct xhci_td *td;
1597         struct scatterlist *sg;
1598         int num_sgs;
1599         int trb_buff_len, this_sg_len, running_total;
1600         bool first_trb;
1601         u64 addr;
1602
1603         struct xhci_generic_trb *start_trb;
1604         int start_cycle;
1605
1606         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1607         num_trbs = count_sg_trbs_needed(xhci, urb);
1608         num_sgs = urb->num_sgs;
1609
1610         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
1611                         ep_index, num_trbs, urb, &td, mem_flags);
1612         if (trb_buff_len < 0)
1613                 return trb_buff_len;
1614         /*
1615          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1616          * until we've finished creating all the other TRBs.  The ring's cycle
1617          * state may change as we enqueue the other TRBs, so save it too.
1618          */
1619         start_trb = &ep_ring->enqueue->generic;
1620         start_cycle = ep_ring->cycle_state;
1621
1622         running_total = 0;
1623         /*
1624          * How much data is in the first TRB?
1625          *
1626          * There are three forces at work for TRB buffer pointers and lengths:
1627          * 1. We don't want to walk off the end of this sg-list entry buffer.
1628          * 2. The transfer length that the driver requested may be smaller than
1629          *    the amount of memory allocated for this scatter-gather list.
1630          * 3. TRBs buffers can't cross 64KB boundaries.
1631          */
1632         sg = urb->sg->sg;
1633         addr = (u64) sg_dma_address(sg);
1634         this_sg_len = sg_dma_len(sg);
1635         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
1636         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1637         if (trb_buff_len > urb->transfer_buffer_length)
1638                 trb_buff_len = urb->transfer_buffer_length;
1639         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
1640                         trb_buff_len);
1641
1642         first_trb = true;
1643         /* Queue the first TRB, even if it's zero-length */
1644         do {
1645                 u32 field = 0;
1646                 u32 length_field = 0;
1647
1648                 /* Don't change the cycle bit of the first TRB until later */
1649                 if (first_trb)
1650                         first_trb = false;
1651                 else
1652                         field |= ep_ring->cycle_state;
1653
1654                 /* Chain all the TRBs together; clear the chain bit in the last
1655                  * TRB to indicate it's the last TRB in the chain.
1656                  */
1657                 if (num_trbs > 1) {
1658                         field |= TRB_CHAIN;
1659                 } else {
1660                         /* FIXME - add check for ZERO_PACKET flag before this */
1661                         td->last_trb = ep_ring->enqueue;
1662                         field |= TRB_IOC;
1663                 }
1664                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
1665                                 "64KB boundary at %#x, end dma = %#x\n",
1666                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
1667                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1668                                 (unsigned int) addr + trb_buff_len);
1669                 if (TRB_MAX_BUFF_SIZE -
1670                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
1671                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1672                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
1673                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1674                                         (unsigned int) addr + trb_buff_len);
1675                 }
1676                 length_field = TRB_LEN(trb_buff_len) |
1677                         TD_REMAINDER(urb->transfer_buffer_length - running_total) |
1678                         TRB_INTR_TARGET(0);
1679                 queue_trb(xhci, ep_ring, false,
1680                                 lower_32_bits(addr),
1681                                 upper_32_bits(addr),
1682                                 length_field,
1683                                 /* We always want to know if the TRB was short,
1684                                  * or we won't get an event when it completes.
1685                                  * (Unless we use event data TRBs, which are a
1686                                  * waste of space and HC resources.)
1687                                  */
1688                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1689                 --num_trbs;
1690                 running_total += trb_buff_len;
1691
1692                 /* Calculate length for next transfer --
1693                  * Are we done queueing all the TRBs for this sg entry?
1694                  */
1695                 this_sg_len -= trb_buff_len;
1696                 if (this_sg_len == 0) {
1697                         --num_sgs;
1698                         if (num_sgs == 0)
1699                                 break;
1700                         sg = sg_next(sg);
1701                         addr = (u64) sg_dma_address(sg);
1702                         this_sg_len = sg_dma_len(sg);
1703                 } else {
1704                         addr += trb_buff_len;
1705                 }
1706
1707                 trb_buff_len = TRB_MAX_BUFF_SIZE -
1708                         (addr & (TRB_MAX_BUFF_SIZE - 1));
1709                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1710                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
1711                         trb_buff_len =
1712                                 urb->transfer_buffer_length - running_total;
1713         } while (running_total < urb->transfer_buffer_length);
1714
1715         check_trb_math(urb, num_trbs, running_total);
1716         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1717         return 0;
1718 }
1719
1720 /* This is very similar to what ehci-q.c qtd_fill() does */
1721 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1722                 struct urb *urb, int slot_id, unsigned int ep_index)
1723 {
1724         struct xhci_ring *ep_ring;
1725         struct xhci_td *td;
1726         int num_trbs;
1727         struct xhci_generic_trb *start_trb;
1728         bool first_trb;
1729         int start_cycle;
1730         u32 field, length_field;
1731
1732         int running_total, trb_buff_len, ret;
1733         u64 addr;
1734
1735         if (urb->sg)
1736                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
1737
1738         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1739
1740         num_trbs = 0;
1741         /* How much data is (potentially) left before the 64KB boundary? */
1742         running_total = TRB_MAX_BUFF_SIZE -
1743                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
1744         running_total &= TRB_MAX_BUFF_SIZE - 1;
1745
1746         /* If there's some data on this 64KB chunk, or we have to send a
1747          * zero-length transfer, we need at least one TRB
1748          */
1749         if (running_total != 0 || urb->transfer_buffer_length == 0)
1750                 num_trbs++;
1751         /* How many more 64KB chunks to transfer, how many more TRBs? */
1752         while (running_total < urb->transfer_buffer_length) {
1753                 num_trbs++;
1754                 running_total += TRB_MAX_BUFF_SIZE;
1755         }
1756         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1757
1758         if (!in_interrupt())
1759                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1760                                 urb->ep->desc.bEndpointAddress,
1761                                 urb->transfer_buffer_length,
1762                                 urb->transfer_buffer_length,
1763                                 (unsigned long long)urb->transfer_dma,
1764                                 num_trbs);
1765
1766         ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
1767                         num_trbs, urb, &td, mem_flags);
1768         if (ret < 0)
1769                 return ret;
1770
1771         /*
1772          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1773          * until we've finished creating all the other TRBs.  The ring's cycle
1774          * state may change as we enqueue the other TRBs, so save it too.
1775          */
1776         start_trb = &ep_ring->enqueue->generic;
1777         start_cycle = ep_ring->cycle_state;
1778
1779         running_total = 0;
1780         /* How much data is in the first TRB? */
1781         addr = (u64) urb->transfer_dma;
1782         trb_buff_len = TRB_MAX_BUFF_SIZE -
1783                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
1784         if (trb_buff_len > urb->transfer_buffer_length)
1785                 trb_buff_len = urb->transfer_buffer_length;
1786
1787         first_trb = true;
1788
1789         /* Queue the first TRB, even if it's zero-length */
1790         do {
1791                 field = 0;
1792
1793                 /* Don't change the cycle bit of the first TRB until later */
1794                 if (first_trb)
1795                         first_trb = false;
1796                 else
1797                         field |= ep_ring->cycle_state;
1798
1799                 /* Chain all the TRBs together; clear the chain bit in the last
1800                  * TRB to indicate it's the last TRB in the chain.
1801                  */
1802                 if (num_trbs > 1) {
1803                         field |= TRB_CHAIN;
1804                 } else {
1805                         /* FIXME - add check for ZERO_PACKET flag before this */
1806                         td->last_trb = ep_ring->enqueue;
1807                         field |= TRB_IOC;
1808                 }
1809                 length_field = TRB_LEN(trb_buff_len) |
1810                         TD_REMAINDER(urb->transfer_buffer_length - running_total) |
1811                         TRB_INTR_TARGET(0);
1812                 queue_trb(xhci, ep_ring, false,
1813                                 lower_32_bits(addr),
1814                                 upper_32_bits(addr),
1815                                 length_field,
1816                                 /* We always want to know if the TRB was short,
1817                                  * or we won't get an event when it completes.
1818                                  * (Unless we use event data TRBs, which are a
1819                                  * waste of space and HC resources.)
1820                                  */
1821                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1822                 --num_trbs;
1823                 running_total += trb_buff_len;
1824
1825                 /* Calculate length for next transfer */
1826                 addr += trb_buff_len;
1827                 trb_buff_len = urb->transfer_buffer_length - running_total;
1828                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
1829                         trb_buff_len = TRB_MAX_BUFF_SIZE;
1830         } while (running_total < urb->transfer_buffer_length);
1831
1832         check_trb_math(urb, num_trbs, running_total);
1833         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1834         return 0;
1835 }
1836
1837 /* Caller must have locked xhci->lock */
1838 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1839                 struct urb *urb, int slot_id, unsigned int ep_index)
1840 {
1841         struct xhci_ring *ep_ring;
1842         int num_trbs;
1843         int ret;
1844         struct usb_ctrlrequest *setup;
1845         struct xhci_generic_trb *start_trb;
1846         int start_cycle;
1847         u32 field, length_field;
1848         struct xhci_td *td;
1849
1850         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1851
1852         /*
1853          * Need to copy setup packet into setup TRB, so we can't use the setup
1854          * DMA address.
1855          */
1856         if (!urb->setup_packet)
1857                 return -EINVAL;
1858
1859         if (!in_interrupt())
1860                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
1861                                 slot_id, ep_index);
1862         /* 1 TRB for setup, 1 for status */
1863         num_trbs = 2;
1864         /*
1865          * Don't need to check if we need additional event data and normal TRBs,
1866          * since data in control transfers will never get bigger than 16MB
1867          * XXX: can we get a buffer that crosses 64KB boundaries?
1868          */
1869         if (urb->transfer_buffer_length > 0)
1870                 num_trbs++;
1871         ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, num_trbs,
1872                         urb, &td, mem_flags);
1873         if (ret < 0)
1874                 return ret;
1875
1876         /*
1877          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1878          * until we've finished creating all the other TRBs.  The ring's cycle
1879          * state may change as we enqueue the other TRBs, so save it too.
1880          */
1881         start_trb = &ep_ring->enqueue->generic;
1882         start_cycle = ep_ring->cycle_state;
1883
1884         /* Queue setup TRB - see section 6.4.1.2.1 */
1885         /* FIXME better way to translate setup_packet into two u32 fields? */
1886         setup = (struct usb_ctrlrequest *) urb->setup_packet;
1887         queue_trb(xhci, ep_ring, false,
1888                         /* FIXME endianness is probably going to bite my ass here. */
1889                         setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
1890                         setup->wIndex | setup->wLength << 16,
1891                         TRB_LEN(8) | TRB_INTR_TARGET(0),
1892                         /* Immediate data in pointer */
1893                         TRB_IDT | TRB_TYPE(TRB_SETUP));
1894
1895         /* If there's data, queue data TRBs */
1896         field = 0;
1897         length_field = TRB_LEN(urb->transfer_buffer_length) |
1898                 TD_REMAINDER(urb->transfer_buffer_length) |
1899                 TRB_INTR_TARGET(0);
1900         if (urb->transfer_buffer_length > 0) {
1901                 if (setup->bRequestType & USB_DIR_IN)
1902                         field |= TRB_DIR_IN;
1903                 queue_trb(xhci, ep_ring, false,
1904                                 lower_32_bits(urb->transfer_dma),
1905                                 upper_32_bits(urb->transfer_dma),
1906                                 length_field,
1907                                 /* Event on short tx */
1908                                 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
1909         }
1910
1911         /* Save the DMA address of the last TRB in the TD */
1912         td->last_trb = ep_ring->enqueue;
1913
1914         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
1915         /* If the device sent data, the status stage is an OUT transfer */
1916         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
1917                 field = 0;
1918         else
1919                 field = TRB_DIR_IN;
1920         queue_trb(xhci, ep_ring, false,
1921                         0,
1922                         0,
1923                         TRB_INTR_TARGET(0),
1924                         /* Event on completion */
1925                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
1926
1927         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1928         return 0;
1929 }
1930
1931 /****           Command Ring Operations         ****/
1932
1933 /* Generic function for queueing a command TRB on the command ring.
1934  * Check to make sure there's room on the command ring for one command TRB.
1935  * Also check that there's room reserved for commands that must not fail.
1936  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
1937  * then only check for the number of reserved spots.
1938  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
1939  * because the command event handler may want to resubmit a failed command.
1940  */
1941 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
1942                 u32 field3, u32 field4, bool command_must_succeed)
1943 {
1944         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
1945         if (!command_must_succeed)
1946                 reserved_trbs++;
1947
1948         if (!room_on_ring(xhci, xhci->cmd_ring, reserved_trbs)) {
1949                 if (!in_interrupt())
1950                         xhci_err(xhci, "ERR: No room for command on command ring\n");
1951                 if (command_must_succeed)
1952                         xhci_err(xhci, "ERR: Reserved TRB counting for "
1953                                         "unfailable commands failed.\n");
1954                 return -ENOMEM;
1955         }
1956         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
1957                         field4 | xhci->cmd_ring->cycle_state);
1958         return 0;
1959 }
1960
1961 /* Queue a no-op command on the command ring */
1962 static int queue_cmd_noop(struct xhci_hcd *xhci)
1963 {
1964         return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false);
1965 }
1966
1967 /*
1968  * Place a no-op command on the command ring to test the command and
1969  * event ring.
1970  */
1971 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
1972 {
1973         if (queue_cmd_noop(xhci) < 0)
1974                 return NULL;
1975         xhci->noops_submitted++;
1976         return xhci_ring_cmd_db;
1977 }
1978
1979 /* Queue a slot enable or disable request on the command ring */
1980 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
1981 {
1982         return queue_command(xhci, 0, 0, 0,
1983                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
1984 }
1985
1986 /* Queue an address device command TRB */
1987 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1988                 u32 slot_id)
1989 {
1990         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
1991                         upper_32_bits(in_ctx_ptr), 0,
1992                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
1993                         false);
1994 }
1995
1996 /* Queue a configure endpoint command TRB */
1997 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1998                 u32 slot_id, bool command_must_succeed)
1999 {
2000         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2001                         upper_32_bits(in_ctx_ptr), 0,
2002                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
2003                         command_must_succeed);
2004 }
2005
2006 /* Queue an evaluate context command TRB */
2007 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2008                 u32 slot_id)
2009 {
2010         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2011                         upper_32_bits(in_ctx_ptr), 0,
2012                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
2013                         false);
2014 }
2015
2016 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
2017                 unsigned int ep_index)
2018 {
2019         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2020         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2021         u32 type = TRB_TYPE(TRB_STOP_RING);
2022
2023         return queue_command(xhci, 0, 0, 0,
2024                         trb_slot_id | trb_ep_index | type, false);
2025 }
2026
2027 /* Set Transfer Ring Dequeue Pointer command.
2028  * This should not be used for endpoints that have streams enabled.
2029  */
2030 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
2031                 unsigned int ep_index, struct xhci_segment *deq_seg,
2032                 union xhci_trb *deq_ptr, u32 cycle_state)
2033 {
2034         dma_addr_t addr;
2035         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2036         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2037         u32 type = TRB_TYPE(TRB_SET_DEQ);
2038
2039         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
2040         if (addr == 0) {
2041                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
2042                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
2043                                 deq_seg, deq_ptr);
2044                 return 0;
2045         }
2046         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
2047                         upper_32_bits(addr), 0,
2048                         trb_slot_id | trb_ep_index | type, false);
2049 }
2050
2051 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
2052                 unsigned int ep_index)
2053 {
2054         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2055         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2056         u32 type = TRB_TYPE(TRB_RESET_EP);
2057
2058         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
2059                         false);
2060 }