drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70 #include "xhci-trace.h"
  71
  72 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  73                 struct xhci_virt_device *virt_dev,
  74                 struct xhci_event_cmd *event);
  75
  76 /*
  77  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  78  * address of the TRB.
  79  */
  80 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  81                 union xhci_trb *trb)
  82 {
  83         unsigned long segment_offset;
  84
  85         if (!seg || !trb || trb < seg->trbs)
  86                 return 0;
  87         /* offset in TRBs */
  88         segment_offset = trb - seg->trbs;
  89         if (segment_offset > TRBS_PER_SEGMENT)
  90                 return 0;
  91         return seg->dma + (segment_offset * sizeof(*trb));
  92 }
  93
  94 /* Does this link TRB point to the first segment in a ring,
  95  * or was the previous TRB the last TRB on the last segment in the ERST?
  96  */
  97 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  98                 struct xhci_segment *seg, union xhci_trb *trb)
  99 {
 100         if (ring == xhci->event_ring)
 101                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 102                         (seg->next == xhci->event_ring->first_seg);
 103         else
 104                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 105 }
 106
 107 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 108  * segment?  I.e. would the updated event TRB pointer step off the end of the
 109  * event seg?
 110  */
 111 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 112                 struct xhci_segment *seg, union xhci_trb *trb)
 113 {
 114         if (ring == xhci->event_ring)
 115                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 116         else
 117                 return TRB_TYPE_LINK_LE32(trb->link.control);
 118 }
 119
 120 static int enqueue_is_link_trb(struct xhci_ring *ring)
 121 {
 122         struct xhci_link_trb *link = &ring->enqueue->link;
 123         return TRB_TYPE_LINK_LE32(link->control);
 124 }
 125
 126 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 127  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 128  * effect the ring dequeue or enqueue pointers.
 129  */
 130 static void next_trb(struct xhci_hcd *xhci,
 131                 struct xhci_ring *ring,
 132                 struct xhci_segment **seg,
 133                 union xhci_trb **trb)
 134 {
 135         if (last_trb(xhci, ring, *seg, *trb)) {
 136                 *seg = (*seg)->next;
 137                 *trb = ((*seg)->trbs);
 138         } else {
 139                 (*trb)++;
 140         }
 141 }
 142
 143 /*
 144  * See Cycle bit rules. SW is the consumer for the event ring only.
 145  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 146  */
 147 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 148 {
 149         unsigned long long addr;
 150
 151         ring->deq_updates++;
 152
 153         /*
 154          * If this is not event ring, and the dequeue pointer
 155          * is not on a link TRB, there is one more usable TRB
 156          */
 157         if (ring->type != TYPE_EVENT &&
 158                         !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
 159                 ring->num_trbs_free++;
 160
 161         do {
 162                 /*
 163                  * Update the dequeue pointer further if that was a link TRB or
 164                  * we're at the end of an event ring segment (which doesn't have
 165                  * link TRBS)
 166                  */
 167                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 168                         if (ring->type == TYPE_EVENT &&
 169                                         last_trb_on_last_seg(xhci, ring,
 170                                                 ring->deq_seg, ring->dequeue)) {
 171                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 172                         }
 173                         ring->deq_seg = ring->deq_seg->next;
 174                         ring->dequeue = ring->deq_seg->trbs;
 175                 } else {
 176                         ring->dequeue++;
 177                 }
 178         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 179
 180         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 181 }
 182
 183 /*
 184  * See Cycle bit rules. SW is the consumer for the event ring only.
 185  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 186  *
 187  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 188  * chain bit is set), then set the chain bit in all the following link TRBs.
 189  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 190  * have their chain bit cleared (so that each Link TRB is a separate TD).
 191  *
 192  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 193  * set, but other sections talk about dealing with the chain bit set.  This was
 194  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 195  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 196  *
 197  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 198  *                      prepare_transfer()?
 199  */
 200 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 201                         bool more_trbs_coming)
 202 {
 203         u32 chain;
 204         union xhci_trb *next;
 205         unsigned long long addr;
 206
 207         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 208         /* If this is not event ring, there is one less usable TRB */
 209         if (ring->type != TYPE_EVENT &&
 210                         !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
 211                 ring->num_trbs_free--;
 212         next = ++(ring->enqueue);
 213
 214         ring->enq_updates++;
 215         /* Update the dequeue pointer further if that was a link TRB or we're at
 216          * the end of an event ring segment (which doesn't have link TRBS)
 217          */
 218         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 219                 if (ring->type != TYPE_EVENT) {
 220                         /*
 221                          * If the caller doesn't plan on enqueueing more
 222                          * TDs before ringing the doorbell, then we
 223                          * don't want to give the link TRB to the
 224                          * hardware just yet.  We'll give the link TRB
 225                          * back in prepare_ring() just before we enqueue
 226                          * the TD at the top of the ring.
 227                          */
 228                         if (!chain && !more_trbs_coming)
 229                                 break;
 230
 231                         /* If we're not dealing with 0.95 hardware or
 232                          * isoc rings on AMD 0.96 host,
 233                          * carry over the chain bit of the previous TRB
 234                          * (which may mean the chain bit is cleared).
 235                          */
 236                         if (!(ring->type == TYPE_ISOC &&
 237                                         (xhci->quirks & XHCI_AMD_0x96_HOST))
 238                                                 && !xhci_link_trb_quirk(xhci)) {
 239                                 next->link.control &=
 240                                         cpu_to_le32(~TRB_CHAIN);
 241                                 next->link.control |=
 242                                         cpu_to_le32(chain);
 243                         }
 244                         /* Give this link TRB to the hardware */
 245                         wmb();
 246                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
 247
 248                         /* Toggle the cycle bit after the last ring segment. */
 249                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 250                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 251                         }
 252                 }
 253                 ring->enq_seg = ring->enq_seg->next;
 254                 ring->enqueue = ring->enq_seg->trbs;
 255                 next = ring->enqueue;
 256         }
 257         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 258 }
 259
 260 /*
 261  * Check to see if there's room to enqueue num_trbs on the ring and make sure
 262  * enqueue pointer will not advance into dequeue segment. See rules above.
 263  */
 264 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 265                 unsigned int num_trbs)
 266 {
 267         int num_trbs_in_deq_seg;
 268
 269         if (ring->num_trbs_free < num_trbs)
 270                 return 0;
 271
 272         if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
 273                 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
 274                 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
 275                         return 0;
 276         }
 277
 278         return 1;
 279 }
 280
 281 /* Ring the host controller doorbell after placing a command on the ring */
 282 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 283 {
 284         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 285                 return;
 286
 287         xhci_dbg(xhci, "// Ding dong!\n");
 288         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 289         /* Flush PCI posted writes */
 290         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 291 }
 292
 293 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 294 {
 295         u64 temp_64;
 296         int ret;
 297
 298         xhci_dbg(xhci, "Abort command ring\n");
 299
 300         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 301                 xhci_dbg(xhci, "The command ring isn't running, "
 302                                 "Have the command ring been stopped?\n");
 303                 return 0;
 304         }
 305
 306         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 307         if (!(temp_64 & CMD_RING_RUNNING)) {
 308                 xhci_dbg(xhci, "Command ring had been stopped\n");
 309                 return 0;
 310         }
 311         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 312         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 313                         &xhci->op_regs->cmd_ring);
 314
 315         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 316          * time the completion od all xHCI commands, including
 317          * the Command Abort operation. If software doesn't see
 318          * CRR negated in a timely manner (e.g. longer than 5
 319          * seconds), then it should assume that the there are
 320          * larger problems with the xHC and assert HCRST.
 321          */
 322         ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
 323                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 324         if (ret < 0) {
 325                 xhci_err(xhci, "Stopped the command ring failed, "
 326                                 "maybe the host is dead\n");
 327                 xhci->xhc_state |= XHCI_STATE_DYING;
 328                 xhci_quiesce(xhci);
 329                 xhci_halt(xhci);
 330                 return -ESHUTDOWN;
 331         }
 332
 333         return 0;
 334 }
 335
 336 static int xhci_queue_cd(struct xhci_hcd *xhci,
 337                 struct xhci_command *command,
 338                 union xhci_trb *cmd_trb)
 339 {
 340         struct xhci_cd *cd;
 341         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 342         if (!cd)
 343                 return -ENOMEM;
 344         INIT_LIST_HEAD(&cd->cancel_cmd_list);
 345
 346         cd->command = command;
 347         cd->cmd_trb = cmd_trb;
 348         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 349
 350         return 0;
 351 }
 352
 353 /*
 354  * Cancel the command which has issue.
 355  *
 356  * Some commands may hang due to waiting for acknowledgement from
 357  * usb device. It is outside of the xHC's ability to control and
 358  * will cause the command ring is blocked. When it occurs software
 359  * should intervene to recover the command ring.
 360  * See Section 4.6.1.1 and 4.6.1.2
 361  */
 362 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 363                 union xhci_trb *cmd_trb)
 364 {
 365         int retval = 0;
 366         unsigned long flags;
 367
 368         spin_lock_irqsave(&xhci->lock, flags);
 369
 370         if (xhci->xhc_state & XHCI_STATE_DYING) {
 371                 xhci_warn(xhci, "Abort the command ring,"
 372                                 " but the xHCI is dead.\n");
 373                 retval = -ESHUTDOWN;
 374                 goto fail;
 375         }
 376
 377         /* queue the cmd desriptor to cancel_cmd_list */
 378         retval = xhci_queue_cd(xhci, command, cmd_trb);
 379         if (retval) {
 380                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
 381                 goto fail;
 382         }
 383
 384         /* abort command ring */
 385         retval = xhci_abort_cmd_ring(xhci);
 386         if (retval) {
 387                 xhci_err(xhci, "Abort command ring failed\n");
 388                 if (unlikely(retval == -ESHUTDOWN)) {
 389                         spin_unlock_irqrestore(&xhci->lock, flags);
 390                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 391                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 392                         return retval;
 393                 }
 394         }
 395
 396 fail:
 397         spin_unlock_irqrestore(&xhci->lock, flags);
 398         return retval;
 399 }
 400
 401 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 402                 unsigned int slot_id,
 403                 unsigned int ep_index,
 404                 unsigned int stream_id)
 405 {
 406         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 407         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 408         unsigned int ep_state = ep->ep_state;
 409
 410         /* Don't ring the doorbell for this endpoint if there are pending
 411          * cancellations because we don't want to interrupt processing.
 412          * We don't want to restart any stream rings if there's a set dequeue
 413          * pointer command pending because the device can choose to start any
 414          * stream once the endpoint is on the HW schedule.
 415          * FIXME - check all the stream rings for pending cancellations.
 416          */
 417         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 418             (ep_state & EP_HALTED))
 419                 return;
 420         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 421         /* The CPU has better things to do at this point than wait for a
 422          * write-posting flush.  It'll get there soon enough.
 423          */
 424 }
 425
 426 /* Ring the doorbell for any rings with pending URBs */
 427 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 428                 unsigned int slot_id,
 429                 unsigned int ep_index)
 430 {
 431         unsigned int stream_id;
 432         struct xhci_virt_ep *ep;
 433
 434         ep = &xhci->devs[slot_id]->eps[ep_index];
 435
 436         /* A ring has pending URBs if its TD list is not empty */
 437         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 438                 if (ep->ring && !(list_empty(&ep->ring->td_list)))
 439                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 440                 return;
 441         }
 442
 443         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 444                         stream_id++) {
 445                 struct xhci_stream_info *stream_info = ep->stream_info;
 446                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 447                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 448                                                 stream_id);
 449         }
 450 }
 451
 452 /*
 453  * Find the segment that trb is in.  Start searching in start_seg.
 454  * If we must move past a segment that has a link TRB with a toggle cycle state
 455  * bit set, then we will toggle the value pointed at by cycle_state.
 456  */
 457 static struct xhci_segment *find_trb_seg(
 458                 struct xhci_segment *start_seg,
 459                 union xhci_trb  *trb, int *cycle_state)
 460 {
 461         struct xhci_segment *cur_seg = start_seg;
 462         struct xhci_generic_trb *generic_trb;
 463
 464         while (cur_seg->trbs > trb ||
 465                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 466                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 467                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 468                         *cycle_state ^= 0x1;
 469                 cur_seg = cur_seg->next;
 470                 if (cur_seg == start_seg)
 471                         /* Looped over the entire list.  Oops! */
 472                         return NULL;
 473         }
 474         return cur_seg;
 475 }
 476
 477
 478 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 479                 unsigned int slot_id, unsigned int ep_index,
 480                 unsigned int stream_id)
 481 {
 482         struct xhci_virt_ep *ep;
 483
 484         ep = &xhci->devs[slot_id]->eps[ep_index];
 485         /* Common case: no streams */
 486         if (!(ep->ep_state & EP_HAS_STREAMS))
 487                 return ep->ring;
 488
 489         if (stream_id == 0) {
 490                 xhci_warn(xhci,
 491                                 "WARN: Slot ID %u, ep index %u has streams, "
 492                                 "but URB has no stream ID.\n",
 493                                 slot_id, ep_index);
 494                 return NULL;
 495         }
 496
 497         if (stream_id < ep->stream_info->num_streams)
 498                 return ep->stream_info->stream_rings[stream_id];
 499
 500         xhci_warn(xhci,
 501                         "WARN: Slot ID %u, ep index %u has "
 502                         "stream IDs 1 to %u allocated, "
 503                         "but stream ID %u is requested.\n",
 504                         slot_id, ep_index,
 505                         ep->stream_info->num_streams - 1,
 506                         stream_id);
 507         return NULL;
 508 }
 509
 510 /* Get the right ring for the given URB.
 511  * If the endpoint supports streams, boundary check the URB's stream ID.
 512  * If the endpoint doesn't support streams, return the singular endpoint ring.
 513  */
 514 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 515                 struct urb *urb)
 516 {
 517         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 518                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 519 }
 520
 521 /*
 522  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 523  * Record the new state of the xHC's endpoint ring dequeue segment,
 524  * dequeue pointer, and new consumer cycle state in state.
 525  * Update our internal representation of the ring's dequeue pointer.
 526  *
 527  * We do this in three jumps:
 528  *  - First we update our new ring state to be the same as when the xHC stopped.
 529  *  - Then we traverse the ring to find the segment that contains
 530  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 531  *    any link TRBs with the toggle cycle bit set.
 532  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 533  *    if we've moved it past a link TRB with the toggle cycle bit set.
 534  *
 535  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 536  * with correct __le32 accesses they should work fine.  Only users of this are
 537  * in here.
 538  */
 539 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 540                 unsigned int slot_id, unsigned int ep_index,
 541                 unsigned int stream_id, struct xhci_td *cur_td,
 542                 struct xhci_dequeue_state *state)
 543 {
 544         struct xhci_virt_device *dev = xhci->devs[slot_id];
 545         struct xhci_ring *ep_ring;
 546         struct xhci_generic_trb *trb;
 547         struct xhci_ep_ctx *ep_ctx;
 548         dma_addr_t addr;
 549
 550         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 551                         ep_index, stream_id);
 552         if (!ep_ring) {
 553                 xhci_warn(xhci, "WARN can't find new dequeue state "
 554                                 "for invalid stream ID %u.\n",
 555                                 stream_id);
 556                 return;
 557         }
 558         state->new_cycle_state = 0;
 559         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 560         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 561                         dev->eps[ep_index].stopped_trb,
 562                         &state->new_cycle_state);
 563         if (!state->new_deq_seg) {
 564                 WARN_ON(1);
 565                 return;
 566         }
 567
 568         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 569         xhci_dbg(xhci, "Finding endpoint context\n");
 570         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 571         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 572
 573         state->new_deq_ptr = cur_td->last_trb;
 574         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 575         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 576                         state->new_deq_ptr,
 577                         &state->new_cycle_state);
 578         if (!state->new_deq_seg) {
 579                 WARN_ON(1);
 580                 return;
 581         }
 582
 583         trb = &state->new_deq_ptr->generic;
 584         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 585             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 586                 state->new_cycle_state ^= 0x1;
 587         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 588
 589         /*
 590          * If there is only one segment in a ring, find_trb_seg()'s while loop
 591          * will not run, and it will return before it has a chance to see if it
 592          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 593          * ended just before the link TRB on a one-segment ring, or if the TD
 594          * wrapped around the top of the ring, because it doesn't have the TD in
 595          * question.  Look for the one-segment case where stalled TRB's address
 596          * is greater than the new dequeue pointer address.
 597          */
 598         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 599                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 600                 state->new_cycle_state ^= 0x1;
 601         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 602
 603         /* Don't update the ring cycle state for the producer (us). */
 604         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 605                         state->new_deq_seg);
 606         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 607         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 608                         (unsigned long long) addr);
 609 }
 610
 611 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 612  * (The last TRB actually points to the ring enqueue pointer, which is not part
 613  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 614  */
 615 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 616                 struct xhci_td *cur_td, bool flip_cycle)
 617 {
 618         struct xhci_segment *cur_seg;
 619         union xhci_trb *cur_trb;
 620
 621         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 622                         true;
 623                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 624                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 625                         /* Unchain any chained Link TRBs, but
 626                          * leave the pointers intact.
 627                          */
 628                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 629                         /* Flip the cycle bit (link TRBs can't be the first
 630                          * or last TRB).
 631                          */
 632                         if (flip_cycle)
 633                                 cur_trb->generic.field[3] ^=
 634                                         cpu_to_le32(TRB_CYCLE);
 635                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 636                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 637                                         "in seg %p (0x%llx dma)\n",
 638                                         cur_trb,
 639                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 640                                         cur_seg,
 641                                         (unsigned long long)cur_seg->dma);
 642                 } else {
 643                         cur_trb->generic.field[0] = 0;
 644                         cur_trb->generic.field[1] = 0;
 645                         cur_trb->generic.field[2] = 0;
 646                         /* Preserve only the cycle bit of this TRB */
 647                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 648                         /* Flip the cycle bit except on the first or last TRB */
 649                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 650                                         cur_trb != cur_td->last_trb)
 651                                 cur_trb->generic.field[3] ^=
 652                                         cpu_to_le32(TRB_CYCLE);
 653                         cur_trb->generic.field[3] |= cpu_to_le32(
 654                                 TRB_TYPE(TRB_TR_NOOP));
 655                         xhci_dbg(xhci, "TRB to noop at offset 0x%llx\n",
 656                                         (unsigned long long)
 657                                         xhci_trb_virt_to_dma(cur_seg, cur_trb));
 658                 }
 659                 if (cur_trb == cur_td->last_trb)
 660                         break;
 661         }
 662 }
 663
 664 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 665                 unsigned int ep_index, unsigned int stream_id,
 666                 struct xhci_segment *deq_seg,
 667                 union xhci_trb *deq_ptr, u32 cycle_state);
 668
 669 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 670                 unsigned int slot_id, unsigned int ep_index,
 671                 unsigned int stream_id,
 672                 struct xhci_dequeue_state *deq_state)
 673 {
 674         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 675
 676         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 677                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 678                         deq_state->new_deq_seg,
 679                         (unsigned long long)deq_state->new_deq_seg->dma,
 680                         deq_state->new_deq_ptr,
 681                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 682                         deq_state->new_cycle_state);
 683         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 684                         deq_state->new_deq_seg,
 685                         deq_state->new_deq_ptr,
 686                         (u32) deq_state->new_cycle_state);
 687         /* Stop the TD queueing code from ringing the doorbell until
 688          * this command completes.  The HC won't set the dequeue pointer
 689          * if the ring is running, and ringing the doorbell starts the
 690          * ring running.
 691          */
 692         ep->ep_state |= SET_DEQ_PENDING;
 693 }
 694
 695 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 696                 struct xhci_virt_ep *ep)
 697 {
 698         ep->ep_state &= ~EP_HALT_PENDING;
 699         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 700          * timer is running on another CPU, we don't decrement stop_cmds_pending
 701          * (since we didn't successfully stop the watchdog timer).
 702          */
 703         if (del_timer(&ep->stop_cmd_timer))
 704                 ep->stop_cmds_pending--;
 705 }
 706
 707 /* Must be called with xhci->lock held in interrupt context */
 708 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 709                 struct xhci_td *cur_td, int status, char *adjective)
 710 {
 711         struct usb_hcd *hcd;
 712         struct urb      *urb;
 713         struct urb_priv *urb_priv;
 714
 715         urb = cur_td->urb;
 716         urb_priv = urb->hcpriv;
 717         urb_priv->td_cnt++;
 718         hcd = bus_to_hcd(urb->dev->bus);
 719
 720         /* Only giveback urb when this is the last td in urb */
 721         if (urb_priv->td_cnt == urb_priv->length) {
 722                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 723                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 724                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 725                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 726                                         usb_amd_quirk_pll_enable();
 727                         }
 728                 }
 729                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 730
 731                 spin_unlock(&xhci->lock);
 732                 usb_hcd_giveback_urb(hcd, urb, status);
 733                 xhci_urb_free_priv(xhci, urb_priv);
 734                 spin_lock(&xhci->lock);
 735         }
 736 }
 737
 738 /*
 739  * When we get a command completion for a Stop Endpoint Command, we need to
 740  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 741  *
 742  *  1. If the HW was in the middle of processing the TD that needs to be
 743  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 744  *     in the TD with a Set Dequeue Pointer Command.
 745  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 746  *     bit cleared) so that the HW will skip over them.
 747  */
 748 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 749                 union xhci_trb *trb, struct xhci_event_cmd *event)
 750 {
 751         unsigned int slot_id;
 752         unsigned int ep_index;
 753         struct xhci_virt_device *virt_dev;
 754         struct xhci_ring *ep_ring;
 755         struct xhci_virt_ep *ep;
 756         struct list_head *entry;
 757         struct xhci_td *cur_td = NULL;
 758         struct xhci_td *last_unlinked_td;
 759
 760         struct xhci_dequeue_state deq_state;
 761
 762         if (unlikely(TRB_TO_SUSPEND_PORT(
 763                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 764                 slot_id = TRB_TO_SLOT_ID(
 765                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 766                 virt_dev = xhci->devs[slot_id];
 767                 if (virt_dev)
 768                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 769                                 event);
 770                 else
 771                         xhci_warn(xhci, "Stop endpoint command "
 772                                 "completion for disabled slot %u\n",
 773                                 slot_id);
 774                 return;
 775         }
 776
 777         memset(&deq_state, 0, sizeof(deq_state));
 778         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 779         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 780         ep = &xhci->devs[slot_id]->eps[ep_index];
 781
 782         if (list_empty(&ep->cancelled_td_list)) {
 783                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 784                 ep->stopped_td = NULL;
 785                 ep->stopped_trb = NULL;
 786                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 787                 return;
 788         }
 789
 790         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 791          * We have the xHCI lock, so nothing can modify this list until we drop
 792          * it.  We're also in the event handler, so we can't get re-interrupted
 793          * if another Stop Endpoint command completes
 794          */
 795         list_for_each(entry, &ep->cancelled_td_list) {
 796                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 797                 xhci_dbg(xhci, "Removing canceled TD starting at 0x%llx (dma).\n",
 798                                 (unsigned long long)xhci_trb_virt_to_dma(
 799                                         cur_td->start_seg, cur_td->first_trb));
 800                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 801                 if (!ep_ring) {
 802                         /* This shouldn't happen unless a driver is mucking
 803                          * with the stream ID after submission.  This will
 804                          * leave the TD on the hardware ring, and the hardware
 805                          * will try to execute it, and may access a buffer
 806                          * that has already been freed.  In the best case, the
 807                          * hardware will execute it, and the event handler will
 808                          * ignore the completion event for that TD, since it was
 809                          * removed from the td_list for that endpoint.  In
 810                          * short, don't muck with the stream ID after
 811                          * submission.
 812                          */
 813                         xhci_warn(xhci, "WARN Cancelled URB %p "
 814                                         "has invalid stream ID %u.\n",
 815                                         cur_td->urb,
 816                                         cur_td->urb->stream_id);
 817                         goto remove_finished_td;
 818                 }
 819                 /*
 820                  * If we stopped on the TD we need to cancel, then we have to
 821                  * move the xHC endpoint ring dequeue pointer past this TD.
 822                  */
 823                 if (cur_td == ep->stopped_td)
 824                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 825                                         cur_td->urb->stream_id,
 826                                         cur_td, &deq_state);
 827                 else
 828                         td_to_noop(xhci, ep_ring, cur_td, false);
 829 remove_finished_td:
 830                 /*
 831                  * The event handler won't see a completion for this TD anymore,
 832                  * so remove it from the endpoint ring's TD list.  Keep it in
 833                  * the cancelled TD list for URB completion later.
 834                  */
 835                 list_del_init(&cur_td->td_list);
 836         }
 837         last_unlinked_td = cur_td;
 838         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 839
 840         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 841         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 842                 xhci_queue_new_dequeue_state(xhci,
 843                                 slot_id, ep_index,
 844                                 ep->stopped_td->urb->stream_id,
 845                                 &deq_state);
 846                 xhci_ring_cmd_db(xhci);
 847         } else {
 848                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 849                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 850         }
 851         ep->stopped_td = NULL;
 852         ep->stopped_trb = NULL;
 853
 854         /*
 855          * Drop the lock and complete the URBs in the cancelled TD list.
 856          * New TDs to be cancelled might be added to the end of the list before
 857          * we can complete all the URBs for the TDs we already unlinked.
 858          * So stop when we've completed the URB for the last TD we unlinked.
 859          */
 860         do {
 861                 cur_td = list_entry(ep->cancelled_td_list.next,
 862                                 struct xhci_td, cancelled_td_list);
 863                 list_del_init(&cur_td->cancelled_td_list);
 864
 865                 /* Clean up the cancelled URB */
 866                 /* Doesn't matter what we pass for status, since the core will
 867                  * just overwrite it (because the URB has been unlinked).
 868                  */
 869                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 870
 871                 /* Stop processing the cancelled list if the watchdog timer is
 872                  * running.
 873                  */
 874                 if (xhci->xhc_state & XHCI_STATE_DYING)
 875                         return;
 876         } while (cur_td != last_unlinked_td);
 877
 878         /* Return to the event handler with xhci->lock re-acquired */
 879 }
 880
 881 /* Watchdog timer function for when a stop endpoint command fails to complete.
 882  * In this case, we assume the host controller is broken or dying or dead.  The
 883  * host may still be completing some other events, so we have to be careful to
 884  * let the event ring handler and the URB dequeueing/enqueueing functions know
 885  * through xhci->state.
 886  *
 887  * The timer may also fire if the host takes a very long time to respond to the
 888  * command, and the stop endpoint command completion handler cannot delete the
 889  * timer before the timer function is called.  Another endpoint cancellation may
 890  * sneak in before the timer function can grab the lock, and that may queue
 891  * another stop endpoint command and add the timer back.  So we cannot use a
 892  * simple flag to say whether there is a pending stop endpoint command for a
 893  * particular endpoint.
 894  *
 895  * Instead we use a combination of that flag and a counter for the number of
 896  * pending stop endpoint commands.  If the timer is the tail end of the last
 897  * stop endpoint command, and the endpoint's command is still pending, we assume
 898  * the host is dying.
 899  */
 900 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 901 {
 902         struct xhci_hcd *xhci;
 903         struct xhci_virt_ep *ep;
 904         struct xhci_virt_ep *temp_ep;
 905         struct xhci_ring *ring;
 906         struct xhci_td *cur_td;
 907         int ret, i, j;
 908         unsigned long flags;
 909
 910         ep = (struct xhci_virt_ep *) arg;
 911         xhci = ep->xhci;
 912
 913         spin_lock_irqsave(&xhci->lock, flags);
 914
 915         ep->stop_cmds_pending--;
 916         if (xhci->xhc_state & XHCI_STATE_DYING) {
 917                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 918                                 "xHCI as DYING, exiting.\n");
 919                 spin_unlock_irqrestore(&xhci->lock, flags);
 920                 return;
 921         }
 922         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 923                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 924                                 "exiting.\n");
 925                 spin_unlock_irqrestore(&xhci->lock, flags);
 926                 return;
 927         }
 928
 929         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 930         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 931         /* Oops, HC is dead or dying or at least not responding to the stop
 932          * endpoint command.
 933          */
 934         xhci->xhc_state |= XHCI_STATE_DYING;
 935         /* Disable interrupts from the host controller and start halting it */
 936         xhci_quiesce(xhci);
 937         spin_unlock_irqrestore(&xhci->lock, flags);
 938
 939         ret = xhci_halt(xhci);
 940
 941         spin_lock_irqsave(&xhci->lock, flags);
 942         if (ret < 0) {
 943                 /* This is bad; the host is not responding to commands and it's
 944                  * not allowing itself to be halted.  At least interrupts are
 945                  * disabled. If we call usb_hc_died(), it will attempt to
 946                  * disconnect all device drivers under this host.  Those
 947                  * disconnect() methods will wait for all URBs to be unlinked,
 948                  * so we must complete them.
 949                  */
 950                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 951                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 952                 /* We could turn all TDs on the rings to no-ops.  This won't
 953                  * help if the host has cached part of the ring, and is slow if
 954                  * we want to preserve the cycle bit.  Skip it and hope the host
 955                  * doesn't touch the memory.
 956                  */
 957         }
 958         for (i = 0; i < MAX_HC_SLOTS; i++) {
 959                 if (!xhci->devs[i])
 960                         continue;
 961                 for (j = 0; j < 31; j++) {
 962                         temp_ep = &xhci->devs[i]->eps[j];
 963                         ring = temp_ep->ring;
 964                         if (!ring)
 965                                 continue;
 966                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 967                                         "ep index %u\n", i, j);
 968                         while (!list_empty(&ring->td_list)) {
 969                                 cur_td = list_first_entry(&ring->td_list,
 970                                                 struct xhci_td,
 971                                                 td_list);
 972                                 list_del_init(&cur_td->td_list);
 973                                 if (!list_empty(&cur_td->cancelled_td_list))
 974                                         list_del_init(&cur_td->cancelled_td_list);
 975                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 976                                                 -ESHUTDOWN, "killed");
 977                         }
 978                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 979                                 cur_td = list_first_entry(
 980                                                 &temp_ep->cancelled_td_list,
 981                                                 struct xhci_td,
 982                                                 cancelled_td_list);
 983                                 list_del_init(&cur_td->cancelled_td_list);
 984                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 985                                                 -ESHUTDOWN, "killed");
 986                         }
 987                 }
 988         }
 989         spin_unlock_irqrestore(&xhci->lock, flags);
 990         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 991         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 992         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 993 }
 994
 995
 996 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
 997                 struct xhci_virt_device *dev,
 998                 struct xhci_ring *ep_ring,
 999                 unsigned int ep_index)
1000 {
1001         union xhci_trb *dequeue_temp;
1002         int num_trbs_free_temp;
1003         bool revert = false;
1004
1005         num_trbs_free_temp = ep_ring->num_trbs_free;
1006         dequeue_temp = ep_ring->dequeue;
1007
1008         /* If we get two back-to-back stalls, and the first stalled transfer
1009          * ends just before a link TRB, the dequeue pointer will be left on
1010          * the link TRB by the code in the while loop.  So we have to update
1011          * the dequeue pointer one segment further, or we'll jump off
1012          * the segment into la-la-land.
1013          */
1014         if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
1015                 ep_ring->deq_seg = ep_ring->deq_seg->next;
1016                 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1017         }
1018
1019         while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1020                 /* We have more usable TRBs */
1021                 ep_ring->num_trbs_free++;
1022                 ep_ring->dequeue++;
1023                 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
1024                                 ep_ring->dequeue)) {
1025                         if (ep_ring->dequeue ==
1026                                         dev->eps[ep_index].queued_deq_ptr)
1027                                 break;
1028                         ep_ring->deq_seg = ep_ring->deq_seg->next;
1029                         ep_ring->dequeue = ep_ring->deq_seg->trbs;
1030                 }
1031                 if (ep_ring->dequeue == dequeue_temp) {
1032                         revert = true;
1033                         break;
1034                 }
1035         }
1036
1037         if (revert) {
1038                 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1039                 ep_ring->num_trbs_free = num_trbs_free_temp;
1040         }
1041 }
1042
1043 /*
1044  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1045  * we need to clear the set deq pending flag in the endpoint ring state, so that
1046  * the TD queueing code can ring the doorbell again.  We also need to ring the
1047  * endpoint doorbell to restart the ring, but only if there aren't more
1048  * cancellations pending.
1049  */
1050 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1051                 struct xhci_event_cmd *event,
1052                 union xhci_trb *trb)
1053 {
1054         unsigned int slot_id;
1055         unsigned int ep_index;
1056         unsigned int stream_id;
1057         struct xhci_ring *ep_ring;
1058         struct xhci_virt_device *dev;
1059         struct xhci_ep_ctx *ep_ctx;
1060         struct xhci_slot_ctx *slot_ctx;
1061
1062         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1063         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1064         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1065         dev = xhci->devs[slot_id];
1066
1067         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1068         if (!ep_ring) {
1069                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1070                                 "freed stream ID %u\n",
1071                                 stream_id);
1072                 /* XXX: Harmless??? */
1073                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1074                 return;
1075         }
1076
1077         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1078         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1079
1080         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1081                 unsigned int ep_state;
1082                 unsigned int slot_state;
1083
1084                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1085                 case COMP_TRB_ERR:
1086                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1087                                         "of stream ID configuration\n");
1088                         break;
1089                 case COMP_CTX_STATE:
1090                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1091                                         "to incorrect slot or ep state.\n");
1092                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1093                         ep_state &= EP_STATE_MASK;
1094                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1095                         slot_state = GET_SLOT_STATE(slot_state);
1096                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1097                                         slot_state, ep_state);
1098                         break;
1099                 case COMP_EBADSLT:
1100                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1101                                         "slot %u was not enabled.\n", slot_id);
1102                         break;
1103                 default:
1104                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1105                                         "completion code of %u.\n",
1106                                   GET_COMP_CODE(le32_to_cpu(event->status)));
1107                         break;
1108                 }
1109                 /* OK what do we do now?  The endpoint state is hosed, and we
1110                  * should never get to this point if the synchronization between
1111                  * queueing, and endpoint state are correct.  This might happen
1112                  * if the device gets disconnected after we've finished
1113                  * cancelling URBs, which might not be an error...
1114                  */
1115         } else {
1116                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1117                          le64_to_cpu(ep_ctx->deq));
1118                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1119                                          dev->eps[ep_index].queued_deq_ptr) ==
1120                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1121                         /* Update the ring's dequeue segment and dequeue pointer
1122                          * to reflect the new position.
1123                          */
1124                         update_ring_for_set_deq_completion(xhci, dev,
1125                                 ep_ring, ep_index);
1126                 } else {
1127                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1128                                         "Ptr command & xHCI internal state.\n");
1129                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1130                                         dev->eps[ep_index].queued_deq_seg,
1131                                         dev->eps[ep_index].queued_deq_ptr);
1132                 }
1133         }
1134
1135         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1136         dev->eps[ep_index].queued_deq_seg = NULL;
1137         dev->eps[ep_index].queued_deq_ptr = NULL;
1138         /* Restart any rings with pending URBs */
1139         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1140 }
1141
1142 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1143                 struct xhci_event_cmd *event,
1144                 union xhci_trb *trb)
1145 {
1146         int slot_id;
1147         unsigned int ep_index;
1148
1149         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1150         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1151         /* This command will only fail if the endpoint wasn't halted,
1152          * but we don't care.
1153          */
1154         xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1155                 "Ignoring reset ep completion code of %u",
1156                  GET_COMP_CODE(le32_to_cpu(event->status)));
1157
1158         /* HW with the reset endpoint quirk needs to have a configure endpoint
1159          * command complete before the endpoint can be used.  Queue that here
1160          * because the HW can't handle two commands being queued in a row.
1161          */
1162         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1163                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1164                                 "Queueing configure endpoint command");
1165                 xhci_queue_configure_endpoint(xhci,
1166                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1167                                 false);
1168                 xhci_ring_cmd_db(xhci);
1169         } else {
1170                 /* Clear our internal halted state and restart the ring(s) */
1171                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1172                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1173         }
1174 }
1175
1176 /* Complete the command and detele it from the devcie's command queue.
1177  */
1178 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1179                 struct xhci_command *command, u32 status)
1180 {
1181         command->status = status;
1182         list_del(&command->cmd_list);
1183         if (command->completion)
1184                 complete(command->completion);
1185         else
1186                 xhci_free_command(xhci, command);
1187 }
1188
1189
1190 /* Check to see if a command in the device's command queue matches this one.
1191  * Signal the completion or free the command, and return 1.  Return 0 if the
1192  * completed command isn't at the head of the command list.
1193  */
1194 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1195                 struct xhci_virt_device *virt_dev,
1196                 struct xhci_event_cmd *event)
1197 {
1198         struct xhci_command *command;
1199
1200         if (list_empty(&virt_dev->cmd_list))
1201                 return 0;
1202
1203         command = list_entry(virt_dev->cmd_list.next,
1204                         struct xhci_command, cmd_list);
1205         if (xhci->cmd_ring->dequeue != command->command_trb)
1206                 return 0;
1207
1208         xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1209                         GET_COMP_CODE(le32_to_cpu(event->status)));
1210         return 1;
1211 }
1212
1213 /*
1214  * Finding the command trb need to be cancelled and modifying it to
1215  * NO OP command. And if the command is in device's command wait
1216  * list, finishing and freeing it.
1217  *
1218  * If we can't find the command trb, we think it had already been
1219  * executed.
1220  */
1221 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1222 {
1223         struct xhci_segment *cur_seg;
1224         union xhci_trb *cmd_trb;
1225         u32 cycle_state;
1226
1227         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1228                 return;
1229
1230         /* find the current segment of command ring */
1231         cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1232                         xhci->cmd_ring->dequeue, &cycle_state);
1233
1234         if (!cur_seg) {
1235                 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1236                                 xhci->cmd_ring->dequeue,
1237                                 (unsigned long long)
1238                                 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1239                                         xhci->cmd_ring->dequeue));
1240                 xhci_debug_ring(xhci, xhci->cmd_ring);
1241                 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1242                 return;
1243         }
1244
1245         /* find the command trb matched by cd from command ring */
1246         for (cmd_trb = xhci->cmd_ring->dequeue;
1247                         cmd_trb != xhci->cmd_ring->enqueue;
1248                         next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1249                 /* If the trb is link trb, continue */
1250                 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1251                         continue;
1252
1253                 if (cur_cd->cmd_trb == cmd_trb) {
1254
1255                         /* If the command in device's command list, we should
1256                          * finish it and free the command structure.
1257                          */
1258                         if (cur_cd->command)
1259                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1260                                         cur_cd->command, COMP_CMD_STOP);
1261
1262                         /* get cycle state from the origin command trb */
1263                         cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1264                                 & TRB_CYCLE;
1265
1266                         /* modify the command trb to NO OP command */
1267                         cmd_trb->generic.field[0] = 0;
1268                         cmd_trb->generic.field[1] = 0;
1269                         cmd_trb->generic.field[2] = 0;
1270                         cmd_trb->generic.field[3] = cpu_to_le32(
1271                                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1272                         break;
1273                 }
1274         }
1275 }
1276
1277 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1278 {
1279         struct xhci_cd *cur_cd, *next_cd;
1280
1281         if (list_empty(&xhci->cancel_cmd_list))
1282                 return;
1283
1284         list_for_each_entry_safe(cur_cd, next_cd,
1285                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1286                 xhci_cmd_to_noop(xhci, cur_cd);
1287                 list_del(&cur_cd->cancel_cmd_list);
1288                 kfree(cur_cd);
1289         }
1290 }
1291
1292 /*
1293  * traversing the cancel_cmd_list. If the command descriptor according
1294  * to cmd_trb is found, the function free it and return 1, otherwise
1295  * return 0.
1296  */
1297 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1298                 union xhci_trb *cmd_trb)
1299 {
1300         struct xhci_cd *cur_cd, *next_cd;
1301
1302         if (list_empty(&xhci->cancel_cmd_list))
1303                 return 0;
1304
1305         list_for_each_entry_safe(cur_cd, next_cd,
1306                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1307                 if (cur_cd->cmd_trb == cmd_trb) {
1308                         if (cur_cd->command)
1309                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1310                                         cur_cd->command, COMP_CMD_STOP);
1311                         list_del(&cur_cd->cancel_cmd_list);
1312                         kfree(cur_cd);
1313                         return 1;
1314                 }
1315         }
1316
1317         return 0;
1318 }
1319
1320 /*
1321  * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1322  * trb pointed by the command ring dequeue pointer is the trb we want to
1323  * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1324  * traverse the cancel_cmd_list to trun the all of the commands according
1325  * to command descriptor to NO-OP trb.
1326  */
1327 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1328                 int cmd_trb_comp_code)
1329 {
1330         int cur_trb_is_good = 0;
1331
1332         /* Searching the cmd trb pointed by the command ring dequeue
1333          * pointer in command descriptor list. If it is found, free it.
1334          */
1335         cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1336                         xhci->cmd_ring->dequeue);
1337
1338         if (cmd_trb_comp_code == COMP_CMD_ABORT)
1339                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1340         else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1341                 /* traversing the cancel_cmd_list and canceling
1342                  * the command according to command descriptor
1343                  */
1344                 xhci_cancel_cmd_in_cd_list(xhci);
1345
1346                 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1347                 /*
1348                  * ring command ring doorbell again to restart the
1349                  * command ring
1350                  */
1351                 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1352                         xhci_ring_cmd_db(xhci);
1353         }
1354         return cur_trb_is_good;
1355 }
1356
1357 static void handle_cmd_completion(struct xhci_hcd *xhci,
1358                 struct xhci_event_cmd *event)
1359 {
1360         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1361         u64 cmd_dma;
1362         dma_addr_t cmd_dequeue_dma;
1363         struct xhci_input_control_ctx *ctrl_ctx;
1364         struct xhci_virt_device *virt_dev;
1365         unsigned int ep_index;
1366         struct xhci_ring *ep_ring;
1367         unsigned int ep_state;
1368
1369         cmd_dma = le64_to_cpu(event->cmd_trb);
1370         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1371                         xhci->cmd_ring->dequeue);
1372         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1373         if (cmd_dequeue_dma == 0) {
1374                 xhci->error_bitmask |= 1 << 4;
1375                 return;
1376         }
1377         /* Does the DMA address match our internal dequeue pointer address? */
1378         if (cmd_dma != (u64) cmd_dequeue_dma) {
1379                 xhci->error_bitmask |= 1 << 5;
1380                 return;
1381         }
1382
1383         trace_xhci_cmd_completion(&xhci->cmd_ring->dequeue->generic,
1384                                         (struct xhci_generic_trb *) event);
1385
1386         if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1387                 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1388                 /* If the return value is 0, we think the trb pointed by
1389                  * command ring dequeue pointer is a good trb. The good
1390                  * trb means we don't want to cancel the trb, but it have
1391                  * been stopped by host. So we should handle it normally.
1392                  * Otherwise, driver should invoke inc_deq() and return.
1393                  */
1394                 if (handle_stopped_cmd_ring(xhci,
1395                                 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1396                         inc_deq(xhci, xhci->cmd_ring);
1397                         return;
1398                 }
1399         }
1400
1401         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1402                 & TRB_TYPE_BITMASK) {
1403         case TRB_TYPE(TRB_ENABLE_SLOT):
1404                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1405                         xhci->slot_id = slot_id;
1406                 else
1407                         xhci->slot_id = 0;
1408                 complete(&xhci->addr_dev);
1409                 break;
1410         case TRB_TYPE(TRB_DISABLE_SLOT):
1411                 if (xhci->devs[slot_id]) {
1412                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1413                                 /* Delete default control endpoint resources */
1414                                 xhci_free_device_endpoint_resources(xhci,
1415                                                 xhci->devs[slot_id], true);
1416                         xhci_free_virt_device(xhci, slot_id);
1417                 }
1418                 break;
1419         case TRB_TYPE(TRB_CONFIG_EP):
1420                 virt_dev = xhci->devs[slot_id];
1421                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1422                         break;
1423                 /*
1424                  * Configure endpoint commands can come from the USB core
1425                  * configuration or alt setting changes, or because the HW
1426                  * needed an extra configure endpoint command after a reset
1427                  * endpoint command or streams were being configured.
1428                  * If the command was for a halted endpoint, the xHCI driver
1429                  * is not waiting on the configure endpoint command.
1430                  */
1431                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1432                                 virt_dev->in_ctx);
1433                 if (!ctrl_ctx) {
1434                         xhci_warn(xhci, "Could not get input context, bad type.\n");
1435                         break;
1436                 }
1437                 /* Input ctx add_flags are the endpoint index plus one */
1438                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1439                 /* A usb_set_interface() call directly after clearing a halted
1440                  * condition may race on this quirky hardware.  Not worth
1441                  * worrying about, since this is prototype hardware.  Not sure
1442                  * if this will work for streams, but streams support was
1443                  * untested on this prototype.
1444                  */
1445                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1446                                 ep_index != (unsigned int) -1 &&
1447                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1448                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1449                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1450                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1451                         if (!(ep_state & EP_HALTED))
1452                                 goto bandwidth_change;
1453                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1454                                         "Completed config ep cmd - "
1455                                         "last ep index = %d, state = %d",
1456                                         ep_index, ep_state);
1457                         /* Clear internal halted state and restart ring(s) */
1458                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1459                                 ~EP_HALTED;
1460                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1461                         break;
1462                 }
1463 bandwidth_change:
1464                 xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,
1465                                 "Completed config ep cmd");
1466                 xhci->devs[slot_id]->cmd_status =
1467                         GET_COMP_CODE(le32_to_cpu(event->status));
1468                 complete(&xhci->devs[slot_id]->cmd_completion);
1469                 break;
1470         case TRB_TYPE(TRB_EVAL_CONTEXT):
1471                 virt_dev = xhci->devs[slot_id];
1472                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1473                         break;
1474                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1475                 complete(&xhci->devs[slot_id]->cmd_completion);
1476                 break;
1477         case TRB_TYPE(TRB_ADDR_DEV):
1478                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1479                 complete(&xhci->addr_dev);
1480                 break;
1481         case TRB_TYPE(TRB_STOP_RING):
1482                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1483                 break;
1484         case TRB_TYPE(TRB_SET_DEQ):
1485                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1486                 break;
1487         case TRB_TYPE(TRB_CMD_NOOP):
1488                 break;
1489         case TRB_TYPE(TRB_RESET_EP):
1490                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1491                 break;
1492         case TRB_TYPE(TRB_RESET_DEV):
1493                 xhci_dbg(xhci, "Completed reset device command.\n");
1494                 slot_id = TRB_TO_SLOT_ID(
1495                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1496                 virt_dev = xhci->devs[slot_id];
1497                 if (virt_dev)
1498                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1499                 else
1500                         xhci_warn(xhci, "Reset device command completion "
1501                                         "for disabled slot %u\n", slot_id);
1502                 break;
1503         case TRB_TYPE(TRB_NEC_GET_FW):
1504                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1505                         xhci->error_bitmask |= 1 << 6;
1506                         break;
1507                 }
1508                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1509                         "NEC firmware version %2x.%02x",
1510                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1511                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1512                 break;
1513         default:
1514                 /* Skip over unknown commands on the event ring */
1515                 xhci->error_bitmask |= 1 << 6;
1516                 break;
1517         }
1518         inc_deq(xhci, xhci->cmd_ring);
1519 }
1520
1521 static void handle_vendor_event(struct xhci_hcd *xhci,
1522                 union xhci_trb *event)
1523 {
1524         u32 trb_type;
1525
1526         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1527         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1528         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1529                 handle_cmd_completion(xhci, &event->event_cmd);
1530 }
1531
1532 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1533  * port registers -- USB 3.0 and USB 2.0).
1534  *
1535  * Returns a zero-based port number, which is suitable for indexing into each of
1536  * the split roothubs' port arrays and bus state arrays.
1537  * Add one to it in order to call xhci_find_slot_id_by_port.
1538  */
1539 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1540                 struct xhci_hcd *xhci, u32 port_id)
1541 {
1542         unsigned int i;
1543         unsigned int num_similar_speed_ports = 0;
1544
1545         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1546          * and usb2_ports are 0-based indexes.  Count the number of similar
1547          * speed ports, up to 1 port before this port.
1548          */
1549         for (i = 0; i < (port_id - 1); i++) {
1550                 u8 port_speed = xhci->port_array[i];
1551
1552                 /*
1553                  * Skip ports that don't have known speeds, or have duplicate
1554                  * Extended Capabilities port speed entries.
1555                  */
1556                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1557                         continue;
1558
1559                 /*
1560                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1561                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1562                  * matches the device speed, it's a similar speed port.
1563                  */
1564                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1565                         num_similar_speed_ports++;
1566         }
1567         return num_similar_speed_ports;
1568 }
1569
1570 static void handle_device_notification(struct xhci_hcd *xhci,
1571                 union xhci_trb *event)
1572 {
1573         u32 slot_id;
1574         struct usb_device *udev;
1575
1576         slot_id = TRB_TO_SLOT_ID(event->generic.field[3]);
1577         if (!xhci->devs[slot_id]) {
1578                 xhci_warn(xhci, "Device Notification event for "
1579                                 "unused slot %u\n", slot_id);
1580                 return;
1581         }
1582
1583         xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1584                         slot_id);
1585         udev = xhci->devs[slot_id]->udev;
1586         if (udev && udev->parent)
1587                 usb_wakeup_notification(udev->parent, udev->portnum);
1588 }
1589
1590 static void handle_port_status(struct xhci_hcd *xhci,
1591                 union xhci_trb *event)
1592 {
1593         struct usb_hcd *hcd;
1594         u32 port_id;
1595         u32 temp, temp1;
1596         int max_ports;
1597         int slot_id;
1598         unsigned int faked_port_index;
1599         u8 major_revision;
1600         struct xhci_bus_state *bus_state;
1601         __le32 __iomem **port_array;
1602         bool bogus_port_status = false;
1603
1604         /* Port status change events always have a successful completion code */
1605         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1606                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1607                 xhci->error_bitmask |= 1 << 8;
1608         }
1609         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1610         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1611
1612         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1613         if ((port_id <= 0) || (port_id > max_ports)) {
1614                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1615                 inc_deq(xhci, xhci->event_ring);
1616                 return;
1617         }
1618
1619         /* Figure out which usb_hcd this port is attached to:
1620          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1621          */
1622         major_revision = xhci->port_array[port_id - 1];
1623
1624         /* Find the right roothub. */
1625         hcd = xhci_to_hcd(xhci);
1626         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1627                 hcd = xhci->shared_hcd;
1628
1629         if (major_revision == 0) {
1630                 xhci_warn(xhci, "Event for port %u not in "
1631                                 "Extended Capabilities, ignoring.\n",
1632                                 port_id);
1633                 bogus_port_status = true;
1634                 goto cleanup;
1635         }
1636         if (major_revision == DUPLICATE_ENTRY) {
1637                 xhci_warn(xhci, "Event for port %u duplicated in"
1638                                 "Extended Capabilities, ignoring.\n",
1639                                 port_id);
1640                 bogus_port_status = true;
1641                 goto cleanup;
1642         }
1643
1644         /*
1645          * Hardware port IDs reported by a Port Status Change Event include USB
1646          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1647          * resume event, but we first need to translate the hardware port ID
1648          * into the index into the ports on the correct split roothub, and the
1649          * correct bus_state structure.
1650          */
1651         bus_state = &xhci->bus_state[hcd_index(hcd)];
1652         if (hcd->speed == HCD_USB3)
1653                 port_array = xhci->usb3_ports;
1654         else
1655                 port_array = xhci->usb2_ports;
1656         /* Find the faked port hub number */
1657         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1658                         port_id);
1659
1660         temp = xhci_readl(xhci, port_array[faked_port_index]);
1661         if (hcd->state == HC_STATE_SUSPENDED) {
1662                 xhci_dbg(xhci, "resume root hub\n");
1663                 usb_hcd_resume_root_hub(hcd);
1664         }
1665
1666         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1667                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1668
1669                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1670                 if (!(temp1 & CMD_RUN)) {
1671                         xhci_warn(xhci, "xHC is not running.\n");
1672                         goto cleanup;
1673                 }
1674
1675                 if (DEV_SUPERSPEED(temp)) {
1676                         xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1677                         /* Set a flag to say the port signaled remote wakeup,
1678                          * so we can tell the difference between the end of
1679                          * device and host initiated resume.
1680                          */
1681                         bus_state->port_remote_wakeup |= 1 << faked_port_index;
1682                         xhci_test_and_clear_bit(xhci, port_array,
1683                                         faked_port_index, PORT_PLC);
1684                         xhci_set_link_state(xhci, port_array, faked_port_index,
1685                                                 XDEV_U0);
1686                         /* Need to wait until the next link state change
1687                          * indicates the device is actually in U0.
1688                          */
1689                         bogus_port_status = true;
1690                         goto cleanup;
1691                 } else {
1692                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1693                         bus_state->resume_done[faked_port_index] = jiffies +
1694                                 msecs_to_jiffies(20);
1695                         set_bit(faked_port_index, &bus_state->resuming_ports);
1696                         mod_timer(&hcd->rh_timer,
1697                                   bus_state->resume_done[faked_port_index]);
1698                         /* Do the rest in GetPortStatus */
1699                 }
1700         }
1701
1702         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1703                         DEV_SUPERSPEED(temp)) {
1704                 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1705                 /* We've just brought the device into U0 through either the
1706                  * Resume state after a device remote wakeup, or through the
1707                  * U3Exit state after a host-initiated resume.  If it's a device
1708                  * initiated remote wake, don't pass up the link state change,
1709                  * so the roothub behavior is consistent with external
1710                  * USB 3.0 hub behavior.
1711                  */
1712                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1713                                 faked_port_index + 1);
1714                 if (slot_id && xhci->devs[slot_id])
1715                         xhci_ring_device(xhci, slot_id);
1716                 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1717                         bus_state->port_remote_wakeup &=
1718                                 ~(1 << faked_port_index);
1719                         xhci_test_and_clear_bit(xhci, port_array,
1720                                         faked_port_index, PORT_PLC);
1721                         usb_wakeup_notification(hcd->self.root_hub,
1722                                         faked_port_index + 1);
1723                         bogus_port_status = true;
1724                         goto cleanup;
1725                 }
1726         }
1727
1728         if (hcd->speed != HCD_USB3)
1729                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1730                                         PORT_PLC);
1731
1732 cleanup:
1733         /* Update event ring dequeue pointer before dropping the lock */
1734         inc_deq(xhci, xhci->event_ring);
1735
1736         /* Don't make the USB core poll the roothub if we got a bad port status
1737          * change event.  Besides, at that point we can't tell which roothub
1738          * (USB 2.0 or USB 3.0) to kick.
1739          */
1740         if (bogus_port_status)
1741                 return;
1742
1743         /*
1744          * xHCI port-status-change events occur when the "or" of all the
1745          * status-change bits in the portsc register changes from 0 to 1.
1746          * New status changes won't cause an event if any other change
1747          * bits are still set.  When an event occurs, switch over to
1748          * polling to avoid losing status changes.
1749          */
1750         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1751         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1752         spin_unlock(&xhci->lock);
1753         /* Pass this up to the core */
1754         usb_hcd_poll_rh_status(hcd);
1755         spin_lock(&xhci->lock);
1756 }
1757
1758 /*
1759  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1760  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1761  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1762  * returns 0.
1763  */
1764 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1765                 union xhci_trb  *start_trb,
1766                 union xhci_trb  *end_trb,
1767                 dma_addr_t      suspect_dma)
1768 {
1769         dma_addr_t start_dma;
1770         dma_addr_t end_seg_dma;
1771         dma_addr_t end_trb_dma;
1772         struct xhci_segment *cur_seg;
1773
1774         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1775         cur_seg = start_seg;
1776
1777         do {
1778                 if (start_dma == 0)
1779                         return NULL;
1780                 /* We may get an event for a Link TRB in the middle of a TD */
1781                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1782                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1783                 /* If the end TRB isn't in this segment, this is set to 0 */
1784                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1785
1786                 if (end_trb_dma > 0) {
1787                         /* The end TRB is in this segment, so suspect should be here */
1788                         if (start_dma <= end_trb_dma) {
1789                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1790                                         return cur_seg;
1791                         } else {
1792                                 /* Case for one segment with
1793                                  * a TD wrapped around to the top
1794                                  */
1795                                 if ((suspect_dma >= start_dma &&
1796                                                         suspect_dma <= end_seg_dma) ||
1797                                                 (suspect_dma >= cur_seg->dma &&
1798                                                  suspect_dma <= end_trb_dma))
1799                                         return cur_seg;
1800                         }
1801                         return NULL;
1802                 } else {
1803                         /* Might still be somewhere in this segment */
1804                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1805                                 return cur_seg;
1806                 }
1807                 cur_seg = cur_seg->next;
1808                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1809         } while (cur_seg != start_seg);
1810
1811         return NULL;
1812 }
1813
1814 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1815                 unsigned int slot_id, unsigned int ep_index,
1816                 unsigned int stream_id,
1817                 struct xhci_td *td, union xhci_trb *event_trb)
1818 {
1819         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1820         ep->ep_state |= EP_HALTED;
1821         ep->stopped_td = td;
1822         ep->stopped_trb = event_trb;
1823         ep->stopped_stream = stream_id;
1824
1825         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1826         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1827
1828         ep->stopped_td = NULL;
1829         ep->stopped_trb = NULL;
1830         ep->stopped_stream = 0;
1831
1832         xhci_ring_cmd_db(xhci);
1833 }
1834
1835 /* Check if an error has halted the endpoint ring.  The class driver will
1836  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1837  * However, a babble and other errors also halt the endpoint ring, and the class
1838  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1839  * Ring Dequeue Pointer command manually.
1840  */
1841 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1842                 struct xhci_ep_ctx *ep_ctx,
1843                 unsigned int trb_comp_code)
1844 {
1845         /* TRB completion codes that may require a manual halt cleanup */
1846         if (trb_comp_code == COMP_TX_ERR ||
1847                         trb_comp_code == COMP_BABBLE ||
1848                         trb_comp_code == COMP_SPLIT_ERR)
1849                 /* The 0.96 spec says a babbling control endpoint
1850                  * is not halted. The 0.96 spec says it is.  Some HW
1851                  * claims to be 0.95 compliant, but it halts the control
1852                  * endpoint anyway.  Check if a babble halted the
1853                  * endpoint.
1854                  */
1855                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1856                     cpu_to_le32(EP_STATE_HALTED))
1857                         return 1;
1858
1859         return 0;
1860 }
1861
1862 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1863 {
1864         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1865                 /* Vendor defined "informational" completion code,
1866                  * treat as not-an-error.
1867                  */
1868                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1869                                 trb_comp_code);
1870                 xhci_dbg(xhci, "Treating code as success.\n");
1871                 return 1;
1872         }
1873         return 0;
1874 }
1875
1876 /*
1877  * Finish the td processing, remove the td from td list;
1878  * Return 1 if the urb can be given back.
1879  */
1880 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1881         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1882         struct xhci_virt_ep *ep, int *status, bool skip)
1883 {
1884         struct xhci_virt_device *xdev;
1885         struct xhci_ring *ep_ring;
1886         unsigned int slot_id;
1887         int ep_index;
1888         struct urb *urb = NULL;
1889         struct xhci_ep_ctx *ep_ctx;
1890         int ret = 0;
1891         struct urb_priv *urb_priv;
1892         u32 trb_comp_code;
1893
1894         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1895         xdev = xhci->devs[slot_id];
1896         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1897         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1898         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1899         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1900
1901         if (skip)
1902                 goto td_cleanup;
1903
1904         if (trb_comp_code == COMP_STOP_INVAL ||
1905                         trb_comp_code == COMP_STOP) {
1906                 /* The Endpoint Stop Command completion will take care of any
1907                  * stopped TDs.  A stopped TD may be restarted, so don't update
1908                  * the ring dequeue pointer or take this TD off any lists yet.
1909                  */
1910                 ep->stopped_td = td;
1911                 ep->stopped_trb = event_trb;
1912                 return 0;
1913         } else {
1914                 if (trb_comp_code == COMP_STALL) {
1915                         /* The transfer is completed from the driver's
1916                          * perspective, but we need to issue a set dequeue
1917                          * command for this stalled endpoint to move the dequeue
1918                          * pointer past the TD.  We can't do that here because
1919                          * the halt condition must be cleared first.  Let the
1920                          * USB class driver clear the stall later.
1921                          */
1922                         ep->stopped_td = td;
1923                         ep->stopped_trb = event_trb;
1924                         ep->stopped_stream = ep_ring->stream_id;
1925                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1926                                         ep_ctx, trb_comp_code)) {
1927                         /* Other types of errors halt the endpoint, but the
1928                          * class driver doesn't call usb_reset_endpoint() unless
1929                          * the error is -EPIPE.  Clear the halted status in the
1930                          * xHCI hardware manually.
1931                          */
1932                         xhci_cleanup_halted_endpoint(xhci,
1933                                         slot_id, ep_index, ep_ring->stream_id,
1934                                         td, event_trb);
1935                 } else {
1936                         /* Update ring dequeue pointer */
1937                         while (ep_ring->dequeue != td->last_trb)
1938                                 inc_deq(xhci, ep_ring);
1939                         inc_deq(xhci, ep_ring);
1940                 }
1941
1942 td_cleanup:
1943                 /* Clean up the endpoint's TD list */
1944                 urb = td->urb;
1945                 urb_priv = urb->hcpriv;
1946
1947                 /* Do one last check of the actual transfer length.
1948                  * If the host controller said we transferred more data than
1949                  * the buffer length, urb->actual_length will be a very big
1950                  * number (since it's unsigned).  Play it safe and say we didn't
1951                  * transfer anything.
1952                  */
1953                 if (urb->actual_length > urb->transfer_buffer_length) {
1954                         xhci_warn(xhci, "URB transfer length is wrong, "
1955                                         "xHC issue? req. len = %u, "
1956                                         "act. len = %u\n",
1957                                         urb->transfer_buffer_length,
1958                                         urb->actual_length);
1959                         urb->actual_length = 0;
1960                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1961                                 *status = -EREMOTEIO;
1962                         else
1963                                 *status = 0;
1964                 }
1965                 list_del_init(&td->td_list);
1966                 /* Was this TD slated to be cancelled but completed anyway? */
1967                 if (!list_empty(&td->cancelled_td_list))
1968                         list_del_init(&td->cancelled_td_list);
1969
1970                 urb_priv->td_cnt++;
1971                 /* Giveback the urb when all the tds are completed */
1972                 if (urb_priv->td_cnt == urb_priv->length) {
1973                         ret = 1;
1974                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1975                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1976                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1977                                         == 0) {
1978                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1979                                                 usb_amd_quirk_pll_enable();
1980                                 }
1981                         }
1982                 }
1983         }
1984
1985         return ret;
1986 }
1987
1988 /*
1989  * Process control tds, update urb status and actual_length.
1990  */
1991 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1992         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1993         struct xhci_virt_ep *ep, int *status)
1994 {
1995         struct xhci_virt_device *xdev;
1996         struct xhci_ring *ep_ring;
1997         unsigned int slot_id;
1998         int ep_index;
1999         struct xhci_ep_ctx *ep_ctx;
2000         u32 trb_comp_code;
2001
2002         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2003         xdev = xhci->devs[slot_id];
2004         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2005         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2006         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2007         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2008
2009         switch (trb_comp_code) {
2010         case COMP_SUCCESS:
2011                 if (event_trb == ep_ring->dequeue) {
2012                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
2013                                         "without IOC set??\n");
2014                         *status = -ESHUTDOWN;
2015                 } else if (event_trb != td->last_trb) {
2016                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
2017                                         "without IOC set??\n");
2018                         *status = -ESHUTDOWN;
2019                 } else {
2020                         *status = 0;
2021                 }
2022                 break;
2023         case COMP_SHORT_TX:
2024                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2025                         *status = -EREMOTEIO;
2026                 else
2027                         *status = 0;
2028                 break;
2029         case COMP_STOP_INVAL:
2030         case COMP_STOP:
2031                 return finish_td(xhci, td, event_trb, event, ep, status, false);
2032         default:
2033                 if (!xhci_requires_manual_halt_cleanup(xhci,
2034                                         ep_ctx, trb_comp_code))
2035                         break;
2036                 xhci_dbg(xhci, "TRB error code %u, "
2037                                 "halted endpoint index = %u\n",
2038                                 trb_comp_code, ep_index);
2039                 /* else fall through */
2040         case COMP_STALL:
2041                 /* Did we transfer part of the data (middle) phase? */
2042                 if (event_trb != ep_ring->dequeue &&
2043                                 event_trb != td->last_trb)
2044                         td->urb->actual_length =
2045                                 td->urb->transfer_buffer_length -
2046                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2047                 else
2048                         td->urb->actual_length = 0;
2049
2050                 xhci_cleanup_halted_endpoint(xhci,
2051                         slot_id, ep_index, 0, td, event_trb);
2052                 return finish_td(xhci, td, event_trb, event, ep, status, true);
2053         }
2054         /*
2055          * Did we transfer any data, despite the errors that might have
2056          * happened?  I.e. did we get past the setup stage?
2057          */
2058         if (event_trb != ep_ring->dequeue) {
2059                 /* The event was for the status stage */
2060                 if (event_trb == td->last_trb) {
2061                         if (td->urb->actual_length != 0) {
2062                                 /* Don't overwrite a previously set error code
2063                                  */
2064                                 if ((*status == -EINPROGRESS || *status == 0) &&
2065                                                 (td->urb->transfer_flags
2066                                                  & URB_SHORT_NOT_OK))
2067                                         /* Did we already see a short data
2068                                          * stage? */
2069                                         *status = -EREMOTEIO;
2070                         } else {
2071                                 td->urb->actual_length =
2072                                         td->urb->transfer_buffer_length;
2073                         }
2074                 } else {
2075                 /* Maybe the event was for the data stage? */
2076                         td->urb->actual_length =
2077                                 td->urb->transfer_buffer_length -
2078                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2079                         xhci_dbg(xhci, "Waiting for status "
2080                                         "stage event\n");
2081                         return 0;
2082                 }
2083         }
2084
2085         return finish_td(xhci, td, event_trb, event, ep, status, false);
2086 }
2087
2088 /*
2089  * Process isochronous tds, update urb packet status and actual_length.
2090  */
2091 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2092         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2093         struct xhci_virt_ep *ep, int *status)
2094 {
2095         struct xhci_ring *ep_ring;
2096         struct urb_priv *urb_priv;
2097         int idx;
2098         int len = 0;
2099         union xhci_trb *cur_trb;
2100         struct xhci_segment *cur_seg;
2101         struct usb_iso_packet_descriptor *frame;
2102         u32 trb_comp_code;
2103         bool skip_td = false;
2104
2105         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2106         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2107         urb_priv = td->urb->hcpriv;
2108         idx = urb_priv->td_cnt;
2109         frame = &td->urb->iso_frame_desc[idx];
2110
2111         /* handle completion code */
2112         switch (trb_comp_code) {
2113         case COMP_SUCCESS:
2114                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2115                         frame->status = 0;
2116                         break;
2117                 }
2118                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2119                         trb_comp_code = COMP_SHORT_TX;
2120         case COMP_SHORT_TX:
2121                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2122                                 -EREMOTEIO : 0;
2123                 break;
2124         case COMP_BW_OVER:
2125                 frame->status = -ECOMM;
2126                 skip_td = true;
2127                 break;
2128         case COMP_BUFF_OVER:
2129         case COMP_BABBLE:
2130                 frame->status = -EOVERFLOW;
2131                 skip_td = true;
2132                 break;
2133         case COMP_DEV_ERR:
2134         case COMP_STALL:
2135         case COMP_TX_ERR:
2136                 frame->status = -EPROTO;
2137                 skip_td = true;
2138                 break;
2139         case COMP_STOP:
2140         case COMP_STOP_INVAL:
2141                 break;
2142         default:
2143                 frame->status = -1;
2144                 break;
2145         }
2146
2147         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2148                 frame->actual_length = frame->length;
2149                 td->urb->actual_length += frame->length;
2150         } else {
2151                 for (cur_trb = ep_ring->dequeue,
2152                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2153                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2154                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2155                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2156                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2157                 }
2158                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2159                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2160
2161                 if (trb_comp_code != COMP_STOP_INVAL) {
2162                         frame->actual_length = len;
2163                         td->urb->actual_length += len;
2164                 }
2165         }
2166
2167         return finish_td(xhci, td, event_trb, event, ep, status, false);
2168 }
2169
2170 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2171                         struct xhci_transfer_event *event,
2172                         struct xhci_virt_ep *ep, int *status)
2173 {
2174         struct xhci_ring *ep_ring;
2175         struct urb_priv *urb_priv;
2176         struct usb_iso_packet_descriptor *frame;
2177         int idx;
2178
2179         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2180         urb_priv = td->urb->hcpriv;
2181         idx = urb_priv->td_cnt;
2182         frame = &td->urb->iso_frame_desc[idx];
2183
2184         /* The transfer is partly done. */
2185         frame->status = -EXDEV;
2186
2187         /* calc actual length */
2188         frame->actual_length = 0;
2189
2190         /* Update ring dequeue pointer */
2191         while (ep_ring->dequeue != td->last_trb)
2192                 inc_deq(xhci, ep_ring);
2193         inc_deq(xhci, ep_ring);
2194
2195         return finish_td(xhci, td, NULL, event, ep, status, true);
2196 }
2197
2198 /*
2199  * Process bulk and interrupt tds, update urb status and actual_length.
2200  */
2201 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2202         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2203         struct xhci_virt_ep *ep, int *status)
2204 {
2205         struct xhci_ring *ep_ring;
2206         union xhci_trb *cur_trb;
2207         struct xhci_segment *cur_seg;
2208         u32 trb_comp_code;
2209
2210         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2211         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2212
2213         switch (trb_comp_code) {
2214         case COMP_SUCCESS:
2215                 /* Double check that the HW transferred everything. */
2216                 if (event_trb != td->last_trb ||
2217                     EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2218                         xhci_warn(xhci, "WARN Successful completion "
2219                                         "on short TX\n");
2220                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2221                                 *status = -EREMOTEIO;
2222                         else
2223                                 *status = 0;
2224                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2225                                 trb_comp_code = COMP_SHORT_TX;
2226                 } else {
2227                         *status = 0;
2228                 }
2229                 break;
2230         case COMP_SHORT_TX:
2231                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2232                         *status = -EREMOTEIO;
2233                 else
2234                         *status = 0;
2235                 break;
2236         default:
2237                 /* Others already handled above */
2238                 break;
2239         }
2240         if (trb_comp_code == COMP_SHORT_TX)
2241                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2242                                 "%d bytes untransferred\n",
2243                                 td->urb->ep->desc.bEndpointAddress,
2244                                 td->urb->transfer_buffer_length,
2245                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2246         /* Fast path - was this the last TRB in the TD for this URB? */
2247         if (event_trb == td->last_trb) {
2248                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2249                         td->urb->actual_length =
2250                                 td->urb->transfer_buffer_length -
2251                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2252                         if (td->urb->transfer_buffer_length <
2253                                         td->urb->actual_length) {
2254                                 xhci_warn(xhci, "HC gave bad length "
2255                                                 "of %d bytes left\n",
2256                                           EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2257                                 td->urb->actual_length = 0;
2258                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2259                                         *status = -EREMOTEIO;
2260                                 else
2261                                         *status = 0;
2262                         }
2263                         /* Don't overwrite a previously set error code */
2264                         if (*status == -EINPROGRESS) {
2265                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2266                                         *status = -EREMOTEIO;
2267                                 else
2268                                         *status = 0;
2269                         }
2270                 } else {
2271                         td->urb->actual_length =
2272                                 td->urb->transfer_buffer_length;
2273                         /* Ignore a short packet completion if the
2274                          * untransferred length was zero.
2275                          */
2276                         if (*status == -EREMOTEIO)
2277                                 *status = 0;
2278                 }
2279         } else {
2280                 /* Slow path - walk the list, starting from the dequeue
2281                  * pointer, to get the actual length transferred.
2282                  */
2283                 td->urb->actual_length = 0;
2284                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2285                                 cur_trb != event_trb;
2286                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2287                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2288                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2289                                 td->urb->actual_length +=
2290                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2291                 }
2292                 /* If the ring didn't stop on a Link or No-op TRB, add
2293                  * in the actual bytes transferred from the Normal TRB
2294                  */
2295                 if (trb_comp_code != COMP_STOP_INVAL)
2296                         td->urb->actual_length +=
2297                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2298                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2299         }
2300
2301         return finish_td(xhci, td, event_trb, event, ep, status, false);
2302 }
2303
2304 /*
2305  * If this function returns an error condition, it means it got a Transfer
2306  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2307  * At this point, the host controller is probably hosed and should be reset.
2308  */
2309 static int handle_tx_event(struct xhci_hcd *xhci,
2310                 struct xhci_transfer_event *event)
2311         __releases(&xhci->lock)
2312         __acquires(&xhci->lock)
2313 {
2314         struct xhci_virt_device *xdev;
2315         struct xhci_virt_ep *ep;
2316         struct xhci_ring *ep_ring;
2317         unsigned int slot_id;
2318         int ep_index;
2319         struct xhci_td *td = NULL;
2320         dma_addr_t event_dma;
2321         struct xhci_segment *event_seg;
2322         union xhci_trb *event_trb;
2323         struct urb *urb = NULL;
2324         int status = -EINPROGRESS;
2325         struct urb_priv *urb_priv;
2326         struct xhci_ep_ctx *ep_ctx;
2327         struct list_head *tmp;
2328         u32 trb_comp_code;
2329         int ret = 0;
2330         int td_num = 0;
2331
2332         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2333         xdev = xhci->devs[slot_id];
2334         if (!xdev) {
2335                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2336                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2337                          (unsigned long long) xhci_trb_virt_to_dma(
2338                                  xhci->event_ring->deq_seg,
2339                                  xhci->event_ring->dequeue),
2340                          lower_32_bits(le64_to_cpu(event->buffer)),
2341                          upper_32_bits(le64_to_cpu(event->buffer)),
2342                          le32_to_cpu(event->transfer_len),
2343                          le32_to_cpu(event->flags));
2344                 xhci_dbg(xhci, "Event ring:\n");
2345                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2346                 return -ENODEV;
2347         }
2348
2349         /* Endpoint ID is 1 based, our index is zero based */
2350         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2351         ep = &xdev->eps[ep_index];
2352         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2353         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2354         if (!ep_ring ||
2355             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2356             EP_STATE_DISABLED) {
2357                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2358                                 "or incorrect stream ring\n");
2359                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2360                          (unsigned long long) xhci_trb_virt_to_dma(
2361                                  xhci->event_ring->deq_seg,
2362                                  xhci->event_ring->dequeue),
2363                          lower_32_bits(le64_to_cpu(event->buffer)),
2364                          upper_32_bits(le64_to_cpu(event->buffer)),
2365                          le32_to_cpu(event->transfer_len),
2366                          le32_to_cpu(event->flags));
2367                 xhci_dbg(xhci, "Event ring:\n");
2368                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2369                 return -ENODEV;
2370         }
2371
2372         /* Count current td numbers if ep->skip is set */
2373         if (ep->skip) {
2374                 list_for_each(tmp, &ep_ring->td_list)
2375                         td_num++;
2376         }
2377
2378         event_dma = le64_to_cpu(event->buffer);
2379         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2380         /* Look for common error cases */
2381         switch (trb_comp_code) {
2382         /* Skip codes that require special handling depending on
2383          * transfer type
2384          */
2385         case COMP_SUCCESS:
2386                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2387                         break;
2388                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2389                         trb_comp_code = COMP_SHORT_TX;
2390                 else
2391                         xhci_warn_ratelimited(xhci,
2392                                         "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2393         case COMP_SHORT_TX:
2394                 break;
2395         case COMP_STOP:
2396                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2397                 break;
2398         case COMP_STOP_INVAL:
2399                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2400                 break;
2401         case COMP_STALL:
2402                 xhci_dbg(xhci, "Stalled endpoint\n");
2403                 ep->ep_state |= EP_HALTED;
2404                 status = -EPIPE;
2405                 break;
2406         case COMP_TRB_ERR:
2407                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2408                 status = -EILSEQ;
2409                 break;
2410         case COMP_SPLIT_ERR:
2411         case COMP_TX_ERR:
2412                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2413                 status = -EPROTO;
2414                 break;
2415         case COMP_BABBLE:
2416                 xhci_dbg(xhci, "Babble error on endpoint\n");
2417                 status = -EOVERFLOW;
2418                 break;
2419         case COMP_DB_ERR:
2420                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2421                 status = -ENOSR;
2422                 break;
2423         case COMP_BW_OVER:
2424                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2425                 break;
2426         case COMP_BUFF_OVER:
2427                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2428                 break;
2429         case COMP_UNDERRUN:
2430                 /*
2431                  * When the Isoch ring is empty, the xHC will generate
2432                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2433                  * Underrun Event for OUT Isoch endpoint.
2434                  */
2435                 xhci_dbg(xhci, "underrun event on endpoint\n");
2436                 if (!list_empty(&ep_ring->td_list))
2437                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2438                                         "still with TDs queued?\n",
2439                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2440                                  ep_index);
2441                 goto cleanup;
2442         case COMP_OVERRUN:
2443                 xhci_dbg(xhci, "overrun event on endpoint\n");
2444                 if (!list_empty(&ep_ring->td_list))
2445                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2446                                         "still with TDs queued?\n",
2447                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2448                                  ep_index);
2449                 goto cleanup;
2450         case COMP_DEV_ERR:
2451                 xhci_warn(xhci, "WARN: detect an incompatible device");
2452                 status = -EPROTO;
2453                 break;
2454         case COMP_MISSED_INT:
2455                 /*
2456                  * When encounter missed service error, one or more isoc tds
2457                  * may be missed by xHC.
2458                  * Set skip flag of the ep_ring; Complete the missed tds as
2459                  * short transfer when process the ep_ring next time.
2460                  */
2461                 ep->skip = true;
2462                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2463                 goto cleanup;
2464         default:
2465                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2466                         status = 0;
2467                         break;
2468                 }
2469                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2470                                 "busted\n");
2471                 goto cleanup;
2472         }
2473
2474         do {
2475                 /* This TRB should be in the TD at the head of this ring's
2476                  * TD list.
2477                  */
2478                 if (list_empty(&ep_ring->td_list)) {
2479                         /*
2480                          * A stopped endpoint may generate an extra completion
2481                          * event if the device was suspended.  Don't print
2482                          * warnings.
2483                          */
2484                         if (!(trb_comp_code == COMP_STOP ||
2485                                                 trb_comp_code == COMP_STOP_INVAL)) {
2486                                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2487                                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2488                                                 ep_index);
2489                                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2490                                                 (le32_to_cpu(event->flags) &
2491                                                  TRB_TYPE_BITMASK)>>10);
2492                                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2493                         }
2494                         if (ep->skip) {
2495                                 ep->skip = false;
2496                                 xhci_dbg(xhci, "td_list is empty while skip "
2497                                                 "flag set. Clear skip flag.\n");
2498                         }
2499                         ret = 0;
2500                         goto cleanup;
2501                 }
2502
2503                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2504                 if (ep->skip && td_num == 0) {
2505                         ep->skip = false;
2506                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2507                                                 "Clear skip flag.\n");
2508                         ret = 0;
2509                         goto cleanup;
2510                 }
2511
2512                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2513                 if (ep->skip)
2514                         td_num--;
2515
2516                 /* Is this a TRB in the currently executing TD? */
2517                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2518                                 td->last_trb, event_dma);
2519
2520                 /*
2521                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2522                  * is not in the current TD pointed by ep_ring->dequeue because
2523                  * that the hardware dequeue pointer still at the previous TRB
2524                  * of the current TD. The previous TRB maybe a Link TD or the
2525                  * last TRB of the previous TD. The command completion handle
2526                  * will take care the rest.
2527                  */
2528                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2529                         ret = 0;
2530                         goto cleanup;
2531                 }
2532
2533                 if (!event_seg) {
2534                         if (!ep->skip ||
2535                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2536                                 /* Some host controllers give a spurious
2537                                  * successful event after a short transfer.
2538                                  * Ignore it.
2539                                  */
2540                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2541                                                 ep_ring->last_td_was_short) {
2542                                         ep_ring->last_td_was_short = false;
2543                                         ret = 0;
2544                                         goto cleanup;
2545                                 }
2546                                 /* HC is busted, give up! */
2547                                 xhci_err(xhci,
2548                                         "ERROR Transfer event TRB DMA ptr not "
2549                                         "part of current TD\n");
2550                                 return -ESHUTDOWN;
2551                         }
2552
2553                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2554                         goto cleanup;
2555                 }
2556                 if (trb_comp_code == COMP_SHORT_TX)
2557                         ep_ring->last_td_was_short = true;
2558                 else
2559                         ep_ring->last_td_was_short = false;
2560
2561                 if (ep->skip) {
2562                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2563                         ep->skip = false;
2564                 }
2565
2566                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2567                                                 sizeof(*event_trb)];
2568                 /*
2569                  * No-op TRB should not trigger interrupts.
2570                  * If event_trb is a no-op TRB, it means the
2571                  * corresponding TD has been cancelled. Just ignore
2572                  * the TD.
2573                  */
2574                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2575                         xhci_dbg(xhci,
2576                                  "event_trb is a no-op TRB. Skip it\n");
2577                         goto cleanup;
2578                 }
2579
2580                 /* Now update the urb's actual_length and give back to
2581                  * the core
2582                  */
2583                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2584                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2585                                                  &status);
2586                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2587                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2588                                                  &status);
2589                 else
2590                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2591                                                  ep, &status);
2592
2593 cleanup:
2594                 /*
2595                  * Do not update event ring dequeue pointer if ep->skip is set.
2596                  * Will roll back to continue process missed tds.
2597                  */
2598                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2599                         inc_deq(xhci, xhci->event_ring);
2600                 }
2601
2602                 if (ret) {
2603                         urb = td->urb;
2604                         urb_priv = urb->hcpriv;
2605                         /* Leave the TD around for the reset endpoint function
2606                          * to use(but only if it's not a control endpoint,
2607                          * since we already queued the Set TR dequeue pointer
2608                          * command for stalled control endpoints).
2609                          */
2610                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2611                                 (trb_comp_code != COMP_STALL &&
2612                                         trb_comp_code != COMP_BABBLE))
2613                                 xhci_urb_free_priv(xhci, urb_priv);
2614                         else
2615                                 kfree(urb_priv);
2616
2617                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2618                         if ((urb->actual_length != urb->transfer_buffer_length &&
2619                                                 (urb->transfer_flags &
2620                                                  URB_SHORT_NOT_OK)) ||
2621                                         (status != 0 &&
2622                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2623                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2624                                                 "expected = %d, status = %d\n",
2625                                                 urb, urb->actual_length,
2626                                                 urb->transfer_buffer_length,
2627                                                 status);
2628                         spin_unlock(&xhci->lock);
2629                         /* EHCI, UHCI, and OHCI always unconditionally set the
2630                          * urb->status of an isochronous endpoint to 0.
2631                          */
2632                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2633                                 status = 0;
2634                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2635                         spin_lock(&xhci->lock);
2636                 }
2637
2638         /*
2639          * If ep->skip is set, it means there are missed tds on the
2640          * endpoint ring need to take care of.
2641          * Process them as short transfer until reach the td pointed by
2642          * the event.
2643          */
2644         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2645
2646         return 0;
2647 }
2648
2649 /*
2650  * This function handles all OS-owned events on the event ring.  It may drop
2651  * xhci->lock between event processing (e.g. to pass up port status changes).
2652  * Returns >0 for "possibly more events to process" (caller should call again),
2653  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2654  */
2655 static int xhci_handle_event(struct xhci_hcd *xhci)
2656 {
2657         union xhci_trb *event;
2658         int update_ptrs = 1;
2659         int ret;
2660
2661         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2662                 xhci->error_bitmask |= 1 << 1;
2663                 return 0;
2664         }
2665
2666         event = xhci->event_ring->dequeue;
2667         /* Does the HC or OS own the TRB? */
2668         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2669             xhci->event_ring->cycle_state) {
2670                 xhci->error_bitmask |= 1 << 2;
2671                 return 0;
2672         }
2673
2674         /*
2675          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2676          * speculative reads of the event's flags/data below.
2677          */
2678         rmb();
2679         /* FIXME: Handle more event types. */
2680         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2681         case TRB_TYPE(TRB_COMPLETION):
2682                 handle_cmd_completion(xhci, &event->event_cmd);
2683                 break;
2684         case TRB_TYPE(TRB_PORT_STATUS):
2685                 handle_port_status(xhci, event);
2686                 update_ptrs = 0;
2687                 break;
2688         case TRB_TYPE(TRB_TRANSFER):
2689                 ret = handle_tx_event(xhci, &event->trans_event);
2690                 if (ret < 0)
2691                         xhci->error_bitmask |= 1 << 9;
2692                 else
2693                         update_ptrs = 0;
2694                 break;
2695         case TRB_TYPE(TRB_DEV_NOTE):
2696                 handle_device_notification(xhci, event);
2697                 break;
2698         default:
2699                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2700                     TRB_TYPE(48))
2701                         handle_vendor_event(xhci, event);
2702                 else
2703                         xhci->error_bitmask |= 1 << 3;
2704         }
2705         /* Any of the above functions may drop and re-acquire the lock, so check
2706          * to make sure a watchdog timer didn't mark the host as non-responsive.
2707          */
2708         if (xhci->xhc_state & XHCI_STATE_DYING) {
2709                 xhci_dbg(xhci, "xHCI host dying, returning from "
2710                                 "event handler.\n");
2711                 return 0;
2712         }
2713
2714         if (update_ptrs)
2715                 /* Update SW event ring dequeue pointer */
2716                 inc_deq(xhci, xhci->event_ring);
2717
2718         /* Are there more items on the event ring?  Caller will call us again to
2719          * check.
2720          */
2721         return 1;
2722 }
2723
2724 /*
2725  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2726  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2727  * indicators of an event TRB error, but we check the status *first* to be safe.
2728  */
2729 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2730 {
2731         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2732         u32 status;
2733         u64 temp_64;
2734         union xhci_trb *event_ring_deq;
2735         dma_addr_t deq;
2736
2737         spin_lock(&xhci->lock);
2738         /* Check if the xHC generated the interrupt, or the irq is shared */
2739         status = xhci_readl(xhci, &xhci->op_regs->status);
2740         if (status == 0xffffffff)
2741                 goto hw_died;
2742
2743         if (!(status & STS_EINT)) {
2744                 spin_unlock(&xhci->lock);
2745                 return IRQ_NONE;
2746         }
2747         if (status & STS_FATAL) {
2748                 xhci_warn(xhci, "WARNING: Host System Error\n");
2749                 xhci_halt(xhci);
2750 hw_died:
2751                 spin_unlock(&xhci->lock);
2752                 return -ESHUTDOWN;
2753         }
2754
2755         /*
2756          * Clear the op reg interrupt status first,
2757          * so we can receive interrupts from other MSI-X interrupters.
2758          * Write 1 to clear the interrupt status.
2759          */
2760         status |= STS_EINT;
2761         xhci_writel(xhci, status, &xhci->op_regs->status);
2762         /* FIXME when MSI-X is supported and there are multiple vectors */
2763         /* Clear the MSI-X event interrupt status */
2764
2765         if (hcd->irq) {
2766                 u32 irq_pending;
2767                 /* Acknowledge the PCI interrupt */
2768                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2769                 irq_pending |= IMAN_IP;
2770                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2771         }
2772
2773         if (xhci->xhc_state & XHCI_STATE_DYING) {
2774                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2775                                 "Shouldn't IRQs be disabled?\n");
2776                 /* Clear the event handler busy flag (RW1C);
2777                  * the event ring should be empty.
2778                  */
2779                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2780                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2781                                 &xhci->ir_set->erst_dequeue);
2782                 spin_unlock(&xhci->lock);
2783
2784                 return IRQ_HANDLED;
2785         }
2786
2787         event_ring_deq = xhci->event_ring->dequeue;
2788         /* FIXME this should be a delayed service routine
2789          * that clears the EHB.
2790          */
2791         while (xhci_handle_event(xhci) > 0) {}
2792
2793         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2794         /* If necessary, update the HW's version of the event ring deq ptr. */
2795         if (event_ring_deq != xhci->event_ring->dequeue) {
2796                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2797                                 xhci->event_ring->dequeue);
2798                 if (deq == 0)
2799                         xhci_warn(xhci, "WARN something wrong with SW event "
2800                                         "ring dequeue ptr.\n");
2801                 /* Update HC event ring dequeue pointer */
2802                 temp_64 &= ERST_PTR_MASK;
2803                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2804         }
2805
2806         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2807         temp_64 |= ERST_EHB;
2808         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2809
2810         spin_unlock(&xhci->lock);
2811
2812         return IRQ_HANDLED;
2813 }
2814
2815 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2816 {
2817         return xhci_irq(hcd);
2818 }
2819
2820 /****           Endpoint Ring Operations        ****/
2821
2822 /*
2823  * Generic function for queueing a TRB on a ring.
2824  * The caller must have checked to make sure there's room on the ring.
2825  *
2826  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2827  *                      prepare_transfer()?
2828  */
2829 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2830                 bool more_trbs_coming,
2831                 u32 field1, u32 field2, u32 field3, u32 field4)
2832 {
2833         struct xhci_generic_trb *trb;
2834
2835         trb = &ring->enqueue->generic;
2836         trb->field[0] = cpu_to_le32(field1);
2837         trb->field[1] = cpu_to_le32(field2);
2838         trb->field[2] = cpu_to_le32(field3);
2839         trb->field[3] = cpu_to_le32(field4);
2840         inc_enq(xhci, ring, more_trbs_coming);
2841 }
2842
2843 /*
2844  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2845  * FIXME allocate segments if the ring is full.
2846  */
2847 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2848                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2849 {
2850         unsigned int num_trbs_needed;
2851
2852         /* Make sure the endpoint has been added to xHC schedule */
2853         switch (ep_state) {
2854         case EP_STATE_DISABLED:
2855                 /*
2856                  * USB core changed config/interfaces without notifying us,
2857                  * or hardware is reporting the wrong state.
2858                  */
2859                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2860                 return -ENOENT;
2861         case EP_STATE_ERROR:
2862                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2863                 /* FIXME event handling code for error needs to clear it */
2864                 /* XXX not sure if this should be -ENOENT or not */
2865                 return -EINVAL;
2866         case EP_STATE_HALTED:
2867                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2868         case EP_STATE_STOPPED:
2869         case EP_STATE_RUNNING:
2870                 break;
2871         default:
2872                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2873                 /*
2874                  * FIXME issue Configure Endpoint command to try to get the HC
2875                  * back into a known state.
2876                  */
2877                 return -EINVAL;
2878         }
2879
2880         while (1) {
2881                 if (room_on_ring(xhci, ep_ring, num_trbs))
2882                         break;
2883
2884                 if (ep_ring == xhci->cmd_ring) {
2885                         xhci_err(xhci, "Do not support expand command ring\n");
2886                         return -ENOMEM;
2887                 }
2888
2889                 xhci_dbg(xhci, "ERROR no room on ep ring, "
2890                                         "try ring expansion\n");
2891                 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2892                 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2893                                         mem_flags)) {
2894                         xhci_err(xhci, "Ring expansion failed\n");
2895                         return -ENOMEM;
2896                 }
2897         }
2898
2899         if (enqueue_is_link_trb(ep_ring)) {
2900                 struct xhci_ring *ring = ep_ring;
2901                 union xhci_trb *next;
2902
2903                 next = ring->enqueue;
2904
2905                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2906                         /* If we're not dealing with 0.95 hardware or isoc rings
2907                          * on AMD 0.96 host, clear the chain bit.
2908                          */
2909                         if (!xhci_link_trb_quirk(xhci) &&
2910                                         !(ring->type == TYPE_ISOC &&
2911                                          (xhci->quirks & XHCI_AMD_0x96_HOST)))
2912                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2913                         else
2914                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2915
2916                         wmb();
2917                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2918
2919                         /* Toggle the cycle bit after the last ring segment. */
2920                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2921                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2922                         }
2923                         ring->enq_seg = ring->enq_seg->next;
2924                         ring->enqueue = ring->enq_seg->trbs;
2925                         next = ring->enqueue;
2926                 }
2927         }
2928
2929         return 0;
2930 }
2931
2932 static int prepare_transfer(struct xhci_hcd *xhci,
2933                 struct xhci_virt_device *xdev,
2934                 unsigned int ep_index,
2935                 unsigned int stream_id,
2936                 unsigned int num_trbs,
2937                 struct urb *urb,
2938                 unsigned int td_index,
2939                 gfp_t mem_flags)
2940 {
2941         int ret;
2942         struct urb_priv *urb_priv;
2943         struct xhci_td  *td;
2944         struct xhci_ring *ep_ring;
2945         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2946
2947         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2948         if (!ep_ring) {
2949                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2950                                 stream_id);
2951                 return -EINVAL;
2952         }
2953
2954         ret = prepare_ring(xhci, ep_ring,
2955                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2956                            num_trbs, mem_flags);
2957         if (ret)
2958                 return ret;
2959
2960         urb_priv = urb->hcpriv;
2961         td = urb_priv->td[td_index];
2962
2963         INIT_LIST_HEAD(&td->td_list);
2964         INIT_LIST_HEAD(&td->cancelled_td_list);
2965
2966         if (td_index == 0) {
2967                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2968                 if (unlikely(ret))
2969                         return ret;
2970         }
2971
2972         td->urb = urb;
2973         /* Add this TD to the tail of the endpoint ring's TD list */
2974         list_add_tail(&td->td_list, &ep_ring->td_list);
2975         td->start_seg = ep_ring->enq_seg;
2976         td->first_trb = ep_ring->enqueue;
2977
2978         urb_priv->td[td_index] = td;
2979
2980         return 0;
2981 }
2982
2983 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2984 {
2985         int num_sgs, num_trbs, running_total, temp, i;
2986         struct scatterlist *sg;
2987
2988         sg = NULL;
2989         num_sgs = urb->num_mapped_sgs;
2990         temp = urb->transfer_buffer_length;
2991
2992         num_trbs = 0;
2993         for_each_sg(urb->sg, sg, num_sgs, i) {
2994                 unsigned int len = sg_dma_len(sg);
2995
2996                 /* Scatter gather list entries may cross 64KB boundaries */
2997                 running_total = TRB_MAX_BUFF_SIZE -
2998                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2999                 running_total &= TRB_MAX_BUFF_SIZE - 1;
3000                 if (running_total != 0)
3001                         num_trbs++;
3002
3003                 /* How many more 64KB chunks to transfer, how many more TRBs? */
3004                 while (running_total < sg_dma_len(sg) && running_total < temp) {
3005                         num_trbs++;
3006                         running_total += TRB_MAX_BUFF_SIZE;
3007                 }
3008                 len = min_t(int, len, temp);
3009                 temp -= len;
3010                 if (temp == 0)
3011                         break;
3012         }
3013         return num_trbs;
3014 }
3015
3016 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
3017 {
3018         if (num_trbs != 0)
3019                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
3020                                 "TRBs, %d left\n", __func__,
3021                                 urb->ep->desc.bEndpointAddress, num_trbs);
3022         if (running_total != urb->transfer_buffer_length)
3023                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3024                                 "queued %#x (%d), asked for %#x (%d)\n",
3025                                 __func__,
3026                                 urb->ep->desc.bEndpointAddress,
3027                                 running_total, running_total,
3028                                 urb->transfer_buffer_length,
3029                                 urb->transfer_buffer_length);
3030 }
3031
3032 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3033                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3034                 struct xhci_generic_trb *start_trb)
3035 {
3036         /*
3037          * Pass all the TRBs to the hardware at once and make sure this write
3038          * isn't reordered.
3039          */
3040         wmb();
3041         if (start_cycle)
3042                 start_trb->field[3] |= cpu_to_le32(start_cycle);
3043         else
3044                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3045         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3046 }
3047
3048 /*
3049  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3050  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3051  * (comprised of sg list entries) can take several service intervals to
3052  * transmit.
3053  */
3054 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3055                 struct urb *urb, int slot_id, unsigned int ep_index)
3056 {
3057         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3058                         xhci->devs[slot_id]->out_ctx, ep_index);
3059         int xhci_interval;
3060         int ep_interval;
3061
3062         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3063         ep_interval = urb->interval;
3064         /* Convert to microframes */
3065         if (urb->dev->speed == USB_SPEED_LOW ||
3066                         urb->dev->speed == USB_SPEED_FULL)
3067                 ep_interval *= 8;
3068         /* FIXME change this to a warning and a suggestion to use the new API
3069          * to set the polling interval (once the API is added).
3070          */
3071         if (xhci_interval != ep_interval) {
3072                 if (printk_ratelimit())
3073                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3074                                         " (%d microframe%s) than xHCI "
3075                                         "(%d microframe%s)\n",
3076                                         ep_interval,
3077                                         ep_interval == 1 ? "" : "s",
3078                                         xhci_interval,
3079                                         xhci_interval == 1 ? "" : "s");
3080                 urb->interval = xhci_interval;
3081                 /* Convert back to frames for LS/FS devices */
3082                 if (urb->dev->speed == USB_SPEED_LOW ||
3083                                 urb->dev->speed == USB_SPEED_FULL)
3084                         urb->interval /= 8;
3085         }
3086         return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3087 }
3088
3089 /*
3090  * The TD size is the number of bytes remaining in the TD (including this TRB),
3091  * right shifted by 10.
3092  * It must fit in bits 21:17, so it can't be bigger than 31.
3093  */
3094 static u32 xhci_td_remainder(unsigned int remainder)
3095 {
3096         u32 max = (1 << (21 - 17 + 1)) - 1;
3097
3098         if ((remainder >> 10) >= max)
3099                 return max << 17;
3100         else
3101                 return (remainder >> 10) << 17;
3102 }
3103
3104 /*
3105  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3106  * packets remaining in the TD (*not* including this TRB).
3107  *
3108  * Total TD packet count = total_packet_count =
3109  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3110  *
3111  * Packets transferred up to and including this TRB = packets_transferred =
3112  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3113  *
3114  * TD size = total_packet_count - packets_transferred
3115  *
3116  * It must fit in bits 21:17, so it can't be bigger than 31.
3117  * The last TRB in a TD must have the TD size set to zero.
3118  */
3119 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3120                 unsigned int total_packet_count, struct urb *urb,
3121                 unsigned int num_trbs_left)
3122 {
3123         int packets_transferred;
3124
3125         /* One TRB with a zero-length data packet. */
3126         if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3127                 return 0;
3128
3129         /* All the TRB queueing functions don't count the current TRB in
3130          * running_total.
3131          */
3132         packets_transferred = (running_total + trb_buff_len) /
3133                 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3134
3135         if ((total_packet_count - packets_transferred) > 31)
3136                 return 31 << 17;
3137         return (total_packet_count - packets_transferred) << 17;
3138 }
3139
3140 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3141                 struct urb *urb, int slot_id, unsigned int ep_index)
3142 {
3143         struct xhci_ring *ep_ring;
3144         unsigned int num_trbs;
3145         struct urb_priv *urb_priv;
3146         struct xhci_td *td;
3147         struct scatterlist *sg;
3148         int num_sgs;
3149         int trb_buff_len, this_sg_len, running_total;
3150         unsigned int total_packet_count;
3151         bool first_trb;
3152         u64 addr;
3153         bool more_trbs_coming;
3154
3155         struct xhci_generic_trb *start_trb;
3156         int start_cycle;
3157
3158         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3159         if (!ep_ring)
3160                 return -EINVAL;
3161
3162         num_trbs = count_sg_trbs_needed(xhci, urb);
3163         num_sgs = urb->num_mapped_sgs;
3164         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3165                         usb_endpoint_maxp(&urb->ep->desc));
3166
3167         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3168                         ep_index, urb->stream_id,
3169                         num_trbs, urb, 0, mem_flags);
3170         if (trb_buff_len < 0)
3171                 return trb_buff_len;
3172
3173         urb_priv = urb->hcpriv;
3174         td = urb_priv->td[0];
3175
3176         /*
3177          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3178          * until we've finished creating all the other TRBs.  The ring's cycle
3179          * state may change as we enqueue the other TRBs, so save it too.
3180          */
3181         start_trb = &ep_ring->enqueue->generic;
3182         start_cycle = ep_ring->cycle_state;
3183
3184         running_total = 0;
3185         /*
3186          * How much data is in the first TRB?
3187          *
3188          * There are three forces at work for TRB buffer pointers and lengths:
3189          * 1. We don't want to walk off the end of this sg-list entry buffer.
3190          * 2. The transfer length that the driver requested may be smaller than
3191          *    the amount of memory allocated for this scatter-gather list.
3192          * 3. TRBs buffers can't cross 64KB boundaries.
3193          */
3194         sg = urb->sg;
3195         addr = (u64) sg_dma_address(sg);
3196         this_sg_len = sg_dma_len(sg);
3197         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3198         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3199         if (trb_buff_len > urb->transfer_buffer_length)
3200                 trb_buff_len = urb->transfer_buffer_length;
3201
3202         first_trb = true;
3203         /* Queue the first TRB, even if it's zero-length */
3204         do {
3205                 u32 field = 0;
3206                 u32 length_field = 0;
3207                 u32 remainder = 0;
3208
3209                 /* Don't change the cycle bit of the first TRB until later */
3210                 if (first_trb) {
3211                         first_trb = false;
3212                         if (start_cycle == 0)
3213                                 field |= 0x1;
3214                 } else
3215                         field |= ep_ring->cycle_state;
3216
3217                 /* Chain all the TRBs together; clear the chain bit in the last
3218                  * TRB to indicate it's the last TRB in the chain.
3219                  */
3220                 if (num_trbs > 1) {
3221                         field |= TRB_CHAIN;
3222                 } else {
3223                         /* FIXME - add check for ZERO_PACKET flag before this */
3224                         td->last_trb = ep_ring->enqueue;
3225                         field |= TRB_IOC;
3226                 }
3227
3228                 /* Only set interrupt on short packet for IN endpoints */
3229                 if (usb_urb_dir_in(urb))
3230                         field |= TRB_ISP;
3231
3232                 if (TRB_MAX_BUFF_SIZE -
3233                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3234                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3235                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3236                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3237                                         (unsigned int) addr + trb_buff_len);
3238                 }
3239
3240                 /* Set the TRB length, TD size, and interrupter fields. */
3241                 if (xhci->hci_version < 0x100) {
3242                         remainder = xhci_td_remainder(
3243                                         urb->transfer_buffer_length -
3244                                         running_total);
3245                 } else {
3246                         remainder = xhci_v1_0_td_remainder(running_total,
3247                                         trb_buff_len, total_packet_count, urb,
3248                                         num_trbs - 1);
3249                 }
3250                 length_field = TRB_LEN(trb_buff_len) |
3251                         remainder |
3252                         TRB_INTR_TARGET(0);
3253
3254                 if (num_trbs > 1)
3255                         more_trbs_coming = true;
3256                 else
3257                         more_trbs_coming = false;
3258                 queue_trb(xhci, ep_ring, more_trbs_coming,
3259                                 lower_32_bits(addr),
3260                                 upper_32_bits(addr),
3261                                 length_field,
3262                                 field | TRB_TYPE(TRB_NORMAL));
3263                 --num_trbs;
3264                 running_total += trb_buff_len;
3265
3266                 /* Calculate length for next transfer --
3267                  * Are we done queueing all the TRBs for this sg entry?
3268                  */
3269                 this_sg_len -= trb_buff_len;
3270                 if (this_sg_len == 0) {
3271                         --num_sgs;
3272                         if (num_sgs == 0)
3273                                 break;
3274                         sg = sg_next(sg);
3275                         addr = (u64) sg_dma_address(sg);
3276                         this_sg_len = sg_dma_len(sg);
3277                 } else {
3278                         addr += trb_buff_len;
3279                 }
3280
3281                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3282                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3283                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3284                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3285                         trb_buff_len =
3286                                 urb->transfer_buffer_length - running_total;
3287         } while (running_total < urb->transfer_buffer_length);
3288
3289         check_trb_math(urb, num_trbs, running_total);
3290         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3291                         start_cycle, start_trb);
3292         return 0;
3293 }
3294
3295 /* This is very similar to what ehci-q.c qtd_fill() does */
3296 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3297                 struct urb *urb, int slot_id, unsigned int ep_index)
3298 {
3299         struct xhci_ring *ep_ring;
3300         struct urb_priv *urb_priv;
3301         struct xhci_td *td;
3302         int num_trbs;
3303         struct xhci_generic_trb *start_trb;
3304         bool first_trb;
3305         bool more_trbs_coming;
3306         int start_cycle;
3307         u32 field, length_field;
3308
3309         int running_total, trb_buff_len, ret;
3310         unsigned int total_packet_count;
3311         u64 addr;
3312
3313         if (urb->num_sgs)
3314                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3315
3316         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3317         if (!ep_ring)
3318                 return -EINVAL;
3319
3320         num_trbs = 0;
3321         /* How much data is (potentially) left before the 64KB boundary? */
3322         running_total = TRB_MAX_BUFF_SIZE -
3323                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3324         running_total &= TRB_MAX_BUFF_SIZE - 1;
3325
3326         /* If there's some data on this 64KB chunk, or we have to send a
3327          * zero-length transfer, we need at least one TRB
3328          */
3329         if (running_total != 0 || urb->transfer_buffer_length == 0)
3330                 num_trbs++;
3331         /* How many more 64KB chunks to transfer, how many more TRBs? */
3332         while (running_total < urb->transfer_buffer_length) {
3333                 num_trbs++;
3334                 running_total += TRB_MAX_BUFF_SIZE;
3335         }
3336         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3337
3338         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3339                         ep_index, urb->stream_id,
3340                         num_trbs, urb, 0, mem_flags);
3341         if (ret < 0)
3342                 return ret;
3343
3344         urb_priv = urb->hcpriv;
3345         td = urb_priv->td[0];
3346
3347         /*
3348          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3349          * until we've finished creating all the other TRBs.  The ring's cycle
3350          * state may change as we enqueue the other TRBs, so save it too.
3351          */
3352         start_trb = &ep_ring->enqueue->generic;
3353         start_cycle = ep_ring->cycle_state;
3354
3355         running_total = 0;
3356         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3357                         usb_endpoint_maxp(&urb->ep->desc));
3358         /* How much data is in the first TRB? */
3359         addr = (u64) urb->transfer_dma;
3360         trb_buff_len = TRB_MAX_BUFF_SIZE -
3361                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3362         if (trb_buff_len > urb->transfer_buffer_length)
3363                 trb_buff_len = urb->transfer_buffer_length;
3364
3365         first_trb = true;
3366
3367         /* Queue the first TRB, even if it's zero-length */
3368         do {
3369                 u32 remainder = 0;
3370                 field = 0;
3371
3372                 /* Don't change the cycle bit of the first TRB until later */
3373                 if (first_trb) {
3374                         first_trb = false;
3375                         if (start_cycle == 0)
3376                                 field |= 0x1;
3377                 } else
3378                         field |= ep_ring->cycle_state;
3379
3380                 /* Chain all the TRBs together; clear the chain bit in the last
3381                  * TRB to indicate it's the last TRB in the chain.
3382                  */
3383                 if (num_trbs > 1) {
3384                         field |= TRB_CHAIN;
3385                 } else {
3386                         /* FIXME - add check for ZERO_PACKET flag before this */
3387                         td->last_trb = ep_ring->enqueue;
3388                         field |= TRB_IOC;
3389                 }
3390
3391                 /* Only set interrupt on short packet for IN endpoints */
3392                 if (usb_urb_dir_in(urb))
3393                         field |= TRB_ISP;
3394
3395                 /* Set the TRB length, TD size, and interrupter fields. */
3396                 if (xhci->hci_version < 0x100) {
3397                         remainder = xhci_td_remainder(
3398                                         urb->transfer_buffer_length -
3399                                         running_total);
3400                 } else {
3401                         remainder = xhci_v1_0_td_remainder(running_total,
3402                                         trb_buff_len, total_packet_count, urb,
3403                                         num_trbs - 1);
3404                 }
3405                 length_field = TRB_LEN(trb_buff_len) |
3406                         remainder |
3407                         TRB_INTR_TARGET(0);
3408
3409                 if (num_trbs > 1)
3410                         more_trbs_coming = true;
3411                 else
3412                         more_trbs_coming = false;
3413                 queue_trb(xhci, ep_ring, more_trbs_coming,
3414                                 lower_32_bits(addr),
3415                                 upper_32_bits(addr),
3416                                 length_field,
3417                                 field | TRB_TYPE(TRB_NORMAL));
3418                 --num_trbs;
3419                 running_total += trb_buff_len;
3420
3421                 /* Calculate length for next transfer */
3422                 addr += trb_buff_len;
3423                 trb_buff_len = urb->transfer_buffer_length - running_total;
3424                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3425                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3426         } while (running_total < urb->transfer_buffer_length);
3427
3428         check_trb_math(urb, num_trbs, running_total);
3429         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3430                         start_cycle, start_trb);
3431         return 0;
3432 }
3433
3434 /* Caller must have locked xhci->lock */
3435 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3436                 struct urb *urb, int slot_id, unsigned int ep_index)
3437 {
3438         struct xhci_ring *ep_ring;
3439         int num_trbs;
3440         int ret;
3441         struct usb_ctrlrequest *setup;
3442         struct xhci_generic_trb *start_trb;
3443         int start_cycle;
3444         u32 field, length_field;
3445         struct urb_priv *urb_priv;
3446         struct xhci_td *td;
3447
3448         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3449         if (!ep_ring)
3450                 return -EINVAL;
3451
3452         /*
3453          * Need to copy setup packet into setup TRB, so we can't use the setup
3454          * DMA address.
3455          */
3456         if (!urb->setup_packet)
3457                 return -EINVAL;
3458
3459         /* 1 TRB for setup, 1 for status */
3460         num_trbs = 2;
3461         /*
3462          * Don't need to check if we need additional event data and normal TRBs,
3463          * since data in control transfers will never get bigger than 16MB
3464          * XXX: can we get a buffer that crosses 64KB boundaries?
3465          */
3466         if (urb->transfer_buffer_length > 0)
3467                 num_trbs++;
3468         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3469                         ep_index, urb->stream_id,
3470                         num_trbs, urb, 0, mem_flags);
3471         if (ret < 0)
3472                 return ret;
3473
3474         urb_priv = urb->hcpriv;
3475         td = urb_priv->td[0];
3476
3477         /*
3478          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3479          * until we've finished creating all the other TRBs.  The ring's cycle
3480          * state may change as we enqueue the other TRBs, so save it too.
3481          */
3482         start_trb = &ep_ring->enqueue->generic;
3483         start_cycle = ep_ring->cycle_state;
3484
3485         /* Queue setup TRB - see section 6.4.1.2.1 */
3486         /* FIXME better way to translate setup_packet into two u32 fields? */
3487         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3488         field = 0;
3489         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3490         if (start_cycle == 0)
3491                 field |= 0x1;
3492
3493         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3494         if (xhci->hci_version == 0x100) {
3495                 if (urb->transfer_buffer_length > 0) {
3496                         if (setup->bRequestType & USB_DIR_IN)
3497                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3498                         else
3499                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3500                 }
3501         }
3502
3503         queue_trb(xhci, ep_ring, true,
3504                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3505                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3506                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3507                   /* Immediate data in pointer */
3508                   field);
3509
3510         /* If there's data, queue data TRBs */
3511         /* Only set interrupt on short packet for IN endpoints */
3512         if (usb_urb_dir_in(urb))
3513                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3514         else
3515                 field = TRB_TYPE(TRB_DATA);
3516
3517         length_field = TRB_LEN(urb->transfer_buffer_length) |
3518                 xhci_td_remainder(urb->transfer_buffer_length) |
3519                 TRB_INTR_TARGET(0);
3520         if (urb->transfer_buffer_length > 0) {
3521                 if (setup->bRequestType & USB_DIR_IN)
3522                         field |= TRB_DIR_IN;
3523                 queue_trb(xhci, ep_ring, true,
3524                                 lower_32_bits(urb->transfer_dma),
3525                                 upper_32_bits(urb->transfer_dma),
3526                                 length_field,
3527                                 field | ep_ring->cycle_state);
3528         }
3529
3530         /* Save the DMA address of the last TRB in the TD */
3531         td->last_trb = ep_ring->enqueue;
3532
3533         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3534         /* If the device sent data, the status stage is an OUT transfer */
3535         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3536                 field = 0;
3537         else
3538                 field = TRB_DIR_IN;
3539         queue_trb(xhci, ep_ring, false,
3540                         0,
3541                         0,
3542                         TRB_INTR_TARGET(0),
3543                         /* Event on completion */
3544                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3545
3546         giveback_first_trb(xhci, slot_id, ep_index, 0,
3547                         start_cycle, start_trb);
3548         return 0;
3549 }
3550
3551 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3552                 struct urb *urb, int i)
3553 {
3554         int num_trbs = 0;
3555         u64 addr, td_len;
3556
3557         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3558         td_len = urb->iso_frame_desc[i].length;
3559
3560         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3561                         TRB_MAX_BUFF_SIZE);
3562         if (num_trbs == 0)
3563                 num_trbs++;
3564
3565         return num_trbs;
3566 }
3567
3568 /*
3569  * The transfer burst count field of the isochronous TRB defines the number of
3570  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3571  * devices can burst up to bMaxBurst number of packets per service interval.
3572  * This field is zero based, meaning a value of zero in the field means one
3573  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3574  * zero.  Only xHCI 1.0 host controllers support this field.
3575  */
3576 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3577                 struct usb_device *udev,
3578                 struct urb *urb, unsigned int total_packet_count)
3579 {
3580         unsigned int max_burst;
3581
3582         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3583                 return 0;
3584
3585         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3586         return roundup(total_packet_count, max_burst + 1) - 1;
3587 }
3588
3589 /*
3590  * Returns the number of packets in the last "burst" of packets.  This field is
3591  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3592  * the last burst packet count is equal to the total number of packets in the
3593  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3594  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3595  * contain 1 to (bMaxBurst + 1) packets.
3596  */
3597 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3598                 struct usb_device *udev,
3599                 struct urb *urb, unsigned int total_packet_count)
3600 {
3601         unsigned int max_burst;
3602         unsigned int residue;
3603
3604         if (xhci->hci_version < 0x100)
3605                 return 0;
3606
3607         switch (udev->speed) {
3608         case USB_SPEED_SUPER:
3609                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3610                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3611                 residue = total_packet_count % (max_burst + 1);
3612                 /* If residue is zero, the last burst contains (max_burst + 1)
3613                  * number of packets, but the TLBPC field is zero-based.
3614                  */
3615                 if (residue == 0)
3616                         return max_burst;
3617                 return residue - 1;
3618         default:
3619                 if (total_packet_count == 0)
3620                         return 0;
3621                 return total_packet_count - 1;
3622         }
3623 }
3624
3625 /* This is for isoc transfer */
3626 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3627                 struct urb *urb, int slot_id, unsigned int ep_index)
3628 {
3629         struct xhci_ring *ep_ring;
3630         struct urb_priv *urb_priv;
3631         struct xhci_td *td;
3632         int num_tds, trbs_per_td;
3633         struct xhci_generic_trb *start_trb;
3634         bool first_trb;
3635         int start_cycle;
3636         u32 field, length_field;
3637         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3638         u64 start_addr, addr;
3639         int i, j;
3640         bool more_trbs_coming;
3641
3642         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3643
3644         num_tds = urb->number_of_packets;
3645         if (num_tds < 1) {
3646                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3647                 return -EINVAL;
3648         }
3649
3650         start_addr = (u64) urb->transfer_dma;
3651         start_trb = &ep_ring->enqueue->generic;
3652         start_cycle = ep_ring->cycle_state;
3653
3654         urb_priv = urb->hcpriv;
3655         /* Queue the first TRB, even if it's zero-length */
3656         for (i = 0; i < num_tds; i++) {
3657                 unsigned int total_packet_count;
3658                 unsigned int burst_count;
3659                 unsigned int residue;
3660
3661                 first_trb = true;
3662                 running_total = 0;
3663                 addr = start_addr + urb->iso_frame_desc[i].offset;
3664                 td_len = urb->iso_frame_desc[i].length;
3665                 td_remain_len = td_len;
3666                 total_packet_count = DIV_ROUND_UP(td_len,
3667                                 GET_MAX_PACKET(
3668                                         usb_endpoint_maxp(&urb->ep->desc)));
3669                 /* A zero-length transfer still involves at least one packet. */
3670                 if (total_packet_count == 0)
3671                         total_packet_count++;
3672                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3673                                 total_packet_count);
3674                 residue = xhci_get_last_burst_packet_count(xhci,
3675                                 urb->dev, urb, total_packet_count);
3676
3677                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3678
3679                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3680                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3681                 if (ret < 0) {
3682                         if (i == 0)
3683                                 return ret;
3684                         goto cleanup;
3685                 }
3686
3687                 td = urb_priv->td[i];
3688                 for (j = 0; j < trbs_per_td; j++) {
3689                         u32 remainder = 0;
3690                         field = 0;
3691
3692                         if (first_trb) {
3693                                 field = TRB_TBC(burst_count) |
3694                                         TRB_TLBPC(residue);
3695                                 /* Queue the isoc TRB */
3696                                 field |= TRB_TYPE(TRB_ISOC);
3697                                 /* Assume URB_ISO_ASAP is set */
3698                                 field |= TRB_SIA;
3699                                 if (i == 0) {
3700                                         if (start_cycle == 0)
3701                                                 field |= 0x1;
3702                                 } else
3703                                         field |= ep_ring->cycle_state;
3704                                 first_trb = false;
3705                         } else {
3706                                 /* Queue other normal TRBs */
3707                                 field |= TRB_TYPE(TRB_NORMAL);
3708                                 field |= ep_ring->cycle_state;
3709                         }
3710
3711                         /* Only set interrupt on short packet for IN EPs */
3712                         if (usb_urb_dir_in(urb))
3713                                 field |= TRB_ISP;
3714
3715                         /* Chain all the TRBs together; clear the chain bit in
3716                          * the last TRB to indicate it's the last TRB in the
3717                          * chain.
3718                          */
3719                         if (j < trbs_per_td - 1) {
3720                                 field |= TRB_CHAIN;
3721                                 more_trbs_coming = true;
3722                         } else {
3723                                 td->last_trb = ep_ring->enqueue;
3724                                 field |= TRB_IOC;
3725                                 if (xhci->hci_version == 0x100 &&
3726                                                 !(xhci->quirks &
3727                                                         XHCI_AVOID_BEI)) {
3728                                         /* Set BEI bit except for the last td */
3729                                         if (i < num_tds - 1)
3730                                                 field |= TRB_BEI;
3731                                 }
3732                                 more_trbs_coming = false;
3733                         }
3734
3735                         /* Calculate TRB length */
3736                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3737                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3738                         if (trb_buff_len > td_remain_len)
3739                                 trb_buff_len = td_remain_len;
3740
3741                         /* Set the TRB length, TD size, & interrupter fields. */
3742                         if (xhci->hci_version < 0x100) {
3743                                 remainder = xhci_td_remainder(
3744                                                 td_len - running_total);
3745                         } else {
3746                                 remainder = xhci_v1_0_td_remainder(
3747                                                 running_total, trb_buff_len,
3748                                                 total_packet_count, urb,
3749                                                 (trbs_per_td - j - 1));
3750                         }
3751                         length_field = TRB_LEN(trb_buff_len) |
3752                                 remainder |
3753                                 TRB_INTR_TARGET(0);
3754
3755                         queue_trb(xhci, ep_ring, more_trbs_coming,
3756                                 lower_32_bits(addr),
3757                                 upper_32_bits(addr),
3758                                 length_field,
3759                                 field);
3760                         running_total += trb_buff_len;
3761
3762                         addr += trb_buff_len;
3763                         td_remain_len -= trb_buff_len;
3764                 }
3765
3766                 /* Check TD length */
3767                 if (running_total != td_len) {
3768                         xhci_err(xhci, "ISOC TD length unmatch\n");
3769                         ret = -EINVAL;
3770                         goto cleanup;
3771                 }
3772         }
3773
3774         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3775                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3776                         usb_amd_quirk_pll_disable();
3777         }
3778         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3779
3780         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3781                         start_cycle, start_trb);
3782         return 0;
3783 cleanup:
3784         /* Clean up a partially enqueued isoc transfer. */
3785
3786         for (i--; i >= 0; i--)
3787                 list_del_init(&urb_priv->td[i]->td_list);
3788
3789         /* Use the first TD as a temporary variable to turn the TDs we've queued
3790          * into No-ops with a software-owned cycle bit. That way the hardware
3791          * won't accidentally start executing bogus TDs when we partially
3792          * overwrite them.  td->first_trb and td->start_seg are already set.
3793          */
3794         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3795         /* Every TRB except the first & last will have its cycle bit flipped. */
3796         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3797
3798         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3799         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3800         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3801         ep_ring->cycle_state = start_cycle;
3802         ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3803         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3804         return ret;
3805 }
3806
3807 /*
3808  * Check transfer ring to guarantee there is enough room for the urb.
3809  * Update ISO URB start_frame and interval.
3810  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3811  * update the urb->start_frame by now.
3812  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3813  */
3814 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3815                 struct urb *urb, int slot_id, unsigned int ep_index)
3816 {
3817         struct xhci_virt_device *xdev;
3818         struct xhci_ring *ep_ring;
3819         struct xhci_ep_ctx *ep_ctx;
3820         int start_frame;
3821         int xhci_interval;
3822         int ep_interval;
3823         int num_tds, num_trbs, i;
3824         int ret;
3825
3826         xdev = xhci->devs[slot_id];
3827         ep_ring = xdev->eps[ep_index].ring;
3828         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3829
3830         num_trbs = 0;
3831         num_tds = urb->number_of_packets;
3832         for (i = 0; i < num_tds; i++)
3833                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3834
3835         /* Check the ring to guarantee there is enough room for the whole urb.
3836          * Do not insert any td of the urb to the ring if the check failed.
3837          */
3838         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3839                            num_trbs, mem_flags);
3840         if (ret)
3841                 return ret;
3842
3843         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3844         start_frame &= 0x3fff;
3845
3846         urb->start_frame = start_frame;
3847         if (urb->dev->speed == USB_SPEED_LOW ||
3848                         urb->dev->speed == USB_SPEED_FULL)
3849                 urb->start_frame >>= 3;
3850
3851         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3852         ep_interval = urb->interval;
3853         /* Convert to microframes */
3854         if (urb->dev->speed == USB_SPEED_LOW ||
3855                         urb->dev->speed == USB_SPEED_FULL)
3856                 ep_interval *= 8;
3857         /* FIXME change this to a warning and a suggestion to use the new API
3858          * to set the polling interval (once the API is added).
3859          */
3860         if (xhci_interval != ep_interval) {
3861                 if (printk_ratelimit())
3862                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3863                                         " (%d microframe%s) than xHCI "
3864                                         "(%d microframe%s)\n",
3865                                         ep_interval,
3866                                         ep_interval == 1 ? "" : "s",
3867                                         xhci_interval,
3868                                         xhci_interval == 1 ? "" : "s");
3869                 urb->interval = xhci_interval;
3870                 /* Convert back to frames for LS/FS devices */
3871                 if (urb->dev->speed == USB_SPEED_LOW ||
3872                                 urb->dev->speed == USB_SPEED_FULL)
3873                         urb->interval /= 8;
3874         }
3875         ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3876
3877         return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3878 }
3879
3880 /****           Command Ring Operations         ****/
3881
3882 /* Generic function for queueing a command TRB on the command ring.
3883  * Check to make sure there's room on the command ring for one command TRB.
3884  * Also check that there's room reserved for commands that must not fail.
3885  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3886  * then only check for the number of reserved spots.
3887  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3888  * because the command event handler may want to resubmit a failed command.
3889  */
3890 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3891                 u32 field3, u32 field4, bool command_must_succeed)
3892 {
3893         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3894         int ret;
3895
3896         if (!command_must_succeed)
3897                 reserved_trbs++;
3898
3899         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3900                         reserved_trbs, GFP_ATOMIC);
3901         if (ret < 0) {
3902                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3903                 if (command_must_succeed)
3904                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3905                                         "unfailable commands failed.\n");
3906                 return ret;
3907         }
3908         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3909                         field4 | xhci->cmd_ring->cycle_state);
3910         return 0;
3911 }
3912
3913 /* Queue a slot enable or disable request on the command ring */
3914 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3915 {
3916         return queue_command(xhci, 0, 0, 0,
3917                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3918 }
3919
3920 /* Queue an address device command TRB */
3921 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3922                 u32 slot_id)
3923 {
3924         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3925                         upper_32_bits(in_ctx_ptr), 0,
3926                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3927                         false);
3928 }
3929
3930 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3931                 u32 field1, u32 field2, u32 field3, u32 field4)
3932 {
3933         return queue_command(xhci, field1, field2, field3, field4, false);
3934 }
3935
3936 /* Queue a reset device command TRB */
3937 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3938 {
3939         return queue_command(xhci, 0, 0, 0,
3940                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3941                         false);
3942 }
3943
3944 /* Queue a configure endpoint command TRB */
3945 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3946                 u32 slot_id, bool command_must_succeed)
3947 {
3948         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3949                         upper_32_bits(in_ctx_ptr), 0,
3950                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3951                         command_must_succeed);
3952 }
3953
3954 /* Queue an evaluate context command TRB */
3955 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3956                 u32 slot_id, bool command_must_succeed)
3957 {
3958         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3959                         upper_32_bits(in_ctx_ptr), 0,
3960                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3961                         command_must_succeed);
3962 }
3963
3964 /*
3965  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3966  * activity on an endpoint that is about to be suspended.
3967  */
3968 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3969                 unsigned int ep_index, int suspend)
3970 {
3971         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3972         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3973         u32 type = TRB_TYPE(TRB_STOP_RING);
3974         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3975
3976         return queue_command(xhci, 0, 0, 0,
3977                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3978 }
3979
3980 /* Set Transfer Ring Dequeue Pointer command.
3981  * This should not be used for endpoints that have streams enabled.
3982  */
3983 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3984                 unsigned int ep_index, unsigned int stream_id,
3985                 struct xhci_segment *deq_seg,
3986                 union xhci_trb *deq_ptr, u32 cycle_state)
3987 {
3988         dma_addr_t addr;
3989         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3990         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3991         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3992         u32 type = TRB_TYPE(TRB_SET_DEQ);
3993         struct xhci_virt_ep *ep;
3994
3995         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3996         if (addr == 0) {
3997                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3998                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3999                                 deq_seg, deq_ptr);
4000                 return 0;
4001         }
4002         ep = &xhci->devs[slot_id]->eps[ep_index];
4003         if ((ep->ep_state & SET_DEQ_PENDING)) {
4004                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4005                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4006                 return 0;
4007         }
4008         ep->queued_deq_seg = deq_seg;
4009         ep->queued_deq_ptr = deq_ptr;
4010         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
4011                         upper_32_bits(addr), trb_stream_id,
4012                         trb_slot_id | trb_ep_index | type, false);
4013 }
4014
4015 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
4016                 unsigned int ep_index)
4017 {
4018         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4019         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4020         u32 type = TRB_TYPE(TRB_RESET_EP);
4021
4022         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
4023                         false);
4024 }