2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
70 #include "xhci-trace.h"
72 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
73 struct xhci_virt_device *virt_dev,
74 struct xhci_event_cmd *event);
77 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
80 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
83 unsigned long segment_offset;
85 if (!seg || !trb || trb < seg->trbs)
88 segment_offset = trb - seg->trbs;
89 if (segment_offset > TRBS_PER_SEGMENT)
91 return seg->dma + (segment_offset * sizeof(*trb));
94 /* Does this link TRB point to the first segment in a ring,
95 * or was the previous TRB the last TRB on the last segment in the ERST?
97 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
98 struct xhci_segment *seg, union xhci_trb *trb)
100 if (ring == xhci->event_ring)
101 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
102 (seg->next == xhci->event_ring->first_seg);
104 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
107 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
108 * segment? I.e. would the updated event TRB pointer step off the end of the
111 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
112 struct xhci_segment *seg, union xhci_trb *trb)
114 if (ring == xhci->event_ring)
115 return trb == &seg->trbs[TRBS_PER_SEGMENT];
117 return TRB_TYPE_LINK_LE32(trb->link.control);
120 static int enqueue_is_link_trb(struct xhci_ring *ring)
122 struct xhci_link_trb *link = &ring->enqueue->link;
123 return TRB_TYPE_LINK_LE32(link->control);
126 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
127 * TRB is in a new segment. This does not skip over link TRBs, and it does not
128 * effect the ring dequeue or enqueue pointers.
130 static void next_trb(struct xhci_hcd *xhci,
131 struct xhci_ring *ring,
132 struct xhci_segment **seg,
133 union xhci_trb **trb)
135 if (last_trb(xhci, ring, *seg, *trb)) {
137 *trb = ((*seg)->trbs);
144 * See Cycle bit rules. SW is the consumer for the event ring only.
145 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
147 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
152 * If this is not event ring, and the dequeue pointer
153 * is not on a link TRB, there is one more usable TRB
155 if (ring->type != TYPE_EVENT &&
156 !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
157 ring->num_trbs_free++;
161 * Update the dequeue pointer further if that was a link TRB or
162 * we're at the end of an event ring segment (which doesn't have
165 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
166 if (ring->type == TYPE_EVENT &&
167 last_trb_on_last_seg(xhci, ring,
168 ring->deq_seg, ring->dequeue)) {
169 ring->cycle_state ^= 1;
171 ring->deq_seg = ring->deq_seg->next;
172 ring->dequeue = ring->deq_seg->trbs;
176 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
180 * See Cycle bit rules. SW is the consumer for the event ring only.
181 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
183 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
184 * chain bit is set), then set the chain bit in all the following link TRBs.
185 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
186 * have their chain bit cleared (so that each Link TRB is a separate TD).
188 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
189 * set, but other sections talk about dealing with the chain bit set. This was
190 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
191 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
193 * @more_trbs_coming: Will you enqueue more TRBs before calling
194 * prepare_transfer()?
196 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
197 bool more_trbs_coming)
200 union xhci_trb *next;
202 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
203 /* If this is not event ring, there is one less usable TRB */
204 if (ring->type != TYPE_EVENT &&
205 !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
206 ring->num_trbs_free--;
207 next = ++(ring->enqueue);
210 /* Update the dequeue pointer further if that was a link TRB or we're at
211 * the end of an event ring segment (which doesn't have link TRBS)
213 while (last_trb(xhci, ring, ring->enq_seg, next)) {
214 if (ring->type != TYPE_EVENT) {
216 * If the caller doesn't plan on enqueueing more
217 * TDs before ringing the doorbell, then we
218 * don't want to give the link TRB to the
219 * hardware just yet. We'll give the link TRB
220 * back in prepare_ring() just before we enqueue
221 * the TD at the top of the ring.
223 if (!chain && !more_trbs_coming)
226 /* If we're not dealing with 0.95 hardware or
227 * isoc rings on AMD 0.96 host,
228 * carry over the chain bit of the previous TRB
229 * (which may mean the chain bit is cleared).
231 if (!(ring->type == TYPE_ISOC &&
232 (xhci->quirks & XHCI_AMD_0x96_HOST))
233 && !xhci_link_trb_quirk(xhci)) {
234 next->link.control &=
235 cpu_to_le32(~TRB_CHAIN);
236 next->link.control |=
239 /* Give this link TRB to the hardware */
241 next->link.control ^= cpu_to_le32(TRB_CYCLE);
243 /* Toggle the cycle bit after the last ring segment. */
244 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
245 ring->cycle_state = (ring->cycle_state ? 0 : 1);
248 ring->enq_seg = ring->enq_seg->next;
249 ring->enqueue = ring->enq_seg->trbs;
250 next = ring->enqueue;
255 * Check to see if there's room to enqueue num_trbs on the ring and make sure
256 * enqueue pointer will not advance into dequeue segment. See rules above.
258 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
259 unsigned int num_trbs)
261 int num_trbs_in_deq_seg;
263 if (ring->num_trbs_free < num_trbs)
266 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
267 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
268 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
275 /* Ring the host controller doorbell after placing a command on the ring */
276 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
278 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
281 xhci_dbg(xhci, "// Ding dong!\n");
282 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
283 /* Flush PCI posted writes */
284 readl(&xhci->dba->doorbell[0]);
287 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
292 xhci_dbg(xhci, "Abort command ring\n");
294 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
295 xhci_dbg(xhci, "The command ring isn't running, "
296 "Have the command ring been stopped?\n");
300 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
301 if (!(temp_64 & CMD_RING_RUNNING)) {
302 xhci_dbg(xhci, "Command ring had been stopped\n");
305 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
306 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
307 &xhci->op_regs->cmd_ring);
309 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
310 * time the completion od all xHCI commands, including
311 * the Command Abort operation. If software doesn't see
312 * CRR negated in a timely manner (e.g. longer than 5
313 * seconds), then it should assume that the there are
314 * larger problems with the xHC and assert HCRST.
316 ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
317 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
319 xhci_err(xhci, "Stopped the command ring failed, "
320 "maybe the host is dead\n");
321 xhci->xhc_state |= XHCI_STATE_DYING;
330 static int xhci_queue_cd(struct xhci_hcd *xhci,
331 struct xhci_command *command,
332 union xhci_trb *cmd_trb)
335 cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
338 INIT_LIST_HEAD(&cd->cancel_cmd_list);
340 cd->command = command;
341 cd->cmd_trb = cmd_trb;
342 list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
348 * Cancel the command which has issue.
350 * Some commands may hang due to waiting for acknowledgement from
351 * usb device. It is outside of the xHC's ability to control and
352 * will cause the command ring is blocked. When it occurs software
353 * should intervene to recover the command ring.
354 * See Section 4.6.1.1 and 4.6.1.2
356 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
357 union xhci_trb *cmd_trb)
362 spin_lock_irqsave(&xhci->lock, flags);
364 if (xhci->xhc_state & XHCI_STATE_DYING) {
365 xhci_warn(xhci, "Abort the command ring,"
366 " but the xHCI is dead.\n");
371 /* queue the cmd desriptor to cancel_cmd_list */
372 retval = xhci_queue_cd(xhci, command, cmd_trb);
374 xhci_warn(xhci, "Queuing command descriptor failed.\n");
378 /* abort command ring */
379 retval = xhci_abort_cmd_ring(xhci);
381 xhci_err(xhci, "Abort command ring failed\n");
382 if (unlikely(retval == -ESHUTDOWN)) {
383 spin_unlock_irqrestore(&xhci->lock, flags);
384 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
385 xhci_dbg(xhci, "xHCI host controller is dead.\n");
391 spin_unlock_irqrestore(&xhci->lock, flags);
395 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
396 unsigned int slot_id,
397 unsigned int ep_index,
398 unsigned int stream_id)
400 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
401 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
402 unsigned int ep_state = ep->ep_state;
404 /* Don't ring the doorbell for this endpoint if there are pending
405 * cancellations because we don't want to interrupt processing.
406 * We don't want to restart any stream rings if there's a set dequeue
407 * pointer command pending because the device can choose to start any
408 * stream once the endpoint is on the HW schedule.
409 * FIXME - check all the stream rings for pending cancellations.
411 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
412 (ep_state & EP_HALTED))
414 writel(DB_VALUE(ep_index, stream_id), db_addr);
415 /* The CPU has better things to do at this point than wait for a
416 * write-posting flush. It'll get there soon enough.
420 /* Ring the doorbell for any rings with pending URBs */
421 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
422 unsigned int slot_id,
423 unsigned int ep_index)
425 unsigned int stream_id;
426 struct xhci_virt_ep *ep;
428 ep = &xhci->devs[slot_id]->eps[ep_index];
430 /* A ring has pending URBs if its TD list is not empty */
431 if (!(ep->ep_state & EP_HAS_STREAMS)) {
432 if (ep->ring && !(list_empty(&ep->ring->td_list)))
433 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
437 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
439 struct xhci_stream_info *stream_info = ep->stream_info;
440 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
441 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
447 * Find the segment that trb is in. Start searching in start_seg.
448 * If we must move past a segment that has a link TRB with a toggle cycle state
449 * bit set, then we will toggle the value pointed at by cycle_state.
451 static struct xhci_segment *find_trb_seg(
452 struct xhci_segment *start_seg,
453 union xhci_trb *trb, int *cycle_state)
455 struct xhci_segment *cur_seg = start_seg;
456 struct xhci_generic_trb *generic_trb;
458 while (cur_seg->trbs > trb ||
459 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
460 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
461 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
463 cur_seg = cur_seg->next;
464 if (cur_seg == start_seg)
465 /* Looped over the entire list. Oops! */
472 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
473 unsigned int slot_id, unsigned int ep_index,
474 unsigned int stream_id)
476 struct xhci_virt_ep *ep;
478 ep = &xhci->devs[slot_id]->eps[ep_index];
479 /* Common case: no streams */
480 if (!(ep->ep_state & EP_HAS_STREAMS))
483 if (stream_id == 0) {
485 "WARN: Slot ID %u, ep index %u has streams, "
486 "but URB has no stream ID.\n",
491 if (stream_id < ep->stream_info->num_streams)
492 return ep->stream_info->stream_rings[stream_id];
495 "WARN: Slot ID %u, ep index %u has "
496 "stream IDs 1 to %u allocated, "
497 "but stream ID %u is requested.\n",
499 ep->stream_info->num_streams - 1,
504 /* Get the right ring for the given URB.
505 * If the endpoint supports streams, boundary check the URB's stream ID.
506 * If the endpoint doesn't support streams, return the singular endpoint ring.
508 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
511 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
512 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
516 * Move the xHC's endpoint ring dequeue pointer past cur_td.
517 * Record the new state of the xHC's endpoint ring dequeue segment,
518 * dequeue pointer, and new consumer cycle state in state.
519 * Update our internal representation of the ring's dequeue pointer.
521 * We do this in three jumps:
522 * - First we update our new ring state to be the same as when the xHC stopped.
523 * - Then we traverse the ring to find the segment that contains
524 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
525 * any link TRBs with the toggle cycle bit set.
526 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
527 * if we've moved it past a link TRB with the toggle cycle bit set.
529 * Some of the uses of xhci_generic_trb are grotty, but if they're done
530 * with correct __le32 accesses they should work fine. Only users of this are
533 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
534 unsigned int slot_id, unsigned int ep_index,
535 unsigned int stream_id, struct xhci_td *cur_td,
536 struct xhci_dequeue_state *state)
538 struct xhci_virt_device *dev = xhci->devs[slot_id];
539 struct xhci_virt_ep *ep = &dev->eps[ep_index];
540 struct xhci_ring *ep_ring;
541 struct xhci_generic_trb *trb;
545 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
546 ep_index, stream_id);
548 xhci_warn(xhci, "WARN can't find new dequeue state "
549 "for invalid stream ID %u.\n",
554 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
555 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
556 "Finding endpoint context");
557 /* 4.6.9 the css flag is written to the stream context for streams */
558 if (ep->ep_state & EP_HAS_STREAMS) {
559 struct xhci_stream_ctx *ctx =
560 &ep->stream_info->stream_ctx_array[stream_id];
561 hw_dequeue = le64_to_cpu(ctx->stream_ring);
563 struct xhci_ep_ctx *ep_ctx
564 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
565 hw_dequeue = le64_to_cpu(ep_ctx->deq);
568 /* Find virtual address and segment of hardware dequeue pointer */
569 state->new_deq_seg = ep_ring->deq_seg;
570 state->new_deq_ptr = ep_ring->dequeue;
571 while (xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr)
572 != (dma_addr_t)(hw_dequeue & ~0xf)) {
573 next_trb(xhci, ep_ring, &state->new_deq_seg,
574 &state->new_deq_ptr);
575 if (state->new_deq_ptr == ep_ring->dequeue) {
581 * Find cycle state for last_trb, starting at old cycle state of
582 * hw_dequeue. If there is only one segment ring, find_trb_seg() will
583 * return immediately and cannot toggle the cycle state if this search
584 * wraps around, so add one more toggle manually in that case.
586 state->new_cycle_state = hw_dequeue & 0x1;
587 if (ep_ring->first_seg == ep_ring->first_seg->next &&
588 cur_td->last_trb < state->new_deq_ptr)
589 state->new_cycle_state ^= 0x1;
591 state->new_deq_ptr = cur_td->last_trb;
592 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
593 "Finding segment containing last TRB in TD.");
594 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
595 state->new_deq_ptr, &state->new_cycle_state);
596 if (!state->new_deq_seg) {
601 /* Increment to find next TRB after last_trb. Cycle if appropriate. */
602 trb = &state->new_deq_ptr->generic;
603 if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
604 (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
605 state->new_cycle_state ^= 0x1;
606 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
608 /* Don't update the ring cycle state for the producer (us). */
609 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
610 "Cycle state = 0x%x", state->new_cycle_state);
612 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
613 "New dequeue segment = %p (virtual)",
615 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
616 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
617 "New dequeue pointer = 0x%llx (DMA)",
618 (unsigned long long) addr);
621 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
622 * (The last TRB actually points to the ring enqueue pointer, which is not part
623 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
625 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
626 struct xhci_td *cur_td, bool flip_cycle)
628 struct xhci_segment *cur_seg;
629 union xhci_trb *cur_trb;
631 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
633 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
634 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
635 /* Unchain any chained Link TRBs, but
636 * leave the pointers intact.
638 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
639 /* Flip the cycle bit (link TRBs can't be the first
643 cur_trb->generic.field[3] ^=
644 cpu_to_le32(TRB_CYCLE);
645 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
646 "Cancel (unchain) link TRB");
647 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
648 "Address = %p (0x%llx dma); "
649 "in seg %p (0x%llx dma)",
651 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
653 (unsigned long long)cur_seg->dma);
655 cur_trb->generic.field[0] = 0;
656 cur_trb->generic.field[1] = 0;
657 cur_trb->generic.field[2] = 0;
658 /* Preserve only the cycle bit of this TRB */
659 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
660 /* Flip the cycle bit except on the first or last TRB */
661 if (flip_cycle && cur_trb != cur_td->first_trb &&
662 cur_trb != cur_td->last_trb)
663 cur_trb->generic.field[3] ^=
664 cpu_to_le32(TRB_CYCLE);
665 cur_trb->generic.field[3] |= cpu_to_le32(
666 TRB_TYPE(TRB_TR_NOOP));
667 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
668 "TRB to noop at offset 0x%llx",
670 xhci_trb_virt_to_dma(cur_seg, cur_trb));
672 if (cur_trb == cur_td->last_trb)
677 static int queue_set_tr_deq(struct xhci_hcd *xhci,
678 struct xhci_command *cmd, int slot_id,
679 unsigned int ep_index, unsigned int stream_id,
680 struct xhci_segment *deq_seg,
681 union xhci_trb *deq_ptr, u32 cycle_state);
683 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
684 struct xhci_command *cmd,
685 unsigned int slot_id, unsigned int ep_index,
686 unsigned int stream_id,
687 struct xhci_dequeue_state *deq_state)
689 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
691 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
692 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
693 "new deq ptr = %p (0x%llx dma), new cycle = %u",
694 deq_state->new_deq_seg,
695 (unsigned long long)deq_state->new_deq_seg->dma,
696 deq_state->new_deq_ptr,
697 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
698 deq_state->new_cycle_state);
699 queue_set_tr_deq(xhci, cmd, slot_id, ep_index, stream_id,
700 deq_state->new_deq_seg,
701 deq_state->new_deq_ptr,
702 (u32) deq_state->new_cycle_state);
703 /* Stop the TD queueing code from ringing the doorbell until
704 * this command completes. The HC won't set the dequeue pointer
705 * if the ring is running, and ringing the doorbell starts the
708 ep->ep_state |= SET_DEQ_PENDING;
711 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
712 struct xhci_virt_ep *ep)
714 ep->ep_state &= ~EP_HALT_PENDING;
715 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
716 * timer is running on another CPU, we don't decrement stop_cmds_pending
717 * (since we didn't successfully stop the watchdog timer).
719 if (del_timer(&ep->stop_cmd_timer))
720 ep->stop_cmds_pending--;
723 /* Must be called with xhci->lock held in interrupt context */
724 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
725 struct xhci_td *cur_td, int status)
729 struct urb_priv *urb_priv;
732 urb_priv = urb->hcpriv;
734 hcd = bus_to_hcd(urb->dev->bus);
736 /* Only giveback urb when this is the last td in urb */
737 if (urb_priv->td_cnt == urb_priv->length) {
738 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
739 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
740 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
741 if (xhci->quirks & XHCI_AMD_PLL_FIX)
742 usb_amd_quirk_pll_enable();
745 usb_hcd_unlink_urb_from_ep(hcd, urb);
747 spin_unlock(&xhci->lock);
748 usb_hcd_giveback_urb(hcd, urb, status);
749 xhci_urb_free_priv(xhci, urb_priv);
750 spin_lock(&xhci->lock);
755 * When we get a command completion for a Stop Endpoint Command, we need to
756 * unlink any cancelled TDs from the ring. There are two ways to do that:
758 * 1. If the HW was in the middle of processing the TD that needs to be
759 * cancelled, then we must move the ring's dequeue pointer past the last TRB
760 * in the TD with a Set Dequeue Pointer Command.
761 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
762 * bit cleared) so that the HW will skip over them.
764 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
765 union xhci_trb *trb, struct xhci_event_cmd *event)
767 unsigned int ep_index;
768 struct xhci_virt_device *virt_dev;
769 struct xhci_ring *ep_ring;
770 struct xhci_virt_ep *ep;
771 struct list_head *entry;
772 struct xhci_td *cur_td = NULL;
773 struct xhci_td *last_unlinked_td;
775 struct xhci_dequeue_state deq_state;
777 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
778 virt_dev = xhci->devs[slot_id];
780 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
783 xhci_warn(xhci, "Stop endpoint command "
784 "completion for disabled slot %u\n",
789 memset(&deq_state, 0, sizeof(deq_state));
790 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
791 ep = &xhci->devs[slot_id]->eps[ep_index];
793 if (list_empty(&ep->cancelled_td_list)) {
794 xhci_stop_watchdog_timer_in_irq(xhci, ep);
795 ep->stopped_td = NULL;
796 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
800 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
801 * We have the xHCI lock, so nothing can modify this list until we drop
802 * it. We're also in the event handler, so we can't get re-interrupted
803 * if another Stop Endpoint command completes
805 list_for_each(entry, &ep->cancelled_td_list) {
806 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
807 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
808 "Removing canceled TD starting at 0x%llx (dma).",
809 (unsigned long long)xhci_trb_virt_to_dma(
810 cur_td->start_seg, cur_td->first_trb));
811 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
813 /* This shouldn't happen unless a driver is mucking
814 * with the stream ID after submission. This will
815 * leave the TD on the hardware ring, and the hardware
816 * will try to execute it, and may access a buffer
817 * that has already been freed. In the best case, the
818 * hardware will execute it, and the event handler will
819 * ignore the completion event for that TD, since it was
820 * removed from the td_list for that endpoint. In
821 * short, don't muck with the stream ID after
824 xhci_warn(xhci, "WARN Cancelled URB %p "
825 "has invalid stream ID %u.\n",
827 cur_td->urb->stream_id);
828 goto remove_finished_td;
831 * If we stopped on the TD we need to cancel, then we have to
832 * move the xHC endpoint ring dequeue pointer past this TD.
834 if (cur_td == ep->stopped_td)
835 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
836 cur_td->urb->stream_id,
839 td_to_noop(xhci, ep_ring, cur_td, false);
842 * The event handler won't see a completion for this TD anymore,
843 * so remove it from the endpoint ring's TD list. Keep it in
844 * the cancelled TD list for URB completion later.
846 list_del_init(&cur_td->td_list);
848 last_unlinked_td = cur_td;
849 xhci_stop_watchdog_timer_in_irq(xhci, ep);
851 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
852 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
853 struct xhci_command *command;
854 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
855 xhci_queue_new_dequeue_state(xhci, command,
857 ep->stopped_td->urb->stream_id,
859 xhci_ring_cmd_db(xhci);
861 /* Otherwise ring the doorbell(s) to restart queued transfers */
862 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
865 /* Clear stopped_td if endpoint is not halted */
866 if (!(ep->ep_state & EP_HALTED))
867 ep->stopped_td = NULL;
870 * Drop the lock and complete the URBs in the cancelled TD list.
871 * New TDs to be cancelled might be added to the end of the list before
872 * we can complete all the URBs for the TDs we already unlinked.
873 * So stop when we've completed the URB for the last TD we unlinked.
876 cur_td = list_entry(ep->cancelled_td_list.next,
877 struct xhci_td, cancelled_td_list);
878 list_del_init(&cur_td->cancelled_td_list);
880 /* Clean up the cancelled URB */
881 /* Doesn't matter what we pass for status, since the core will
882 * just overwrite it (because the URB has been unlinked).
884 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
886 /* Stop processing the cancelled list if the watchdog timer is
889 if (xhci->xhc_state & XHCI_STATE_DYING)
891 } while (cur_td != last_unlinked_td);
893 /* Return to the event handler with xhci->lock re-acquired */
896 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
898 struct xhci_td *cur_td;
900 while (!list_empty(&ring->td_list)) {
901 cur_td = list_first_entry(&ring->td_list,
902 struct xhci_td, td_list);
903 list_del_init(&cur_td->td_list);
904 if (!list_empty(&cur_td->cancelled_td_list))
905 list_del_init(&cur_td->cancelled_td_list);
906 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
910 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
911 int slot_id, int ep_index)
913 struct xhci_td *cur_td;
914 struct xhci_virt_ep *ep;
915 struct xhci_ring *ring;
917 ep = &xhci->devs[slot_id]->eps[ep_index];
918 if ((ep->ep_state & EP_HAS_STREAMS) ||
919 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
922 for (stream_id = 0; stream_id < ep->stream_info->num_streams;
924 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
925 "Killing URBs for slot ID %u, ep index %u, stream %u",
926 slot_id, ep_index, stream_id + 1);
927 xhci_kill_ring_urbs(xhci,
928 ep->stream_info->stream_rings[stream_id]);
934 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
935 "Killing URBs for slot ID %u, ep index %u",
937 xhci_kill_ring_urbs(xhci, ring);
939 while (!list_empty(&ep->cancelled_td_list)) {
940 cur_td = list_first_entry(&ep->cancelled_td_list,
941 struct xhci_td, cancelled_td_list);
942 list_del_init(&cur_td->cancelled_td_list);
943 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
947 /* Watchdog timer function for when a stop endpoint command fails to complete.
948 * In this case, we assume the host controller is broken or dying or dead. The
949 * host may still be completing some other events, so we have to be careful to
950 * let the event ring handler and the URB dequeueing/enqueueing functions know
951 * through xhci->state.
953 * The timer may also fire if the host takes a very long time to respond to the
954 * command, and the stop endpoint command completion handler cannot delete the
955 * timer before the timer function is called. Another endpoint cancellation may
956 * sneak in before the timer function can grab the lock, and that may queue
957 * another stop endpoint command and add the timer back. So we cannot use a
958 * simple flag to say whether there is a pending stop endpoint command for a
959 * particular endpoint.
961 * Instead we use a combination of that flag and a counter for the number of
962 * pending stop endpoint commands. If the timer is the tail end of the last
963 * stop endpoint command, and the endpoint's command is still pending, we assume
966 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
968 struct xhci_hcd *xhci;
969 struct xhci_virt_ep *ep;
973 ep = (struct xhci_virt_ep *) arg;
976 spin_lock_irqsave(&xhci->lock, flags);
978 ep->stop_cmds_pending--;
979 if (xhci->xhc_state & XHCI_STATE_DYING) {
980 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
981 "Stop EP timer ran, but another timer marked "
982 "xHCI as DYING, exiting.");
983 spin_unlock_irqrestore(&xhci->lock, flags);
986 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
987 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
988 "Stop EP timer ran, but no command pending, "
990 spin_unlock_irqrestore(&xhci->lock, flags);
994 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
995 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
996 /* Oops, HC is dead or dying or at least not responding to the stop
999 xhci->xhc_state |= XHCI_STATE_DYING;
1000 /* Disable interrupts from the host controller and start halting it */
1002 spin_unlock_irqrestore(&xhci->lock, flags);
1004 ret = xhci_halt(xhci);
1006 spin_lock_irqsave(&xhci->lock, flags);
1008 /* This is bad; the host is not responding to commands and it's
1009 * not allowing itself to be halted. At least interrupts are
1010 * disabled. If we call usb_hc_died(), it will attempt to
1011 * disconnect all device drivers under this host. Those
1012 * disconnect() methods will wait for all URBs to be unlinked,
1013 * so we must complete them.
1015 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
1016 xhci_warn(xhci, "Completing active URBs anyway.\n");
1017 /* We could turn all TDs on the rings to no-ops. This won't
1018 * help if the host has cached part of the ring, and is slow if
1019 * we want to preserve the cycle bit. Skip it and hope the host
1020 * doesn't touch the memory.
1023 for (i = 0; i < MAX_HC_SLOTS; i++) {
1026 for (j = 0; j < 31; j++)
1027 xhci_kill_endpoint_urbs(xhci, i, j);
1029 spin_unlock_irqrestore(&xhci->lock, flags);
1030 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1031 "Calling usb_hc_died()");
1032 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1033 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1034 "xHCI host controller is dead.");
1038 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1039 struct xhci_virt_device *dev,
1040 struct xhci_ring *ep_ring,
1041 unsigned int ep_index)
1043 union xhci_trb *dequeue_temp;
1044 int num_trbs_free_temp;
1045 bool revert = false;
1047 num_trbs_free_temp = ep_ring->num_trbs_free;
1048 dequeue_temp = ep_ring->dequeue;
1050 /* If we get two back-to-back stalls, and the first stalled transfer
1051 * ends just before a link TRB, the dequeue pointer will be left on
1052 * the link TRB by the code in the while loop. So we have to update
1053 * the dequeue pointer one segment further, or we'll jump off
1054 * the segment into la-la-land.
1056 if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
1057 ep_ring->deq_seg = ep_ring->deq_seg->next;
1058 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1061 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1062 /* We have more usable TRBs */
1063 ep_ring->num_trbs_free++;
1065 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
1066 ep_ring->dequeue)) {
1067 if (ep_ring->dequeue ==
1068 dev->eps[ep_index].queued_deq_ptr)
1070 ep_ring->deq_seg = ep_ring->deq_seg->next;
1071 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1073 if (ep_ring->dequeue == dequeue_temp) {
1080 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1081 ep_ring->num_trbs_free = num_trbs_free_temp;
1086 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1087 * we need to clear the set deq pending flag in the endpoint ring state, so that
1088 * the TD queueing code can ring the doorbell again. We also need to ring the
1089 * endpoint doorbell to restart the ring, but only if there aren't more
1090 * cancellations pending.
1092 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1093 union xhci_trb *trb, u32 cmd_comp_code)
1095 unsigned int ep_index;
1096 unsigned int stream_id;
1097 struct xhci_ring *ep_ring;
1098 struct xhci_virt_device *dev;
1099 struct xhci_virt_ep *ep;
1100 struct xhci_ep_ctx *ep_ctx;
1101 struct xhci_slot_ctx *slot_ctx;
1103 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1104 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1105 dev = xhci->devs[slot_id];
1106 ep = &dev->eps[ep_index];
1108 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1110 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1112 /* XXX: Harmless??? */
1113 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1117 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1118 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1120 if (cmd_comp_code != COMP_SUCCESS) {
1121 unsigned int ep_state;
1122 unsigned int slot_state;
1124 switch (cmd_comp_code) {
1126 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1128 case COMP_CTX_STATE:
1129 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1130 ep_state = le32_to_cpu(ep_ctx->ep_info);
1131 ep_state &= EP_STATE_MASK;
1132 slot_state = le32_to_cpu(slot_ctx->dev_state);
1133 slot_state = GET_SLOT_STATE(slot_state);
1134 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1135 "Slot state = %u, EP state = %u",
1136 slot_state, ep_state);
1139 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1143 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1147 /* OK what do we do now? The endpoint state is hosed, and we
1148 * should never get to this point if the synchronization between
1149 * queueing, and endpoint state are correct. This might happen
1150 * if the device gets disconnected after we've finished
1151 * cancelling URBs, which might not be an error...
1155 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1156 if (ep->ep_state & EP_HAS_STREAMS) {
1157 struct xhci_stream_ctx *ctx =
1158 &ep->stream_info->stream_ctx_array[stream_id];
1159 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1161 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1163 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1164 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1165 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1166 ep->queued_deq_ptr) == deq) {
1167 /* Update the ring's dequeue segment and dequeue pointer
1168 * to reflect the new position.
1170 update_ring_for_set_deq_completion(xhci, dev,
1173 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1174 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1175 ep->queued_deq_seg, ep->queued_deq_ptr);
1179 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1180 dev->eps[ep_index].queued_deq_seg = NULL;
1181 dev->eps[ep_index].queued_deq_ptr = NULL;
1182 /* Restart any rings with pending URBs */
1183 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1186 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1187 union xhci_trb *trb, u32 cmd_comp_code)
1189 unsigned int ep_index;
1191 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1192 /* This command will only fail if the endpoint wasn't halted,
1193 * but we don't care.
1195 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1196 "Ignoring reset ep completion code of %u", cmd_comp_code);
1198 /* HW with the reset endpoint quirk needs to have a configure endpoint
1199 * command complete before the endpoint can be used. Queue that here
1200 * because the HW can't handle two commands being queued in a row.
1202 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1203 struct xhci_command *command;
1204 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1205 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1206 "Queueing configure endpoint command");
1207 xhci_queue_configure_endpoint(xhci, command,
1208 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1210 xhci_ring_cmd_db(xhci);
1212 /* Clear our internal halted state and restart the ring(s) */
1213 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1214 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1218 /* Complete the command and detele it from the devcie's command queue.
1220 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1221 struct xhci_command *command, u32 status)
1223 command->status = status;
1224 list_del(&command->cmd_list);
1225 if (command->completion)
1226 complete(command->completion);
1228 xhci_free_command(xhci, command);
1232 /* Check to see if a command in the device's command queue matches this one.
1233 * Signal the completion or free the command, and return 1. Return 0 if the
1234 * completed command isn't at the head of the command list.
1236 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1237 struct xhci_virt_device *virt_dev,
1238 struct xhci_event_cmd *event)
1240 struct xhci_command *command;
1242 if (list_empty(&virt_dev->cmd_list))
1245 command = list_entry(virt_dev->cmd_list.next,
1246 struct xhci_command, cmd_list);
1247 if (xhci->cmd_ring->dequeue != command->command_trb)
1250 xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1251 GET_COMP_CODE(le32_to_cpu(event->status)));
1256 * Finding the command trb need to be cancelled and modifying it to
1257 * NO OP command. And if the command is in device's command wait
1258 * list, finishing and freeing it.
1260 * If we can't find the command trb, we think it had already been
1263 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1265 struct xhci_segment *cur_seg;
1266 union xhci_trb *cmd_trb;
1269 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1272 /* find the current segment of command ring */
1273 cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1274 xhci->cmd_ring->dequeue, &cycle_state);
1277 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1278 xhci->cmd_ring->dequeue,
1279 (unsigned long long)
1280 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1281 xhci->cmd_ring->dequeue));
1282 xhci_debug_ring(xhci, xhci->cmd_ring);
1283 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1287 /* find the command trb matched by cd from command ring */
1288 for (cmd_trb = xhci->cmd_ring->dequeue;
1289 cmd_trb != xhci->cmd_ring->enqueue;
1290 next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1291 /* If the trb is link trb, continue */
1292 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1295 if (cur_cd->cmd_trb == cmd_trb) {
1297 /* If the command in device's command list, we should
1298 * finish it and free the command structure.
1300 if (cur_cd->command)
1301 xhci_complete_cmd_in_cmd_wait_list(xhci,
1302 cur_cd->command, COMP_CMD_STOP);
1304 /* get cycle state from the origin command trb */
1305 cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1308 /* modify the command trb to NO OP command */
1309 cmd_trb->generic.field[0] = 0;
1310 cmd_trb->generic.field[1] = 0;
1311 cmd_trb->generic.field[2] = 0;
1312 cmd_trb->generic.field[3] = cpu_to_le32(
1313 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1319 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1321 struct xhci_cd *cur_cd, *next_cd;
1323 if (list_empty(&xhci->cancel_cmd_list))
1326 list_for_each_entry_safe(cur_cd, next_cd,
1327 &xhci->cancel_cmd_list, cancel_cmd_list) {
1328 xhci_cmd_to_noop(xhci, cur_cd);
1329 list_del(&cur_cd->cancel_cmd_list);
1335 * traversing the cancel_cmd_list. If the command descriptor according
1336 * to cmd_trb is found, the function free it and return 1, otherwise
1339 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1340 union xhci_trb *cmd_trb)
1342 struct xhci_cd *cur_cd, *next_cd;
1344 if (list_empty(&xhci->cancel_cmd_list))
1347 list_for_each_entry_safe(cur_cd, next_cd,
1348 &xhci->cancel_cmd_list, cancel_cmd_list) {
1349 if (cur_cd->cmd_trb == cmd_trb) {
1350 if (cur_cd->command)
1351 xhci_complete_cmd_in_cmd_wait_list(xhci,
1352 cur_cd->command, COMP_CMD_STOP);
1353 list_del(&cur_cd->cancel_cmd_list);
1363 * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1364 * trb pointed by the command ring dequeue pointer is the trb we want to
1365 * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1366 * traverse the cancel_cmd_list to trun the all of the commands according
1367 * to command descriptor to NO-OP trb.
1369 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1370 int cmd_trb_comp_code)
1372 int cur_trb_is_good = 0;
1374 /* Searching the cmd trb pointed by the command ring dequeue
1375 * pointer in command descriptor list. If it is found, free it.
1377 cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1378 xhci->cmd_ring->dequeue);
1380 if (cmd_trb_comp_code == COMP_CMD_ABORT)
1381 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1382 else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1383 /* traversing the cancel_cmd_list and canceling
1384 * the command according to command descriptor
1386 xhci_cancel_cmd_in_cd_list(xhci);
1388 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1390 * ring command ring doorbell again to restart the
1393 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1394 xhci_ring_cmd_db(xhci);
1396 return cur_trb_is_good;
1399 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1402 if (cmd_comp_code == COMP_SUCCESS)
1403 xhci->slot_id = slot_id;
1406 complete(&xhci->addr_dev);
1409 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1411 struct xhci_virt_device *virt_dev;
1413 virt_dev = xhci->devs[slot_id];
1416 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1417 /* Delete default control endpoint resources */
1418 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1419 xhci_free_virt_device(xhci, slot_id);
1422 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1423 struct xhci_event_cmd *event, u32 cmd_comp_code)
1425 struct xhci_virt_device *virt_dev;
1426 struct xhci_input_control_ctx *ctrl_ctx;
1427 unsigned int ep_index;
1428 unsigned int ep_state;
1429 u32 add_flags, drop_flags;
1431 virt_dev = xhci->devs[slot_id];
1432 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1435 * Configure endpoint commands can come from the USB core
1436 * configuration or alt setting changes, or because the HW
1437 * needed an extra configure endpoint command after a reset
1438 * endpoint command or streams were being configured.
1439 * If the command was for a halted endpoint, the xHCI driver
1440 * is not waiting on the configure endpoint command.
1442 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1444 xhci_warn(xhci, "Could not get input context, bad type.\n");
1448 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1449 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1450 /* Input ctx add_flags are the endpoint index plus one */
1451 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1453 /* A usb_set_interface() call directly after clearing a halted
1454 * condition may race on this quirky hardware. Not worth
1455 * worrying about, since this is prototype hardware. Not sure
1456 * if this will work for streams, but streams support was
1457 * untested on this prototype.
1459 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1460 ep_index != (unsigned int) -1 &&
1461 add_flags - SLOT_FLAG == drop_flags) {
1462 ep_state = virt_dev->eps[ep_index].ep_state;
1463 if (!(ep_state & EP_HALTED))
1465 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1466 "Completed config ep cmd - "
1467 "last ep index = %d, state = %d",
1468 ep_index, ep_state);
1469 /* Clear internal halted state and restart ring(s) */
1470 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1471 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1477 static void xhci_handle_cmd_eval_ctx(struct xhci_hcd *xhci, int slot_id,
1478 struct xhci_event_cmd *event, u32 cmd_comp_code)
1480 struct xhci_virt_device *virt_dev;
1482 virt_dev = xhci->devs[slot_id];
1483 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1485 virt_dev->cmd_status = cmd_comp_code;
1486 complete(&virt_dev->cmd_completion);
1489 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id,
1492 xhci->devs[slot_id]->cmd_status = cmd_comp_code;
1493 complete(&xhci->addr_dev);
1496 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1497 struct xhci_event_cmd *event)
1499 struct xhci_virt_device *virt_dev;
1501 xhci_dbg(xhci, "Completed reset device command.\n");
1502 virt_dev = xhci->devs[slot_id];
1504 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1506 xhci_warn(xhci, "Reset device command completion "
1507 "for disabled slot %u\n", slot_id);
1510 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1511 struct xhci_event_cmd *event)
1513 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1514 xhci->error_bitmask |= 1 << 6;
1517 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1518 "NEC firmware version %2x.%02x",
1519 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1520 NEC_FW_MINOR(le32_to_cpu(event->status)));
1523 static void handle_cmd_completion(struct xhci_hcd *xhci,
1524 struct xhci_event_cmd *event)
1526 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1528 dma_addr_t cmd_dequeue_dma;
1530 union xhci_trb *cmd_trb;
1533 cmd_dma = le64_to_cpu(event->cmd_trb);
1534 cmd_trb = xhci->cmd_ring->dequeue;
1535 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1537 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1538 if (cmd_dequeue_dma == 0) {
1539 xhci->error_bitmask |= 1 << 4;
1542 /* Does the DMA address match our internal dequeue pointer address? */
1543 if (cmd_dma != (u64) cmd_dequeue_dma) {
1544 xhci->error_bitmask |= 1 << 5;
1548 trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1550 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1551 if (cmd_comp_code == COMP_CMD_ABORT || cmd_comp_code == COMP_CMD_STOP) {
1552 /* If the return value is 0, we think the trb pointed by
1553 * command ring dequeue pointer is a good trb. The good
1554 * trb means we don't want to cancel the trb, but it have
1555 * been stopped by host. So we should handle it normally.
1556 * Otherwise, driver should invoke inc_deq() and return.
1558 if (handle_stopped_cmd_ring(xhci, cmd_comp_code)) {
1559 inc_deq(xhci, xhci->cmd_ring);
1562 /* There is no command to handle if we get a stop event when the
1563 * command ring is empty, event->cmd_trb points to the next
1566 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1570 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1572 case TRB_ENABLE_SLOT:
1573 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1575 case TRB_DISABLE_SLOT:
1576 xhci_handle_cmd_disable_slot(xhci, slot_id);
1579 xhci_handle_cmd_config_ep(xhci, slot_id, event, cmd_comp_code);
1581 case TRB_EVAL_CONTEXT:
1582 xhci_handle_cmd_eval_ctx(xhci, slot_id, event, cmd_comp_code);
1585 xhci_handle_cmd_addr_dev(xhci, slot_id, cmd_comp_code);
1588 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1589 le32_to_cpu(cmd_trb->generic.field[3])));
1590 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1593 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1594 le32_to_cpu(cmd_trb->generic.field[3])));
1595 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1600 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1601 le32_to_cpu(cmd_trb->generic.field[3])));
1602 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1605 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1606 le32_to_cpu(cmd_trb->generic.field[3])));
1607 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1609 case TRB_NEC_GET_FW:
1610 xhci_handle_cmd_nec_get_fw(xhci, event);
1613 /* Skip over unknown commands on the event ring */
1614 xhci->error_bitmask |= 1 << 6;
1617 inc_deq(xhci, xhci->cmd_ring);
1620 static void handle_vendor_event(struct xhci_hcd *xhci,
1621 union xhci_trb *event)
1625 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1626 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1627 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1628 handle_cmd_completion(xhci, &event->event_cmd);
1631 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1632 * port registers -- USB 3.0 and USB 2.0).
1634 * Returns a zero-based port number, which is suitable for indexing into each of
1635 * the split roothubs' port arrays and bus state arrays.
1636 * Add one to it in order to call xhci_find_slot_id_by_port.
1638 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1639 struct xhci_hcd *xhci, u32 port_id)
1642 unsigned int num_similar_speed_ports = 0;
1644 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1645 * and usb2_ports are 0-based indexes. Count the number of similar
1646 * speed ports, up to 1 port before this port.
1648 for (i = 0; i < (port_id - 1); i++) {
1649 u8 port_speed = xhci->port_array[i];
1652 * Skip ports that don't have known speeds, or have duplicate
1653 * Extended Capabilities port speed entries.
1655 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1659 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1660 * 1.1 ports are under the USB 2.0 hub. If the port speed
1661 * matches the device speed, it's a similar speed port.
1663 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1664 num_similar_speed_ports++;
1666 return num_similar_speed_ports;
1669 static void handle_device_notification(struct xhci_hcd *xhci,
1670 union xhci_trb *event)
1673 struct usb_device *udev;
1675 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1676 if (!xhci->devs[slot_id]) {
1677 xhci_warn(xhci, "Device Notification event for "
1678 "unused slot %u\n", slot_id);
1682 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1684 udev = xhci->devs[slot_id]->udev;
1685 if (udev && udev->parent)
1686 usb_wakeup_notification(udev->parent, udev->portnum);
1689 static void handle_port_status(struct xhci_hcd *xhci,
1690 union xhci_trb *event)
1692 struct usb_hcd *hcd;
1697 unsigned int faked_port_index;
1699 struct xhci_bus_state *bus_state;
1700 __le32 __iomem **port_array;
1701 bool bogus_port_status = false;
1703 /* Port status change events always have a successful completion code */
1704 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1705 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1706 xhci->error_bitmask |= 1 << 8;
1708 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1709 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1711 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1712 if ((port_id <= 0) || (port_id > max_ports)) {
1713 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1714 inc_deq(xhci, xhci->event_ring);
1718 /* Figure out which usb_hcd this port is attached to:
1719 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1721 major_revision = xhci->port_array[port_id - 1];
1723 /* Find the right roothub. */
1724 hcd = xhci_to_hcd(xhci);
1725 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1726 hcd = xhci->shared_hcd;
1728 if (major_revision == 0) {
1729 xhci_warn(xhci, "Event for port %u not in "
1730 "Extended Capabilities, ignoring.\n",
1732 bogus_port_status = true;
1735 if (major_revision == DUPLICATE_ENTRY) {
1736 xhci_warn(xhci, "Event for port %u duplicated in"
1737 "Extended Capabilities, ignoring.\n",
1739 bogus_port_status = true;
1744 * Hardware port IDs reported by a Port Status Change Event include USB
1745 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1746 * resume event, but we first need to translate the hardware port ID
1747 * into the index into the ports on the correct split roothub, and the
1748 * correct bus_state structure.
1750 bus_state = &xhci->bus_state[hcd_index(hcd)];
1751 if (hcd->speed == HCD_USB3)
1752 port_array = xhci->usb3_ports;
1754 port_array = xhci->usb2_ports;
1755 /* Find the faked port hub number */
1756 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1759 temp = readl(port_array[faked_port_index]);
1760 if (hcd->state == HC_STATE_SUSPENDED) {
1761 xhci_dbg(xhci, "resume root hub\n");
1762 usb_hcd_resume_root_hub(hcd);
1765 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1766 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1768 temp1 = readl(&xhci->op_regs->command);
1769 if (!(temp1 & CMD_RUN)) {
1770 xhci_warn(xhci, "xHC is not running.\n");
1774 if (DEV_SUPERSPEED(temp)) {
1775 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1776 /* Set a flag to say the port signaled remote wakeup,
1777 * so we can tell the difference between the end of
1778 * device and host initiated resume.
1780 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1781 xhci_test_and_clear_bit(xhci, port_array,
1782 faked_port_index, PORT_PLC);
1783 xhci_set_link_state(xhci, port_array, faked_port_index,
1785 /* Need to wait until the next link state change
1786 * indicates the device is actually in U0.
1788 bogus_port_status = true;
1791 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1792 bus_state->resume_done[faked_port_index] = jiffies +
1793 msecs_to_jiffies(20);
1794 set_bit(faked_port_index, &bus_state->resuming_ports);
1795 mod_timer(&hcd->rh_timer,
1796 bus_state->resume_done[faked_port_index]);
1797 /* Do the rest in GetPortStatus */
1801 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1802 DEV_SUPERSPEED(temp)) {
1803 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1804 /* We've just brought the device into U0 through either the
1805 * Resume state after a device remote wakeup, or through the
1806 * U3Exit state after a host-initiated resume. If it's a device
1807 * initiated remote wake, don't pass up the link state change,
1808 * so the roothub behavior is consistent with external
1809 * USB 3.0 hub behavior.
1811 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1812 faked_port_index + 1);
1813 if (slot_id && xhci->devs[slot_id])
1814 xhci_ring_device(xhci, slot_id);
1815 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1816 bus_state->port_remote_wakeup &=
1817 ~(1 << faked_port_index);
1818 xhci_test_and_clear_bit(xhci, port_array,
1819 faked_port_index, PORT_PLC);
1820 usb_wakeup_notification(hcd->self.root_hub,
1821 faked_port_index + 1);
1822 bogus_port_status = true;
1828 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1829 * RExit to a disconnect state). If so, let the the driver know it's
1830 * out of the RExit state.
1832 if (!DEV_SUPERSPEED(temp) &&
1833 test_and_clear_bit(faked_port_index,
1834 &bus_state->rexit_ports)) {
1835 complete(&bus_state->rexit_done[faked_port_index]);
1836 bogus_port_status = true;
1840 if (hcd->speed != HCD_USB3)
1841 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1845 /* Update event ring dequeue pointer before dropping the lock */
1846 inc_deq(xhci, xhci->event_ring);
1848 /* Don't make the USB core poll the roothub if we got a bad port status
1849 * change event. Besides, at that point we can't tell which roothub
1850 * (USB 2.0 or USB 3.0) to kick.
1852 if (bogus_port_status)
1856 * xHCI port-status-change events occur when the "or" of all the
1857 * status-change bits in the portsc register changes from 0 to 1.
1858 * New status changes won't cause an event if any other change
1859 * bits are still set. When an event occurs, switch over to
1860 * polling to avoid losing status changes.
1862 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1863 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1864 spin_unlock(&xhci->lock);
1865 /* Pass this up to the core */
1866 usb_hcd_poll_rh_status(hcd);
1867 spin_lock(&xhci->lock);
1871 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1872 * at end_trb, which may be in another segment. If the suspect DMA address is a
1873 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1876 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1877 union xhci_trb *start_trb,
1878 union xhci_trb *end_trb,
1879 dma_addr_t suspect_dma)
1881 dma_addr_t start_dma;
1882 dma_addr_t end_seg_dma;
1883 dma_addr_t end_trb_dma;
1884 struct xhci_segment *cur_seg;
1886 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1887 cur_seg = start_seg;
1892 /* We may get an event for a Link TRB in the middle of a TD */
1893 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1894 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1895 /* If the end TRB isn't in this segment, this is set to 0 */
1896 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1898 if (end_trb_dma > 0) {
1899 /* The end TRB is in this segment, so suspect should be here */
1900 if (start_dma <= end_trb_dma) {
1901 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1904 /* Case for one segment with
1905 * a TD wrapped around to the top
1907 if ((suspect_dma >= start_dma &&
1908 suspect_dma <= end_seg_dma) ||
1909 (suspect_dma >= cur_seg->dma &&
1910 suspect_dma <= end_trb_dma))
1915 /* Might still be somewhere in this segment */
1916 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1919 cur_seg = cur_seg->next;
1920 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1921 } while (cur_seg != start_seg);
1926 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1927 unsigned int slot_id, unsigned int ep_index,
1928 unsigned int stream_id,
1929 struct xhci_td *td, union xhci_trb *event_trb)
1931 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1932 struct xhci_command *command;
1933 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1937 ep->ep_state |= EP_HALTED;
1938 ep->stopped_td = td;
1939 ep->stopped_stream = stream_id;
1941 xhci_queue_reset_ep(xhci, command, slot_id, ep_index);
1942 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1944 ep->stopped_td = NULL;
1945 ep->stopped_stream = 0;
1947 xhci_ring_cmd_db(xhci);
1950 /* Check if an error has halted the endpoint ring. The class driver will
1951 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1952 * However, a babble and other errors also halt the endpoint ring, and the class
1953 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1954 * Ring Dequeue Pointer command manually.
1956 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1957 struct xhci_ep_ctx *ep_ctx,
1958 unsigned int trb_comp_code)
1960 /* TRB completion codes that may require a manual halt cleanup */
1961 if (trb_comp_code == COMP_TX_ERR ||
1962 trb_comp_code == COMP_BABBLE ||
1963 trb_comp_code == COMP_SPLIT_ERR)
1964 /* The 0.96 spec says a babbling control endpoint
1965 * is not halted. The 0.96 spec says it is. Some HW
1966 * claims to be 0.95 compliant, but it halts the control
1967 * endpoint anyway. Check if a babble halted the
1970 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1971 cpu_to_le32(EP_STATE_HALTED))
1977 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1979 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1980 /* Vendor defined "informational" completion code,
1981 * treat as not-an-error.
1983 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1985 xhci_dbg(xhci, "Treating code as success.\n");
1992 * Finish the td processing, remove the td from td list;
1993 * Return 1 if the urb can be given back.
1995 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1996 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1997 struct xhci_virt_ep *ep, int *status, bool skip)
1999 struct xhci_virt_device *xdev;
2000 struct xhci_ring *ep_ring;
2001 unsigned int slot_id;
2003 struct urb *urb = NULL;
2004 struct xhci_ep_ctx *ep_ctx;
2006 struct urb_priv *urb_priv;
2009 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2010 xdev = xhci->devs[slot_id];
2011 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2012 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2013 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2014 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2019 if (trb_comp_code == COMP_STOP_INVAL ||
2020 trb_comp_code == COMP_STOP) {
2021 /* The Endpoint Stop Command completion will take care of any
2022 * stopped TDs. A stopped TD may be restarted, so don't update
2023 * the ring dequeue pointer or take this TD off any lists yet.
2025 ep->stopped_td = td;
2028 if (trb_comp_code == COMP_STALL) {
2029 /* The transfer is completed from the driver's
2030 * perspective, but we need to issue a set dequeue
2031 * command for this stalled endpoint to move the dequeue
2032 * pointer past the TD. We can't do that here because
2033 * the halt condition must be cleared first. Let the
2034 * USB class driver clear the stall later.
2036 ep->stopped_td = td;
2037 ep->stopped_stream = ep_ring->stream_id;
2038 } else if (xhci_requires_manual_halt_cleanup(xhci,
2039 ep_ctx, trb_comp_code)) {
2040 /* Other types of errors halt the endpoint, but the
2041 * class driver doesn't call usb_reset_endpoint() unless
2042 * the error is -EPIPE. Clear the halted status in the
2043 * xHCI hardware manually.
2045 xhci_cleanup_halted_endpoint(xhci,
2046 slot_id, ep_index, ep_ring->stream_id,
2049 /* Update ring dequeue pointer */
2050 while (ep_ring->dequeue != td->last_trb)
2051 inc_deq(xhci, ep_ring);
2052 inc_deq(xhci, ep_ring);
2056 /* Clean up the endpoint's TD list */
2058 urb_priv = urb->hcpriv;
2060 /* Do one last check of the actual transfer length.
2061 * If the host controller said we transferred more data than
2062 * the buffer length, urb->actual_length will be a very big
2063 * number (since it's unsigned). Play it safe and say we didn't
2064 * transfer anything.
2066 if (urb->actual_length > urb->transfer_buffer_length) {
2067 xhci_warn(xhci, "URB transfer length is wrong, "
2068 "xHC issue? req. len = %u, "
2070 urb->transfer_buffer_length,
2071 urb->actual_length);
2072 urb->actual_length = 0;
2073 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2074 *status = -EREMOTEIO;
2078 list_del_init(&td->td_list);
2079 /* Was this TD slated to be cancelled but completed anyway? */
2080 if (!list_empty(&td->cancelled_td_list))
2081 list_del_init(&td->cancelled_td_list);
2084 /* Giveback the urb when all the tds are completed */
2085 if (urb_priv->td_cnt == urb_priv->length) {
2087 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2088 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
2089 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
2091 if (xhci->quirks & XHCI_AMD_PLL_FIX)
2092 usb_amd_quirk_pll_enable();
2102 * Process control tds, update urb status and actual_length.
2104 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2105 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2106 struct xhci_virt_ep *ep, int *status)
2108 struct xhci_virt_device *xdev;
2109 struct xhci_ring *ep_ring;
2110 unsigned int slot_id;
2112 struct xhci_ep_ctx *ep_ctx;
2115 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2116 xdev = xhci->devs[slot_id];
2117 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2118 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2119 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2120 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2122 switch (trb_comp_code) {
2124 if (event_trb == ep_ring->dequeue) {
2125 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
2126 "without IOC set??\n");
2127 *status = -ESHUTDOWN;
2128 } else if (event_trb != td->last_trb) {
2129 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
2130 "without IOC set??\n");
2131 *status = -ESHUTDOWN;
2137 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2138 *status = -EREMOTEIO;
2142 case COMP_STOP_INVAL:
2144 return finish_td(xhci, td, event_trb, event, ep, status, false);
2146 if (!xhci_requires_manual_halt_cleanup(xhci,
2147 ep_ctx, trb_comp_code))
2149 xhci_dbg(xhci, "TRB error code %u, "
2150 "halted endpoint index = %u\n",
2151 trb_comp_code, ep_index);
2152 /* else fall through */
2154 /* Did we transfer part of the data (middle) phase? */
2155 if (event_trb != ep_ring->dequeue &&
2156 event_trb != td->last_trb)
2157 td->urb->actual_length =
2158 td->urb->transfer_buffer_length -
2159 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2161 td->urb->actual_length = 0;
2163 xhci_cleanup_halted_endpoint(xhci,
2164 slot_id, ep_index, 0, td, event_trb);
2165 return finish_td(xhci, td, event_trb, event, ep, status, true);
2168 * Did we transfer any data, despite the errors that might have
2169 * happened? I.e. did we get past the setup stage?
2171 if (event_trb != ep_ring->dequeue) {
2172 /* The event was for the status stage */
2173 if (event_trb == td->last_trb) {
2174 if (td->urb->actual_length != 0) {
2175 /* Don't overwrite a previously set error code
2177 if ((*status == -EINPROGRESS || *status == 0) &&
2178 (td->urb->transfer_flags
2179 & URB_SHORT_NOT_OK))
2180 /* Did we already see a short data
2182 *status = -EREMOTEIO;
2184 td->urb->actual_length =
2185 td->urb->transfer_buffer_length;
2188 /* Maybe the event was for the data stage? */
2189 td->urb->actual_length =
2190 td->urb->transfer_buffer_length -
2191 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2192 xhci_dbg(xhci, "Waiting for status "
2198 return finish_td(xhci, td, event_trb, event, ep, status, false);
2202 * Process isochronous tds, update urb packet status and actual_length.
2204 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2205 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2206 struct xhci_virt_ep *ep, int *status)
2208 struct xhci_ring *ep_ring;
2209 struct urb_priv *urb_priv;
2212 union xhci_trb *cur_trb;
2213 struct xhci_segment *cur_seg;
2214 struct usb_iso_packet_descriptor *frame;
2216 bool skip_td = false;
2218 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2219 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2220 urb_priv = td->urb->hcpriv;
2221 idx = urb_priv->td_cnt;
2222 frame = &td->urb->iso_frame_desc[idx];
2224 /* handle completion code */
2225 switch (trb_comp_code) {
2227 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2231 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2232 trb_comp_code = COMP_SHORT_TX;
2234 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2238 frame->status = -ECOMM;
2241 case COMP_BUFF_OVER:
2243 frame->status = -EOVERFLOW;
2249 frame->status = -EPROTO;
2253 case COMP_STOP_INVAL:
2260 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2261 frame->actual_length = frame->length;
2262 td->urb->actual_length += frame->length;
2264 for (cur_trb = ep_ring->dequeue,
2265 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2266 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2267 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2268 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2269 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2271 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2272 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2274 if (trb_comp_code != COMP_STOP_INVAL) {
2275 frame->actual_length = len;
2276 td->urb->actual_length += len;
2280 return finish_td(xhci, td, event_trb, event, ep, status, false);
2283 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2284 struct xhci_transfer_event *event,
2285 struct xhci_virt_ep *ep, int *status)
2287 struct xhci_ring *ep_ring;
2288 struct urb_priv *urb_priv;
2289 struct usb_iso_packet_descriptor *frame;
2292 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2293 urb_priv = td->urb->hcpriv;
2294 idx = urb_priv->td_cnt;
2295 frame = &td->urb->iso_frame_desc[idx];
2297 /* The transfer is partly done. */
2298 frame->status = -EXDEV;
2300 /* calc actual length */
2301 frame->actual_length = 0;
2303 /* Update ring dequeue pointer */
2304 while (ep_ring->dequeue != td->last_trb)
2305 inc_deq(xhci, ep_ring);
2306 inc_deq(xhci, ep_ring);
2308 return finish_td(xhci, td, NULL, event, ep, status, true);
2312 * Process bulk and interrupt tds, update urb status and actual_length.
2314 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2315 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2316 struct xhci_virt_ep *ep, int *status)
2318 struct xhci_ring *ep_ring;
2319 union xhci_trb *cur_trb;
2320 struct xhci_segment *cur_seg;
2323 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2324 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2326 switch (trb_comp_code) {
2328 /* Double check that the HW transferred everything. */
2329 if (event_trb != td->last_trb ||
2330 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2331 xhci_warn(xhci, "WARN Successful completion "
2333 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2334 *status = -EREMOTEIO;
2337 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2338 trb_comp_code = COMP_SHORT_TX;
2344 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2345 *status = -EREMOTEIO;
2350 /* Others already handled above */
2353 if (trb_comp_code == COMP_SHORT_TX)
2354 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2355 "%d bytes untransferred\n",
2356 td->urb->ep->desc.bEndpointAddress,
2357 td->urb->transfer_buffer_length,
2358 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2359 /* Fast path - was this the last TRB in the TD for this URB? */
2360 if (event_trb == td->last_trb) {
2361 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2362 td->urb->actual_length =
2363 td->urb->transfer_buffer_length -
2364 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2365 if (td->urb->transfer_buffer_length <
2366 td->urb->actual_length) {
2367 xhci_warn(xhci, "HC gave bad length "
2368 "of %d bytes left\n",
2369 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2370 td->urb->actual_length = 0;
2371 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2372 *status = -EREMOTEIO;
2376 /* Don't overwrite a previously set error code */
2377 if (*status == -EINPROGRESS) {
2378 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2379 *status = -EREMOTEIO;
2384 td->urb->actual_length =
2385 td->urb->transfer_buffer_length;
2386 /* Ignore a short packet completion if the
2387 * untransferred length was zero.
2389 if (*status == -EREMOTEIO)
2393 /* Slow path - walk the list, starting from the dequeue
2394 * pointer, to get the actual length transferred.
2396 td->urb->actual_length = 0;
2397 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2398 cur_trb != event_trb;
2399 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2400 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2401 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2402 td->urb->actual_length +=
2403 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2405 /* If the ring didn't stop on a Link or No-op TRB, add
2406 * in the actual bytes transferred from the Normal TRB
2408 if (trb_comp_code != COMP_STOP_INVAL)
2409 td->urb->actual_length +=
2410 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2411 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2414 return finish_td(xhci, td, event_trb, event, ep, status, false);
2418 * If this function returns an error condition, it means it got a Transfer
2419 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2420 * At this point, the host controller is probably hosed and should be reset.
2422 static int handle_tx_event(struct xhci_hcd *xhci,
2423 struct xhci_transfer_event *event)
2424 __releases(&xhci->lock)
2425 __acquires(&xhci->lock)
2427 struct xhci_virt_device *xdev;
2428 struct xhci_virt_ep *ep;
2429 struct xhci_ring *ep_ring;
2430 unsigned int slot_id;
2432 struct xhci_td *td = NULL;
2433 dma_addr_t event_dma;
2434 struct xhci_segment *event_seg;
2435 union xhci_trb *event_trb;
2436 struct urb *urb = NULL;
2437 int status = -EINPROGRESS;
2438 struct urb_priv *urb_priv;
2439 struct xhci_ep_ctx *ep_ctx;
2440 struct list_head *tmp;
2445 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2446 xdev = xhci->devs[slot_id];
2448 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2449 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2450 (unsigned long long) xhci_trb_virt_to_dma(
2451 xhci->event_ring->deq_seg,
2452 xhci->event_ring->dequeue),
2453 lower_32_bits(le64_to_cpu(event->buffer)),
2454 upper_32_bits(le64_to_cpu(event->buffer)),
2455 le32_to_cpu(event->transfer_len),
2456 le32_to_cpu(event->flags));
2457 xhci_dbg(xhci, "Event ring:\n");
2458 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2462 /* Endpoint ID is 1 based, our index is zero based */
2463 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2464 ep = &xdev->eps[ep_index];
2465 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2466 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2468 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2469 EP_STATE_DISABLED) {
2470 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2471 "or incorrect stream ring\n");
2472 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2473 (unsigned long long) xhci_trb_virt_to_dma(
2474 xhci->event_ring->deq_seg,
2475 xhci->event_ring->dequeue),
2476 lower_32_bits(le64_to_cpu(event->buffer)),
2477 upper_32_bits(le64_to_cpu(event->buffer)),
2478 le32_to_cpu(event->transfer_len),
2479 le32_to_cpu(event->flags));
2480 xhci_dbg(xhci, "Event ring:\n");
2481 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2485 /* Count current td numbers if ep->skip is set */
2487 list_for_each(tmp, &ep_ring->td_list)
2491 event_dma = le64_to_cpu(event->buffer);
2492 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2493 /* Look for common error cases */
2494 switch (trb_comp_code) {
2495 /* Skip codes that require special handling depending on
2499 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2501 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2502 trb_comp_code = COMP_SHORT_TX;
2504 xhci_warn_ratelimited(xhci,
2505 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2509 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2511 case COMP_STOP_INVAL:
2512 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2515 xhci_dbg(xhci, "Stalled endpoint\n");
2516 ep->ep_state |= EP_HALTED;
2520 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2523 case COMP_SPLIT_ERR:
2525 xhci_dbg(xhci, "Transfer error on endpoint\n");
2529 xhci_dbg(xhci, "Babble error on endpoint\n");
2530 status = -EOVERFLOW;
2533 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2537 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2539 case COMP_BUFF_OVER:
2540 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2544 * When the Isoch ring is empty, the xHC will generate
2545 * a Ring Overrun Event for IN Isoch endpoint or Ring
2546 * Underrun Event for OUT Isoch endpoint.
2548 xhci_dbg(xhci, "underrun event on endpoint\n");
2549 if (!list_empty(&ep_ring->td_list))
2550 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2551 "still with TDs queued?\n",
2552 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2556 xhci_dbg(xhci, "overrun event on endpoint\n");
2557 if (!list_empty(&ep_ring->td_list))
2558 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2559 "still with TDs queued?\n",
2560 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2564 xhci_warn(xhci, "WARN: detect an incompatible device");
2567 case COMP_MISSED_INT:
2569 * When encounter missed service error, one or more isoc tds
2570 * may be missed by xHC.
2571 * Set skip flag of the ep_ring; Complete the missed tds as
2572 * short transfer when process the ep_ring next time.
2575 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2578 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2582 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2588 /* This TRB should be in the TD at the head of this ring's
2591 if (list_empty(&ep_ring->td_list)) {
2593 * A stopped endpoint may generate an extra completion
2594 * event if the device was suspended. Don't print
2597 if (!(trb_comp_code == COMP_STOP ||
2598 trb_comp_code == COMP_STOP_INVAL)) {
2599 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2600 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2602 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2603 (le32_to_cpu(event->flags) &
2604 TRB_TYPE_BITMASK)>>10);
2605 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2609 xhci_dbg(xhci, "td_list is empty while skip "
2610 "flag set. Clear skip flag.\n");
2616 /* We've skipped all the TDs on the ep ring when ep->skip set */
2617 if (ep->skip && td_num == 0) {
2619 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2620 "Clear skip flag.\n");
2625 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2629 /* Is this a TRB in the currently executing TD? */
2630 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2631 td->last_trb, event_dma);
2634 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2635 * is not in the current TD pointed by ep_ring->dequeue because
2636 * that the hardware dequeue pointer still at the previous TRB
2637 * of the current TD. The previous TRB maybe a Link TD or the
2638 * last TRB of the previous TD. The command completion handle
2639 * will take care the rest.
2641 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2648 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2649 /* Some host controllers give a spurious
2650 * successful event after a short transfer.
2653 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2654 ep_ring->last_td_was_short) {
2655 ep_ring->last_td_was_short = false;
2659 /* HC is busted, give up! */
2661 "ERROR Transfer event TRB DMA ptr not "
2662 "part of current TD\n");
2666 ret = skip_isoc_td(xhci, td, event, ep, &status);
2669 if (trb_comp_code == COMP_SHORT_TX)
2670 ep_ring->last_td_was_short = true;
2672 ep_ring->last_td_was_short = false;
2675 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2679 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2680 sizeof(*event_trb)];
2682 * No-op TRB should not trigger interrupts.
2683 * If event_trb is a no-op TRB, it means the
2684 * corresponding TD has been cancelled. Just ignore
2687 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2689 "event_trb is a no-op TRB. Skip it\n");
2693 /* Now update the urb's actual_length and give back to
2696 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2697 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2699 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2700 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2703 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2708 * Do not update event ring dequeue pointer if ep->skip is set.
2709 * Will roll back to continue process missed tds.
2711 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2712 inc_deq(xhci, xhci->event_ring);
2717 urb_priv = urb->hcpriv;
2718 /* Leave the TD around for the reset endpoint function
2719 * to use(but only if it's not a control endpoint,
2720 * since we already queued the Set TR dequeue pointer
2721 * command for stalled control endpoints).
2723 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2724 (trb_comp_code != COMP_STALL &&
2725 trb_comp_code != COMP_BABBLE))
2726 xhci_urb_free_priv(xhci, urb_priv);
2730 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2731 if ((urb->actual_length != urb->transfer_buffer_length &&
2732 (urb->transfer_flags &
2733 URB_SHORT_NOT_OK)) ||
2735 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2736 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2737 "expected = %d, status = %d\n",
2738 urb, urb->actual_length,
2739 urb->transfer_buffer_length,
2741 spin_unlock(&xhci->lock);
2742 /* EHCI, UHCI, and OHCI always unconditionally set the
2743 * urb->status of an isochronous endpoint to 0.
2745 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2747 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2748 spin_lock(&xhci->lock);
2752 * If ep->skip is set, it means there are missed tds on the
2753 * endpoint ring need to take care of.
2754 * Process them as short transfer until reach the td pointed by
2757 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2763 * This function handles all OS-owned events on the event ring. It may drop
2764 * xhci->lock between event processing (e.g. to pass up port status changes).
2765 * Returns >0 for "possibly more events to process" (caller should call again),
2766 * otherwise 0 if done. In future, <0 returns should indicate error code.
2768 static int xhci_handle_event(struct xhci_hcd *xhci)
2770 union xhci_trb *event;
2771 int update_ptrs = 1;
2774 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2775 xhci->error_bitmask |= 1 << 1;
2779 event = xhci->event_ring->dequeue;
2780 /* Does the HC or OS own the TRB? */
2781 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2782 xhci->event_ring->cycle_state) {
2783 xhci->error_bitmask |= 1 << 2;
2788 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2789 * speculative reads of the event's flags/data below.
2792 /* FIXME: Handle more event types. */
2793 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2794 case TRB_TYPE(TRB_COMPLETION):
2795 handle_cmd_completion(xhci, &event->event_cmd);
2797 case TRB_TYPE(TRB_PORT_STATUS):
2798 handle_port_status(xhci, event);
2801 case TRB_TYPE(TRB_TRANSFER):
2802 ret = handle_tx_event(xhci, &event->trans_event);
2804 xhci->error_bitmask |= 1 << 9;
2808 case TRB_TYPE(TRB_DEV_NOTE):
2809 handle_device_notification(xhci, event);
2812 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2814 handle_vendor_event(xhci, event);
2816 xhci->error_bitmask |= 1 << 3;
2818 /* Any of the above functions may drop and re-acquire the lock, so check
2819 * to make sure a watchdog timer didn't mark the host as non-responsive.
2821 if (xhci->xhc_state & XHCI_STATE_DYING) {
2822 xhci_dbg(xhci, "xHCI host dying, returning from "
2823 "event handler.\n");
2828 /* Update SW event ring dequeue pointer */
2829 inc_deq(xhci, xhci->event_ring);
2831 /* Are there more items on the event ring? Caller will call us again to
2838 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2839 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2840 * indicators of an event TRB error, but we check the status *first* to be safe.
2842 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2844 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2847 union xhci_trb *event_ring_deq;
2850 spin_lock(&xhci->lock);
2851 /* Check if the xHC generated the interrupt, or the irq is shared */
2852 status = readl(&xhci->op_regs->status);
2853 if (status == 0xffffffff)
2856 if (!(status & STS_EINT)) {
2857 spin_unlock(&xhci->lock);
2860 if (status & STS_FATAL) {
2861 xhci_warn(xhci, "WARNING: Host System Error\n");
2864 spin_unlock(&xhci->lock);
2869 * Clear the op reg interrupt status first,
2870 * so we can receive interrupts from other MSI-X interrupters.
2871 * Write 1 to clear the interrupt status.
2874 writel(status, &xhci->op_regs->status);
2875 /* FIXME when MSI-X is supported and there are multiple vectors */
2876 /* Clear the MSI-X event interrupt status */
2880 /* Acknowledge the PCI interrupt */
2881 irq_pending = readl(&xhci->ir_set->irq_pending);
2882 irq_pending |= IMAN_IP;
2883 writel(irq_pending, &xhci->ir_set->irq_pending);
2886 if (xhci->xhc_state & XHCI_STATE_DYING) {
2887 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2888 "Shouldn't IRQs be disabled?\n");
2889 /* Clear the event handler busy flag (RW1C);
2890 * the event ring should be empty.
2892 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2893 xhci_write_64(xhci, temp_64 | ERST_EHB,
2894 &xhci->ir_set->erst_dequeue);
2895 spin_unlock(&xhci->lock);
2900 event_ring_deq = xhci->event_ring->dequeue;
2901 /* FIXME this should be a delayed service routine
2902 * that clears the EHB.
2904 while (xhci_handle_event(xhci) > 0) {}
2906 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2907 /* If necessary, update the HW's version of the event ring deq ptr. */
2908 if (event_ring_deq != xhci->event_ring->dequeue) {
2909 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2910 xhci->event_ring->dequeue);
2912 xhci_warn(xhci, "WARN something wrong with SW event "
2913 "ring dequeue ptr.\n");
2914 /* Update HC event ring dequeue pointer */
2915 temp_64 &= ERST_PTR_MASK;
2916 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2919 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2920 temp_64 |= ERST_EHB;
2921 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2923 spin_unlock(&xhci->lock);
2928 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2930 return xhci_irq(hcd);
2933 /**** Endpoint Ring Operations ****/
2936 * Generic function for queueing a TRB on a ring.
2937 * The caller must have checked to make sure there's room on the ring.
2939 * @more_trbs_coming: Will you enqueue more TRBs before calling
2940 * prepare_transfer()?
2942 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2943 bool more_trbs_coming,
2944 u32 field1, u32 field2, u32 field3, u32 field4)
2946 struct xhci_generic_trb *trb;
2948 trb = &ring->enqueue->generic;
2949 trb->field[0] = cpu_to_le32(field1);
2950 trb->field[1] = cpu_to_le32(field2);
2951 trb->field[2] = cpu_to_le32(field3);
2952 trb->field[3] = cpu_to_le32(field4);
2953 inc_enq(xhci, ring, more_trbs_coming);
2957 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2958 * FIXME allocate segments if the ring is full.
2960 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2961 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2963 unsigned int num_trbs_needed;
2965 /* Make sure the endpoint has been added to xHC schedule */
2967 case EP_STATE_DISABLED:
2969 * USB core changed config/interfaces without notifying us,
2970 * or hardware is reporting the wrong state.
2972 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2974 case EP_STATE_ERROR:
2975 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2976 /* FIXME event handling code for error needs to clear it */
2977 /* XXX not sure if this should be -ENOENT or not */
2979 case EP_STATE_HALTED:
2980 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2981 case EP_STATE_STOPPED:
2982 case EP_STATE_RUNNING:
2985 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2987 * FIXME issue Configure Endpoint command to try to get the HC
2988 * back into a known state.
2994 if (room_on_ring(xhci, ep_ring, num_trbs))
2997 if (ep_ring == xhci->cmd_ring) {
2998 xhci_err(xhci, "Do not support expand command ring\n");
3002 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3003 "ERROR no room on ep ring, try ring expansion");
3004 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
3005 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
3007 xhci_err(xhci, "Ring expansion failed\n");
3012 if (enqueue_is_link_trb(ep_ring)) {
3013 struct xhci_ring *ring = ep_ring;
3014 union xhci_trb *next;
3016 next = ring->enqueue;
3018 while (last_trb(xhci, ring, ring->enq_seg, next)) {
3019 /* If we're not dealing with 0.95 hardware or isoc rings
3020 * on AMD 0.96 host, clear the chain bit.
3022 if (!xhci_link_trb_quirk(xhci) &&
3023 !(ring->type == TYPE_ISOC &&
3024 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3025 next->link.control &= cpu_to_le32(~TRB_CHAIN);
3027 next->link.control |= cpu_to_le32(TRB_CHAIN);
3030 next->link.control ^= cpu_to_le32(TRB_CYCLE);
3032 /* Toggle the cycle bit after the last ring segment. */
3033 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
3034 ring->cycle_state = (ring->cycle_state ? 0 : 1);
3036 ring->enq_seg = ring->enq_seg->next;
3037 ring->enqueue = ring->enq_seg->trbs;
3038 next = ring->enqueue;
3045 static int prepare_transfer(struct xhci_hcd *xhci,
3046 struct xhci_virt_device *xdev,
3047 unsigned int ep_index,
3048 unsigned int stream_id,
3049 unsigned int num_trbs,
3051 unsigned int td_index,
3055 struct urb_priv *urb_priv;
3057 struct xhci_ring *ep_ring;
3058 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3060 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
3062 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3067 ret = prepare_ring(xhci, ep_ring,
3068 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3069 num_trbs, mem_flags);
3073 urb_priv = urb->hcpriv;
3074 td = urb_priv->td[td_index];
3076 INIT_LIST_HEAD(&td->td_list);
3077 INIT_LIST_HEAD(&td->cancelled_td_list);
3079 if (td_index == 0) {
3080 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3086 /* Add this TD to the tail of the endpoint ring's TD list */
3087 list_add_tail(&td->td_list, &ep_ring->td_list);
3088 td->start_seg = ep_ring->enq_seg;
3089 td->first_trb = ep_ring->enqueue;
3091 urb_priv->td[td_index] = td;
3096 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
3098 int num_sgs, num_trbs, running_total, temp, i;
3099 struct scatterlist *sg;
3102 num_sgs = urb->num_mapped_sgs;
3103 temp = urb->transfer_buffer_length;
3106 for_each_sg(urb->sg, sg, num_sgs, i) {
3107 unsigned int len = sg_dma_len(sg);
3109 /* Scatter gather list entries may cross 64KB boundaries */
3110 running_total = TRB_MAX_BUFF_SIZE -
3111 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
3112 running_total &= TRB_MAX_BUFF_SIZE - 1;
3113 if (running_total != 0)
3116 /* How many more 64KB chunks to transfer, how many more TRBs? */
3117 while (running_total < sg_dma_len(sg) && running_total < temp) {
3119 running_total += TRB_MAX_BUFF_SIZE;
3121 len = min_t(int, len, temp);
3129 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
3132 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
3133 "TRBs, %d left\n", __func__,
3134 urb->ep->desc.bEndpointAddress, num_trbs);
3135 if (running_total != urb->transfer_buffer_length)
3136 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3137 "queued %#x (%d), asked for %#x (%d)\n",
3139 urb->ep->desc.bEndpointAddress,
3140 running_total, running_total,
3141 urb->transfer_buffer_length,
3142 urb->transfer_buffer_length);
3145 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3146 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3147 struct xhci_generic_trb *start_trb)
3150 * Pass all the TRBs to the hardware at once and make sure this write
3155 start_trb->field[3] |= cpu_to_le32(start_cycle);
3157 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3158 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3162 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3163 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3164 * (comprised of sg list entries) can take several service intervals to
3167 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3168 struct urb *urb, int slot_id, unsigned int ep_index)
3170 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3171 xhci->devs[slot_id]->out_ctx, ep_index);
3175 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3176 ep_interval = urb->interval;
3177 /* Convert to microframes */
3178 if (urb->dev->speed == USB_SPEED_LOW ||
3179 urb->dev->speed == USB_SPEED_FULL)
3181 /* FIXME change this to a warning and a suggestion to use the new API
3182 * to set the polling interval (once the API is added).
3184 if (xhci_interval != ep_interval) {
3185 dev_dbg_ratelimited(&urb->dev->dev,
3186 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3187 ep_interval, ep_interval == 1 ? "" : "s",
3188 xhci_interval, xhci_interval == 1 ? "" : "s");
3189 urb->interval = xhci_interval;
3190 /* Convert back to frames for LS/FS devices */
3191 if (urb->dev->speed == USB_SPEED_LOW ||
3192 urb->dev->speed == USB_SPEED_FULL)
3195 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3199 * The TD size is the number of bytes remaining in the TD (including this TRB),
3200 * right shifted by 10.
3201 * It must fit in bits 21:17, so it can't be bigger than 31.
3203 static u32 xhci_td_remainder(unsigned int remainder)
3205 u32 max = (1 << (21 - 17 + 1)) - 1;
3207 if ((remainder >> 10) >= max)
3210 return (remainder >> 10) << 17;
3214 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3215 * packets remaining in the TD (*not* including this TRB).
3217 * Total TD packet count = total_packet_count =
3218 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3220 * Packets transferred up to and including this TRB = packets_transferred =
3221 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3223 * TD size = total_packet_count - packets_transferred
3225 * It must fit in bits 21:17, so it can't be bigger than 31.
3226 * The last TRB in a TD must have the TD size set to zero.
3228 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3229 unsigned int total_packet_count, struct urb *urb,
3230 unsigned int num_trbs_left)
3232 int packets_transferred;
3234 /* One TRB with a zero-length data packet. */
3235 if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3238 /* All the TRB queueing functions don't count the current TRB in
3241 packets_transferred = (running_total + trb_buff_len) /
3242 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3244 if ((total_packet_count - packets_transferred) > 31)
3246 return (total_packet_count - packets_transferred) << 17;
3249 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3250 struct urb *urb, int slot_id, unsigned int ep_index)
3252 struct xhci_ring *ep_ring;
3253 unsigned int num_trbs;
3254 struct urb_priv *urb_priv;
3256 struct scatterlist *sg;
3258 int trb_buff_len, this_sg_len, running_total;
3259 unsigned int total_packet_count;
3262 bool more_trbs_coming;
3264 struct xhci_generic_trb *start_trb;
3267 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3271 num_trbs = count_sg_trbs_needed(xhci, urb);
3272 num_sgs = urb->num_mapped_sgs;
3273 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3274 usb_endpoint_maxp(&urb->ep->desc));
3276 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3277 ep_index, urb->stream_id,
3278 num_trbs, urb, 0, mem_flags);
3279 if (trb_buff_len < 0)
3280 return trb_buff_len;
3282 urb_priv = urb->hcpriv;
3283 td = urb_priv->td[0];
3286 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3287 * until we've finished creating all the other TRBs. The ring's cycle
3288 * state may change as we enqueue the other TRBs, so save it too.
3290 start_trb = &ep_ring->enqueue->generic;
3291 start_cycle = ep_ring->cycle_state;
3295 * How much data is in the first TRB?
3297 * There are three forces at work for TRB buffer pointers and lengths:
3298 * 1. We don't want to walk off the end of this sg-list entry buffer.
3299 * 2. The transfer length that the driver requested may be smaller than
3300 * the amount of memory allocated for this scatter-gather list.
3301 * 3. TRBs buffers can't cross 64KB boundaries.
3304 addr = (u64) sg_dma_address(sg);
3305 this_sg_len = sg_dma_len(sg);
3306 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3307 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3308 if (trb_buff_len > urb->transfer_buffer_length)
3309 trb_buff_len = urb->transfer_buffer_length;
3312 /* Queue the first TRB, even if it's zero-length */
3315 u32 length_field = 0;
3318 /* Don't change the cycle bit of the first TRB until later */
3321 if (start_cycle == 0)
3324 field |= ep_ring->cycle_state;
3326 /* Chain all the TRBs together; clear the chain bit in the last
3327 * TRB to indicate it's the last TRB in the chain.
3332 /* FIXME - add check for ZERO_PACKET flag before this */
3333 td->last_trb = ep_ring->enqueue;
3337 /* Only set interrupt on short packet for IN endpoints */
3338 if (usb_urb_dir_in(urb))
3341 if (TRB_MAX_BUFF_SIZE -
3342 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3343 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3344 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3345 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3346 (unsigned int) addr + trb_buff_len);
3349 /* Set the TRB length, TD size, and interrupter fields. */
3350 if (xhci->hci_version < 0x100) {
3351 remainder = xhci_td_remainder(
3352 urb->transfer_buffer_length -
3355 remainder = xhci_v1_0_td_remainder(running_total,
3356 trb_buff_len, total_packet_count, urb,
3359 length_field = TRB_LEN(trb_buff_len) |
3364 more_trbs_coming = true;
3366 more_trbs_coming = false;
3367 queue_trb(xhci, ep_ring, more_trbs_coming,
3368 lower_32_bits(addr),
3369 upper_32_bits(addr),
3371 field | TRB_TYPE(TRB_NORMAL));
3373 running_total += trb_buff_len;
3375 /* Calculate length for next transfer --
3376 * Are we done queueing all the TRBs for this sg entry?
3378 this_sg_len -= trb_buff_len;
3379 if (this_sg_len == 0) {
3384 addr = (u64) sg_dma_address(sg);
3385 this_sg_len = sg_dma_len(sg);
3387 addr += trb_buff_len;
3390 trb_buff_len = TRB_MAX_BUFF_SIZE -
3391 (addr & (TRB_MAX_BUFF_SIZE - 1));
3392 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3393 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3395 urb->transfer_buffer_length - running_total;
3396 } while (running_total < urb->transfer_buffer_length);
3398 check_trb_math(urb, num_trbs, running_total);
3399 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3400 start_cycle, start_trb);
3404 /* This is very similar to what ehci-q.c qtd_fill() does */
3405 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3406 struct urb *urb, int slot_id, unsigned int ep_index)
3408 struct xhci_ring *ep_ring;
3409 struct urb_priv *urb_priv;
3412 struct xhci_generic_trb *start_trb;
3414 bool more_trbs_coming;
3416 u32 field, length_field;
3418 int running_total, trb_buff_len, ret;
3419 unsigned int total_packet_count;
3423 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3425 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3430 /* How much data is (potentially) left before the 64KB boundary? */
3431 running_total = TRB_MAX_BUFF_SIZE -
3432 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3433 running_total &= TRB_MAX_BUFF_SIZE - 1;
3435 /* If there's some data on this 64KB chunk, or we have to send a
3436 * zero-length transfer, we need at least one TRB
3438 if (running_total != 0 || urb->transfer_buffer_length == 0)
3440 /* How many more 64KB chunks to transfer, how many more TRBs? */
3441 while (running_total < urb->transfer_buffer_length) {
3443 running_total += TRB_MAX_BUFF_SIZE;
3445 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3447 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3448 ep_index, urb->stream_id,
3449 num_trbs, urb, 0, mem_flags);
3453 urb_priv = urb->hcpriv;
3454 td = urb_priv->td[0];
3457 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3458 * until we've finished creating all the other TRBs. The ring's cycle
3459 * state may change as we enqueue the other TRBs, so save it too.
3461 start_trb = &ep_ring->enqueue->generic;
3462 start_cycle = ep_ring->cycle_state;
3465 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3466 usb_endpoint_maxp(&urb->ep->desc));
3467 /* How much data is in the first TRB? */
3468 addr = (u64) urb->transfer_dma;
3469 trb_buff_len = TRB_MAX_BUFF_SIZE -
3470 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3471 if (trb_buff_len > urb->transfer_buffer_length)
3472 trb_buff_len = urb->transfer_buffer_length;
3476 /* Queue the first TRB, even if it's zero-length */
3481 /* Don't change the cycle bit of the first TRB until later */
3484 if (start_cycle == 0)
3487 field |= ep_ring->cycle_state;
3489 /* Chain all the TRBs together; clear the chain bit in the last
3490 * TRB to indicate it's the last TRB in the chain.
3495 /* FIXME - add check for ZERO_PACKET flag before this */
3496 td->last_trb = ep_ring->enqueue;
3500 /* Only set interrupt on short packet for IN endpoints */
3501 if (usb_urb_dir_in(urb))
3504 /* Set the TRB length, TD size, and interrupter fields. */
3505 if (xhci->hci_version < 0x100) {
3506 remainder = xhci_td_remainder(
3507 urb->transfer_buffer_length -
3510 remainder = xhci_v1_0_td_remainder(running_total,
3511 trb_buff_len, total_packet_count, urb,
3514 length_field = TRB_LEN(trb_buff_len) |
3519 more_trbs_coming = true;
3521 more_trbs_coming = false;
3522 queue_trb(xhci, ep_ring, more_trbs_coming,
3523 lower_32_bits(addr),
3524 upper_32_bits(addr),
3526 field | TRB_TYPE(TRB_NORMAL));
3528 running_total += trb_buff_len;
3530 /* Calculate length for next transfer */
3531 addr += trb_buff_len;
3532 trb_buff_len = urb->transfer_buffer_length - running_total;
3533 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3534 trb_buff_len = TRB_MAX_BUFF_SIZE;
3535 } while (running_total < urb->transfer_buffer_length);
3537 check_trb_math(urb, num_trbs, running_total);
3538 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3539 start_cycle, start_trb);
3543 /* Caller must have locked xhci->lock */
3544 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3545 struct urb *urb, int slot_id, unsigned int ep_index)
3547 struct xhci_ring *ep_ring;
3550 struct usb_ctrlrequest *setup;
3551 struct xhci_generic_trb *start_trb;
3553 u32 field, length_field;
3554 struct urb_priv *urb_priv;
3557 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3562 * Need to copy setup packet into setup TRB, so we can't use the setup
3565 if (!urb->setup_packet)
3568 /* 1 TRB for setup, 1 for status */
3571 * Don't need to check if we need additional event data and normal TRBs,
3572 * since data in control transfers will never get bigger than 16MB
3573 * XXX: can we get a buffer that crosses 64KB boundaries?
3575 if (urb->transfer_buffer_length > 0)
3577 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3578 ep_index, urb->stream_id,
3579 num_trbs, urb, 0, mem_flags);
3583 urb_priv = urb->hcpriv;
3584 td = urb_priv->td[0];
3587 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3588 * until we've finished creating all the other TRBs. The ring's cycle
3589 * state may change as we enqueue the other TRBs, so save it too.
3591 start_trb = &ep_ring->enqueue->generic;
3592 start_cycle = ep_ring->cycle_state;
3594 /* Queue setup TRB - see section 6.4.1.2.1 */
3595 /* FIXME better way to translate setup_packet into two u32 fields? */
3596 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3598 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3599 if (start_cycle == 0)
3602 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3603 if (xhci->hci_version == 0x100) {
3604 if (urb->transfer_buffer_length > 0) {
3605 if (setup->bRequestType & USB_DIR_IN)
3606 field |= TRB_TX_TYPE(TRB_DATA_IN);
3608 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3612 queue_trb(xhci, ep_ring, true,
3613 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3614 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3615 TRB_LEN(8) | TRB_INTR_TARGET(0),
3616 /* Immediate data in pointer */
3619 /* If there's data, queue data TRBs */
3620 /* Only set interrupt on short packet for IN endpoints */
3621 if (usb_urb_dir_in(urb))
3622 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3624 field = TRB_TYPE(TRB_DATA);
3626 length_field = TRB_LEN(urb->transfer_buffer_length) |
3627 xhci_td_remainder(urb->transfer_buffer_length) |
3629 if (urb->transfer_buffer_length > 0) {
3630 if (setup->bRequestType & USB_DIR_IN)
3631 field |= TRB_DIR_IN;
3632 queue_trb(xhci, ep_ring, true,
3633 lower_32_bits(urb->transfer_dma),
3634 upper_32_bits(urb->transfer_dma),
3636 field | ep_ring->cycle_state);
3639 /* Save the DMA address of the last TRB in the TD */
3640 td->last_trb = ep_ring->enqueue;
3642 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3643 /* If the device sent data, the status stage is an OUT transfer */
3644 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3648 queue_trb(xhci, ep_ring, false,
3652 /* Event on completion */
3653 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3655 giveback_first_trb(xhci, slot_id, ep_index, 0,
3656 start_cycle, start_trb);
3660 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3661 struct urb *urb, int i)
3666 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3667 td_len = urb->iso_frame_desc[i].length;
3669 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3678 * The transfer burst count field of the isochronous TRB defines the number of
3679 * bursts that are required to move all packets in this TD. Only SuperSpeed
3680 * devices can burst up to bMaxBurst number of packets per service interval.
3681 * This field is zero based, meaning a value of zero in the field means one
3682 * burst. Basically, for everything but SuperSpeed devices, this field will be
3683 * zero. Only xHCI 1.0 host controllers support this field.
3685 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3686 struct usb_device *udev,
3687 struct urb *urb, unsigned int total_packet_count)
3689 unsigned int max_burst;
3691 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3694 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3695 return roundup(total_packet_count, max_burst + 1) - 1;
3699 * Returns the number of packets in the last "burst" of packets. This field is
3700 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3701 * the last burst packet count is equal to the total number of packets in the
3702 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3703 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3704 * contain 1 to (bMaxBurst + 1) packets.
3706 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3707 struct usb_device *udev,
3708 struct urb *urb, unsigned int total_packet_count)
3710 unsigned int max_burst;
3711 unsigned int residue;
3713 if (xhci->hci_version < 0x100)
3716 switch (udev->speed) {
3717 case USB_SPEED_SUPER:
3718 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3719 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3720 residue = total_packet_count % (max_burst + 1);
3721 /* If residue is zero, the last burst contains (max_burst + 1)
3722 * number of packets, but the TLBPC field is zero-based.
3728 if (total_packet_count == 0)
3730 return total_packet_count - 1;
3734 /* This is for isoc transfer */
3735 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3736 struct urb *urb, int slot_id, unsigned int ep_index)
3738 struct xhci_ring *ep_ring;
3739 struct urb_priv *urb_priv;
3741 int num_tds, trbs_per_td;
3742 struct xhci_generic_trb *start_trb;
3745 u32 field, length_field;
3746 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3747 u64 start_addr, addr;
3749 bool more_trbs_coming;
3751 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3753 num_tds = urb->number_of_packets;
3755 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3759 start_addr = (u64) urb->transfer_dma;
3760 start_trb = &ep_ring->enqueue->generic;
3761 start_cycle = ep_ring->cycle_state;
3763 urb_priv = urb->hcpriv;
3764 /* Queue the first TRB, even if it's zero-length */
3765 for (i = 0; i < num_tds; i++) {
3766 unsigned int total_packet_count;
3767 unsigned int burst_count;
3768 unsigned int residue;
3772 addr = start_addr + urb->iso_frame_desc[i].offset;
3773 td_len = urb->iso_frame_desc[i].length;
3774 td_remain_len = td_len;
3775 total_packet_count = DIV_ROUND_UP(td_len,
3777 usb_endpoint_maxp(&urb->ep->desc)));
3778 /* A zero-length transfer still involves at least one packet. */
3779 if (total_packet_count == 0)
3780 total_packet_count++;
3781 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3782 total_packet_count);
3783 residue = xhci_get_last_burst_packet_count(xhci,
3784 urb->dev, urb, total_packet_count);
3786 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3788 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3789 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3796 td = urb_priv->td[i];
3797 for (j = 0; j < trbs_per_td; j++) {
3802 field = TRB_TBC(burst_count) |
3804 /* Queue the isoc TRB */
3805 field |= TRB_TYPE(TRB_ISOC);
3806 /* Assume URB_ISO_ASAP is set */
3809 if (start_cycle == 0)
3812 field |= ep_ring->cycle_state;
3815 /* Queue other normal TRBs */
3816 field |= TRB_TYPE(TRB_NORMAL);
3817 field |= ep_ring->cycle_state;
3820 /* Only set interrupt on short packet for IN EPs */
3821 if (usb_urb_dir_in(urb))
3824 /* Chain all the TRBs together; clear the chain bit in
3825 * the last TRB to indicate it's the last TRB in the
3828 if (j < trbs_per_td - 1) {
3830 more_trbs_coming = true;
3832 td->last_trb = ep_ring->enqueue;
3834 if (xhci->hci_version == 0x100 &&
3837 /* Set BEI bit except for the last td */
3838 if (i < num_tds - 1)
3841 more_trbs_coming = false;
3844 /* Calculate TRB length */
3845 trb_buff_len = TRB_MAX_BUFF_SIZE -
3846 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3847 if (trb_buff_len > td_remain_len)
3848 trb_buff_len = td_remain_len;
3850 /* Set the TRB length, TD size, & interrupter fields. */
3851 if (xhci->hci_version < 0x100) {
3852 remainder = xhci_td_remainder(
3853 td_len - running_total);
3855 remainder = xhci_v1_0_td_remainder(
3856 running_total, trb_buff_len,
3857 total_packet_count, urb,
3858 (trbs_per_td - j - 1));
3860 length_field = TRB_LEN(trb_buff_len) |
3864 queue_trb(xhci, ep_ring, more_trbs_coming,
3865 lower_32_bits(addr),
3866 upper_32_bits(addr),
3869 running_total += trb_buff_len;
3871 addr += trb_buff_len;
3872 td_remain_len -= trb_buff_len;
3875 /* Check TD length */
3876 if (running_total != td_len) {
3877 xhci_err(xhci, "ISOC TD length unmatch\n");
3883 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3884 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3885 usb_amd_quirk_pll_disable();
3887 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3889 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3890 start_cycle, start_trb);
3893 /* Clean up a partially enqueued isoc transfer. */
3895 for (i--; i >= 0; i--)
3896 list_del_init(&urb_priv->td[i]->td_list);
3898 /* Use the first TD as a temporary variable to turn the TDs we've queued
3899 * into No-ops with a software-owned cycle bit. That way the hardware
3900 * won't accidentally start executing bogus TDs when we partially
3901 * overwrite them. td->first_trb and td->start_seg are already set.
3903 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3904 /* Every TRB except the first & last will have its cycle bit flipped. */
3905 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3907 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3908 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3909 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3910 ep_ring->cycle_state = start_cycle;
3911 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3912 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3917 * Check transfer ring to guarantee there is enough room for the urb.
3918 * Update ISO URB start_frame and interval.
3919 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3920 * update the urb->start_frame by now.
3921 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3923 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3924 struct urb *urb, int slot_id, unsigned int ep_index)
3926 struct xhci_virt_device *xdev;
3927 struct xhci_ring *ep_ring;
3928 struct xhci_ep_ctx *ep_ctx;
3932 int num_tds, num_trbs, i;
3935 xdev = xhci->devs[slot_id];
3936 ep_ring = xdev->eps[ep_index].ring;
3937 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3940 num_tds = urb->number_of_packets;
3941 for (i = 0; i < num_tds; i++)
3942 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3944 /* Check the ring to guarantee there is enough room for the whole urb.
3945 * Do not insert any td of the urb to the ring if the check failed.
3947 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3948 num_trbs, mem_flags);
3952 start_frame = readl(&xhci->run_regs->microframe_index);
3953 start_frame &= 0x3fff;
3955 urb->start_frame = start_frame;
3956 if (urb->dev->speed == USB_SPEED_LOW ||
3957 urb->dev->speed == USB_SPEED_FULL)
3958 urb->start_frame >>= 3;
3960 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3961 ep_interval = urb->interval;
3962 /* Convert to microframes */
3963 if (urb->dev->speed == USB_SPEED_LOW ||
3964 urb->dev->speed == USB_SPEED_FULL)
3966 /* FIXME change this to a warning and a suggestion to use the new API
3967 * to set the polling interval (once the API is added).
3969 if (xhci_interval != ep_interval) {
3970 dev_dbg_ratelimited(&urb->dev->dev,
3971 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3972 ep_interval, ep_interval == 1 ? "" : "s",
3973 xhci_interval, xhci_interval == 1 ? "" : "s");
3974 urb->interval = xhci_interval;
3975 /* Convert back to frames for LS/FS devices */
3976 if (urb->dev->speed == USB_SPEED_LOW ||
3977 urb->dev->speed == USB_SPEED_FULL)
3980 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3982 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3985 /**** Command Ring Operations ****/
3987 /* Generic function for queueing a command TRB on the command ring.
3988 * Check to make sure there's room on the command ring for one command TRB.
3989 * Also check that there's room reserved for commands that must not fail.
3990 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3991 * then only check for the number of reserved spots.
3992 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3993 * because the command event handler may want to resubmit a failed command.
3995 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3996 u32 field1, u32 field2,
3997 u32 field3, u32 field4, bool command_must_succeed)
3999 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4002 if (!command_must_succeed)
4005 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4006 reserved_trbs, GFP_ATOMIC);
4008 xhci_err(xhci, "ERR: No room for command on command ring\n");
4009 if (command_must_succeed)
4010 xhci_err(xhci, "ERR: Reserved TRB counting for "
4011 "unfailable commands failed.\n");
4014 if (cmd->completion)
4015 cmd->command_trb = xhci->cmd_ring->enqueue;
4019 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4020 field4 | xhci->cmd_ring->cycle_state);
4024 /* Queue a slot enable or disable request on the command ring */
4025 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4026 u32 trb_type, u32 slot_id)
4028 return queue_command(xhci, cmd, 0, 0, 0,
4029 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4032 /* Queue an address device command TRB */
4033 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4034 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4036 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4037 upper_32_bits(in_ctx_ptr), 0,
4038 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4039 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4042 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4043 u32 field1, u32 field2, u32 field3, u32 field4)
4045 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4048 /* Queue a reset device command TRB */
4049 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4052 return queue_command(xhci, cmd, 0, 0, 0,
4053 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4057 /* Queue a configure endpoint command TRB */
4058 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4059 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4060 u32 slot_id, bool command_must_succeed)
4062 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4063 upper_32_bits(in_ctx_ptr), 0,
4064 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4065 command_must_succeed);
4068 /* Queue an evaluate context command TRB */
4069 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4070 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4072 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4073 upper_32_bits(in_ctx_ptr), 0,
4074 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4075 command_must_succeed);
4079 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4080 * activity on an endpoint that is about to be suspended.
4082 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4083 int slot_id, unsigned int ep_index, int suspend)
4085 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4086 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4087 u32 type = TRB_TYPE(TRB_STOP_RING);
4088 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4090 return queue_command(xhci, cmd, 0, 0, 0,
4091 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4094 /* Set Transfer Ring Dequeue Pointer command.
4095 * This should not be used for endpoints that have streams enabled.
4097 static int queue_set_tr_deq(struct xhci_hcd *xhci, struct xhci_command *cmd,
4099 unsigned int ep_index, unsigned int stream_id,
4100 struct xhci_segment *deq_seg,
4101 union xhci_trb *deq_ptr, u32 cycle_state)
4104 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4105 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4106 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4108 u32 type = TRB_TYPE(TRB_SET_DEQ);
4109 struct xhci_virt_ep *ep;
4111 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
4113 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4114 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4118 ep = &xhci->devs[slot_id]->eps[ep_index];
4119 if ((ep->ep_state & SET_DEQ_PENDING)) {
4120 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4121 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4124 ep->queued_deq_seg = deq_seg;
4125 ep->queued_deq_ptr = deq_ptr;
4127 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4128 return queue_command(xhci, cmd,
4129 lower_32_bits(addr) | trb_sct | cycle_state,
4130 upper_32_bits(addr), trb_stream_id,
4131 trb_slot_id | trb_ep_index | type, false);
4134 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4135 int slot_id, unsigned int ep_index)
4137 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4138 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4139 u32 type = TRB_TYPE(TRB_RESET_EP);
4141 return queue_command(xhci, cmd, 0, 0, 0,
4142 trb_slot_id | trb_ep_index | type, false);