2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
72 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
75 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
78 unsigned long segment_offset;
80 if (!seg || !trb || trb < seg->trbs)
83 segment_offset = trb - seg->trbs;
84 if (segment_offset > TRBS_PER_SEGMENT)
86 return seg->dma + (segment_offset * sizeof(*trb));
89 /* Does this link TRB point to the first segment in a ring,
90 * or was the previous TRB the last TRB on the last segment in the ERST?
92 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
93 struct xhci_segment *seg, union xhci_trb *trb)
95 if (ring == xhci->event_ring)
96 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
97 (seg->next == xhci->event_ring->first_seg);
99 return trb->link.control & LINK_TOGGLE;
102 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
103 * segment? I.e. would the updated event TRB pointer step off the end of the
106 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
107 struct xhci_segment *seg, union xhci_trb *trb)
109 if (ring == xhci->event_ring)
110 return trb == &seg->trbs[TRBS_PER_SEGMENT];
112 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
115 static inline int enqueue_is_link_trb(struct xhci_ring *ring)
117 struct xhci_link_trb *link = &ring->enqueue->link;
118 return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK));
121 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
122 * TRB is in a new segment. This does not skip over link TRBs, and it does not
123 * effect the ring dequeue or enqueue pointers.
125 static void next_trb(struct xhci_hcd *xhci,
126 struct xhci_ring *ring,
127 struct xhci_segment **seg,
128 union xhci_trb **trb)
130 if (last_trb(xhci, ring, *seg, *trb)) {
132 *trb = ((*seg)->trbs);
139 * See Cycle bit rules. SW is the consumer for the event ring only.
140 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
142 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
144 union xhci_trb *next = ++(ring->dequeue);
145 unsigned long long addr;
148 /* Update the dequeue pointer further if that was a link TRB or we're at
149 * the end of an event ring segment (which doesn't have link TRBS)
151 while (last_trb(xhci, ring, ring->deq_seg, next)) {
152 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
153 ring->cycle_state = (ring->cycle_state ? 0 : 1);
155 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
157 (unsigned int) ring->cycle_state);
159 ring->deq_seg = ring->deq_seg->next;
160 ring->dequeue = ring->deq_seg->trbs;
161 next = ring->dequeue;
163 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
164 if (ring == xhci->event_ring)
165 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
166 else if (ring == xhci->cmd_ring)
167 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
169 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
173 * See Cycle bit rules. SW is the consumer for the event ring only.
174 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
176 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
177 * chain bit is set), then set the chain bit in all the following link TRBs.
178 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
179 * have their chain bit cleared (so that each Link TRB is a separate TD).
181 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
182 * set, but other sections talk about dealing with the chain bit set. This was
183 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
184 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
186 * @more_trbs_coming: Will you enqueue more TRBs before calling
187 * prepare_transfer()?
189 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
190 bool consumer, bool more_trbs_coming)
193 union xhci_trb *next;
194 unsigned long long addr;
196 chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
197 next = ++(ring->enqueue);
200 /* Update the dequeue pointer further if that was a link TRB or we're at
201 * the end of an event ring segment (which doesn't have link TRBS)
203 while (last_trb(xhci, ring, ring->enq_seg, next)) {
205 if (ring != xhci->event_ring) {
207 * If the caller doesn't plan on enqueueing more
208 * TDs before ringing the doorbell, then we
209 * don't want to give the link TRB to the
210 * hardware just yet. We'll give the link TRB
211 * back in prepare_ring() just before we enqueue
212 * the TD at the top of the ring.
214 if (!chain && !more_trbs_coming)
217 /* If we're not dealing with 0.95 hardware,
218 * carry over the chain bit of the previous TRB
219 * (which may mean the chain bit is cleared).
221 if (!xhci_link_trb_quirk(xhci)) {
222 next->link.control &= ~TRB_CHAIN;
223 next->link.control |= chain;
225 /* Give this link TRB to the hardware */
227 next->link.control ^= TRB_CYCLE;
229 /* Toggle the cycle bit after the last ring segment. */
230 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
231 ring->cycle_state = (ring->cycle_state ? 0 : 1);
233 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
235 (unsigned int) ring->cycle_state);
238 ring->enq_seg = ring->enq_seg->next;
239 ring->enqueue = ring->enq_seg->trbs;
240 next = ring->enqueue;
242 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
243 if (ring == xhci->event_ring)
244 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
245 else if (ring == xhci->cmd_ring)
246 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
248 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
252 * Check to see if there's room to enqueue num_trbs on the ring. See rules
254 * FIXME: this would be simpler and faster if we just kept track of the number
255 * of free TRBs in a ring.
257 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
258 unsigned int num_trbs)
261 union xhci_trb *enq = ring->enqueue;
262 struct xhci_segment *enq_seg = ring->enq_seg;
263 struct xhci_segment *cur_seg;
264 unsigned int left_on_ring;
266 /* If we are currently pointing to a link TRB, advance the
267 * enqueue pointer before checking for space */
268 while (last_trb(xhci, ring, enq_seg, enq)) {
269 enq_seg = enq_seg->next;
273 /* Check if ring is empty */
274 if (enq == ring->dequeue) {
275 /* Can't use link trbs */
276 left_on_ring = TRBS_PER_SEGMENT - 1;
277 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
278 cur_seg = cur_seg->next)
279 left_on_ring += TRBS_PER_SEGMENT - 1;
281 /* Always need one TRB free in the ring. */
283 if (num_trbs > left_on_ring) {
284 xhci_warn(xhci, "Not enough room on ring; "
285 "need %u TRBs, %u TRBs left\n",
286 num_trbs, left_on_ring);
291 /* Make sure there's an extra empty TRB available */
292 for (i = 0; i <= num_trbs; ++i) {
293 if (enq == ring->dequeue)
296 while (last_trb(xhci, ring, enq_seg, enq)) {
297 enq_seg = enq_seg->next;
304 void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
309 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
310 xhci->event_ring->dequeue);
311 if (deq == 0 && !in_interrupt())
312 xhci_warn(xhci, "WARN something wrong with SW event ring "
314 /* Update HC event ring dequeue pointer */
315 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
316 temp &= ERST_PTR_MASK;
317 /* Don't clear the EHB bit (which is RW1C) because
318 * there might be more events to service.
321 xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");
322 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
323 &xhci->ir_set->erst_dequeue);
326 /* Ring the host controller doorbell after placing a command on the ring */
327 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
331 xhci_dbg(xhci, "// Ding dong!\n");
332 temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
333 xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
334 /* Flush PCI posted writes */
335 xhci_readl(xhci, &xhci->dba->doorbell[0]);
338 static void ring_ep_doorbell(struct xhci_hcd *xhci,
339 unsigned int slot_id,
340 unsigned int ep_index,
341 unsigned int stream_id)
343 struct xhci_virt_ep *ep;
344 unsigned int ep_state;
346 __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
348 ep = &xhci->devs[slot_id]->eps[ep_index];
349 ep_state = ep->ep_state;
350 /* Don't ring the doorbell for this endpoint if there are pending
351 * cancellations because the we don't want to interrupt processing.
352 * We don't want to restart any stream rings if there's a set dequeue
353 * pointer command pending because the device can choose to start any
354 * stream once the endpoint is on the HW schedule.
355 * FIXME - check all the stream rings for pending cancellations.
357 if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING)
358 && !(ep_state & EP_HALTED)) {
359 field = xhci_readl(xhci, db_addr) & DB_MASK;
360 field |= EPI_TO_DB(ep_index) | STREAM_ID_TO_DB(stream_id);
361 xhci_writel(xhci, field, db_addr);
362 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
363 * isn't time-critical and we shouldn't make the CPU wait for
366 xhci_readl(xhci, db_addr);
370 /* Ring the doorbell for any rings with pending URBs */
371 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
372 unsigned int slot_id,
373 unsigned int ep_index)
375 unsigned int stream_id;
376 struct xhci_virt_ep *ep;
378 ep = &xhci->devs[slot_id]->eps[ep_index];
380 /* A ring has pending URBs if its TD list is not empty */
381 if (!(ep->ep_state & EP_HAS_STREAMS)) {
382 if (!(list_empty(&ep->ring->td_list)))
383 ring_ep_doorbell(xhci, slot_id, ep_index, 0);
387 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
389 struct xhci_stream_info *stream_info = ep->stream_info;
390 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
391 ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
396 * Find the segment that trb is in. Start searching in start_seg.
397 * If we must move past a segment that has a link TRB with a toggle cycle state
398 * bit set, then we will toggle the value pointed at by cycle_state.
400 static struct xhci_segment *find_trb_seg(
401 struct xhci_segment *start_seg,
402 union xhci_trb *trb, int *cycle_state)
404 struct xhci_segment *cur_seg = start_seg;
405 struct xhci_generic_trb *generic_trb;
407 while (cur_seg->trbs > trb ||
408 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
409 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
410 if ((generic_trb->field[3] & TRB_TYPE_BITMASK) ==
411 TRB_TYPE(TRB_LINK) &&
412 (generic_trb->field[3] & LINK_TOGGLE))
413 *cycle_state = ~(*cycle_state) & 0x1;
414 cur_seg = cur_seg->next;
415 if (cur_seg == start_seg)
416 /* Looped over the entire list. Oops! */
423 * Move the xHC's endpoint ring dequeue pointer past cur_td.
424 * Record the new state of the xHC's endpoint ring dequeue segment,
425 * dequeue pointer, and new consumer cycle state in state.
426 * Update our internal representation of the ring's dequeue pointer.
428 * We do this in three jumps:
429 * - First we update our new ring state to be the same as when the xHC stopped.
430 * - Then we traverse the ring to find the segment that contains
431 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
432 * any link TRBs with the toggle cycle bit set.
433 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
434 * if we've moved it past a link TRB with the toggle cycle bit set.
436 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
437 unsigned int slot_id, unsigned int ep_index,
438 unsigned int stream_id, struct xhci_td *cur_td,
439 struct xhci_dequeue_state *state)
441 struct xhci_virt_device *dev = xhci->devs[slot_id];
442 struct xhci_ring *ep_ring;
443 struct xhci_generic_trb *trb;
444 struct xhci_ep_ctx *ep_ctx;
447 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
448 ep_index, stream_id);
450 xhci_warn(xhci, "WARN can't find new dequeue state "
451 "for invalid stream ID %u.\n",
455 state->new_cycle_state = 0;
456 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
457 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
458 dev->eps[ep_index].stopped_trb,
459 &state->new_cycle_state);
460 if (!state->new_deq_seg)
462 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
463 xhci_dbg(xhci, "Finding endpoint context\n");
464 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
465 state->new_cycle_state = 0x1 & ep_ctx->deq;
467 state->new_deq_ptr = cur_td->last_trb;
468 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
469 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
471 &state->new_cycle_state);
472 if (!state->new_deq_seg)
475 trb = &state->new_deq_ptr->generic;
476 if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) &&
477 (trb->field[3] & LINK_TOGGLE))
478 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
479 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
481 /* Don't update the ring cycle state for the producer (us). */
482 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
484 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
485 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
486 (unsigned long long) addr);
487 xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
488 ep_ring->dequeue = state->new_deq_ptr;
489 ep_ring->deq_seg = state->new_deq_seg;
492 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
493 struct xhci_td *cur_td)
495 struct xhci_segment *cur_seg;
496 union xhci_trb *cur_trb;
498 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
500 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
501 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
502 TRB_TYPE(TRB_LINK)) {
503 /* Unchain any chained Link TRBs, but
504 * leave the pointers intact.
506 cur_trb->generic.field[3] &= ~TRB_CHAIN;
507 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
508 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
509 "in seg %p (0x%llx dma)\n",
511 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
513 (unsigned long long)cur_seg->dma);
515 cur_trb->generic.field[0] = 0;
516 cur_trb->generic.field[1] = 0;
517 cur_trb->generic.field[2] = 0;
518 /* Preserve only the cycle bit of this TRB */
519 cur_trb->generic.field[3] &= TRB_CYCLE;
520 cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
521 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
522 "in seg %p (0x%llx dma)\n",
524 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
526 (unsigned long long)cur_seg->dma);
528 if (cur_trb == cur_td->last_trb)
533 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
534 unsigned int ep_index, unsigned int stream_id,
535 struct xhci_segment *deq_seg,
536 union xhci_trb *deq_ptr, u32 cycle_state);
538 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
539 unsigned int slot_id, unsigned int ep_index,
540 unsigned int stream_id,
541 struct xhci_dequeue_state *deq_state)
543 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
545 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
546 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
547 deq_state->new_deq_seg,
548 (unsigned long long)deq_state->new_deq_seg->dma,
549 deq_state->new_deq_ptr,
550 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
551 deq_state->new_cycle_state);
552 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
553 deq_state->new_deq_seg,
554 deq_state->new_deq_ptr,
555 (u32) deq_state->new_cycle_state);
556 /* Stop the TD queueing code from ringing the doorbell until
557 * this command completes. The HC won't set the dequeue pointer
558 * if the ring is running, and ringing the doorbell starts the
561 ep->ep_state |= SET_DEQ_PENDING;
564 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
565 struct xhci_virt_ep *ep)
567 ep->ep_state &= ~EP_HALT_PENDING;
568 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
569 * timer is running on another CPU, we don't decrement stop_cmds_pending
570 * (since we didn't successfully stop the watchdog timer).
572 if (del_timer(&ep->stop_cmd_timer))
573 ep->stop_cmds_pending--;
576 /* Must be called with xhci->lock held in interrupt context */
577 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
578 struct xhci_td *cur_td, int status, char *adjective)
580 struct usb_hcd *hcd = xhci_to_hcd(xhci);
582 struct urb_priv *urb_priv;
585 urb_priv = urb->hcpriv;
588 /* Only giveback urb when this is the last td in urb */
589 if (urb_priv->td_cnt == urb_priv->length) {
590 usb_hcd_unlink_urb_from_ep(hcd, urb);
591 xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb);
593 spin_unlock(&xhci->lock);
594 usb_hcd_giveback_urb(hcd, urb, status);
595 xhci_urb_free_priv(xhci, urb_priv);
596 spin_lock(&xhci->lock);
597 xhci_dbg(xhci, "%s URB given back\n", adjective);
602 * When we get a command completion for a Stop Endpoint Command, we need to
603 * unlink any cancelled TDs from the ring. There are two ways to do that:
605 * 1. If the HW was in the middle of processing the TD that needs to be
606 * cancelled, then we must move the ring's dequeue pointer past the last TRB
607 * in the TD with a Set Dequeue Pointer Command.
608 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
609 * bit cleared) so that the HW will skip over them.
611 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
614 unsigned int slot_id;
615 unsigned int ep_index;
616 struct xhci_ring *ep_ring;
617 struct xhci_virt_ep *ep;
618 struct list_head *entry;
619 struct xhci_td *cur_td = NULL;
620 struct xhci_td *last_unlinked_td;
622 struct xhci_dequeue_state deq_state;
624 memset(&deq_state, 0, sizeof(deq_state));
625 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
626 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
627 ep = &xhci->devs[slot_id]->eps[ep_index];
629 if (list_empty(&ep->cancelled_td_list)) {
630 xhci_stop_watchdog_timer_in_irq(xhci, ep);
631 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
635 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
636 * We have the xHCI lock, so nothing can modify this list until we drop
637 * it. We're also in the event handler, so we can't get re-interrupted
638 * if another Stop Endpoint command completes
640 list_for_each(entry, &ep->cancelled_td_list) {
641 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
642 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
644 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
645 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
647 /* This shouldn't happen unless a driver is mucking
648 * with the stream ID after submission. This will
649 * leave the TD on the hardware ring, and the hardware
650 * will try to execute it, and may access a buffer
651 * that has already been freed. In the best case, the
652 * hardware will execute it, and the event handler will
653 * ignore the completion event for that TD, since it was
654 * removed from the td_list for that endpoint. In
655 * short, don't muck with the stream ID after
658 xhci_warn(xhci, "WARN Cancelled URB %p "
659 "has invalid stream ID %u.\n",
661 cur_td->urb->stream_id);
662 goto remove_finished_td;
665 * If we stopped on the TD we need to cancel, then we have to
666 * move the xHC endpoint ring dequeue pointer past this TD.
668 if (cur_td == ep->stopped_td)
669 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
670 cur_td->urb->stream_id,
673 td_to_noop(xhci, ep_ring, cur_td);
676 * The event handler won't see a completion for this TD anymore,
677 * so remove it from the endpoint ring's TD list. Keep it in
678 * the cancelled TD list for URB completion later.
680 list_del(&cur_td->td_list);
682 last_unlinked_td = cur_td;
683 xhci_stop_watchdog_timer_in_irq(xhci, ep);
685 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
686 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
687 xhci_queue_new_dequeue_state(xhci,
689 ep->stopped_td->urb->stream_id,
691 xhci_ring_cmd_db(xhci);
693 /* Otherwise ring the doorbell(s) to restart queued transfers */
694 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
696 ep->stopped_td = NULL;
697 ep->stopped_trb = NULL;
700 * Drop the lock and complete the URBs in the cancelled TD list.
701 * New TDs to be cancelled might be added to the end of the list before
702 * we can complete all the URBs for the TDs we already unlinked.
703 * So stop when we've completed the URB for the last TD we unlinked.
706 cur_td = list_entry(ep->cancelled_td_list.next,
707 struct xhci_td, cancelled_td_list);
708 list_del(&cur_td->cancelled_td_list);
710 /* Clean up the cancelled URB */
711 /* Doesn't matter what we pass for status, since the core will
712 * just overwrite it (because the URB has been unlinked).
714 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
716 /* Stop processing the cancelled list if the watchdog timer is
719 if (xhci->xhc_state & XHCI_STATE_DYING)
721 } while (cur_td != last_unlinked_td);
723 /* Return to the event handler with xhci->lock re-acquired */
726 /* Watchdog timer function for when a stop endpoint command fails to complete.
727 * In this case, we assume the host controller is broken or dying or dead. The
728 * host may still be completing some other events, so we have to be careful to
729 * let the event ring handler and the URB dequeueing/enqueueing functions know
730 * through xhci->state.
732 * The timer may also fire if the host takes a very long time to respond to the
733 * command, and the stop endpoint command completion handler cannot delete the
734 * timer before the timer function is called. Another endpoint cancellation may
735 * sneak in before the timer function can grab the lock, and that may queue
736 * another stop endpoint command and add the timer back. So we cannot use a
737 * simple flag to say whether there is a pending stop endpoint command for a
738 * particular endpoint.
740 * Instead we use a combination of that flag and a counter for the number of
741 * pending stop endpoint commands. If the timer is the tail end of the last
742 * stop endpoint command, and the endpoint's command is still pending, we assume
745 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
747 struct xhci_hcd *xhci;
748 struct xhci_virt_ep *ep;
749 struct xhci_virt_ep *temp_ep;
750 struct xhci_ring *ring;
751 struct xhci_td *cur_td;
754 ep = (struct xhci_virt_ep *) arg;
757 spin_lock(&xhci->lock);
759 ep->stop_cmds_pending--;
760 if (xhci->xhc_state & XHCI_STATE_DYING) {
761 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
762 "xHCI as DYING, exiting.\n");
763 spin_unlock(&xhci->lock);
766 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
767 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
769 spin_unlock(&xhci->lock);
773 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
774 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
775 /* Oops, HC is dead or dying or at least not responding to the stop
778 xhci->xhc_state |= XHCI_STATE_DYING;
779 /* Disable interrupts from the host controller and start halting it */
781 spin_unlock(&xhci->lock);
783 ret = xhci_halt(xhci);
785 spin_lock(&xhci->lock);
787 /* This is bad; the host is not responding to commands and it's
788 * not allowing itself to be halted. At least interrupts are
789 * disabled, so we can set HC_STATE_HALT and notify the
790 * USB core. But if we call usb_hc_died(), it will attempt to
791 * disconnect all device drivers under this host. Those
792 * disconnect() methods will wait for all URBs to be unlinked,
793 * so we must complete them.
795 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
796 xhci_warn(xhci, "Completing active URBs anyway.\n");
797 /* We could turn all TDs on the rings to no-ops. This won't
798 * help if the host has cached part of the ring, and is slow if
799 * we want to preserve the cycle bit. Skip it and hope the host
800 * doesn't touch the memory.
803 for (i = 0; i < MAX_HC_SLOTS; i++) {
806 for (j = 0; j < 31; j++) {
807 temp_ep = &xhci->devs[i]->eps[j];
808 ring = temp_ep->ring;
811 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
812 "ep index %u\n", i, j);
813 while (!list_empty(&ring->td_list)) {
814 cur_td = list_first_entry(&ring->td_list,
817 list_del(&cur_td->td_list);
818 if (!list_empty(&cur_td->cancelled_td_list))
819 list_del(&cur_td->cancelled_td_list);
820 xhci_giveback_urb_in_irq(xhci, cur_td,
821 -ESHUTDOWN, "killed");
823 while (!list_empty(&temp_ep->cancelled_td_list)) {
824 cur_td = list_first_entry(
825 &temp_ep->cancelled_td_list,
828 list_del(&cur_td->cancelled_td_list);
829 xhci_giveback_urb_in_irq(xhci, cur_td,
830 -ESHUTDOWN, "killed");
834 spin_unlock(&xhci->lock);
835 xhci_to_hcd(xhci)->state = HC_STATE_HALT;
836 xhci_dbg(xhci, "Calling usb_hc_died()\n");
837 usb_hc_died(xhci_to_hcd(xhci));
838 xhci_dbg(xhci, "xHCI host controller is dead.\n");
842 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
843 * we need to clear the set deq pending flag in the endpoint ring state, so that
844 * the TD queueing code can ring the doorbell again. We also need to ring the
845 * endpoint doorbell to restart the ring, but only if there aren't more
846 * cancellations pending.
848 static void handle_set_deq_completion(struct xhci_hcd *xhci,
849 struct xhci_event_cmd *event,
852 unsigned int slot_id;
853 unsigned int ep_index;
854 unsigned int stream_id;
855 struct xhci_ring *ep_ring;
856 struct xhci_virt_device *dev;
857 struct xhci_ep_ctx *ep_ctx;
858 struct xhci_slot_ctx *slot_ctx;
860 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
861 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
862 stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]);
863 dev = xhci->devs[slot_id];
865 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
867 xhci_warn(xhci, "WARN Set TR deq ptr command for "
868 "freed stream ID %u\n",
870 /* XXX: Harmless??? */
871 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
875 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
876 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
878 if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
879 unsigned int ep_state;
880 unsigned int slot_state;
882 switch (GET_COMP_CODE(event->status)) {
884 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
885 "of stream ID configuration\n");
888 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
889 "to incorrect slot or ep state.\n");
890 ep_state = ep_ctx->ep_info;
891 ep_state &= EP_STATE_MASK;
892 slot_state = slot_ctx->dev_state;
893 slot_state = GET_SLOT_STATE(slot_state);
894 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
895 slot_state, ep_state);
898 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
899 "slot %u was not enabled.\n", slot_id);
902 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
903 "completion code of %u.\n",
904 GET_COMP_CODE(event->status));
907 /* OK what do we do now? The endpoint state is hosed, and we
908 * should never get to this point if the synchronization between
909 * queueing, and endpoint state are correct. This might happen
910 * if the device gets disconnected after we've finished
911 * cancelling URBs, which might not be an error...
914 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
918 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
919 /* Restart any rings with pending URBs */
920 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
923 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
924 struct xhci_event_cmd *event,
928 unsigned int ep_index;
930 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
931 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
932 /* This command will only fail if the endpoint wasn't halted,
935 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
936 (unsigned int) GET_COMP_CODE(event->status));
938 /* HW with the reset endpoint quirk needs to have a configure endpoint
939 * command complete before the endpoint can be used. Queue that here
940 * because the HW can't handle two commands being queued in a row.
942 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
943 xhci_dbg(xhci, "Queueing configure endpoint command\n");
944 xhci_queue_configure_endpoint(xhci,
945 xhci->devs[slot_id]->in_ctx->dma, slot_id,
947 xhci_ring_cmd_db(xhci);
949 /* Clear our internal halted state and restart the ring(s) */
950 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
951 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
955 /* Check to see if a command in the device's command queue matches this one.
956 * Signal the completion or free the command, and return 1. Return 0 if the
957 * completed command isn't at the head of the command list.
959 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
960 struct xhci_virt_device *virt_dev,
961 struct xhci_event_cmd *event)
963 struct xhci_command *command;
965 if (list_empty(&virt_dev->cmd_list))
968 command = list_entry(virt_dev->cmd_list.next,
969 struct xhci_command, cmd_list);
970 if (xhci->cmd_ring->dequeue != command->command_trb)
974 GET_COMP_CODE(event->status);
975 list_del(&command->cmd_list);
976 if (command->completion)
977 complete(command->completion);
979 xhci_free_command(xhci, command);
983 static void handle_cmd_completion(struct xhci_hcd *xhci,
984 struct xhci_event_cmd *event)
986 int slot_id = TRB_TO_SLOT_ID(event->flags);
988 dma_addr_t cmd_dequeue_dma;
989 struct xhci_input_control_ctx *ctrl_ctx;
990 struct xhci_virt_device *virt_dev;
991 unsigned int ep_index;
992 struct xhci_ring *ep_ring;
993 unsigned int ep_state;
995 cmd_dma = event->cmd_trb;
996 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
997 xhci->cmd_ring->dequeue);
998 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
999 if (cmd_dequeue_dma == 0) {
1000 xhci->error_bitmask |= 1 << 4;
1003 /* Does the DMA address match our internal dequeue pointer address? */
1004 if (cmd_dma != (u64) cmd_dequeue_dma) {
1005 xhci->error_bitmask |= 1 << 5;
1008 switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
1009 case TRB_TYPE(TRB_ENABLE_SLOT):
1010 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
1011 xhci->slot_id = slot_id;
1014 complete(&xhci->addr_dev);
1016 case TRB_TYPE(TRB_DISABLE_SLOT):
1017 if (xhci->devs[slot_id])
1018 xhci_free_virt_device(xhci, slot_id);
1020 case TRB_TYPE(TRB_CONFIG_EP):
1021 virt_dev = xhci->devs[slot_id];
1022 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1025 * Configure endpoint commands can come from the USB core
1026 * configuration or alt setting changes, or because the HW
1027 * needed an extra configure endpoint command after a reset
1028 * endpoint command or streams were being configured.
1029 * If the command was for a halted endpoint, the xHCI driver
1030 * is not waiting on the configure endpoint command.
1032 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1034 /* Input ctx add_flags are the endpoint index plus one */
1035 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
1036 /* A usb_set_interface() call directly after clearing a halted
1037 * condition may race on this quirky hardware. Not worth
1038 * worrying about, since this is prototype hardware. Not sure
1039 * if this will work for streams, but streams support was
1040 * untested on this prototype.
1042 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1043 ep_index != (unsigned int) -1 &&
1044 ctrl_ctx->add_flags - SLOT_FLAG ==
1045 ctrl_ctx->drop_flags) {
1046 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1047 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1048 if (!(ep_state & EP_HALTED))
1049 goto bandwidth_change;
1050 xhci_dbg(xhci, "Completed config ep cmd - "
1051 "last ep index = %d, state = %d\n",
1052 ep_index, ep_state);
1053 /* Clear internal halted state and restart ring(s) */
1054 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1056 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1060 xhci_dbg(xhci, "Completed config ep cmd\n");
1061 xhci->devs[slot_id]->cmd_status =
1062 GET_COMP_CODE(event->status);
1063 complete(&xhci->devs[slot_id]->cmd_completion);
1065 case TRB_TYPE(TRB_EVAL_CONTEXT):
1066 virt_dev = xhci->devs[slot_id];
1067 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1069 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1070 complete(&xhci->devs[slot_id]->cmd_completion);
1072 case TRB_TYPE(TRB_ADDR_DEV):
1073 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1074 complete(&xhci->addr_dev);
1076 case TRB_TYPE(TRB_STOP_RING):
1077 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
1079 case TRB_TYPE(TRB_SET_DEQ):
1080 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1082 case TRB_TYPE(TRB_CMD_NOOP):
1083 ++xhci->noops_handled;
1085 case TRB_TYPE(TRB_RESET_EP):
1086 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1088 case TRB_TYPE(TRB_RESET_DEV):
1089 xhci_dbg(xhci, "Completed reset device command.\n");
1090 slot_id = TRB_TO_SLOT_ID(
1091 xhci->cmd_ring->dequeue->generic.field[3]);
1092 virt_dev = xhci->devs[slot_id];
1094 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1096 xhci_warn(xhci, "Reset device command completion "
1097 "for disabled slot %u\n", slot_id);
1099 case TRB_TYPE(TRB_NEC_GET_FW):
1100 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1101 xhci->error_bitmask |= 1 << 6;
1104 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1105 NEC_FW_MAJOR(event->status),
1106 NEC_FW_MINOR(event->status));
1109 /* Skip over unknown commands on the event ring */
1110 xhci->error_bitmask |= 1 << 6;
1113 inc_deq(xhci, xhci->cmd_ring, false);
1116 static void handle_vendor_event(struct xhci_hcd *xhci,
1117 union xhci_trb *event)
1121 trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]);
1122 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1123 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1124 handle_cmd_completion(xhci, &event->event_cmd);
1127 static void handle_port_status(struct xhci_hcd *xhci,
1128 union xhci_trb *event)
1132 /* Port status change events always have a successful completion code */
1133 if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
1134 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1135 xhci->error_bitmask |= 1 << 8;
1137 /* FIXME: core doesn't care about all port link state changes yet */
1138 port_id = GET_PORT_ID(event->generic.field[0]);
1139 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1141 /* Update event ring dequeue pointer before dropping the lock */
1142 inc_deq(xhci, xhci->event_ring, true);
1143 xhci_set_hc_event_deq(xhci);
1145 spin_unlock(&xhci->lock);
1146 /* Pass this up to the core */
1147 usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
1148 spin_lock(&xhci->lock);
1152 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1153 * at end_trb, which may be in another segment. If the suspect DMA address is a
1154 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1157 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1158 union xhci_trb *start_trb,
1159 union xhci_trb *end_trb,
1160 dma_addr_t suspect_dma)
1162 dma_addr_t start_dma;
1163 dma_addr_t end_seg_dma;
1164 dma_addr_t end_trb_dma;
1165 struct xhci_segment *cur_seg;
1167 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1168 cur_seg = start_seg;
1173 /* We may get an event for a Link TRB in the middle of a TD */
1174 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1175 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1176 /* If the end TRB isn't in this segment, this is set to 0 */
1177 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1179 if (end_trb_dma > 0) {
1180 /* The end TRB is in this segment, so suspect should be here */
1181 if (start_dma <= end_trb_dma) {
1182 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1185 /* Case for one segment with
1186 * a TD wrapped around to the top
1188 if ((suspect_dma >= start_dma &&
1189 suspect_dma <= end_seg_dma) ||
1190 (suspect_dma >= cur_seg->dma &&
1191 suspect_dma <= end_trb_dma))
1196 /* Might still be somewhere in this segment */
1197 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1200 cur_seg = cur_seg->next;
1201 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1202 } while (cur_seg != start_seg);
1207 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1208 unsigned int slot_id, unsigned int ep_index,
1209 unsigned int stream_id,
1210 struct xhci_td *td, union xhci_trb *event_trb)
1212 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1213 ep->ep_state |= EP_HALTED;
1214 ep->stopped_td = td;
1215 ep->stopped_trb = event_trb;
1216 ep->stopped_stream = stream_id;
1218 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1219 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1221 ep->stopped_td = NULL;
1222 ep->stopped_trb = NULL;
1223 ep->stopped_stream = 0;
1225 xhci_ring_cmd_db(xhci);
1228 /* Check if an error has halted the endpoint ring. The class driver will
1229 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1230 * However, a babble and other errors also halt the endpoint ring, and the class
1231 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1232 * Ring Dequeue Pointer command manually.
1234 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1235 struct xhci_ep_ctx *ep_ctx,
1236 unsigned int trb_comp_code)
1238 /* TRB completion codes that may require a manual halt cleanup */
1239 if (trb_comp_code == COMP_TX_ERR ||
1240 trb_comp_code == COMP_BABBLE ||
1241 trb_comp_code == COMP_SPLIT_ERR)
1242 /* The 0.96 spec says a babbling control endpoint
1243 * is not halted. The 0.96 spec says it is. Some HW
1244 * claims to be 0.95 compliant, but it halts the control
1245 * endpoint anyway. Check if a babble halted the
1248 if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED)
1254 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1256 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1257 /* Vendor defined "informational" completion code,
1258 * treat as not-an-error.
1260 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1262 xhci_dbg(xhci, "Treating code as success.\n");
1269 * Finish the td processing, remove the td from td list;
1270 * Return 1 if the urb can be given back.
1272 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1273 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1274 struct xhci_virt_ep *ep, int *status, bool skip)
1276 struct xhci_virt_device *xdev;
1277 struct xhci_ring *ep_ring;
1278 unsigned int slot_id;
1280 struct urb *urb = NULL;
1281 struct xhci_ep_ctx *ep_ctx;
1283 struct urb_priv *urb_priv;
1286 slot_id = TRB_TO_SLOT_ID(event->flags);
1287 xdev = xhci->devs[slot_id];
1288 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1289 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1290 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1291 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1296 if (trb_comp_code == COMP_STOP_INVAL ||
1297 trb_comp_code == COMP_STOP) {
1298 /* The Endpoint Stop Command completion will take care of any
1299 * stopped TDs. A stopped TD may be restarted, so don't update
1300 * the ring dequeue pointer or take this TD off any lists yet.
1302 ep->stopped_td = td;
1303 ep->stopped_trb = event_trb;
1306 if (trb_comp_code == COMP_STALL) {
1307 /* The transfer is completed from the driver's
1308 * perspective, but we need to issue a set dequeue
1309 * command for this stalled endpoint to move the dequeue
1310 * pointer past the TD. We can't do that here because
1311 * the halt condition must be cleared first. Let the
1312 * USB class driver clear the stall later.
1314 ep->stopped_td = td;
1315 ep->stopped_trb = event_trb;
1316 ep->stopped_stream = ep_ring->stream_id;
1317 } else if (xhci_requires_manual_halt_cleanup(xhci,
1318 ep_ctx, trb_comp_code)) {
1319 /* Other types of errors halt the endpoint, but the
1320 * class driver doesn't call usb_reset_endpoint() unless
1321 * the error is -EPIPE. Clear the halted status in the
1322 * xHCI hardware manually.
1324 xhci_cleanup_halted_endpoint(xhci,
1325 slot_id, ep_index, ep_ring->stream_id,
1328 /* Update ring dequeue pointer */
1329 while (ep_ring->dequeue != td->last_trb)
1330 inc_deq(xhci, ep_ring, false);
1331 inc_deq(xhci, ep_ring, false);
1335 /* Clean up the endpoint's TD list */
1337 urb_priv = urb->hcpriv;
1339 /* Do one last check of the actual transfer length.
1340 * If the host controller said we transferred more data than
1341 * the buffer length, urb->actual_length will be a very big
1342 * number (since it's unsigned). Play it safe and say we didn't
1343 * transfer anything.
1345 if (urb->actual_length > urb->transfer_buffer_length) {
1346 xhci_warn(xhci, "URB transfer length is wrong, "
1347 "xHC issue? req. len = %u, "
1349 urb->transfer_buffer_length,
1350 urb->actual_length);
1351 urb->actual_length = 0;
1352 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1353 *status = -EREMOTEIO;
1357 list_del(&td->td_list);
1358 /* Was this TD slated to be cancelled but completed anyway? */
1359 if (!list_empty(&td->cancelled_td_list))
1360 list_del(&td->cancelled_td_list);
1363 /* Giveback the urb when all the tds are completed */
1364 if (urb_priv->td_cnt == urb_priv->length)
1372 * Process control tds, update urb status and actual_length.
1374 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1375 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1376 struct xhci_virt_ep *ep, int *status)
1378 struct xhci_virt_device *xdev;
1379 struct xhci_ring *ep_ring;
1380 unsigned int slot_id;
1382 struct xhci_ep_ctx *ep_ctx;
1385 slot_id = TRB_TO_SLOT_ID(event->flags);
1386 xdev = xhci->devs[slot_id];
1387 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1388 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1389 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1390 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1392 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1393 switch (trb_comp_code) {
1395 if (event_trb == ep_ring->dequeue) {
1396 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1397 "without IOC set??\n");
1398 *status = -ESHUTDOWN;
1399 } else if (event_trb != td->last_trb) {
1400 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1401 "without IOC set??\n");
1402 *status = -ESHUTDOWN;
1404 xhci_dbg(xhci, "Successful control transfer!\n");
1409 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1410 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1411 *status = -EREMOTEIO;
1416 if (!xhci_requires_manual_halt_cleanup(xhci,
1417 ep_ctx, trb_comp_code))
1419 xhci_dbg(xhci, "TRB error code %u, "
1420 "halted endpoint index = %u\n",
1421 trb_comp_code, ep_index);
1422 /* else fall through */
1424 /* Did we transfer part of the data (middle) phase? */
1425 if (event_trb != ep_ring->dequeue &&
1426 event_trb != td->last_trb)
1427 td->urb->actual_length =
1428 td->urb->transfer_buffer_length
1429 - TRB_LEN(event->transfer_len);
1431 td->urb->actual_length = 0;
1433 xhci_cleanup_halted_endpoint(xhci,
1434 slot_id, ep_index, 0, td, event_trb);
1435 return finish_td(xhci, td, event_trb, event, ep, status, true);
1438 * Did we transfer any data, despite the errors that might have
1439 * happened? I.e. did we get past the setup stage?
1441 if (event_trb != ep_ring->dequeue) {
1442 /* The event was for the status stage */
1443 if (event_trb == td->last_trb) {
1444 if (td->urb->actual_length != 0) {
1445 /* Don't overwrite a previously set error code
1447 if ((*status == -EINPROGRESS || *status == 0) &&
1448 (td->urb->transfer_flags
1449 & URB_SHORT_NOT_OK))
1450 /* Did we already see a short data
1452 *status = -EREMOTEIO;
1454 td->urb->actual_length =
1455 td->urb->transfer_buffer_length;
1458 /* Maybe the event was for the data stage? */
1459 if (trb_comp_code != COMP_STOP_INVAL) {
1460 /* We didn't stop on a link TRB in the middle */
1461 td->urb->actual_length =
1462 td->urb->transfer_buffer_length -
1463 TRB_LEN(event->transfer_len);
1464 xhci_dbg(xhci, "Waiting for status "
1471 return finish_td(xhci, td, event_trb, event, ep, status, false);
1475 * Process isochronous tds, update urb packet status and actual_length.
1477 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1478 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1479 struct xhci_virt_ep *ep, int *status)
1481 struct xhci_ring *ep_ring;
1482 struct urb_priv *urb_priv;
1486 union xhci_trb *cur_trb;
1487 struct xhci_segment *cur_seg;
1490 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1491 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1492 urb_priv = td->urb->hcpriv;
1493 idx = urb_priv->td_cnt;
1496 /* The transfer is partly done */
1498 td->urb->iso_frame_desc[idx].status = -EXDEV;
1500 /* handle completion code */
1501 switch (trb_comp_code) {
1503 td->urb->iso_frame_desc[idx].status = 0;
1504 xhci_dbg(xhci, "Successful isoc transfer!\n");
1507 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1508 td->urb->iso_frame_desc[idx].status =
1511 td->urb->iso_frame_desc[idx].status = 0;
1514 td->urb->iso_frame_desc[idx].status = -ECOMM;
1517 case COMP_BUFF_OVER:
1519 td->urb->iso_frame_desc[idx].status = -EOVERFLOW;
1523 td->urb->iso_frame_desc[idx].status = -EPROTO;
1527 case COMP_STOP_INVAL:
1530 td->urb->iso_frame_desc[idx].status = -1;
1535 /* calc actual length */
1537 td->urb->iso_frame_desc[idx].actual_length = 0;
1538 return finish_td(xhci, td, event_trb, event, ep, status, true);
1541 if (trb_comp_code == COMP_SUCCESS || skip_td == 1) {
1542 td->urb->iso_frame_desc[idx].actual_length =
1543 td->urb->iso_frame_desc[idx].length;
1544 td->urb->actual_length +=
1545 td->urb->iso_frame_desc[idx].length;
1547 for (cur_trb = ep_ring->dequeue,
1548 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1549 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1550 if ((cur_trb->generic.field[3] &
1551 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1552 (cur_trb->generic.field[3] &
1553 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1555 TRB_LEN(cur_trb->generic.field[2]);
1557 len += TRB_LEN(cur_trb->generic.field[2]) -
1558 TRB_LEN(event->transfer_len);
1560 if (trb_comp_code != COMP_STOP_INVAL) {
1561 td->urb->iso_frame_desc[idx].actual_length = len;
1562 td->urb->actual_length += len;
1566 if ((idx == urb_priv->length - 1) && *status == -EINPROGRESS)
1569 return finish_td(xhci, td, event_trb, event, ep, status, false);
1573 * Process bulk and interrupt tds, update urb status and actual_length.
1575 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1576 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1577 struct xhci_virt_ep *ep, int *status)
1579 struct xhci_ring *ep_ring;
1580 union xhci_trb *cur_trb;
1581 struct xhci_segment *cur_seg;
1584 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1585 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1587 switch (trb_comp_code) {
1589 /* Double check that the HW transferred everything. */
1590 if (event_trb != td->last_trb) {
1591 xhci_warn(xhci, "WARN Successful completion "
1593 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1594 *status = -EREMOTEIO;
1598 if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1599 xhci_dbg(xhci, "Successful bulk "
1602 xhci_dbg(xhci, "Successful interrupt "
1608 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1609 *status = -EREMOTEIO;
1614 /* Others already handled above */
1617 dev_dbg(&td->urb->dev->dev,
1618 "ep %#x - asked for %d bytes, "
1619 "%d bytes untransferred\n",
1620 td->urb->ep->desc.bEndpointAddress,
1621 td->urb->transfer_buffer_length,
1622 TRB_LEN(event->transfer_len));
1623 /* Fast path - was this the last TRB in the TD for this URB? */
1624 if (event_trb == td->last_trb) {
1625 if (TRB_LEN(event->transfer_len) != 0) {
1626 td->urb->actual_length =
1627 td->urb->transfer_buffer_length -
1628 TRB_LEN(event->transfer_len);
1629 if (td->urb->transfer_buffer_length <
1630 td->urb->actual_length) {
1631 xhci_warn(xhci, "HC gave bad length "
1632 "of %d bytes left\n",
1633 TRB_LEN(event->transfer_len));
1634 td->urb->actual_length = 0;
1635 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1636 *status = -EREMOTEIO;
1640 /* Don't overwrite a previously set error code */
1641 if (*status == -EINPROGRESS) {
1642 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1643 *status = -EREMOTEIO;
1648 td->urb->actual_length =
1649 td->urb->transfer_buffer_length;
1650 /* Ignore a short packet completion if the
1651 * untransferred length was zero.
1653 if (*status == -EREMOTEIO)
1657 /* Slow path - walk the list, starting from the dequeue
1658 * pointer, to get the actual length transferred.
1660 td->urb->actual_length = 0;
1661 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1662 cur_trb != event_trb;
1663 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1664 if ((cur_trb->generic.field[3] &
1665 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1666 (cur_trb->generic.field[3] &
1667 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1668 td->urb->actual_length +=
1669 TRB_LEN(cur_trb->generic.field[2]);
1671 /* If the ring didn't stop on a Link or No-op TRB, add
1672 * in the actual bytes transferred from the Normal TRB
1674 if (trb_comp_code != COMP_STOP_INVAL)
1675 td->urb->actual_length +=
1676 TRB_LEN(cur_trb->generic.field[2]) -
1677 TRB_LEN(event->transfer_len);
1680 return finish_td(xhci, td, event_trb, event, ep, status, false);
1684 * If this function returns an error condition, it means it got a Transfer
1685 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1686 * At this point, the host controller is probably hosed and should be reset.
1688 static int handle_tx_event(struct xhci_hcd *xhci,
1689 struct xhci_transfer_event *event)
1691 struct xhci_virt_device *xdev;
1692 struct xhci_virt_ep *ep;
1693 struct xhci_ring *ep_ring;
1694 unsigned int slot_id;
1696 struct xhci_td *td = NULL;
1697 dma_addr_t event_dma;
1698 struct xhci_segment *event_seg;
1699 union xhci_trb *event_trb;
1700 struct urb *urb = NULL;
1701 int status = -EINPROGRESS;
1702 struct urb_priv *urb_priv;
1703 struct xhci_ep_ctx *ep_ctx;
1707 slot_id = TRB_TO_SLOT_ID(event->flags);
1708 xdev = xhci->devs[slot_id];
1710 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1714 /* Endpoint ID is 1 based, our index is zero based */
1715 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1716 xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1717 ep = &xdev->eps[ep_index];
1718 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1719 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1721 (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
1722 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1723 "or incorrect stream ring\n");
1727 event_dma = event->buffer;
1728 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1729 /* Look for common error cases */
1730 switch (trb_comp_code) {
1731 /* Skip codes that require special handling depending on
1738 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1740 case COMP_STOP_INVAL:
1741 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1744 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1745 ep->ep_state |= EP_HALTED;
1749 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1752 case COMP_SPLIT_ERR:
1754 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1758 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1759 status = -EOVERFLOW;
1762 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1766 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
1768 case COMP_BUFF_OVER:
1769 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
1773 * When the Isoch ring is empty, the xHC will generate
1774 * a Ring Overrun Event for IN Isoch endpoint or Ring
1775 * Underrun Event for OUT Isoch endpoint.
1777 xhci_dbg(xhci, "underrun event on endpoint\n");
1778 if (!list_empty(&ep_ring->td_list))
1779 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
1780 "still with TDs queued?\n",
1781 TRB_TO_SLOT_ID(event->flags), ep_index);
1784 xhci_dbg(xhci, "overrun event on endpoint\n");
1785 if (!list_empty(&ep_ring->td_list))
1786 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
1787 "still with TDs queued?\n",
1788 TRB_TO_SLOT_ID(event->flags), ep_index);
1790 case COMP_MISSED_INT:
1792 * When encounter missed service error, one or more isoc tds
1793 * may be missed by xHC.
1794 * Set skip flag of the ep_ring; Complete the missed tds as
1795 * short transfer when process the ep_ring next time.
1798 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
1801 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
1805 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
1811 /* This TRB should be in the TD at the head of this ring's
1814 if (list_empty(&ep_ring->td_list)) {
1815 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
1816 "with no TDs queued?\n",
1817 TRB_TO_SLOT_ID(event->flags), ep_index);
1818 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1819 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1820 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
1823 xhci_dbg(xhci, "td_list is empty while skip "
1824 "flag set. Clear skip flag.\n");
1830 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
1831 /* Is this a TRB in the currently executing TD? */
1832 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
1833 td->last_trb, event_dma);
1834 if (event_seg && ep->skip) {
1835 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
1839 (!ep->skip || !usb_endpoint_xfer_isoc(&td->urb->ep->desc))) {
1840 /* HC is busted, give up! */
1841 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not "
1842 "part of current TD\n");
1847 event_trb = &event_seg->trbs[(event_dma -
1848 event_seg->dma) / sizeof(*event_trb)];
1850 * No-op TRB should not trigger interrupts.
1851 * If event_trb is a no-op TRB, it means the
1852 * corresponding TD has been cancelled. Just ignore
1855 if ((event_trb->generic.field[3] & TRB_TYPE_BITMASK)
1856 == TRB_TYPE(TRB_TR_NOOP)) {
1857 xhci_dbg(xhci, "event_trb is a no-op TRB. "
1863 /* Now update the urb's actual_length and give back to
1866 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
1867 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
1869 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
1870 ret = process_isoc_td(xhci, td, event_trb, event, ep,
1873 ret = process_bulk_intr_td(xhci, td, event_trb, event,
1878 * Do not update event ring dequeue pointer if ep->skip is set.
1879 * Will roll back to continue process missed tds.
1881 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
1882 inc_deq(xhci, xhci->event_ring, true);
1883 xhci_set_hc_event_deq(xhci);
1888 urb_priv = urb->hcpriv;
1889 /* Leave the TD around for the reset endpoint function
1890 * to use(but only if it's not a control endpoint,
1891 * since we already queued the Set TR dequeue pointer
1892 * command for stalled control endpoints).
1894 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1895 (trb_comp_code != COMP_STALL &&
1896 trb_comp_code != COMP_BABBLE))
1897 xhci_urb_free_priv(xhci, urb_priv);
1899 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1900 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
1902 urb, urb->actual_length, status);
1903 spin_unlock(&xhci->lock);
1904 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1905 spin_lock(&xhci->lock);
1909 * If ep->skip is set, it means there are missed tds on the
1910 * endpoint ring need to take care of.
1911 * Process them as short transfer until reach the td pointed by
1914 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
1920 * This function handles all OS-owned events on the event ring. It may drop
1921 * xhci->lock between event processing (e.g. to pass up port status changes).
1923 void xhci_handle_event(struct xhci_hcd *xhci)
1925 union xhci_trb *event;
1926 int update_ptrs = 1;
1929 xhci_dbg(xhci, "In %s\n", __func__);
1930 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1931 xhci->error_bitmask |= 1 << 1;
1935 event = xhci->event_ring->dequeue;
1936 /* Does the HC or OS own the TRB? */
1937 if ((event->event_cmd.flags & TRB_CYCLE) !=
1938 xhci->event_ring->cycle_state) {
1939 xhci->error_bitmask |= 1 << 2;
1942 xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1944 /* FIXME: Handle more event types. */
1945 switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1946 case TRB_TYPE(TRB_COMPLETION):
1947 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1948 handle_cmd_completion(xhci, &event->event_cmd);
1949 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1951 case TRB_TYPE(TRB_PORT_STATUS):
1952 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1953 handle_port_status(xhci, event);
1954 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1957 case TRB_TYPE(TRB_TRANSFER):
1958 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
1959 ret = handle_tx_event(xhci, &event->trans_event);
1960 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
1962 xhci->error_bitmask |= 1 << 9;
1967 if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48))
1968 handle_vendor_event(xhci, event);
1970 xhci->error_bitmask |= 1 << 3;
1972 /* Any of the above functions may drop and re-acquire the lock, so check
1973 * to make sure a watchdog timer didn't mark the host as non-responsive.
1975 if (xhci->xhc_state & XHCI_STATE_DYING) {
1976 xhci_dbg(xhci, "xHCI host dying, returning from "
1977 "event handler.\n");
1982 /* Update SW and HC event ring dequeue pointer */
1983 inc_deq(xhci, xhci->event_ring, true);
1984 xhci_set_hc_event_deq(xhci);
1986 /* Are there more items on the event ring? */
1987 xhci_handle_event(xhci);
1990 /**** Endpoint Ring Operations ****/
1993 * Generic function for queueing a TRB on a ring.
1994 * The caller must have checked to make sure there's room on the ring.
1996 * @more_trbs_coming: Will you enqueue more TRBs before calling
1997 * prepare_transfer()?
1999 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2000 bool consumer, bool more_trbs_coming,
2001 u32 field1, u32 field2, u32 field3, u32 field4)
2003 struct xhci_generic_trb *trb;
2005 trb = &ring->enqueue->generic;
2006 trb->field[0] = field1;
2007 trb->field[1] = field2;
2008 trb->field[2] = field3;
2009 trb->field[3] = field4;
2010 inc_enq(xhci, ring, consumer, more_trbs_coming);
2014 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2015 * FIXME allocate segments if the ring is full.
2017 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2018 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2020 /* Make sure the endpoint has been added to xHC schedule */
2021 xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
2023 case EP_STATE_DISABLED:
2025 * USB core changed config/interfaces without notifying us,
2026 * or hardware is reporting the wrong state.
2028 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2030 case EP_STATE_ERROR:
2031 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2032 /* FIXME event handling code for error needs to clear it */
2033 /* XXX not sure if this should be -ENOENT or not */
2035 case EP_STATE_HALTED:
2036 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2037 case EP_STATE_STOPPED:
2038 case EP_STATE_RUNNING:
2041 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2043 * FIXME issue Configure Endpoint command to try to get the HC
2044 * back into a known state.
2048 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2049 /* FIXME allocate more room */
2050 xhci_err(xhci, "ERROR no room on ep ring\n");
2054 if (enqueue_is_link_trb(ep_ring)) {
2055 struct xhci_ring *ring = ep_ring;
2056 union xhci_trb *next;
2058 xhci_dbg(xhci, "prepare_ring: pointing to link trb\n");
2059 next = ring->enqueue;
2061 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2063 /* If we're not dealing with 0.95 hardware,
2064 * clear the chain bit.
2066 if (!xhci_link_trb_quirk(xhci))
2067 next->link.control &= ~TRB_CHAIN;
2069 next->link.control |= TRB_CHAIN;
2072 next->link.control ^= (u32) TRB_CYCLE;
2074 /* Toggle the cycle bit after the last ring segment. */
2075 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2076 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2077 if (!in_interrupt()) {
2078 xhci_dbg(xhci, "queue_trb: Toggle cycle "
2079 "state for ring %p = %i\n",
2080 ring, (unsigned int)ring->cycle_state);
2083 ring->enq_seg = ring->enq_seg->next;
2084 ring->enqueue = ring->enq_seg->trbs;
2085 next = ring->enqueue;
2092 static int prepare_transfer(struct xhci_hcd *xhci,
2093 struct xhci_virt_device *xdev,
2094 unsigned int ep_index,
2095 unsigned int stream_id,
2096 unsigned int num_trbs,
2098 unsigned int td_index,
2102 struct urb_priv *urb_priv;
2104 struct xhci_ring *ep_ring;
2105 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2107 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2109 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2114 ret = prepare_ring(xhci, ep_ring,
2115 ep_ctx->ep_info & EP_STATE_MASK,
2116 num_trbs, mem_flags);
2120 urb_priv = urb->hcpriv;
2121 td = urb_priv->td[td_index];
2123 INIT_LIST_HEAD(&td->td_list);
2124 INIT_LIST_HEAD(&td->cancelled_td_list);
2126 if (td_index == 0) {
2127 ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
2128 if (unlikely(ret)) {
2129 xhci_urb_free_priv(xhci, urb_priv);
2136 /* Add this TD to the tail of the endpoint ring's TD list */
2137 list_add_tail(&td->td_list, &ep_ring->td_list);
2138 td->start_seg = ep_ring->enq_seg;
2139 td->first_trb = ep_ring->enqueue;
2141 urb_priv->td[td_index] = td;
2146 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2148 int num_sgs, num_trbs, running_total, temp, i;
2149 struct scatterlist *sg;
2152 num_sgs = urb->num_sgs;
2153 temp = urb->transfer_buffer_length;
2155 xhci_dbg(xhci, "count sg list trbs: \n");
2157 for_each_sg(urb->sg, sg, num_sgs, i) {
2158 unsigned int previous_total_trbs = num_trbs;
2159 unsigned int len = sg_dma_len(sg);
2161 /* Scatter gather list entries may cross 64KB boundaries */
2162 running_total = TRB_MAX_BUFF_SIZE -
2163 (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2164 if (running_total != 0)
2167 /* How many more 64KB chunks to transfer, how many more TRBs? */
2168 while (running_total < sg_dma_len(sg)) {
2170 running_total += TRB_MAX_BUFF_SIZE;
2172 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2173 i, (unsigned long long)sg_dma_address(sg),
2174 len, len, num_trbs - previous_total_trbs);
2176 len = min_t(int, len, temp);
2181 xhci_dbg(xhci, "\n");
2182 if (!in_interrupt())
2183 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
2184 urb->ep->desc.bEndpointAddress,
2185 urb->transfer_buffer_length,
2190 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2193 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2194 "TRBs, %d left\n", __func__,
2195 urb->ep->desc.bEndpointAddress, num_trbs);
2196 if (running_total != urb->transfer_buffer_length)
2197 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2198 "queued %#x (%d), asked for %#x (%d)\n",
2200 urb->ep->desc.bEndpointAddress,
2201 running_total, running_total,
2202 urb->transfer_buffer_length,
2203 urb->transfer_buffer_length);
2206 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2207 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2208 struct xhci_generic_trb *start_trb, struct xhci_td *td)
2211 * Pass all the TRBs to the hardware at once and make sure this write
2215 start_trb->field[3] |= start_cycle;
2216 ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2220 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2221 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2222 * (comprised of sg list entries) can take several service intervals to
2225 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2226 struct urb *urb, int slot_id, unsigned int ep_index)
2228 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2229 xhci->devs[slot_id]->out_ctx, ep_index);
2233 xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
2234 ep_interval = urb->interval;
2235 /* Convert to microframes */
2236 if (urb->dev->speed == USB_SPEED_LOW ||
2237 urb->dev->speed == USB_SPEED_FULL)
2239 /* FIXME change this to a warning and a suggestion to use the new API
2240 * to set the polling interval (once the API is added).
2242 if (xhci_interval != ep_interval) {
2243 if (!printk_ratelimit())
2244 dev_dbg(&urb->dev->dev, "Driver uses different interval"
2245 " (%d microframe%s) than xHCI "
2246 "(%d microframe%s)\n",
2248 ep_interval == 1 ? "" : "s",
2250 xhci_interval == 1 ? "" : "s");
2251 urb->interval = xhci_interval;
2252 /* Convert back to frames for LS/FS devices */
2253 if (urb->dev->speed == USB_SPEED_LOW ||
2254 urb->dev->speed == USB_SPEED_FULL)
2257 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2261 * The TD size is the number of bytes remaining in the TD (including this TRB),
2262 * right shifted by 10.
2263 * It must fit in bits 21:17, so it can't be bigger than 31.
2265 static u32 xhci_td_remainder(unsigned int remainder)
2267 u32 max = (1 << (21 - 17 + 1)) - 1;
2269 if ((remainder >> 10) >= max)
2272 return (remainder >> 10) << 17;
2275 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2276 struct urb *urb, int slot_id, unsigned int ep_index)
2278 struct xhci_ring *ep_ring;
2279 unsigned int num_trbs;
2280 struct urb_priv *urb_priv;
2282 struct scatterlist *sg;
2284 int trb_buff_len, this_sg_len, running_total;
2287 bool more_trbs_coming;
2289 struct xhci_generic_trb *start_trb;
2292 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2296 num_trbs = count_sg_trbs_needed(xhci, urb);
2297 num_sgs = urb->num_sgs;
2299 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2300 ep_index, urb->stream_id,
2301 num_trbs, urb, 0, mem_flags);
2302 if (trb_buff_len < 0)
2303 return trb_buff_len;
2305 urb_priv = urb->hcpriv;
2306 td = urb_priv->td[0];
2309 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2310 * until we've finished creating all the other TRBs. The ring's cycle
2311 * state may change as we enqueue the other TRBs, so save it too.
2313 start_trb = &ep_ring->enqueue->generic;
2314 start_cycle = ep_ring->cycle_state;
2318 * How much data is in the first TRB?
2320 * There are three forces at work for TRB buffer pointers and lengths:
2321 * 1. We don't want to walk off the end of this sg-list entry buffer.
2322 * 2. The transfer length that the driver requested may be smaller than
2323 * the amount of memory allocated for this scatter-gather list.
2324 * 3. TRBs buffers can't cross 64KB boundaries.
2327 addr = (u64) sg_dma_address(sg);
2328 this_sg_len = sg_dma_len(sg);
2329 trb_buff_len = TRB_MAX_BUFF_SIZE -
2330 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2331 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2332 if (trb_buff_len > urb->transfer_buffer_length)
2333 trb_buff_len = urb->transfer_buffer_length;
2334 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2338 /* Queue the first TRB, even if it's zero-length */
2341 u32 length_field = 0;
2344 /* Don't change the cycle bit of the first TRB until later */
2348 field |= ep_ring->cycle_state;
2350 /* Chain all the TRBs together; clear the chain bit in the last
2351 * TRB to indicate it's the last TRB in the chain.
2356 /* FIXME - add check for ZERO_PACKET flag before this */
2357 td->last_trb = ep_ring->enqueue;
2360 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2361 "64KB boundary at %#x, end dma = %#x\n",
2362 (unsigned int) addr, trb_buff_len, trb_buff_len,
2363 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2364 (unsigned int) addr + trb_buff_len);
2365 if (TRB_MAX_BUFF_SIZE -
2366 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
2367 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2368 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2369 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2370 (unsigned int) addr + trb_buff_len);
2372 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2374 length_field = TRB_LEN(trb_buff_len) |
2378 more_trbs_coming = true;
2380 more_trbs_coming = false;
2381 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2382 lower_32_bits(addr),
2383 upper_32_bits(addr),
2385 /* We always want to know if the TRB was short,
2386 * or we won't get an event when it completes.
2387 * (Unless we use event data TRBs, which are a
2388 * waste of space and HC resources.)
2390 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2392 running_total += trb_buff_len;
2394 /* Calculate length for next transfer --
2395 * Are we done queueing all the TRBs for this sg entry?
2397 this_sg_len -= trb_buff_len;
2398 if (this_sg_len == 0) {
2403 addr = (u64) sg_dma_address(sg);
2404 this_sg_len = sg_dma_len(sg);
2406 addr += trb_buff_len;
2409 trb_buff_len = TRB_MAX_BUFF_SIZE -
2410 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2411 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2412 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2414 urb->transfer_buffer_length - running_total;
2415 } while (running_total < urb->transfer_buffer_length);
2417 check_trb_math(urb, num_trbs, running_total);
2418 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2419 start_cycle, start_trb, td);
2423 /* This is very similar to what ehci-q.c qtd_fill() does */
2424 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2425 struct urb *urb, int slot_id, unsigned int ep_index)
2427 struct xhci_ring *ep_ring;
2428 struct urb_priv *urb_priv;
2431 struct xhci_generic_trb *start_trb;
2433 bool more_trbs_coming;
2435 u32 field, length_field;
2437 int running_total, trb_buff_len, ret;
2441 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2443 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2448 /* How much data is (potentially) left before the 64KB boundary? */
2449 running_total = TRB_MAX_BUFF_SIZE -
2450 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2452 /* If there's some data on this 64KB chunk, or we have to send a
2453 * zero-length transfer, we need at least one TRB
2455 if (running_total != 0 || urb->transfer_buffer_length == 0)
2457 /* How many more 64KB chunks to transfer, how many more TRBs? */
2458 while (running_total < urb->transfer_buffer_length) {
2460 running_total += TRB_MAX_BUFF_SIZE;
2462 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2464 if (!in_interrupt())
2465 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
2466 urb->ep->desc.bEndpointAddress,
2467 urb->transfer_buffer_length,
2468 urb->transfer_buffer_length,
2469 (unsigned long long)urb->transfer_dma,
2472 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2473 ep_index, urb->stream_id,
2474 num_trbs, urb, 0, mem_flags);
2478 urb_priv = urb->hcpriv;
2479 td = urb_priv->td[0];
2482 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2483 * until we've finished creating all the other TRBs. The ring's cycle
2484 * state may change as we enqueue the other TRBs, so save it too.
2486 start_trb = &ep_ring->enqueue->generic;
2487 start_cycle = ep_ring->cycle_state;
2490 /* How much data is in the first TRB? */
2491 addr = (u64) urb->transfer_dma;
2492 trb_buff_len = TRB_MAX_BUFF_SIZE -
2493 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2494 if (urb->transfer_buffer_length < trb_buff_len)
2495 trb_buff_len = urb->transfer_buffer_length;
2499 /* Queue the first TRB, even if it's zero-length */
2504 /* Don't change the cycle bit of the first TRB until later */
2508 field |= ep_ring->cycle_state;
2510 /* Chain all the TRBs together; clear the chain bit in the last
2511 * TRB to indicate it's the last TRB in the chain.
2516 /* FIXME - add check for ZERO_PACKET flag before this */
2517 td->last_trb = ep_ring->enqueue;
2520 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2522 length_field = TRB_LEN(trb_buff_len) |
2526 more_trbs_coming = true;
2528 more_trbs_coming = false;
2529 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2530 lower_32_bits(addr),
2531 upper_32_bits(addr),
2533 /* We always want to know if the TRB was short,
2534 * or we won't get an event when it completes.
2535 * (Unless we use event data TRBs, which are a
2536 * waste of space and HC resources.)
2538 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2540 running_total += trb_buff_len;
2542 /* Calculate length for next transfer */
2543 addr += trb_buff_len;
2544 trb_buff_len = urb->transfer_buffer_length - running_total;
2545 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2546 trb_buff_len = TRB_MAX_BUFF_SIZE;
2547 } while (running_total < urb->transfer_buffer_length);
2549 check_trb_math(urb, num_trbs, running_total);
2550 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2551 start_cycle, start_trb, td);
2555 /* Caller must have locked xhci->lock */
2556 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2557 struct urb *urb, int slot_id, unsigned int ep_index)
2559 struct xhci_ring *ep_ring;
2562 struct usb_ctrlrequest *setup;
2563 struct xhci_generic_trb *start_trb;
2565 u32 field, length_field;
2566 struct urb_priv *urb_priv;
2569 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2574 * Need to copy setup packet into setup TRB, so we can't use the setup
2577 if (!urb->setup_packet)
2580 if (!in_interrupt())
2581 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
2583 /* 1 TRB for setup, 1 for status */
2586 * Don't need to check if we need additional event data and normal TRBs,
2587 * since data in control transfers will never get bigger than 16MB
2588 * XXX: can we get a buffer that crosses 64KB boundaries?
2590 if (urb->transfer_buffer_length > 0)
2592 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2593 ep_index, urb->stream_id,
2594 num_trbs, urb, 0, mem_flags);
2598 urb_priv = urb->hcpriv;
2599 td = urb_priv->td[0];
2602 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2603 * until we've finished creating all the other TRBs. The ring's cycle
2604 * state may change as we enqueue the other TRBs, so save it too.
2606 start_trb = &ep_ring->enqueue->generic;
2607 start_cycle = ep_ring->cycle_state;
2609 /* Queue setup TRB - see section 6.4.1.2.1 */
2610 /* FIXME better way to translate setup_packet into two u32 fields? */
2611 setup = (struct usb_ctrlrequest *) urb->setup_packet;
2612 queue_trb(xhci, ep_ring, false, true,
2613 /* FIXME endianness is probably going to bite my ass here. */
2614 setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
2615 setup->wIndex | setup->wLength << 16,
2616 TRB_LEN(8) | TRB_INTR_TARGET(0),
2617 /* Immediate data in pointer */
2618 TRB_IDT | TRB_TYPE(TRB_SETUP));
2620 /* If there's data, queue data TRBs */
2622 length_field = TRB_LEN(urb->transfer_buffer_length) |
2623 xhci_td_remainder(urb->transfer_buffer_length) |
2625 if (urb->transfer_buffer_length > 0) {
2626 if (setup->bRequestType & USB_DIR_IN)
2627 field |= TRB_DIR_IN;
2628 queue_trb(xhci, ep_ring, false, true,
2629 lower_32_bits(urb->transfer_dma),
2630 upper_32_bits(urb->transfer_dma),
2632 /* Event on short tx */
2633 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
2636 /* Save the DMA address of the last TRB in the TD */
2637 td->last_trb = ep_ring->enqueue;
2639 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2640 /* If the device sent data, the status stage is an OUT transfer */
2641 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
2645 queue_trb(xhci, ep_ring, false, false,
2649 /* Event on completion */
2650 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
2652 giveback_first_trb(xhci, slot_id, ep_index, 0,
2653 start_cycle, start_trb, td);
2657 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
2658 struct urb *urb, int i)
2661 u64 addr, td_len, running_total;
2663 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
2664 td_len = urb->iso_frame_desc[i].length;
2666 running_total = TRB_MAX_BUFF_SIZE -
2667 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2668 if (running_total != 0)
2671 while (running_total < td_len) {
2673 running_total += TRB_MAX_BUFF_SIZE;
2679 /* This is for isoc transfer */
2680 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2681 struct urb *urb, int slot_id, unsigned int ep_index)
2683 struct xhci_ring *ep_ring;
2684 struct urb_priv *urb_priv;
2686 int num_tds, trbs_per_td;
2687 struct xhci_generic_trb *start_trb;
2690 u32 field, length_field;
2691 int running_total, trb_buff_len, td_len, td_remain_len, ret;
2692 u64 start_addr, addr;
2695 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
2697 num_tds = urb->number_of_packets;
2699 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
2703 if (!in_interrupt())
2704 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d),"
2705 " addr = %#llx, num_tds = %d\n",
2706 urb->ep->desc.bEndpointAddress,
2707 urb->transfer_buffer_length,
2708 urb->transfer_buffer_length,
2709 (unsigned long long)urb->transfer_dma,
2712 start_addr = (u64) urb->transfer_dma;
2713 start_trb = &ep_ring->enqueue->generic;
2714 start_cycle = ep_ring->cycle_state;
2716 /* Queue the first TRB, even if it's zero-length */
2717 for (i = 0; i < num_tds; i++) {
2721 addr = start_addr + urb->iso_frame_desc[i].offset;
2722 td_len = urb->iso_frame_desc[i].length;
2723 td_remain_len = td_len;
2725 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
2727 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
2728 urb->stream_id, trbs_per_td, urb, i, mem_flags);
2732 urb_priv = urb->hcpriv;
2733 td = urb_priv->td[i];
2735 for (j = 0; j < trbs_per_td; j++) {
2740 /* Queue the isoc TRB */
2741 field |= TRB_TYPE(TRB_ISOC);
2742 /* Assume URB_ISO_ASAP is set */
2745 field |= ep_ring->cycle_state;
2748 /* Queue other normal TRBs */
2749 field |= TRB_TYPE(TRB_NORMAL);
2750 field |= ep_ring->cycle_state;
2753 /* Chain all the TRBs together; clear the chain bit in
2754 * the last TRB to indicate it's the last TRB in the
2757 if (j < trbs_per_td - 1) {
2760 td->last_trb = ep_ring->enqueue;
2764 /* Calculate TRB length */
2765 trb_buff_len = TRB_MAX_BUFF_SIZE -
2766 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2767 if (trb_buff_len > td_remain_len)
2768 trb_buff_len = td_remain_len;
2770 remainder = xhci_td_remainder(td_len - running_total);
2771 length_field = TRB_LEN(trb_buff_len) |
2774 queue_trb(xhci, ep_ring, false, false,
2775 lower_32_bits(addr),
2776 upper_32_bits(addr),
2778 /* We always want to know if the TRB was short,
2779 * or we won't get an event when it completes.
2780 * (Unless we use event data TRBs, which are a
2781 * waste of space and HC resources.)
2784 running_total += trb_buff_len;
2786 addr += trb_buff_len;
2787 td_remain_len -= trb_buff_len;
2790 /* Check TD length */
2791 if (running_total != td_len) {
2792 xhci_err(xhci, "ISOC TD length unmatch\n");
2798 start_trb->field[3] |= start_cycle;
2800 ring_ep_doorbell(xhci, slot_id, ep_index, urb->stream_id);
2805 * Check transfer ring to guarantee there is enough room for the urb.
2806 * Update ISO URB start_frame and interval.
2807 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
2808 * update the urb->start_frame by now.
2809 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
2811 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2812 struct urb *urb, int slot_id, unsigned int ep_index)
2814 struct xhci_virt_device *xdev;
2815 struct xhci_ring *ep_ring;
2816 struct xhci_ep_ctx *ep_ctx;
2820 int num_tds, num_trbs, i;
2823 xdev = xhci->devs[slot_id];
2824 ep_ring = xdev->eps[ep_index].ring;
2825 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2828 num_tds = urb->number_of_packets;
2829 for (i = 0; i < num_tds; i++)
2830 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
2832 /* Check the ring to guarantee there is enough room for the whole urb.
2833 * Do not insert any td of the urb to the ring if the check failed.
2835 ret = prepare_ring(xhci, ep_ring, ep_ctx->ep_info & EP_STATE_MASK,
2836 num_trbs, mem_flags);
2840 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
2841 start_frame &= 0x3fff;
2843 urb->start_frame = start_frame;
2844 if (urb->dev->speed == USB_SPEED_LOW ||
2845 urb->dev->speed == USB_SPEED_FULL)
2846 urb->start_frame >>= 3;
2848 xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
2849 ep_interval = urb->interval;
2850 /* Convert to microframes */
2851 if (urb->dev->speed == USB_SPEED_LOW ||
2852 urb->dev->speed == USB_SPEED_FULL)
2854 /* FIXME change this to a warning and a suggestion to use the new API
2855 * to set the polling interval (once the API is added).
2857 if (xhci_interval != ep_interval) {
2858 if (!printk_ratelimit())
2859 dev_dbg(&urb->dev->dev, "Driver uses different interval"
2860 " (%d microframe%s) than xHCI "
2861 "(%d microframe%s)\n",
2863 ep_interval == 1 ? "" : "s",
2865 xhci_interval == 1 ? "" : "s");
2866 urb->interval = xhci_interval;
2867 /* Convert back to frames for LS/FS devices */
2868 if (urb->dev->speed == USB_SPEED_LOW ||
2869 urb->dev->speed == USB_SPEED_FULL)
2872 return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2875 /**** Command Ring Operations ****/
2877 /* Generic function for queueing a command TRB on the command ring.
2878 * Check to make sure there's room on the command ring for one command TRB.
2879 * Also check that there's room reserved for commands that must not fail.
2880 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
2881 * then only check for the number of reserved spots.
2882 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
2883 * because the command event handler may want to resubmit a failed command.
2885 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
2886 u32 field3, u32 field4, bool command_must_succeed)
2888 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
2891 if (!command_must_succeed)
2894 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
2895 reserved_trbs, GFP_ATOMIC);
2897 xhci_err(xhci, "ERR: No room for command on command ring\n");
2898 if (command_must_succeed)
2899 xhci_err(xhci, "ERR: Reserved TRB counting for "
2900 "unfailable commands failed.\n");
2903 queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
2904 field4 | xhci->cmd_ring->cycle_state);
2908 /* Queue a no-op command on the command ring */
2909 static int queue_cmd_noop(struct xhci_hcd *xhci)
2911 return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false);
2915 * Place a no-op command on the command ring to test the command and
2918 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
2920 if (queue_cmd_noop(xhci) < 0)
2922 xhci->noops_submitted++;
2923 return xhci_ring_cmd_db;
2926 /* Queue a slot enable or disable request on the command ring */
2927 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
2929 return queue_command(xhci, 0, 0, 0,
2930 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
2933 /* Queue an address device command TRB */
2934 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2937 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2938 upper_32_bits(in_ctx_ptr), 0,
2939 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
2943 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
2944 u32 field1, u32 field2, u32 field3, u32 field4)
2946 return queue_command(xhci, field1, field2, field3, field4, false);
2949 /* Queue a reset device command TRB */
2950 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
2952 return queue_command(xhci, 0, 0, 0,
2953 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
2957 /* Queue a configure endpoint command TRB */
2958 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2959 u32 slot_id, bool command_must_succeed)
2961 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2962 upper_32_bits(in_ctx_ptr), 0,
2963 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
2964 command_must_succeed);
2967 /* Queue an evaluate context command TRB */
2968 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2971 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2972 upper_32_bits(in_ctx_ptr), 0,
2973 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
2977 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
2978 unsigned int ep_index)
2980 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2981 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2982 u32 type = TRB_TYPE(TRB_STOP_RING);
2984 return queue_command(xhci, 0, 0, 0,
2985 trb_slot_id | trb_ep_index | type, false);
2988 /* Set Transfer Ring Dequeue Pointer command.
2989 * This should not be used for endpoints that have streams enabled.
2991 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
2992 unsigned int ep_index, unsigned int stream_id,
2993 struct xhci_segment *deq_seg,
2994 union xhci_trb *deq_ptr, u32 cycle_state)
2997 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2998 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2999 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3000 u32 type = TRB_TYPE(TRB_SET_DEQ);
3002 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3004 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3005 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3009 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3010 upper_32_bits(addr), trb_stream_id,
3011 trb_slot_id | trb_ep_index | type, false);
3014 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3015 unsigned int ep_index)
3017 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3018 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3019 u32 type = TRB_TYPE(TRB_RESET_EP);
3021 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,