2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72 struct xhci_virt_device *virt_dev,
73 struct xhci_event_cmd *event);
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
82 unsigned long segment_offset;
84 if (!seg || !trb || trb < seg->trbs)
87 segment_offset = trb - seg->trbs;
88 if (segment_offset > TRBS_PER_SEGMENT)
90 return seg->dma + (segment_offset * sizeof(*trb));
93 /* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
97 struct xhci_segment *seg, union xhci_trb *trb)
99 if (ring == xhci->event_ring)
100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101 (seg->next == xhci->event_ring->first_seg);
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
111 struct xhci_segment *seg, union xhci_trb *trb)
113 if (ring == xhci->event_ring)
114 return trb == &seg->trbs[TRBS_PER_SEGMENT];
116 return (le32_to_cpu(trb->link.control) & TRB_TYPE_BITMASK)
117 == TRB_TYPE(TRB_LINK);
120 static int enqueue_is_link_trb(struct xhci_ring *ring)
122 struct xhci_link_trb *link = &ring->enqueue->link;
123 return ((le32_to_cpu(link->control) & TRB_TYPE_BITMASK) ==
127 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
128 * TRB is in a new segment. This does not skip over link TRBs, and it does not
129 * effect the ring dequeue or enqueue pointers.
131 static void next_trb(struct xhci_hcd *xhci,
132 struct xhci_ring *ring,
133 struct xhci_segment **seg,
134 union xhci_trb **trb)
136 if (last_trb(xhci, ring, *seg, *trb)) {
138 *trb = ((*seg)->trbs);
145 * See Cycle bit rules. SW is the consumer for the event ring only.
146 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
148 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
150 unsigned long long addr;
156 * Update the dequeue pointer further if that was a link TRB or
157 * we're at the end of an event ring segment (which doesn't have
160 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
161 if (consumer && last_trb_on_last_seg(xhci, ring,
162 ring->deq_seg, ring->dequeue)) {
164 xhci_dbg(xhci, "Toggle cycle state "
165 "for ring %p = %i\n",
169 ring->cycle_state = (ring->cycle_state ? 0 : 1);
171 ring->deq_seg = ring->deq_seg->next;
172 ring->dequeue = ring->deq_seg->trbs;
176 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
178 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
182 * See Cycle bit rules. SW is the consumer for the event ring only.
183 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
185 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
186 * chain bit is set), then set the chain bit in all the following link TRBs.
187 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
188 * have their chain bit cleared (so that each Link TRB is a separate TD).
190 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
191 * set, but other sections talk about dealing with the chain bit set. This was
192 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
193 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
195 * @more_trbs_coming: Will you enqueue more TRBs before calling
196 * prepare_transfer()?
198 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
199 bool consumer, bool more_trbs_coming, bool isoc)
202 union xhci_trb *next;
203 unsigned long long addr;
205 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
206 next = ++(ring->enqueue);
209 /* Update the dequeue pointer further if that was a link TRB or we're at
210 * the end of an event ring segment (which doesn't have link TRBS)
212 while (last_trb(xhci, ring, ring->enq_seg, next)) {
214 if (ring != xhci->event_ring) {
216 * If the caller doesn't plan on enqueueing more
217 * TDs before ringing the doorbell, then we
218 * don't want to give the link TRB to the
219 * hardware just yet. We'll give the link TRB
220 * back in prepare_ring() just before we enqueue
221 * the TD at the top of the ring.
223 if (!chain && !more_trbs_coming)
226 /* If we're not dealing with 0.95 hardware or
227 * isoc rings on AMD 0.96 host,
228 * carry over the chain bit of the previous TRB
229 * (which may mean the chain bit is cleared).
231 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
232 && !xhci_link_trb_quirk(xhci)) {
233 next->link.control &=
234 cpu_to_le32(~TRB_CHAIN);
235 next->link.control |=
238 /* Give this link TRB to the hardware */
240 next->link.control ^= cpu_to_le32(TRB_CYCLE);
242 /* Toggle the cycle bit after the last ring segment. */
243 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
244 ring->cycle_state = (ring->cycle_state ? 0 : 1);
246 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
248 (unsigned int) ring->cycle_state);
251 ring->enq_seg = ring->enq_seg->next;
252 ring->enqueue = ring->enq_seg->trbs;
253 next = ring->enqueue;
255 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
259 * Check to see if there's room to enqueue num_trbs on the ring. See rules
261 * FIXME: this would be simpler and faster if we just kept track of the number
262 * of free TRBs in a ring.
264 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
265 unsigned int num_trbs)
268 union xhci_trb *enq = ring->enqueue;
269 struct xhci_segment *enq_seg = ring->enq_seg;
270 struct xhci_segment *cur_seg;
271 unsigned int left_on_ring;
273 /* If we are currently pointing to a link TRB, advance the
274 * enqueue pointer before checking for space */
275 while (last_trb(xhci, ring, enq_seg, enq)) {
276 enq_seg = enq_seg->next;
280 /* Check if ring is empty */
281 if (enq == ring->dequeue) {
282 /* Can't use link trbs */
283 left_on_ring = TRBS_PER_SEGMENT - 1;
284 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
285 cur_seg = cur_seg->next)
286 left_on_ring += TRBS_PER_SEGMENT - 1;
288 /* Always need one TRB free in the ring. */
290 if (num_trbs > left_on_ring) {
291 xhci_warn(xhci, "Not enough room on ring; "
292 "need %u TRBs, %u TRBs left\n",
293 num_trbs, left_on_ring);
298 /* Make sure there's an extra empty TRB available */
299 for (i = 0; i <= num_trbs; ++i) {
300 if (enq == ring->dequeue)
303 while (last_trb(xhci, ring, enq_seg, enq)) {
304 enq_seg = enq_seg->next;
311 /* Ring the host controller doorbell after placing a command on the ring */
312 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
314 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
317 xhci_dbg(xhci, "// Ding dong!\n");
318 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
319 /* Flush PCI posted writes */
320 xhci_readl(xhci, &xhci->dba->doorbell[0]);
323 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
328 xhci_dbg(xhci, "Abort command ring\n");
330 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
331 xhci_dbg(xhci, "The command ring isn't running, "
332 "Have the command ring been stopped?\n");
336 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
337 if (!(temp_64 & CMD_RING_RUNNING)) {
338 xhci_dbg(xhci, "Command ring had been stopped\n");
341 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
342 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
343 &xhci->op_regs->cmd_ring);
345 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
346 * time the completion od all xHCI commands, including
347 * the Command Abort operation. If software doesn't see
348 * CRR negated in a timely manner (e.g. longer than 5
349 * seconds), then it should assume that the there are
350 * larger problems with the xHC and assert HCRST.
352 ret = handshake(xhci, &xhci->op_regs->cmd_ring,
353 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
355 xhci_err(xhci, "Stopped the command ring failed, "
356 "maybe the host is dead\n");
357 xhci->xhc_state |= XHCI_STATE_DYING;
366 static int xhci_queue_cd(struct xhci_hcd *xhci,
367 struct xhci_command *command,
368 union xhci_trb *cmd_trb)
371 cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
374 INIT_LIST_HEAD(&cd->cancel_cmd_list);
376 cd->command = command;
377 cd->cmd_trb = cmd_trb;
378 list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
384 * Cancel the command which has issue.
386 * Some commands may hang due to waiting for acknowledgement from
387 * usb device. It is outside of the xHC's ability to control and
388 * will cause the command ring is blocked. When it occurs software
389 * should intervene to recover the command ring.
390 * See Section 4.6.1.1 and 4.6.1.2
392 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
393 union xhci_trb *cmd_trb)
398 spin_lock_irqsave(&xhci->lock, flags);
400 if (xhci->xhc_state & XHCI_STATE_DYING) {
401 xhci_warn(xhci, "Abort the command ring,"
402 " but the xHCI is dead.\n");
407 /* queue the cmd desriptor to cancel_cmd_list */
408 retval = xhci_queue_cd(xhci, command, cmd_trb);
410 xhci_warn(xhci, "Queuing command descriptor failed.\n");
414 /* abort command ring */
415 retval = xhci_abort_cmd_ring(xhci);
417 xhci_err(xhci, "Abort command ring failed\n");
418 if (unlikely(retval == -ESHUTDOWN)) {
419 spin_unlock_irqrestore(&xhci->lock, flags);
420 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
421 xhci_dbg(xhci, "xHCI host controller is dead.\n");
427 spin_unlock_irqrestore(&xhci->lock, flags);
431 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
432 unsigned int slot_id,
433 unsigned int ep_index,
434 unsigned int stream_id)
436 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
437 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
438 unsigned int ep_state = ep->ep_state;
440 /* Don't ring the doorbell for this endpoint if there are pending
441 * cancellations because we don't want to interrupt processing.
442 * We don't want to restart any stream rings if there's a set dequeue
443 * pointer command pending because the device can choose to start any
444 * stream once the endpoint is on the HW schedule.
445 * FIXME - check all the stream rings for pending cancellations.
447 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
448 (ep_state & EP_HALTED))
450 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
451 /* The CPU has better things to do at this point than wait for a
452 * write-posting flush. It'll get there soon enough.
456 /* Ring the doorbell for any rings with pending URBs */
457 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
458 unsigned int slot_id,
459 unsigned int ep_index)
461 unsigned int stream_id;
462 struct xhci_virt_ep *ep;
464 ep = &xhci->devs[slot_id]->eps[ep_index];
466 /* A ring has pending URBs if its TD list is not empty */
467 if (!(ep->ep_state & EP_HAS_STREAMS)) {
468 if (!(list_empty(&ep->ring->td_list)))
469 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
473 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
475 struct xhci_stream_info *stream_info = ep->stream_info;
476 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
477 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
483 * Find the segment that trb is in. Start searching in start_seg.
484 * If we must move past a segment that has a link TRB with a toggle cycle state
485 * bit set, then we will toggle the value pointed at by cycle_state.
487 static struct xhci_segment *find_trb_seg(
488 struct xhci_segment *start_seg,
489 union xhci_trb *trb, int *cycle_state)
491 struct xhci_segment *cur_seg = start_seg;
492 struct xhci_generic_trb *generic_trb;
494 while (cur_seg->trbs > trb ||
495 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
496 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
497 if (le32_to_cpu(generic_trb->field[3]) & LINK_TOGGLE)
499 cur_seg = cur_seg->next;
500 if (cur_seg == start_seg)
501 /* Looped over the entire list. Oops! */
508 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
509 unsigned int slot_id, unsigned int ep_index,
510 unsigned int stream_id)
512 struct xhci_virt_ep *ep;
514 ep = &xhci->devs[slot_id]->eps[ep_index];
515 /* Common case: no streams */
516 if (!(ep->ep_state & EP_HAS_STREAMS))
519 if (stream_id == 0) {
521 "WARN: Slot ID %u, ep index %u has streams, "
522 "but URB has no stream ID.\n",
527 if (stream_id < ep->stream_info->num_streams)
528 return ep->stream_info->stream_rings[stream_id];
531 "WARN: Slot ID %u, ep index %u has "
532 "stream IDs 1 to %u allocated, "
533 "but stream ID %u is requested.\n",
535 ep->stream_info->num_streams - 1,
540 /* Get the right ring for the given URB.
541 * If the endpoint supports streams, boundary check the URB's stream ID.
542 * If the endpoint doesn't support streams, return the singular endpoint ring.
544 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
547 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
548 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
552 * Move the xHC's endpoint ring dequeue pointer past cur_td.
553 * Record the new state of the xHC's endpoint ring dequeue segment,
554 * dequeue pointer, and new consumer cycle state in state.
555 * Update our internal representation of the ring's dequeue pointer.
557 * We do this in three jumps:
558 * - First we update our new ring state to be the same as when the xHC stopped.
559 * - Then we traverse the ring to find the segment that contains
560 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
561 * any link TRBs with the toggle cycle bit set.
562 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
563 * if we've moved it past a link TRB with the toggle cycle bit set.
565 * Some of the uses of xhci_generic_trb are grotty, but if they're done
566 * with correct __le32 accesses they should work fine. Only users of this are
569 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
570 unsigned int slot_id, unsigned int ep_index,
571 unsigned int stream_id, struct xhci_td *cur_td,
572 struct xhci_dequeue_state *state)
574 struct xhci_virt_device *dev = xhci->devs[slot_id];
575 struct xhci_ring *ep_ring;
576 struct xhci_generic_trb *trb;
577 struct xhci_ep_ctx *ep_ctx;
580 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
581 ep_index, stream_id);
583 xhci_warn(xhci, "WARN can't find new dequeue state "
584 "for invalid stream ID %u.\n",
588 state->new_cycle_state = 0;
589 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
590 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
591 dev->eps[ep_index].stopped_trb,
592 &state->new_cycle_state);
593 if (!state->new_deq_seg) {
598 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
599 xhci_dbg(xhci, "Finding endpoint context\n");
600 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
601 state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
603 state->new_deq_ptr = cur_td->last_trb;
604 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
605 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
607 &state->new_cycle_state);
608 if (!state->new_deq_seg) {
613 trb = &state->new_deq_ptr->generic;
614 if ((le32_to_cpu(trb->field[3]) & TRB_TYPE_BITMASK) ==
615 TRB_TYPE(TRB_LINK) && (le32_to_cpu(trb->field[3]) & LINK_TOGGLE))
616 state->new_cycle_state ^= 0x1;
617 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
620 * If there is only one segment in a ring, find_trb_seg()'s while loop
621 * will not run, and it will return before it has a chance to see if it
622 * needs to toggle the cycle bit. It can't tell if the stalled transfer
623 * ended just before the link TRB on a one-segment ring, or if the TD
624 * wrapped around the top of the ring, because it doesn't have the TD in
625 * question. Look for the one-segment case where stalled TRB's address
626 * is greater than the new dequeue pointer address.
628 if (ep_ring->first_seg == ep_ring->first_seg->next &&
629 state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
630 state->new_cycle_state ^= 0x1;
631 xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
633 /* Don't update the ring cycle state for the producer (us). */
634 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
636 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
637 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
638 (unsigned long long) addr);
641 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
642 * (The last TRB actually points to the ring enqueue pointer, which is not part
643 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
645 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
646 struct xhci_td *cur_td, bool flip_cycle)
648 struct xhci_segment *cur_seg;
649 union xhci_trb *cur_trb;
651 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
653 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
654 if ((le32_to_cpu(cur_trb->generic.field[3]) & TRB_TYPE_BITMASK)
655 == TRB_TYPE(TRB_LINK)) {
656 /* Unchain any chained Link TRBs, but
657 * leave the pointers intact.
659 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
660 /* Flip the cycle bit (link TRBs can't be the first
664 cur_trb->generic.field[3] ^=
665 cpu_to_le32(TRB_CYCLE);
666 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
667 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
668 "in seg %p (0x%llx dma)\n",
670 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
672 (unsigned long long)cur_seg->dma);
674 cur_trb->generic.field[0] = 0;
675 cur_trb->generic.field[1] = 0;
676 cur_trb->generic.field[2] = 0;
677 /* Preserve only the cycle bit of this TRB */
678 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
679 /* Flip the cycle bit except on the first or last TRB */
680 if (flip_cycle && cur_trb != cur_td->first_trb &&
681 cur_trb != cur_td->last_trb)
682 cur_trb->generic.field[3] ^=
683 cpu_to_le32(TRB_CYCLE);
684 cur_trb->generic.field[3] |= cpu_to_le32(
685 TRB_TYPE(TRB_TR_NOOP));
686 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
687 "in seg %p (0x%llx dma)\n",
689 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
691 (unsigned long long)cur_seg->dma);
693 if (cur_trb == cur_td->last_trb)
698 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
699 unsigned int ep_index, unsigned int stream_id,
700 struct xhci_segment *deq_seg,
701 union xhci_trb *deq_ptr, u32 cycle_state);
703 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
704 unsigned int slot_id, unsigned int ep_index,
705 unsigned int stream_id,
706 struct xhci_dequeue_state *deq_state)
708 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
710 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
711 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
712 deq_state->new_deq_seg,
713 (unsigned long long)deq_state->new_deq_seg->dma,
714 deq_state->new_deq_ptr,
715 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
716 deq_state->new_cycle_state);
717 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
718 deq_state->new_deq_seg,
719 deq_state->new_deq_ptr,
720 (u32) deq_state->new_cycle_state);
721 /* Stop the TD queueing code from ringing the doorbell until
722 * this command completes. The HC won't set the dequeue pointer
723 * if the ring is running, and ringing the doorbell starts the
726 ep->ep_state |= SET_DEQ_PENDING;
729 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
730 struct xhci_virt_ep *ep)
732 ep->ep_state &= ~EP_HALT_PENDING;
733 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
734 * timer is running on another CPU, we don't decrement stop_cmds_pending
735 * (since we didn't successfully stop the watchdog timer).
737 if (del_timer(&ep->stop_cmd_timer))
738 ep->stop_cmds_pending--;
741 /* Must be called with xhci->lock held in interrupt context */
742 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
743 struct xhci_td *cur_td, int status, char *adjective)
747 struct urb_priv *urb_priv;
750 urb_priv = urb->hcpriv;
752 hcd = bus_to_hcd(urb->dev->bus);
754 /* Only giveback urb when this is the last td in urb */
755 if (urb_priv->td_cnt == urb_priv->length) {
756 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
757 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
758 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
759 if (xhci->quirks & XHCI_AMD_PLL_FIX)
760 usb_amd_quirk_pll_enable();
763 usb_hcd_unlink_urb_from_ep(hcd, urb);
765 spin_unlock(&xhci->lock);
766 usb_hcd_giveback_urb(hcd, urb, status);
767 xhci_urb_free_priv(xhci, urb_priv);
768 spin_lock(&xhci->lock);
773 * When we get a command completion for a Stop Endpoint Command, we need to
774 * unlink any cancelled TDs from the ring. There are two ways to do that:
776 * 1. If the HW was in the middle of processing the TD that needs to be
777 * cancelled, then we must move the ring's dequeue pointer past the last TRB
778 * in the TD with a Set Dequeue Pointer Command.
779 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
780 * bit cleared) so that the HW will skip over them.
782 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
783 union xhci_trb *trb, struct xhci_event_cmd *event)
785 unsigned int slot_id;
786 unsigned int ep_index;
787 struct xhci_virt_device *virt_dev;
788 struct xhci_ring *ep_ring;
789 struct xhci_virt_ep *ep;
790 struct list_head *entry;
791 struct xhci_td *cur_td = NULL;
792 struct xhci_td *last_unlinked_td;
794 struct xhci_dequeue_state deq_state;
796 if (unlikely(TRB_TO_SUSPEND_PORT(
797 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
798 slot_id = TRB_TO_SLOT_ID(
799 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
800 virt_dev = xhci->devs[slot_id];
802 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
805 xhci_warn(xhci, "Stop endpoint command "
806 "completion for disabled slot %u\n",
811 memset(&deq_state, 0, sizeof(deq_state));
812 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
813 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
814 ep = &xhci->devs[slot_id]->eps[ep_index];
816 if (list_empty(&ep->cancelled_td_list)) {
817 xhci_stop_watchdog_timer_in_irq(xhci, ep);
818 ep->stopped_td = NULL;
819 ep->stopped_trb = NULL;
820 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
824 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
825 * We have the xHCI lock, so nothing can modify this list until we drop
826 * it. We're also in the event handler, so we can't get re-interrupted
827 * if another Stop Endpoint command completes
829 list_for_each(entry, &ep->cancelled_td_list) {
830 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
831 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
833 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
834 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
836 /* This shouldn't happen unless a driver is mucking
837 * with the stream ID after submission. This will
838 * leave the TD on the hardware ring, and the hardware
839 * will try to execute it, and may access a buffer
840 * that has already been freed. In the best case, the
841 * hardware will execute it, and the event handler will
842 * ignore the completion event for that TD, since it was
843 * removed from the td_list for that endpoint. In
844 * short, don't muck with the stream ID after
847 xhci_warn(xhci, "WARN Cancelled URB %p "
848 "has invalid stream ID %u.\n",
850 cur_td->urb->stream_id);
851 goto remove_finished_td;
854 * If we stopped on the TD we need to cancel, then we have to
855 * move the xHC endpoint ring dequeue pointer past this TD.
857 if (cur_td == ep->stopped_td)
858 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
859 cur_td->urb->stream_id,
862 td_to_noop(xhci, ep_ring, cur_td, false);
865 * The event handler won't see a completion for this TD anymore,
866 * so remove it from the endpoint ring's TD list. Keep it in
867 * the cancelled TD list for URB completion later.
869 list_del_init(&cur_td->td_list);
871 last_unlinked_td = cur_td;
872 xhci_stop_watchdog_timer_in_irq(xhci, ep);
874 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
875 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
876 xhci_queue_new_dequeue_state(xhci,
878 ep->stopped_td->urb->stream_id,
880 xhci_ring_cmd_db(xhci);
882 /* Otherwise ring the doorbell(s) to restart queued transfers */
883 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
885 ep->stopped_td = NULL;
886 ep->stopped_trb = NULL;
889 * Drop the lock and complete the URBs in the cancelled TD list.
890 * New TDs to be cancelled might be added to the end of the list before
891 * we can complete all the URBs for the TDs we already unlinked.
892 * So stop when we've completed the URB for the last TD we unlinked.
895 cur_td = list_entry(ep->cancelled_td_list.next,
896 struct xhci_td, cancelled_td_list);
897 list_del_init(&cur_td->cancelled_td_list);
899 /* Clean up the cancelled URB */
900 /* Doesn't matter what we pass for status, since the core will
901 * just overwrite it (because the URB has been unlinked).
903 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
905 /* Stop processing the cancelled list if the watchdog timer is
908 if (xhci->xhc_state & XHCI_STATE_DYING)
910 } while (cur_td != last_unlinked_td);
912 /* Return to the event handler with xhci->lock re-acquired */
915 /* Watchdog timer function for when a stop endpoint command fails to complete.
916 * In this case, we assume the host controller is broken or dying or dead. The
917 * host may still be completing some other events, so we have to be careful to
918 * let the event ring handler and the URB dequeueing/enqueueing functions know
919 * through xhci->state.
921 * The timer may also fire if the host takes a very long time to respond to the
922 * command, and the stop endpoint command completion handler cannot delete the
923 * timer before the timer function is called. Another endpoint cancellation may
924 * sneak in before the timer function can grab the lock, and that may queue
925 * another stop endpoint command and add the timer back. So we cannot use a
926 * simple flag to say whether there is a pending stop endpoint command for a
927 * particular endpoint.
929 * Instead we use a combination of that flag and a counter for the number of
930 * pending stop endpoint commands. If the timer is the tail end of the last
931 * stop endpoint command, and the endpoint's command is still pending, we assume
934 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
936 struct xhci_hcd *xhci;
937 struct xhci_virt_ep *ep;
938 struct xhci_virt_ep *temp_ep;
939 struct xhci_ring *ring;
940 struct xhci_td *cur_td;
944 ep = (struct xhci_virt_ep *) arg;
947 spin_lock_irqsave(&xhci->lock, flags);
949 ep->stop_cmds_pending--;
950 if (xhci->xhc_state & XHCI_STATE_DYING) {
951 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
952 "xHCI as DYING, exiting.\n");
953 spin_unlock_irqrestore(&xhci->lock, flags);
956 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
957 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
959 spin_unlock_irqrestore(&xhci->lock, flags);
963 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
964 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
965 /* Oops, HC is dead or dying or at least not responding to the stop
968 xhci->xhc_state |= XHCI_STATE_DYING;
969 /* Disable interrupts from the host controller and start halting it */
971 spin_unlock_irqrestore(&xhci->lock, flags);
973 ret = xhci_halt(xhci);
975 spin_lock_irqsave(&xhci->lock, flags);
977 /* This is bad; the host is not responding to commands and it's
978 * not allowing itself to be halted. At least interrupts are
979 * disabled. If we call usb_hc_died(), it will attempt to
980 * disconnect all device drivers under this host. Those
981 * disconnect() methods will wait for all URBs to be unlinked,
982 * so we must complete them.
984 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
985 xhci_warn(xhci, "Completing active URBs anyway.\n");
986 /* We could turn all TDs on the rings to no-ops. This won't
987 * help if the host has cached part of the ring, and is slow if
988 * we want to preserve the cycle bit. Skip it and hope the host
989 * doesn't touch the memory.
992 for (i = 0; i < MAX_HC_SLOTS; i++) {
995 for (j = 0; j < 31; j++) {
996 temp_ep = &xhci->devs[i]->eps[j];
997 ring = temp_ep->ring;
1000 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
1001 "ep index %u\n", i, j);
1002 while (!list_empty(&ring->td_list)) {
1003 cur_td = list_first_entry(&ring->td_list,
1006 list_del_init(&cur_td->td_list);
1007 if (!list_empty(&cur_td->cancelled_td_list))
1008 list_del_init(&cur_td->cancelled_td_list);
1009 xhci_giveback_urb_in_irq(xhci, cur_td,
1010 -ESHUTDOWN, "killed");
1012 while (!list_empty(&temp_ep->cancelled_td_list)) {
1013 cur_td = list_first_entry(
1014 &temp_ep->cancelled_td_list,
1017 list_del_init(&cur_td->cancelled_td_list);
1018 xhci_giveback_urb_in_irq(xhci, cur_td,
1019 -ESHUTDOWN, "killed");
1023 spin_unlock_irqrestore(&xhci->lock, flags);
1024 xhci_dbg(xhci, "Calling usb_hc_died()\n");
1025 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1026 xhci_dbg(xhci, "xHCI host controller is dead.\n");
1030 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1031 * we need to clear the set deq pending flag in the endpoint ring state, so that
1032 * the TD queueing code can ring the doorbell again. We also need to ring the
1033 * endpoint doorbell to restart the ring, but only if there aren't more
1034 * cancellations pending.
1036 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1037 struct xhci_event_cmd *event,
1038 union xhci_trb *trb)
1040 unsigned int slot_id;
1041 unsigned int ep_index;
1042 unsigned int stream_id;
1043 struct xhci_ring *ep_ring;
1044 struct xhci_virt_device *dev;
1045 struct xhci_ep_ctx *ep_ctx;
1046 struct xhci_slot_ctx *slot_ctx;
1048 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1049 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1050 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1051 dev = xhci->devs[slot_id];
1053 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1055 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1056 "freed stream ID %u\n",
1058 /* XXX: Harmless??? */
1059 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1063 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1064 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1066 if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1067 unsigned int ep_state;
1068 unsigned int slot_state;
1070 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1072 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1073 "of stream ID configuration\n");
1075 case COMP_CTX_STATE:
1076 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1077 "to incorrect slot or ep state.\n");
1078 ep_state = le32_to_cpu(ep_ctx->ep_info);
1079 ep_state &= EP_STATE_MASK;
1080 slot_state = le32_to_cpu(slot_ctx->dev_state);
1081 slot_state = GET_SLOT_STATE(slot_state);
1082 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1083 slot_state, ep_state);
1086 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1087 "slot %u was not enabled.\n", slot_id);
1090 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1091 "completion code of %u.\n",
1092 GET_COMP_CODE(le32_to_cpu(event->status)));
1095 /* OK what do we do now? The endpoint state is hosed, and we
1096 * should never get to this point if the synchronization between
1097 * queueing, and endpoint state are correct. This might happen
1098 * if the device gets disconnected after we've finished
1099 * cancelling URBs, which might not be an error...
1102 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1103 le64_to_cpu(ep_ctx->deq));
1104 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1105 dev->eps[ep_index].queued_deq_ptr) ==
1106 (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1107 /* Update the ring's dequeue segment and dequeue pointer
1108 * to reflect the new position.
1110 ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
1111 ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
1113 xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1114 "Ptr command & xHCI internal state.\n");
1115 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1116 dev->eps[ep_index].queued_deq_seg,
1117 dev->eps[ep_index].queued_deq_ptr);
1121 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1122 dev->eps[ep_index].queued_deq_seg = NULL;
1123 dev->eps[ep_index].queued_deq_ptr = NULL;
1124 /* Restart any rings with pending URBs */
1125 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1128 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1129 struct xhci_event_cmd *event,
1130 union xhci_trb *trb)
1133 unsigned int ep_index;
1135 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1136 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1137 /* This command will only fail if the endpoint wasn't halted,
1138 * but we don't care.
1140 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1141 (unsigned int) GET_COMP_CODE(le32_to_cpu(event->status)));
1143 /* HW with the reset endpoint quirk needs to have a configure endpoint
1144 * command complete before the endpoint can be used. Queue that here
1145 * because the HW can't handle two commands being queued in a row.
1147 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1148 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1149 xhci_queue_configure_endpoint(xhci,
1150 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1152 xhci_ring_cmd_db(xhci);
1154 /* Clear our internal halted state and restart the ring(s) */
1155 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1156 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1160 /* Complete the command and detele it from the devcie's command queue.
1162 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1163 struct xhci_command *command, u32 status)
1165 command->status = status;
1166 list_del(&command->cmd_list);
1167 if (command->completion)
1168 complete(command->completion);
1170 xhci_free_command(xhci, command);
1174 /* Check to see if a command in the device's command queue matches this one.
1175 * Signal the completion or free the command, and return 1. Return 0 if the
1176 * completed command isn't at the head of the command list.
1178 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1179 struct xhci_virt_device *virt_dev,
1180 struct xhci_event_cmd *event)
1182 struct xhci_command *command;
1184 if (list_empty(&virt_dev->cmd_list))
1187 command = list_entry(virt_dev->cmd_list.next,
1188 struct xhci_command, cmd_list);
1189 if (xhci->cmd_ring->dequeue != command->command_trb)
1192 xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1193 GET_COMP_CODE(le32_to_cpu(event->status)));
1198 * Finding the command trb need to be cancelled and modifying it to
1199 * NO OP command. And if the command is in device's command wait
1200 * list, finishing and freeing it.
1202 * If we can't find the command trb, we think it had already been
1205 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1207 struct xhci_segment *cur_seg;
1208 union xhci_trb *cmd_trb;
1211 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1214 /* find the current segment of command ring */
1215 cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1216 xhci->cmd_ring->dequeue, &cycle_state);
1219 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1220 xhci->cmd_ring->dequeue,
1221 (unsigned long long)
1222 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1223 xhci->cmd_ring->dequeue));
1224 xhci_debug_ring(xhci, xhci->cmd_ring);
1225 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1229 /* find the command trb matched by cd from command ring */
1230 for (cmd_trb = xhci->cmd_ring->dequeue;
1231 cmd_trb != xhci->cmd_ring->enqueue;
1232 next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1233 /* If the trb is link trb, continue */
1234 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1237 if (cur_cd->cmd_trb == cmd_trb) {
1239 /* If the command in device's command list, we should
1240 * finish it and free the command structure.
1242 if (cur_cd->command)
1243 xhci_complete_cmd_in_cmd_wait_list(xhci,
1244 cur_cd->command, COMP_CMD_STOP);
1246 /* get cycle state from the origin command trb */
1247 cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1250 /* modify the command trb to NO OP command */
1251 cmd_trb->generic.field[0] = 0;
1252 cmd_trb->generic.field[1] = 0;
1253 cmd_trb->generic.field[2] = 0;
1254 cmd_trb->generic.field[3] = cpu_to_le32(
1255 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1261 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1263 struct xhci_cd *cur_cd, *next_cd;
1265 if (list_empty(&xhci->cancel_cmd_list))
1268 list_for_each_entry_safe(cur_cd, next_cd,
1269 &xhci->cancel_cmd_list, cancel_cmd_list) {
1270 xhci_cmd_to_noop(xhci, cur_cd);
1271 list_del(&cur_cd->cancel_cmd_list);
1277 * traversing the cancel_cmd_list. If the command descriptor according
1278 * to cmd_trb is found, the function free it and return 1, otherwise
1281 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1282 union xhci_trb *cmd_trb)
1284 struct xhci_cd *cur_cd, *next_cd;
1286 if (list_empty(&xhci->cancel_cmd_list))
1289 list_for_each_entry_safe(cur_cd, next_cd,
1290 &xhci->cancel_cmd_list, cancel_cmd_list) {
1291 if (cur_cd->cmd_trb == cmd_trb) {
1292 if (cur_cd->command)
1293 xhci_complete_cmd_in_cmd_wait_list(xhci,
1294 cur_cd->command, COMP_CMD_STOP);
1295 list_del(&cur_cd->cancel_cmd_list);
1305 * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1306 * trb pointed by the command ring dequeue pointer is the trb we want to
1307 * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1308 * traverse the cancel_cmd_list to trun the all of the commands according
1309 * to command descriptor to NO-OP trb.
1311 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1312 int cmd_trb_comp_code)
1314 int cur_trb_is_good = 0;
1316 /* Searching the cmd trb pointed by the command ring dequeue
1317 * pointer in command descriptor list. If it is found, free it.
1319 cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1320 xhci->cmd_ring->dequeue);
1322 if (cmd_trb_comp_code == COMP_CMD_ABORT)
1323 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1324 else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1325 /* traversing the cancel_cmd_list and canceling
1326 * the command according to command descriptor
1328 xhci_cancel_cmd_in_cd_list(xhci);
1330 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1332 * ring command ring doorbell again to restart the
1335 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1336 xhci_ring_cmd_db(xhci);
1338 return cur_trb_is_good;
1341 static void handle_cmd_completion(struct xhci_hcd *xhci,
1342 struct xhci_event_cmd *event)
1344 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1346 dma_addr_t cmd_dequeue_dma;
1347 struct xhci_input_control_ctx *ctrl_ctx;
1348 struct xhci_virt_device *virt_dev;
1349 unsigned int ep_index;
1350 struct xhci_ring *ep_ring;
1351 unsigned int ep_state;
1353 cmd_dma = le64_to_cpu(event->cmd_trb);
1354 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1355 xhci->cmd_ring->dequeue);
1356 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1357 if (cmd_dequeue_dma == 0) {
1358 xhci->error_bitmask |= 1 << 4;
1361 /* Does the DMA address match our internal dequeue pointer address? */
1362 if (cmd_dma != (u64) cmd_dequeue_dma) {
1363 xhci->error_bitmask |= 1 << 5;
1367 if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1368 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1369 /* If the return value is 0, we think the trb pointed by
1370 * command ring dequeue pointer is a good trb. The good
1371 * trb means we don't want to cancel the trb, but it have
1372 * been stopped by host. So we should handle it normally.
1373 * Otherwise, driver should invoke inc_deq() and return.
1375 if (handle_stopped_cmd_ring(xhci,
1376 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1377 inc_deq(xhci, xhci->cmd_ring, false);
1382 switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1383 & TRB_TYPE_BITMASK) {
1384 case TRB_TYPE(TRB_ENABLE_SLOT):
1385 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1386 xhci->slot_id = slot_id;
1389 complete(&xhci->addr_dev);
1391 case TRB_TYPE(TRB_DISABLE_SLOT):
1392 if (xhci->devs[slot_id]) {
1393 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1394 /* Delete default control endpoint resources */
1395 xhci_free_device_endpoint_resources(xhci,
1396 xhci->devs[slot_id], true);
1397 xhci_free_virt_device(xhci, slot_id);
1400 case TRB_TYPE(TRB_CONFIG_EP):
1401 virt_dev = xhci->devs[slot_id];
1402 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1405 * Configure endpoint commands can come from the USB core
1406 * configuration or alt setting changes, or because the HW
1407 * needed an extra configure endpoint command after a reset
1408 * endpoint command or streams were being configured.
1409 * If the command was for a halted endpoint, the xHCI driver
1410 * is not waiting on the configure endpoint command.
1412 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1414 /* Input ctx add_flags are the endpoint index plus one */
1415 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1416 /* A usb_set_interface() call directly after clearing a halted
1417 * condition may race on this quirky hardware. Not worth
1418 * worrying about, since this is prototype hardware. Not sure
1419 * if this will work for streams, but streams support was
1420 * untested on this prototype.
1422 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1423 ep_index != (unsigned int) -1 &&
1424 le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1425 le32_to_cpu(ctrl_ctx->drop_flags)) {
1426 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1427 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1428 if (!(ep_state & EP_HALTED))
1429 goto bandwidth_change;
1430 xhci_dbg(xhci, "Completed config ep cmd - "
1431 "last ep index = %d, state = %d\n",
1432 ep_index, ep_state);
1433 /* Clear internal halted state and restart ring(s) */
1434 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1436 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1440 xhci_dbg(xhci, "Completed config ep cmd\n");
1441 xhci->devs[slot_id]->cmd_status =
1442 GET_COMP_CODE(le32_to_cpu(event->status));
1443 complete(&xhci->devs[slot_id]->cmd_completion);
1445 case TRB_TYPE(TRB_EVAL_CONTEXT):
1446 virt_dev = xhci->devs[slot_id];
1447 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1449 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1450 complete(&xhci->devs[slot_id]->cmd_completion);
1452 case TRB_TYPE(TRB_ADDR_DEV):
1453 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1454 complete(&xhci->addr_dev);
1456 case TRB_TYPE(TRB_STOP_RING):
1457 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1459 case TRB_TYPE(TRB_SET_DEQ):
1460 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1462 case TRB_TYPE(TRB_CMD_NOOP):
1464 case TRB_TYPE(TRB_RESET_EP):
1465 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1467 case TRB_TYPE(TRB_RESET_DEV):
1468 xhci_dbg(xhci, "Completed reset device command.\n");
1469 slot_id = TRB_TO_SLOT_ID(
1470 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1471 virt_dev = xhci->devs[slot_id];
1473 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1475 xhci_warn(xhci, "Reset device command completion "
1476 "for disabled slot %u\n", slot_id);
1478 case TRB_TYPE(TRB_NEC_GET_FW):
1479 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1480 xhci->error_bitmask |= 1 << 6;
1483 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1484 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1485 NEC_FW_MINOR(le32_to_cpu(event->status)));
1488 /* Skip over unknown commands on the event ring */
1489 xhci->error_bitmask |= 1 << 6;
1492 inc_deq(xhci, xhci->cmd_ring, false);
1495 static void handle_vendor_event(struct xhci_hcd *xhci,
1496 union xhci_trb *event)
1500 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1501 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1502 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1503 handle_cmd_completion(xhci, &event->event_cmd);
1506 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1507 * port registers -- USB 3.0 and USB 2.0).
1509 * Returns a zero-based port number, which is suitable for indexing into each of
1510 * the split roothubs' port arrays and bus state arrays.
1511 * Add one to it in order to call xhci_find_slot_id_by_port.
1513 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1514 struct xhci_hcd *xhci, u32 port_id)
1517 unsigned int num_similar_speed_ports = 0;
1519 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1520 * and usb2_ports are 0-based indexes. Count the number of similar
1521 * speed ports, up to 1 port before this port.
1523 for (i = 0; i < (port_id - 1); i++) {
1524 u8 port_speed = xhci->port_array[i];
1527 * Skip ports that don't have known speeds, or have duplicate
1528 * Extended Capabilities port speed entries.
1530 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1534 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1535 * 1.1 ports are under the USB 2.0 hub. If the port speed
1536 * matches the device speed, it's a similar speed port.
1538 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1539 num_similar_speed_ports++;
1541 return num_similar_speed_ports;
1544 static void handle_port_status(struct xhci_hcd *xhci,
1545 union xhci_trb *event)
1547 struct usb_hcd *hcd;
1552 unsigned int faked_port_index;
1554 struct xhci_bus_state *bus_state;
1555 __le32 __iomem **port_array;
1556 bool bogus_port_status = false;
1558 /* Port status change events always have a successful completion code */
1559 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1560 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1561 xhci->error_bitmask |= 1 << 8;
1563 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1564 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1566 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1567 if ((port_id <= 0) || (port_id > max_ports)) {
1568 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1569 bogus_port_status = true;
1573 /* Figure out which usb_hcd this port is attached to:
1574 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1576 major_revision = xhci->port_array[port_id - 1];
1577 if (major_revision == 0) {
1578 xhci_warn(xhci, "Event for port %u not in "
1579 "Extended Capabilities, ignoring.\n",
1581 bogus_port_status = true;
1584 if (major_revision == DUPLICATE_ENTRY) {
1585 xhci_warn(xhci, "Event for port %u duplicated in"
1586 "Extended Capabilities, ignoring.\n",
1588 bogus_port_status = true;
1593 * Hardware port IDs reported by a Port Status Change Event include USB
1594 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1595 * resume event, but we first need to translate the hardware port ID
1596 * into the index into the ports on the correct split roothub, and the
1597 * correct bus_state structure.
1599 /* Find the right roothub. */
1600 hcd = xhci_to_hcd(xhci);
1601 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1602 hcd = xhci->shared_hcd;
1603 bus_state = &xhci->bus_state[hcd_index(hcd)];
1604 if (hcd->speed == HCD_USB3)
1605 port_array = xhci->usb3_ports;
1607 port_array = xhci->usb2_ports;
1608 /* Find the faked port hub number */
1609 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1612 temp = xhci_readl(xhci, port_array[faked_port_index]);
1613 if (hcd->state == HC_STATE_SUSPENDED) {
1614 xhci_dbg(xhci, "resume root hub\n");
1615 usb_hcd_resume_root_hub(hcd);
1618 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1619 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1621 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1622 if (!(temp1 & CMD_RUN)) {
1623 xhci_warn(xhci, "xHC is not running.\n");
1627 if (DEV_SUPERSPEED(temp)) {
1628 xhci_dbg(xhci, "resume SS port %d\n", port_id);
1629 temp = xhci_port_state_to_neutral(temp);
1630 temp &= ~PORT_PLS_MASK;
1631 temp |= PORT_LINK_STROBE | XDEV_U0;
1632 xhci_writel(xhci, temp, port_array[faked_port_index]);
1633 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1634 faked_port_index + 1);
1636 xhci_dbg(xhci, "slot_id is zero\n");
1639 xhci_ring_device(xhci, slot_id);
1640 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1641 /* Clear PORT_PLC */
1642 xhci_test_and_clear_bit(xhci, port_array,
1643 faked_port_index, PORT_PLC);
1645 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1646 bus_state->resume_done[faked_port_index] = jiffies +
1647 msecs_to_jiffies(20);
1648 mod_timer(&hcd->rh_timer,
1649 bus_state->resume_done[faked_port_index]);
1650 /* Do the rest in GetPortStatus */
1654 if (hcd->speed != HCD_USB3)
1655 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1659 /* Update event ring dequeue pointer before dropping the lock */
1660 inc_deq(xhci, xhci->event_ring, true);
1662 /* Don't make the USB core poll the roothub if we got a bad port status
1663 * change event. Besides, at that point we can't tell which roothub
1664 * (USB 2.0 or USB 3.0) to kick.
1666 if (bogus_port_status)
1669 spin_unlock(&xhci->lock);
1670 /* Pass this up to the core */
1671 usb_hcd_poll_rh_status(hcd);
1672 spin_lock(&xhci->lock);
1676 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1677 * at end_trb, which may be in another segment. If the suspect DMA address is a
1678 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1681 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1682 union xhci_trb *start_trb,
1683 union xhci_trb *end_trb,
1684 dma_addr_t suspect_dma)
1686 dma_addr_t start_dma;
1687 dma_addr_t end_seg_dma;
1688 dma_addr_t end_trb_dma;
1689 struct xhci_segment *cur_seg;
1691 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1692 cur_seg = start_seg;
1697 /* We may get an event for a Link TRB in the middle of a TD */
1698 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1699 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1700 /* If the end TRB isn't in this segment, this is set to 0 */
1701 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1703 if (end_trb_dma > 0) {
1704 /* The end TRB is in this segment, so suspect should be here */
1705 if (start_dma <= end_trb_dma) {
1706 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1709 /* Case for one segment with
1710 * a TD wrapped around to the top
1712 if ((suspect_dma >= start_dma &&
1713 suspect_dma <= end_seg_dma) ||
1714 (suspect_dma >= cur_seg->dma &&
1715 suspect_dma <= end_trb_dma))
1720 /* Might still be somewhere in this segment */
1721 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1724 cur_seg = cur_seg->next;
1725 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1726 } while (cur_seg != start_seg);
1731 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1732 unsigned int slot_id, unsigned int ep_index,
1733 unsigned int stream_id,
1734 struct xhci_td *td, union xhci_trb *event_trb)
1736 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1737 ep->ep_state |= EP_HALTED;
1738 ep->stopped_td = td;
1739 ep->stopped_trb = event_trb;
1740 ep->stopped_stream = stream_id;
1742 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1743 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1745 ep->stopped_td = NULL;
1746 ep->stopped_trb = NULL;
1747 ep->stopped_stream = 0;
1749 xhci_ring_cmd_db(xhci);
1752 /* Check if an error has halted the endpoint ring. The class driver will
1753 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1754 * However, a babble and other errors also halt the endpoint ring, and the class
1755 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1756 * Ring Dequeue Pointer command manually.
1758 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1759 struct xhci_ep_ctx *ep_ctx,
1760 unsigned int trb_comp_code)
1762 /* TRB completion codes that may require a manual halt cleanup */
1763 if (trb_comp_code == COMP_TX_ERR ||
1764 trb_comp_code == COMP_BABBLE ||
1765 trb_comp_code == COMP_SPLIT_ERR)
1766 /* The 0.96 spec says a babbling control endpoint
1767 * is not halted. The 0.96 spec says it is. Some HW
1768 * claims to be 0.95 compliant, but it halts the control
1769 * endpoint anyway. Check if a babble halted the
1772 if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == EP_STATE_HALTED)
1778 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1780 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1781 /* Vendor defined "informational" completion code,
1782 * treat as not-an-error.
1784 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1786 xhci_dbg(xhci, "Treating code as success.\n");
1793 * Finish the td processing, remove the td from td list;
1794 * Return 1 if the urb can be given back.
1796 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1797 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1798 struct xhci_virt_ep *ep, int *status, bool skip)
1800 struct xhci_virt_device *xdev;
1801 struct xhci_ring *ep_ring;
1802 unsigned int slot_id;
1804 struct urb *urb = NULL;
1805 struct xhci_ep_ctx *ep_ctx;
1807 struct urb_priv *urb_priv;
1810 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1811 xdev = xhci->devs[slot_id];
1812 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1813 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1814 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1815 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1820 if (trb_comp_code == COMP_STOP_INVAL ||
1821 trb_comp_code == COMP_STOP) {
1822 /* The Endpoint Stop Command completion will take care of any
1823 * stopped TDs. A stopped TD may be restarted, so don't update
1824 * the ring dequeue pointer or take this TD off any lists yet.
1826 ep->stopped_td = td;
1827 ep->stopped_trb = event_trb;
1830 if (trb_comp_code == COMP_STALL) {
1831 /* The transfer is completed from the driver's
1832 * perspective, but we need to issue a set dequeue
1833 * command for this stalled endpoint to move the dequeue
1834 * pointer past the TD. We can't do that here because
1835 * the halt condition must be cleared first. Let the
1836 * USB class driver clear the stall later.
1838 ep->stopped_td = td;
1839 ep->stopped_trb = event_trb;
1840 ep->stopped_stream = ep_ring->stream_id;
1841 } else if (xhci_requires_manual_halt_cleanup(xhci,
1842 ep_ctx, trb_comp_code)) {
1843 /* Other types of errors halt the endpoint, but the
1844 * class driver doesn't call usb_reset_endpoint() unless
1845 * the error is -EPIPE. Clear the halted status in the
1846 * xHCI hardware manually.
1848 xhci_cleanup_halted_endpoint(xhci,
1849 slot_id, ep_index, ep_ring->stream_id,
1852 /* Update ring dequeue pointer */
1853 while (ep_ring->dequeue != td->last_trb)
1854 inc_deq(xhci, ep_ring, false);
1855 inc_deq(xhci, ep_ring, false);
1859 /* Clean up the endpoint's TD list */
1861 urb_priv = urb->hcpriv;
1863 /* Do one last check of the actual transfer length.
1864 * If the host controller said we transferred more data than
1865 * the buffer length, urb->actual_length will be a very big
1866 * number (since it's unsigned). Play it safe and say we didn't
1867 * transfer anything.
1869 if (urb->actual_length > urb->transfer_buffer_length) {
1870 xhci_warn(xhci, "URB transfer length is wrong, "
1871 "xHC issue? req. len = %u, "
1873 urb->transfer_buffer_length,
1874 urb->actual_length);
1875 urb->actual_length = 0;
1876 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1877 *status = -EREMOTEIO;
1881 list_del_init(&td->td_list);
1882 /* Was this TD slated to be cancelled but completed anyway? */
1883 if (!list_empty(&td->cancelled_td_list))
1884 list_del_init(&td->cancelled_td_list);
1887 /* Giveback the urb when all the tds are completed */
1888 if (urb_priv->td_cnt == urb_priv->length) {
1890 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1891 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1892 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1894 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1895 usb_amd_quirk_pll_enable();
1905 * Process control tds, update urb status and actual_length.
1907 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1908 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1909 struct xhci_virt_ep *ep, int *status)
1911 struct xhci_virt_device *xdev;
1912 struct xhci_ring *ep_ring;
1913 unsigned int slot_id;
1915 struct xhci_ep_ctx *ep_ctx;
1918 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1919 xdev = xhci->devs[slot_id];
1920 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1921 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1922 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1923 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1925 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1926 switch (trb_comp_code) {
1928 if (event_trb == ep_ring->dequeue) {
1929 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1930 "without IOC set??\n");
1931 *status = -ESHUTDOWN;
1932 } else if (event_trb != td->last_trb) {
1933 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1934 "without IOC set??\n");
1935 *status = -ESHUTDOWN;
1941 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1942 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1943 *status = -EREMOTEIO;
1947 case COMP_STOP_INVAL:
1949 return finish_td(xhci, td, event_trb, event, ep, status, false);
1951 if (!xhci_requires_manual_halt_cleanup(xhci,
1952 ep_ctx, trb_comp_code))
1954 xhci_dbg(xhci, "TRB error code %u, "
1955 "halted endpoint index = %u\n",
1956 trb_comp_code, ep_index);
1957 /* else fall through */
1959 /* Did we transfer part of the data (middle) phase? */
1960 if (event_trb != ep_ring->dequeue &&
1961 event_trb != td->last_trb)
1962 td->urb->actual_length =
1963 td->urb->transfer_buffer_length
1964 - TRB_LEN(le32_to_cpu(event->transfer_len));
1966 td->urb->actual_length = 0;
1968 xhci_cleanup_halted_endpoint(xhci,
1969 slot_id, ep_index, 0, td, event_trb);
1970 return finish_td(xhci, td, event_trb, event, ep, status, true);
1973 * Did we transfer any data, despite the errors that might have
1974 * happened? I.e. did we get past the setup stage?
1976 if (event_trb != ep_ring->dequeue) {
1977 /* The event was for the status stage */
1978 if (event_trb == td->last_trb) {
1979 if (td->urb->actual_length != 0) {
1980 /* Don't overwrite a previously set error code
1982 if ((*status == -EINPROGRESS || *status == 0) &&
1983 (td->urb->transfer_flags
1984 & URB_SHORT_NOT_OK))
1985 /* Did we already see a short data
1987 *status = -EREMOTEIO;
1989 td->urb->actual_length =
1990 td->urb->transfer_buffer_length;
1993 /* Maybe the event was for the data stage? */
1994 td->urb->actual_length =
1995 td->urb->transfer_buffer_length -
1996 TRB_LEN(le32_to_cpu(event->transfer_len));
1997 xhci_dbg(xhci, "Waiting for status "
2003 return finish_td(xhci, td, event_trb, event, ep, status, false);
2007 * Process isochronous tds, update urb packet status and actual_length.
2009 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2010 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2011 struct xhci_virt_ep *ep, int *status)
2013 struct xhci_ring *ep_ring;
2014 struct urb_priv *urb_priv;
2017 union xhci_trb *cur_trb;
2018 struct xhci_segment *cur_seg;
2019 struct usb_iso_packet_descriptor *frame;
2021 bool skip_td = false;
2023 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2024 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2025 urb_priv = td->urb->hcpriv;
2026 idx = urb_priv->td_cnt;
2027 frame = &td->urb->iso_frame_desc[idx];
2029 /* handle completion code */
2030 switch (trb_comp_code) {
2032 if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2036 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2037 trb_comp_code = COMP_SHORT_TX;
2039 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2043 frame->status = -ECOMM;
2046 case COMP_BUFF_OVER:
2048 frame->status = -EOVERFLOW;
2054 frame->status = -EPROTO;
2058 case COMP_STOP_INVAL:
2065 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2066 frame->actual_length = frame->length;
2067 td->urb->actual_length += frame->length;
2069 for (cur_trb = ep_ring->dequeue,
2070 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2071 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2072 if ((le32_to_cpu(cur_trb->generic.field[3]) &
2073 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
2074 (le32_to_cpu(cur_trb->generic.field[3]) &
2075 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
2076 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2078 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2079 TRB_LEN(le32_to_cpu(event->transfer_len));
2081 if (trb_comp_code != COMP_STOP_INVAL) {
2082 frame->actual_length = len;
2083 td->urb->actual_length += len;
2087 return finish_td(xhci, td, event_trb, event, ep, status, false);
2090 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2091 struct xhci_transfer_event *event,
2092 struct xhci_virt_ep *ep, int *status)
2094 struct xhci_ring *ep_ring;
2095 struct urb_priv *urb_priv;
2096 struct usb_iso_packet_descriptor *frame;
2099 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2100 urb_priv = td->urb->hcpriv;
2101 idx = urb_priv->td_cnt;
2102 frame = &td->urb->iso_frame_desc[idx];
2104 /* The transfer is partly done. */
2105 frame->status = -EXDEV;
2107 /* calc actual length */
2108 frame->actual_length = 0;
2110 /* Update ring dequeue pointer */
2111 while (ep_ring->dequeue != td->last_trb)
2112 inc_deq(xhci, ep_ring, false);
2113 inc_deq(xhci, ep_ring, false);
2115 return finish_td(xhci, td, NULL, event, ep, status, true);
2119 * Process bulk and interrupt tds, update urb status and actual_length.
2121 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2122 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2123 struct xhci_virt_ep *ep, int *status)
2125 struct xhci_ring *ep_ring;
2126 union xhci_trb *cur_trb;
2127 struct xhci_segment *cur_seg;
2130 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2131 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2133 switch (trb_comp_code) {
2135 /* Double check that the HW transferred everything. */
2136 if (event_trb != td->last_trb ||
2137 TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2138 xhci_warn(xhci, "WARN Successful completion "
2140 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2141 *status = -EREMOTEIO;
2144 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2145 trb_comp_code = COMP_SHORT_TX;
2151 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2152 *status = -EREMOTEIO;
2157 /* Others already handled above */
2160 if (trb_comp_code == COMP_SHORT_TX)
2161 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2162 "%d bytes untransferred\n",
2163 td->urb->ep->desc.bEndpointAddress,
2164 td->urb->transfer_buffer_length,
2165 TRB_LEN(le32_to_cpu(event->transfer_len)));
2166 /* Fast path - was this the last TRB in the TD for this URB? */
2167 if (event_trb == td->last_trb) {
2168 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2169 td->urb->actual_length =
2170 td->urb->transfer_buffer_length -
2171 TRB_LEN(le32_to_cpu(event->transfer_len));
2172 if (td->urb->transfer_buffer_length <
2173 td->urb->actual_length) {
2174 xhci_warn(xhci, "HC gave bad length "
2175 "of %d bytes left\n",
2176 TRB_LEN(le32_to_cpu(event->transfer_len)));
2177 td->urb->actual_length = 0;
2178 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2179 *status = -EREMOTEIO;
2183 /* Don't overwrite a previously set error code */
2184 if (*status == -EINPROGRESS) {
2185 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2186 *status = -EREMOTEIO;
2191 td->urb->actual_length =
2192 td->urb->transfer_buffer_length;
2193 /* Ignore a short packet completion if the
2194 * untransferred length was zero.
2196 if (*status == -EREMOTEIO)
2200 /* Slow path - walk the list, starting from the dequeue
2201 * pointer, to get the actual length transferred.
2203 td->urb->actual_length = 0;
2204 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2205 cur_trb != event_trb;
2206 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2207 if ((le32_to_cpu(cur_trb->generic.field[3]) &
2208 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
2209 (le32_to_cpu(cur_trb->generic.field[3]) &
2210 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
2211 td->urb->actual_length +=
2212 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2214 /* If the ring didn't stop on a Link or No-op TRB, add
2215 * in the actual bytes transferred from the Normal TRB
2217 if (trb_comp_code != COMP_STOP_INVAL)
2218 td->urb->actual_length +=
2219 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2220 TRB_LEN(le32_to_cpu(event->transfer_len));
2223 return finish_td(xhci, td, event_trb, event, ep, status, false);
2227 * If this function returns an error condition, it means it got a Transfer
2228 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2229 * At this point, the host controller is probably hosed and should be reset.
2231 static int handle_tx_event(struct xhci_hcd *xhci,
2232 struct xhci_transfer_event *event)
2234 struct xhci_virt_device *xdev;
2235 struct xhci_virt_ep *ep;
2236 struct xhci_ring *ep_ring;
2237 unsigned int slot_id;
2239 struct xhci_td *td = NULL;
2240 dma_addr_t event_dma;
2241 struct xhci_segment *event_seg;
2242 union xhci_trb *event_trb;
2243 struct urb *urb = NULL;
2244 int status = -EINPROGRESS;
2245 struct urb_priv *urb_priv;
2246 struct xhci_ep_ctx *ep_ctx;
2247 struct list_head *tmp;
2252 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2253 xdev = xhci->devs[slot_id];
2255 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2259 /* Endpoint ID is 1 based, our index is zero based */
2260 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2261 ep = &xdev->eps[ep_index];
2262 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2263 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2265 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2266 EP_STATE_DISABLED) {
2267 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2268 "or incorrect stream ring\n");
2272 /* Count current td numbers if ep->skip is set */
2274 list_for_each(tmp, &ep_ring->td_list)
2278 event_dma = le64_to_cpu(event->buffer);
2279 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2280 /* Look for common error cases */
2281 switch (trb_comp_code) {
2282 /* Skip codes that require special handling depending on
2286 if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2288 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2289 trb_comp_code = COMP_SHORT_TX;
2291 xhci_warn(xhci, "WARN Successful completion on short TX: "
2292 "needs XHCI_TRUST_TX_LENGTH quirk?\n");
2296 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2298 case COMP_STOP_INVAL:
2299 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2302 xhci_warn(xhci, "WARN: Stalled endpoint\n");
2303 ep->ep_state |= EP_HALTED;
2307 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2310 case COMP_SPLIT_ERR:
2312 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
2316 xhci_warn(xhci, "WARN: babble error on endpoint\n");
2317 status = -EOVERFLOW;
2320 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2324 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2326 case COMP_BUFF_OVER:
2327 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2331 * When the Isoch ring is empty, the xHC will generate
2332 * a Ring Overrun Event for IN Isoch endpoint or Ring
2333 * Underrun Event for OUT Isoch endpoint.
2335 xhci_dbg(xhci, "underrun event on endpoint\n");
2336 if (!list_empty(&ep_ring->td_list))
2337 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2338 "still with TDs queued?\n",
2339 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2343 xhci_dbg(xhci, "overrun event on endpoint\n");
2344 if (!list_empty(&ep_ring->td_list))
2345 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2346 "still with TDs queued?\n",
2347 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2351 xhci_warn(xhci, "WARN: detect an incompatible device");
2354 case COMP_MISSED_INT:
2356 * When encounter missed service error, one or more isoc tds
2357 * may be missed by xHC.
2358 * Set skip flag of the ep_ring; Complete the missed tds as
2359 * short transfer when process the ep_ring next time.
2362 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2365 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2369 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2375 /* This TRB should be in the TD at the head of this ring's
2378 if (list_empty(&ep_ring->td_list)) {
2379 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2380 "with no TDs queued?\n",
2381 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2383 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2384 (unsigned int) (le32_to_cpu(event->flags)
2385 & TRB_TYPE_BITMASK)>>10);
2386 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2389 xhci_dbg(xhci, "td_list is empty while skip "
2390 "flag set. Clear skip flag.\n");
2396 /* We've skipped all the TDs on the ep ring when ep->skip set */
2397 if (ep->skip && td_num == 0) {
2399 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2400 "Clear skip flag.\n");
2405 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2409 /* Is this a TRB in the currently executing TD? */
2410 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2411 td->last_trb, event_dma);
2414 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2415 * is not in the current TD pointed by ep_ring->dequeue because
2416 * that the hardware dequeue pointer still at the previous TRB
2417 * of the current TD. The previous TRB maybe a Link TD or the
2418 * last TRB of the previous TD. The command completion handle
2419 * will take care the rest.
2421 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2428 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2429 /* Some host controllers give a spurious
2430 * successful event after a short transfer.
2433 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2434 ep_ring->last_td_was_short) {
2435 ep_ring->last_td_was_short = false;
2439 /* HC is busted, give up! */
2441 "ERROR Transfer event TRB DMA ptr not "
2442 "part of current TD\n");
2446 ret = skip_isoc_td(xhci, td, event, ep, &status);
2449 if (trb_comp_code == COMP_SHORT_TX)
2450 ep_ring->last_td_was_short = true;
2452 ep_ring->last_td_was_short = false;
2455 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2459 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2460 sizeof(*event_trb)];
2462 * No-op TRB should not trigger interrupts.
2463 * If event_trb is a no-op TRB, it means the
2464 * corresponding TD has been cancelled. Just ignore
2467 if ((le32_to_cpu(event_trb->generic.field[3])
2469 == TRB_TYPE(TRB_TR_NOOP)) {
2471 "event_trb is a no-op TRB. Skip it\n");
2475 /* Now update the urb's actual_length and give back to
2478 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2479 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2481 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2482 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2485 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2490 * Do not update event ring dequeue pointer if ep->skip is set.
2491 * Will roll back to continue process missed tds.
2493 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2494 inc_deq(xhci, xhci->event_ring, true);
2499 urb_priv = urb->hcpriv;
2500 /* Leave the TD around for the reset endpoint function
2501 * to use(but only if it's not a control endpoint,
2502 * since we already queued the Set TR dequeue pointer
2503 * command for stalled control endpoints).
2505 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2506 (trb_comp_code != COMP_STALL &&
2507 trb_comp_code != COMP_BABBLE))
2508 xhci_urb_free_priv(xhci, urb_priv);
2510 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2511 if ((urb->actual_length != urb->transfer_buffer_length &&
2512 (urb->transfer_flags &
2513 URB_SHORT_NOT_OK)) ||
2515 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2516 "expected = %x, status = %d\n",
2517 urb, urb->actual_length,
2518 urb->transfer_buffer_length,
2520 spin_unlock(&xhci->lock);
2521 /* EHCI, UHCI, and OHCI always unconditionally set the
2522 * urb->status of an isochronous endpoint to 0.
2524 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2526 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2527 spin_lock(&xhci->lock);
2531 * If ep->skip is set, it means there are missed tds on the
2532 * endpoint ring need to take care of.
2533 * Process them as short transfer until reach the td pointed by
2536 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2542 * This function handles all OS-owned events on the event ring. It may drop
2543 * xhci->lock between event processing (e.g. to pass up port status changes).
2544 * Returns >0 for "possibly more events to process" (caller should call again),
2545 * otherwise 0 if done. In future, <0 returns should indicate error code.
2547 static int xhci_handle_event(struct xhci_hcd *xhci)
2549 union xhci_trb *event;
2550 int update_ptrs = 1;
2553 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2554 xhci->error_bitmask |= 1 << 1;
2558 event = xhci->event_ring->dequeue;
2559 /* Does the HC or OS own the TRB? */
2560 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2561 xhci->event_ring->cycle_state) {
2562 xhci->error_bitmask |= 1 << 2;
2567 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2568 * speculative reads of the event's flags/data below.
2571 /* FIXME: Handle more event types. */
2572 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2573 case TRB_TYPE(TRB_COMPLETION):
2574 handle_cmd_completion(xhci, &event->event_cmd);
2576 case TRB_TYPE(TRB_PORT_STATUS):
2577 handle_port_status(xhci, event);
2580 case TRB_TYPE(TRB_TRANSFER):
2581 ret = handle_tx_event(xhci, &event->trans_event);
2583 xhci->error_bitmask |= 1 << 9;
2588 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2590 handle_vendor_event(xhci, event);
2592 xhci->error_bitmask |= 1 << 3;
2594 /* Any of the above functions may drop and re-acquire the lock, so check
2595 * to make sure a watchdog timer didn't mark the host as non-responsive.
2597 if (xhci->xhc_state & XHCI_STATE_DYING) {
2598 xhci_dbg(xhci, "xHCI host dying, returning from "
2599 "event handler.\n");
2604 /* Update SW event ring dequeue pointer */
2605 inc_deq(xhci, xhci->event_ring, true);
2607 /* Are there more items on the event ring? Caller will call us again to
2614 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2615 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2616 * indicators of an event TRB error, but we check the status *first* to be safe.
2618 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2620 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2622 union xhci_trb *trb;
2624 union xhci_trb *event_ring_deq;
2627 spin_lock(&xhci->lock);
2628 trb = xhci->event_ring->dequeue;
2629 /* Check if the xHC generated the interrupt, or the irq is shared */
2630 status = xhci_readl(xhci, &xhci->op_regs->status);
2631 if (status == 0xffffffff)
2634 if (!(status & STS_EINT)) {
2635 spin_unlock(&xhci->lock);
2638 if (status & STS_FATAL) {
2639 xhci_warn(xhci, "WARNING: Host System Error\n");
2642 spin_unlock(&xhci->lock);
2647 * Clear the op reg interrupt status first,
2648 * so we can receive interrupts from other MSI-X interrupters.
2649 * Write 1 to clear the interrupt status.
2652 xhci_writel(xhci, status, &xhci->op_regs->status);
2653 /* FIXME when MSI-X is supported and there are multiple vectors */
2654 /* Clear the MSI-X event interrupt status */
2656 if (hcd->irq != -1) {
2658 /* Acknowledge the PCI interrupt */
2659 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2660 irq_pending |= IMAN_IP;
2661 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2664 if (xhci->xhc_state & XHCI_STATE_DYING) {
2665 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2666 "Shouldn't IRQs be disabled?\n");
2667 /* Clear the event handler busy flag (RW1C);
2668 * the event ring should be empty.
2670 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2671 xhci_write_64(xhci, temp_64 | ERST_EHB,
2672 &xhci->ir_set->erst_dequeue);
2673 spin_unlock(&xhci->lock);
2678 event_ring_deq = xhci->event_ring->dequeue;
2679 /* FIXME this should be a delayed service routine
2680 * that clears the EHB.
2682 while (xhci_handle_event(xhci) > 0) {}
2684 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2685 /* If necessary, update the HW's version of the event ring deq ptr. */
2686 if (event_ring_deq != xhci->event_ring->dequeue) {
2687 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2688 xhci->event_ring->dequeue);
2690 xhci_warn(xhci, "WARN something wrong with SW event "
2691 "ring dequeue ptr.\n");
2692 /* Update HC event ring dequeue pointer */
2693 temp_64 &= ERST_PTR_MASK;
2694 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2697 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2698 temp_64 |= ERST_EHB;
2699 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2701 spin_unlock(&xhci->lock);
2706 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2709 struct xhci_hcd *xhci;
2711 xhci = hcd_to_xhci(hcd);
2712 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2713 if (xhci->shared_hcd)
2714 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2716 ret = xhci_irq(hcd);
2721 /**** Endpoint Ring Operations ****/
2724 * Generic function for queueing a TRB on a ring.
2725 * The caller must have checked to make sure there's room on the ring.
2727 * @more_trbs_coming: Will you enqueue more TRBs before calling
2728 * prepare_transfer()?
2730 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2731 bool consumer, bool more_trbs_coming, bool isoc,
2732 u32 field1, u32 field2, u32 field3, u32 field4)
2734 struct xhci_generic_trb *trb;
2736 trb = &ring->enqueue->generic;
2737 trb->field[0] = cpu_to_le32(field1);
2738 trb->field[1] = cpu_to_le32(field2);
2739 trb->field[2] = cpu_to_le32(field3);
2740 trb->field[3] = cpu_to_le32(field4);
2741 inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2745 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2746 * FIXME allocate segments if the ring is full.
2748 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2749 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2751 /* Make sure the endpoint has been added to xHC schedule */
2753 case EP_STATE_DISABLED:
2755 * USB core changed config/interfaces without notifying us,
2756 * or hardware is reporting the wrong state.
2758 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2760 case EP_STATE_ERROR:
2761 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2762 /* FIXME event handling code for error needs to clear it */
2763 /* XXX not sure if this should be -ENOENT or not */
2765 case EP_STATE_HALTED:
2766 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2767 case EP_STATE_STOPPED:
2768 case EP_STATE_RUNNING:
2771 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2773 * FIXME issue Configure Endpoint command to try to get the HC
2774 * back into a known state.
2778 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2779 /* FIXME allocate more room */
2780 xhci_err(xhci, "ERROR no room on ep ring\n");
2784 if (enqueue_is_link_trb(ep_ring)) {
2785 struct xhci_ring *ring = ep_ring;
2786 union xhci_trb *next;
2788 next = ring->enqueue;
2790 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2791 /* If we're not dealing with 0.95 hardware or isoc rings
2792 * on AMD 0.96 host, clear the chain bit.
2794 if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2795 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2796 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2798 next->link.control |= cpu_to_le32(TRB_CHAIN);
2801 next->link.control ^= cpu_to_le32((u32) TRB_CYCLE);
2803 /* Toggle the cycle bit after the last ring segment. */
2804 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2805 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2806 if (!in_interrupt()) {
2807 xhci_dbg(xhci, "queue_trb: Toggle cycle "
2808 "state for ring %p = %i\n",
2809 ring, (unsigned int)ring->cycle_state);
2812 ring->enq_seg = ring->enq_seg->next;
2813 ring->enqueue = ring->enq_seg->trbs;
2814 next = ring->enqueue;
2821 static int prepare_transfer(struct xhci_hcd *xhci,
2822 struct xhci_virt_device *xdev,
2823 unsigned int ep_index,
2824 unsigned int stream_id,
2825 unsigned int num_trbs,
2827 unsigned int td_index,
2832 struct urb_priv *urb_priv;
2834 struct xhci_ring *ep_ring;
2835 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2837 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2839 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2844 ret = prepare_ring(xhci, ep_ring,
2845 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2846 num_trbs, isoc, mem_flags);
2850 urb_priv = urb->hcpriv;
2851 td = urb_priv->td[td_index];
2853 INIT_LIST_HEAD(&td->td_list);
2854 INIT_LIST_HEAD(&td->cancelled_td_list);
2856 if (td_index == 0) {
2857 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2863 /* Add this TD to the tail of the endpoint ring's TD list */
2864 list_add_tail(&td->td_list, &ep_ring->td_list);
2865 td->start_seg = ep_ring->enq_seg;
2866 td->first_trb = ep_ring->enqueue;
2868 urb_priv->td[td_index] = td;
2873 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2875 int num_sgs, num_trbs, running_total, temp, i;
2876 struct scatterlist *sg;
2879 num_sgs = urb->num_mapped_sgs;
2880 temp = urb->transfer_buffer_length;
2882 xhci_dbg(xhci, "count sg list trbs: \n");
2884 for_each_sg(urb->sg, sg, num_sgs, i) {
2885 unsigned int previous_total_trbs = num_trbs;
2886 unsigned int len = sg_dma_len(sg);
2888 /* Scatter gather list entries may cross 64KB boundaries */
2889 running_total = TRB_MAX_BUFF_SIZE -
2890 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2891 running_total &= TRB_MAX_BUFF_SIZE - 1;
2892 if (running_total != 0)
2895 /* How many more 64KB chunks to transfer, how many more TRBs? */
2896 while (running_total < sg_dma_len(sg) && running_total < temp) {
2898 running_total += TRB_MAX_BUFF_SIZE;
2900 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2901 i, (unsigned long long)sg_dma_address(sg),
2902 len, len, num_trbs - previous_total_trbs);
2904 len = min_t(int, len, temp);
2909 xhci_dbg(xhci, "\n");
2910 if (!in_interrupt())
2911 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2913 urb->ep->desc.bEndpointAddress,
2914 urb->transfer_buffer_length,
2919 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2922 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2923 "TRBs, %d left\n", __func__,
2924 urb->ep->desc.bEndpointAddress, num_trbs);
2925 if (running_total != urb->transfer_buffer_length)
2926 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2927 "queued %#x (%d), asked for %#x (%d)\n",
2929 urb->ep->desc.bEndpointAddress,
2930 running_total, running_total,
2931 urb->transfer_buffer_length,
2932 urb->transfer_buffer_length);
2935 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2936 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2937 struct xhci_generic_trb *start_trb)
2940 * Pass all the TRBs to the hardware at once and make sure this write
2945 start_trb->field[3] |= cpu_to_le32(start_cycle);
2947 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2948 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2952 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2953 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2954 * (comprised of sg list entries) can take several service intervals to
2957 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2958 struct urb *urb, int slot_id, unsigned int ep_index)
2960 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2961 xhci->devs[slot_id]->out_ctx, ep_index);
2965 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2966 ep_interval = urb->interval;
2967 /* Convert to microframes */
2968 if (urb->dev->speed == USB_SPEED_LOW ||
2969 urb->dev->speed == USB_SPEED_FULL)
2971 /* FIXME change this to a warning and a suggestion to use the new API
2972 * to set the polling interval (once the API is added).
2974 if (xhci_interval != ep_interval) {
2975 if (printk_ratelimit())
2976 dev_dbg(&urb->dev->dev, "Driver uses different interval"
2977 " (%d microframe%s) than xHCI "
2978 "(%d microframe%s)\n",
2980 ep_interval == 1 ? "" : "s",
2982 xhci_interval == 1 ? "" : "s");
2983 urb->interval = xhci_interval;
2984 /* Convert back to frames for LS/FS devices */
2985 if (urb->dev->speed == USB_SPEED_LOW ||
2986 urb->dev->speed == USB_SPEED_FULL)
2989 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2993 * The TD size is the number of bytes remaining in the TD (including this TRB),
2994 * right shifted by 10.
2995 * It must fit in bits 21:17, so it can't be bigger than 31.
2997 static u32 xhci_td_remainder(unsigned int remainder)
2999 u32 max = (1 << (21 - 17 + 1)) - 1;
3001 if ((remainder >> 10) >= max)
3004 return (remainder >> 10) << 17;
3008 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
3009 * the TD (*not* including this TRB).
3011 * Total TD packet count = total_packet_count =
3012 * roundup(TD size in bytes / wMaxPacketSize)
3014 * Packets transferred up to and including this TRB = packets_transferred =
3015 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3017 * TD size = total_packet_count - packets_transferred
3019 * It must fit in bits 21:17, so it can't be bigger than 31.
3022 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3023 unsigned int total_packet_count, struct urb *urb)
3025 int packets_transferred;
3027 /* One TRB with a zero-length data packet. */
3028 if (running_total == 0 && trb_buff_len == 0)
3031 /* All the TRB queueing functions don't count the current TRB in
3034 packets_transferred = (running_total + trb_buff_len) /
3035 le16_to_cpu(urb->ep->desc.wMaxPacketSize);
3037 return xhci_td_remainder(total_packet_count - packets_transferred);
3040 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3041 struct urb *urb, int slot_id, unsigned int ep_index)
3043 struct xhci_ring *ep_ring;
3044 unsigned int num_trbs;
3045 struct urb_priv *urb_priv;
3047 struct scatterlist *sg;
3049 int trb_buff_len, this_sg_len, running_total;
3050 unsigned int total_packet_count;
3053 bool more_trbs_coming;
3055 struct xhci_generic_trb *start_trb;
3058 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3062 num_trbs = count_sg_trbs_needed(xhci, urb);
3063 num_sgs = urb->num_mapped_sgs;
3064 total_packet_count = roundup(urb->transfer_buffer_length,
3065 le16_to_cpu(urb->ep->desc.wMaxPacketSize));
3067 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3068 ep_index, urb->stream_id,
3069 num_trbs, urb, 0, false, mem_flags);
3070 if (trb_buff_len < 0)
3071 return trb_buff_len;
3073 urb_priv = urb->hcpriv;
3074 td = urb_priv->td[0];
3077 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3078 * until we've finished creating all the other TRBs. The ring's cycle
3079 * state may change as we enqueue the other TRBs, so save it too.
3081 start_trb = &ep_ring->enqueue->generic;
3082 start_cycle = ep_ring->cycle_state;
3086 * How much data is in the first TRB?
3088 * There are three forces at work for TRB buffer pointers and lengths:
3089 * 1. We don't want to walk off the end of this sg-list entry buffer.
3090 * 2. The transfer length that the driver requested may be smaller than
3091 * the amount of memory allocated for this scatter-gather list.
3092 * 3. TRBs buffers can't cross 64KB boundaries.
3095 addr = (u64) sg_dma_address(sg);
3096 this_sg_len = sg_dma_len(sg);
3097 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3098 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3099 if (trb_buff_len > urb->transfer_buffer_length)
3100 trb_buff_len = urb->transfer_buffer_length;
3101 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
3105 /* Queue the first TRB, even if it's zero-length */
3108 u32 length_field = 0;
3111 /* Don't change the cycle bit of the first TRB until later */
3114 if (start_cycle == 0)
3117 field |= ep_ring->cycle_state;
3119 /* Chain all the TRBs together; clear the chain bit in the last
3120 * TRB to indicate it's the last TRB in the chain.
3125 /* FIXME - add check for ZERO_PACKET flag before this */
3126 td->last_trb = ep_ring->enqueue;
3130 /* Only set interrupt on short packet for IN endpoints */
3131 if (usb_urb_dir_in(urb))
3134 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
3135 "64KB boundary at %#x, end dma = %#x\n",
3136 (unsigned int) addr, trb_buff_len, trb_buff_len,
3137 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3138 (unsigned int) addr + trb_buff_len);
3139 if (TRB_MAX_BUFF_SIZE -
3140 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3141 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3142 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3143 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3144 (unsigned int) addr + trb_buff_len);
3147 /* Set the TRB length, TD size, and interrupter fields. */
3148 if (xhci->hci_version < 0x100) {
3149 remainder = xhci_td_remainder(
3150 urb->transfer_buffer_length -
3153 remainder = xhci_v1_0_td_remainder(running_total,
3154 trb_buff_len, total_packet_count, urb);
3156 length_field = TRB_LEN(trb_buff_len) |
3161 more_trbs_coming = true;
3163 more_trbs_coming = false;
3164 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3165 lower_32_bits(addr),
3166 upper_32_bits(addr),
3168 field | TRB_TYPE(TRB_NORMAL));
3170 running_total += trb_buff_len;
3172 /* Calculate length for next transfer --
3173 * Are we done queueing all the TRBs for this sg entry?
3175 this_sg_len -= trb_buff_len;
3176 if (this_sg_len == 0) {
3181 addr = (u64) sg_dma_address(sg);
3182 this_sg_len = sg_dma_len(sg);
3184 addr += trb_buff_len;
3187 trb_buff_len = TRB_MAX_BUFF_SIZE -
3188 (addr & (TRB_MAX_BUFF_SIZE - 1));
3189 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3190 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3192 urb->transfer_buffer_length - running_total;
3193 } while (running_total < urb->transfer_buffer_length);
3195 check_trb_math(urb, num_trbs, running_total);
3196 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3197 start_cycle, start_trb);
3201 /* This is very similar to what ehci-q.c qtd_fill() does */
3202 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3203 struct urb *urb, int slot_id, unsigned int ep_index)
3205 struct xhci_ring *ep_ring;
3206 struct urb_priv *urb_priv;
3209 struct xhci_generic_trb *start_trb;
3211 bool more_trbs_coming;
3213 u32 field, length_field;
3215 int running_total, trb_buff_len, ret;
3216 unsigned int total_packet_count;
3220 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3222 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3227 /* How much data is (potentially) left before the 64KB boundary? */
3228 running_total = TRB_MAX_BUFF_SIZE -
3229 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3230 running_total &= TRB_MAX_BUFF_SIZE - 1;
3232 /* If there's some data on this 64KB chunk, or we have to send a
3233 * zero-length transfer, we need at least one TRB
3235 if (running_total != 0 || urb->transfer_buffer_length == 0)
3237 /* How many more 64KB chunks to transfer, how many more TRBs? */
3238 while (running_total < urb->transfer_buffer_length) {
3240 running_total += TRB_MAX_BUFF_SIZE;
3242 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3244 if (!in_interrupt())
3245 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
3246 "addr = %#llx, num_trbs = %d\n",
3247 urb->ep->desc.bEndpointAddress,
3248 urb->transfer_buffer_length,
3249 urb->transfer_buffer_length,
3250 (unsigned long long)urb->transfer_dma,
3253 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3254 ep_index, urb->stream_id,
3255 num_trbs, urb, 0, false, mem_flags);
3259 urb_priv = urb->hcpriv;
3260 td = urb_priv->td[0];
3263 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3264 * until we've finished creating all the other TRBs. The ring's cycle
3265 * state may change as we enqueue the other TRBs, so save it too.
3267 start_trb = &ep_ring->enqueue->generic;
3268 start_cycle = ep_ring->cycle_state;
3271 total_packet_count = roundup(urb->transfer_buffer_length,
3272 le16_to_cpu(urb->ep->desc.wMaxPacketSize));
3273 /* How much data is in the first TRB? */
3274 addr = (u64) urb->transfer_dma;
3275 trb_buff_len = TRB_MAX_BUFF_SIZE -
3276 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3277 if (trb_buff_len > urb->transfer_buffer_length)
3278 trb_buff_len = urb->transfer_buffer_length;
3282 /* Queue the first TRB, even if it's zero-length */
3287 /* Don't change the cycle bit of the first TRB until later */
3290 if (start_cycle == 0)
3293 field |= ep_ring->cycle_state;
3295 /* Chain all the TRBs together; clear the chain bit in the last
3296 * TRB to indicate it's the last TRB in the chain.
3301 /* FIXME - add check for ZERO_PACKET flag before this */
3302 td->last_trb = ep_ring->enqueue;
3306 /* Only set interrupt on short packet for IN endpoints */
3307 if (usb_urb_dir_in(urb))
3310 /* Set the TRB length, TD size, and interrupter fields. */
3311 if (xhci->hci_version < 0x100) {
3312 remainder = xhci_td_remainder(
3313 urb->transfer_buffer_length -
3316 remainder = xhci_v1_0_td_remainder(running_total,
3317 trb_buff_len, total_packet_count, urb);
3319 length_field = TRB_LEN(trb_buff_len) |
3324 more_trbs_coming = true;
3326 more_trbs_coming = false;
3327 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3328 lower_32_bits(addr),
3329 upper_32_bits(addr),
3331 field | TRB_TYPE(TRB_NORMAL));
3333 running_total += trb_buff_len;
3335 /* Calculate length for next transfer */
3336 addr += trb_buff_len;
3337 trb_buff_len = urb->transfer_buffer_length - running_total;
3338 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3339 trb_buff_len = TRB_MAX_BUFF_SIZE;
3340 } while (running_total < urb->transfer_buffer_length);
3342 check_trb_math(urb, num_trbs, running_total);
3343 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3344 start_cycle, start_trb);
3348 /* Caller must have locked xhci->lock */
3349 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3350 struct urb *urb, int slot_id, unsigned int ep_index)
3352 struct xhci_ring *ep_ring;
3355 struct usb_ctrlrequest *setup;
3356 struct xhci_generic_trb *start_trb;
3358 u32 field, length_field;
3359 struct urb_priv *urb_priv;
3362 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3367 * Need to copy setup packet into setup TRB, so we can't use the setup
3370 if (!urb->setup_packet)
3373 if (!in_interrupt())
3374 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3376 /* 1 TRB for setup, 1 for status */
3379 * Don't need to check if we need additional event data and normal TRBs,
3380 * since data in control transfers will never get bigger than 16MB
3381 * XXX: can we get a buffer that crosses 64KB boundaries?
3383 if (urb->transfer_buffer_length > 0)
3385 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3386 ep_index, urb->stream_id,
3387 num_trbs, urb, 0, false, mem_flags);
3391 urb_priv = urb->hcpriv;
3392 td = urb_priv->td[0];
3395 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3396 * until we've finished creating all the other TRBs. The ring's cycle
3397 * state may change as we enqueue the other TRBs, so save it too.
3399 start_trb = &ep_ring->enqueue->generic;
3400 start_cycle = ep_ring->cycle_state;
3402 /* Queue setup TRB - see section 6.4.1.2.1 */
3403 /* FIXME better way to translate setup_packet into two u32 fields? */
3404 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3406 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3407 if (start_cycle == 0)
3410 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3411 if (xhci->hci_version == 0x100) {
3412 if (urb->transfer_buffer_length > 0) {
3413 if (setup->bRequestType & USB_DIR_IN)
3414 field |= TRB_TX_TYPE(TRB_DATA_IN);
3416 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3420 queue_trb(xhci, ep_ring, false, true, false,
3421 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3422 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3423 TRB_LEN(8) | TRB_INTR_TARGET(0),
3424 /* Immediate data in pointer */
3427 /* If there's data, queue data TRBs */
3428 /* Only set interrupt on short packet for IN endpoints */
3429 if (usb_urb_dir_in(urb))
3430 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3432 field = TRB_TYPE(TRB_DATA);
3434 length_field = TRB_LEN(urb->transfer_buffer_length) |
3435 xhci_td_remainder(urb->transfer_buffer_length) |
3437 if (urb->transfer_buffer_length > 0) {
3438 if (setup->bRequestType & USB_DIR_IN)
3439 field |= TRB_DIR_IN;
3440 queue_trb(xhci, ep_ring, false, true, false,
3441 lower_32_bits(urb->transfer_dma),
3442 upper_32_bits(urb->transfer_dma),
3444 field | ep_ring->cycle_state);
3447 /* Save the DMA address of the last TRB in the TD */
3448 td->last_trb = ep_ring->enqueue;
3450 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3451 /* If the device sent data, the status stage is an OUT transfer */
3452 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3456 queue_trb(xhci, ep_ring, false, false, false,
3460 /* Event on completion */
3461 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3463 giveback_first_trb(xhci, slot_id, ep_index, 0,
3464 start_cycle, start_trb);
3468 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3469 struct urb *urb, int i)
3474 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3475 td_len = urb->iso_frame_desc[i].length;
3477 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3486 * The transfer burst count field of the isochronous TRB defines the number of
3487 * bursts that are required to move all packets in this TD. Only SuperSpeed
3488 * devices can burst up to bMaxBurst number of packets per service interval.
3489 * This field is zero based, meaning a value of zero in the field means one
3490 * burst. Basically, for everything but SuperSpeed devices, this field will be
3491 * zero. Only xHCI 1.0 host controllers support this field.
3493 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3494 struct usb_device *udev,
3495 struct urb *urb, unsigned int total_packet_count)
3497 unsigned int max_burst;
3499 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3502 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3503 return roundup(total_packet_count, max_burst + 1) - 1;
3507 * Returns the number of packets in the last "burst" of packets. This field is
3508 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3509 * the last burst packet count is equal to the total number of packets in the
3510 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3511 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3512 * contain 1 to (bMaxBurst + 1) packets.
3514 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3515 struct usb_device *udev,
3516 struct urb *urb, unsigned int total_packet_count)
3518 unsigned int max_burst;
3519 unsigned int residue;
3521 if (xhci->hci_version < 0x100)
3524 switch (udev->speed) {
3525 case USB_SPEED_SUPER:
3526 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3527 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3528 residue = total_packet_count % (max_burst + 1);
3529 /* If residue is zero, the last burst contains (max_burst + 1)
3530 * number of packets, but the TLBPC field is zero-based.
3536 if (total_packet_count == 0)
3538 return total_packet_count - 1;
3542 /* This is for isoc transfer */
3543 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3544 struct urb *urb, int slot_id, unsigned int ep_index)
3546 struct xhci_ring *ep_ring;
3547 struct urb_priv *urb_priv;
3549 int num_tds, trbs_per_td;
3550 struct xhci_generic_trb *start_trb;
3553 u32 field, length_field;
3554 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3555 u64 start_addr, addr;
3557 bool more_trbs_coming;
3559 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3561 num_tds = urb->number_of_packets;
3563 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3567 if (!in_interrupt())
3568 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3569 " addr = %#llx, num_tds = %d\n",
3570 urb->ep->desc.bEndpointAddress,
3571 urb->transfer_buffer_length,
3572 urb->transfer_buffer_length,
3573 (unsigned long long)urb->transfer_dma,
3576 start_addr = (u64) urb->transfer_dma;
3577 start_trb = &ep_ring->enqueue->generic;
3578 start_cycle = ep_ring->cycle_state;
3580 urb_priv = urb->hcpriv;
3581 /* Queue the first TRB, even if it's zero-length */
3582 for (i = 0; i < num_tds; i++) {
3583 unsigned int total_packet_count;
3584 unsigned int burst_count;
3585 unsigned int residue;
3589 addr = start_addr + urb->iso_frame_desc[i].offset;
3590 td_len = urb->iso_frame_desc[i].length;
3591 td_remain_len = td_len;
3592 total_packet_count = roundup(td_len,
3593 le16_to_cpu(urb->ep->desc.wMaxPacketSize));
3594 /* A zero-length transfer still involves at least one packet. */
3595 if (total_packet_count == 0)
3596 total_packet_count++;
3597 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3598 total_packet_count);
3599 residue = xhci_get_last_burst_packet_count(xhci,
3600 urb->dev, urb, total_packet_count);
3602 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3604 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3605 urb->stream_id, trbs_per_td, urb, i, true,
3613 td = urb_priv->td[i];
3614 for (j = 0; j < trbs_per_td; j++) {
3619 field = TRB_TBC(burst_count) |
3621 /* Queue the isoc TRB */
3622 field |= TRB_TYPE(TRB_ISOC);
3623 /* Assume URB_ISO_ASAP is set */
3626 if (start_cycle == 0)
3629 field |= ep_ring->cycle_state;
3632 /* Queue other normal TRBs */
3633 field |= TRB_TYPE(TRB_NORMAL);
3634 field |= ep_ring->cycle_state;
3637 /* Only set interrupt on short packet for IN EPs */
3638 if (usb_urb_dir_in(urb))
3641 /* Chain all the TRBs together; clear the chain bit in
3642 * the last TRB to indicate it's the last TRB in the
3645 if (j < trbs_per_td - 1) {
3647 more_trbs_coming = true;
3649 td->last_trb = ep_ring->enqueue;
3651 if (xhci->hci_version == 0x100 &&
3654 /* Set BEI bit except for the last td */
3655 if (i < num_tds - 1)
3658 more_trbs_coming = false;
3661 /* Calculate TRB length */
3662 trb_buff_len = TRB_MAX_BUFF_SIZE -
3663 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3664 if (trb_buff_len > td_remain_len)
3665 trb_buff_len = td_remain_len;
3667 /* Set the TRB length, TD size, & interrupter fields. */
3668 if (xhci->hci_version < 0x100) {
3669 remainder = xhci_td_remainder(
3670 td_len - running_total);
3672 remainder = xhci_v1_0_td_remainder(
3673 running_total, trb_buff_len,
3674 total_packet_count, urb);
3676 length_field = TRB_LEN(trb_buff_len) |
3680 queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3681 lower_32_bits(addr),
3682 upper_32_bits(addr),
3685 running_total += trb_buff_len;
3687 addr += trb_buff_len;
3688 td_remain_len -= trb_buff_len;
3691 /* Check TD length */
3692 if (running_total != td_len) {
3693 xhci_err(xhci, "ISOC TD length unmatch\n");
3699 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3700 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3701 usb_amd_quirk_pll_disable();
3703 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3705 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3706 start_cycle, start_trb);
3709 /* Clean up a partially enqueued isoc transfer. */
3711 for (i--; i >= 0; i--)
3712 list_del_init(&urb_priv->td[i]->td_list);
3714 /* Use the first TD as a temporary variable to turn the TDs we've queued
3715 * into No-ops with a software-owned cycle bit. That way the hardware
3716 * won't accidentally start executing bogus TDs when we partially
3717 * overwrite them. td->first_trb and td->start_seg are already set.
3719 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3720 /* Every TRB except the first & last will have its cycle bit flipped. */
3721 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3723 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3724 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3725 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3726 ep_ring->cycle_state = start_cycle;
3727 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3732 * Check transfer ring to guarantee there is enough room for the urb.
3733 * Update ISO URB start_frame and interval.
3734 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3735 * update the urb->start_frame by now.
3736 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3738 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3739 struct urb *urb, int slot_id, unsigned int ep_index)
3741 struct xhci_virt_device *xdev;
3742 struct xhci_ring *ep_ring;
3743 struct xhci_ep_ctx *ep_ctx;
3747 int num_tds, num_trbs, i;
3750 xdev = xhci->devs[slot_id];
3751 ep_ring = xdev->eps[ep_index].ring;
3752 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3755 num_tds = urb->number_of_packets;
3756 for (i = 0; i < num_tds; i++)
3757 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3759 /* Check the ring to guarantee there is enough room for the whole urb.
3760 * Do not insert any td of the urb to the ring if the check failed.
3762 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3763 num_trbs, true, mem_flags);
3767 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3768 start_frame &= 0x3fff;
3770 urb->start_frame = start_frame;
3771 if (urb->dev->speed == USB_SPEED_LOW ||
3772 urb->dev->speed == USB_SPEED_FULL)
3773 urb->start_frame >>= 3;
3775 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3776 ep_interval = urb->interval;
3777 /* Convert to microframes */
3778 if (urb->dev->speed == USB_SPEED_LOW ||
3779 urb->dev->speed == USB_SPEED_FULL)
3781 /* FIXME change this to a warning and a suggestion to use the new API
3782 * to set the polling interval (once the API is added).
3784 if (xhci_interval != ep_interval) {
3785 if (printk_ratelimit())
3786 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3787 " (%d microframe%s) than xHCI "
3788 "(%d microframe%s)\n",
3790 ep_interval == 1 ? "" : "s",
3792 xhci_interval == 1 ? "" : "s");
3793 urb->interval = xhci_interval;
3794 /* Convert back to frames for LS/FS devices */
3795 if (urb->dev->speed == USB_SPEED_LOW ||
3796 urb->dev->speed == USB_SPEED_FULL)
3799 return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3802 /**** Command Ring Operations ****/
3804 /* Generic function for queueing a command TRB on the command ring.
3805 * Check to make sure there's room on the command ring for one command TRB.
3806 * Also check that there's room reserved for commands that must not fail.
3807 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3808 * then only check for the number of reserved spots.
3809 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3810 * because the command event handler may want to resubmit a failed command.
3812 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3813 u32 field3, u32 field4, bool command_must_succeed)
3815 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3818 if (!command_must_succeed)
3821 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3822 reserved_trbs, false, GFP_ATOMIC);
3824 xhci_err(xhci, "ERR: No room for command on command ring\n");
3825 if (command_must_succeed)
3826 xhci_err(xhci, "ERR: Reserved TRB counting for "
3827 "unfailable commands failed.\n");
3830 queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3831 field3, field4 | xhci->cmd_ring->cycle_state);
3835 /* Queue a slot enable or disable request on the command ring */
3836 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3838 return queue_command(xhci, 0, 0, 0,
3839 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3842 /* Queue an address device command TRB */
3843 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3846 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3847 upper_32_bits(in_ctx_ptr), 0,
3848 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3852 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3853 u32 field1, u32 field2, u32 field3, u32 field4)
3855 return queue_command(xhci, field1, field2, field3, field4, false);
3858 /* Queue a reset device command TRB */
3859 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3861 return queue_command(xhci, 0, 0, 0,
3862 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3866 /* Queue a configure endpoint command TRB */
3867 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3868 u32 slot_id, bool command_must_succeed)
3870 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3871 upper_32_bits(in_ctx_ptr), 0,
3872 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3873 command_must_succeed);
3876 /* Queue an evaluate context command TRB */
3877 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3880 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3881 upper_32_bits(in_ctx_ptr), 0,
3882 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3887 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3888 * activity on an endpoint that is about to be suspended.
3890 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3891 unsigned int ep_index, int suspend)
3893 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3894 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3895 u32 type = TRB_TYPE(TRB_STOP_RING);
3896 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3898 return queue_command(xhci, 0, 0, 0,
3899 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3902 /* Set Transfer Ring Dequeue Pointer command.
3903 * This should not be used for endpoints that have streams enabled.
3905 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3906 unsigned int ep_index, unsigned int stream_id,
3907 struct xhci_segment *deq_seg,
3908 union xhci_trb *deq_ptr, u32 cycle_state)
3911 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3912 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3913 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3914 u32 type = TRB_TYPE(TRB_SET_DEQ);
3915 struct xhci_virt_ep *ep;
3917 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3919 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3920 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3924 ep = &xhci->devs[slot_id]->eps[ep_index];
3925 if ((ep->ep_state & SET_DEQ_PENDING)) {
3926 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3927 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3930 ep->queued_deq_seg = deq_seg;
3931 ep->queued_deq_ptr = deq_ptr;
3932 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3933 upper_32_bits(addr), trb_stream_id,
3934 trb_slot_id | trb_ep_index | type, false);
3937 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3938 unsigned int ep_index)
3940 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3941 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3942 u32 type = TRB_TYPE(TRB_RESET_EP);
3944 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,