2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
70 #include "xhci-trace.h"
72 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
73 struct xhci_virt_device *virt_dev,
74 struct xhci_event_cmd *event);
77 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
80 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
83 unsigned long segment_offset;
85 if (!seg || !trb || trb < seg->trbs)
88 segment_offset = trb - seg->trbs;
89 if (segment_offset > TRBS_PER_SEGMENT)
91 return seg->dma + (segment_offset * sizeof(*trb));
94 /* Does this link TRB point to the first segment in a ring,
95 * or was the previous TRB the last TRB on the last segment in the ERST?
97 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
98 struct xhci_segment *seg, union xhci_trb *trb)
100 if (ring == xhci->event_ring)
101 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
102 (seg->next == xhci->event_ring->first_seg);
104 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
107 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
108 * segment? I.e. would the updated event TRB pointer step off the end of the
111 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
112 struct xhci_segment *seg, union xhci_trb *trb)
114 if (ring == xhci->event_ring)
115 return trb == &seg->trbs[TRBS_PER_SEGMENT];
117 return TRB_TYPE_LINK_LE32(trb->link.control);
120 static int enqueue_is_link_trb(struct xhci_ring *ring)
122 struct xhci_link_trb *link = &ring->enqueue->link;
123 return TRB_TYPE_LINK_LE32(link->control);
126 union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring)
128 /* Enqueue pointer can be left pointing to the link TRB,
129 * we must handle that
131 if (TRB_TYPE_LINK_LE32(ring->enqueue->link.control))
132 return ring->enq_seg->next->trbs;
133 return ring->enqueue;
136 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
137 * TRB is in a new segment. This does not skip over link TRBs, and it does not
138 * effect the ring dequeue or enqueue pointers.
140 static void next_trb(struct xhci_hcd *xhci,
141 struct xhci_ring *ring,
142 struct xhci_segment **seg,
143 union xhci_trb **trb)
145 if (last_trb(xhci, ring, *seg, *trb)) {
147 *trb = ((*seg)->trbs);
154 * See Cycle bit rules. SW is the consumer for the event ring only.
155 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
157 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
162 * If this is not event ring, and the dequeue pointer
163 * is not on a link TRB, there is one more usable TRB
165 if (ring->type != TYPE_EVENT &&
166 !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
167 ring->num_trbs_free++;
171 * Update the dequeue pointer further if that was a link TRB or
172 * we're at the end of an event ring segment (which doesn't have
175 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
176 if (ring->type == TYPE_EVENT &&
177 last_trb_on_last_seg(xhci, ring,
178 ring->deq_seg, ring->dequeue)) {
179 ring->cycle_state ^= 1;
181 ring->deq_seg = ring->deq_seg->next;
182 ring->dequeue = ring->deq_seg->trbs;
186 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
190 * See Cycle bit rules. SW is the consumer for the event ring only.
191 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
193 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
194 * chain bit is set), then set the chain bit in all the following link TRBs.
195 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
196 * have their chain bit cleared (so that each Link TRB is a separate TD).
198 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
199 * set, but other sections talk about dealing with the chain bit set. This was
200 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
201 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
203 * @more_trbs_coming: Will you enqueue more TRBs before calling
204 * prepare_transfer()?
206 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
207 bool more_trbs_coming)
210 union xhci_trb *next;
212 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
213 /* If this is not event ring, there is one less usable TRB */
214 if (ring->type != TYPE_EVENT &&
215 !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
216 ring->num_trbs_free--;
217 next = ++(ring->enqueue);
220 /* Update the dequeue pointer further if that was a link TRB or we're at
221 * the end of an event ring segment (which doesn't have link TRBS)
223 while (last_trb(xhci, ring, ring->enq_seg, next)) {
224 if (ring->type != TYPE_EVENT) {
226 * If the caller doesn't plan on enqueueing more
227 * TDs before ringing the doorbell, then we
228 * don't want to give the link TRB to the
229 * hardware just yet. We'll give the link TRB
230 * back in prepare_ring() just before we enqueue
231 * the TD at the top of the ring.
233 if (!chain && !more_trbs_coming)
236 /* If we're not dealing with 0.95 hardware or
237 * isoc rings on AMD 0.96 host,
238 * carry over the chain bit of the previous TRB
239 * (which may mean the chain bit is cleared).
241 if (!(ring->type == TYPE_ISOC &&
242 (xhci->quirks & XHCI_AMD_0x96_HOST))
243 && !xhci_link_trb_quirk(xhci)) {
244 next->link.control &=
245 cpu_to_le32(~TRB_CHAIN);
246 next->link.control |=
249 /* Give this link TRB to the hardware */
251 next->link.control ^= cpu_to_le32(TRB_CYCLE);
253 /* Toggle the cycle bit after the last ring segment. */
254 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
255 ring->cycle_state = (ring->cycle_state ? 0 : 1);
258 ring->enq_seg = ring->enq_seg->next;
259 ring->enqueue = ring->enq_seg->trbs;
260 next = ring->enqueue;
265 * Check to see if there's room to enqueue num_trbs on the ring and make sure
266 * enqueue pointer will not advance into dequeue segment. See rules above.
268 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
269 unsigned int num_trbs)
271 int num_trbs_in_deq_seg;
273 if (ring->num_trbs_free < num_trbs)
276 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
277 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
278 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
285 /* Ring the host controller doorbell after placing a command on the ring */
286 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
288 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
291 xhci_dbg(xhci, "// Ding dong!\n");
292 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
293 /* Flush PCI posted writes */
294 readl(&xhci->dba->doorbell[0]);
297 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
302 xhci_dbg(xhci, "Abort command ring\n");
304 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
305 xhci_dbg(xhci, "The command ring isn't running, "
306 "Have the command ring been stopped?\n");
310 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
311 if (!(temp_64 & CMD_RING_RUNNING)) {
312 xhci_dbg(xhci, "Command ring had been stopped\n");
315 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
316 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
317 &xhci->op_regs->cmd_ring);
319 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
320 * time the completion od all xHCI commands, including
321 * the Command Abort operation. If software doesn't see
322 * CRR negated in a timely manner (e.g. longer than 5
323 * seconds), then it should assume that the there are
324 * larger problems with the xHC and assert HCRST.
326 ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
327 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
329 xhci_err(xhci, "Stopped the command ring failed, "
330 "maybe the host is dead\n");
331 xhci->xhc_state |= XHCI_STATE_DYING;
340 static int xhci_queue_cd(struct xhci_hcd *xhci,
341 struct xhci_command *command,
342 union xhci_trb *cmd_trb)
345 cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
348 INIT_LIST_HEAD(&cd->cancel_cmd_list);
350 cd->command = command;
351 cd->cmd_trb = cmd_trb;
352 list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
358 * Cancel the command which has issue.
360 * Some commands may hang due to waiting for acknowledgement from
361 * usb device. It is outside of the xHC's ability to control and
362 * will cause the command ring is blocked. When it occurs software
363 * should intervene to recover the command ring.
364 * See Section 4.6.1.1 and 4.6.1.2
366 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
367 union xhci_trb *cmd_trb)
372 spin_lock_irqsave(&xhci->lock, flags);
374 if (xhci->xhc_state & XHCI_STATE_DYING) {
375 xhci_warn(xhci, "Abort the command ring,"
376 " but the xHCI is dead.\n");
381 /* queue the cmd desriptor to cancel_cmd_list */
382 retval = xhci_queue_cd(xhci, command, cmd_trb);
384 xhci_warn(xhci, "Queuing command descriptor failed.\n");
388 /* abort command ring */
389 retval = xhci_abort_cmd_ring(xhci);
391 xhci_err(xhci, "Abort command ring failed\n");
392 if (unlikely(retval == -ESHUTDOWN)) {
393 spin_unlock_irqrestore(&xhci->lock, flags);
394 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
395 xhci_dbg(xhci, "xHCI host controller is dead.\n");
401 spin_unlock_irqrestore(&xhci->lock, flags);
405 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
406 unsigned int slot_id,
407 unsigned int ep_index,
408 unsigned int stream_id)
410 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
411 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
412 unsigned int ep_state = ep->ep_state;
414 /* Don't ring the doorbell for this endpoint if there are pending
415 * cancellations because we don't want to interrupt processing.
416 * We don't want to restart any stream rings if there's a set dequeue
417 * pointer command pending because the device can choose to start any
418 * stream once the endpoint is on the HW schedule.
419 * FIXME - check all the stream rings for pending cancellations.
421 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
422 (ep_state & EP_HALTED))
424 writel(DB_VALUE(ep_index, stream_id), db_addr);
425 /* The CPU has better things to do at this point than wait for a
426 * write-posting flush. It'll get there soon enough.
430 /* Ring the doorbell for any rings with pending URBs */
431 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
432 unsigned int slot_id,
433 unsigned int ep_index)
435 unsigned int stream_id;
436 struct xhci_virt_ep *ep;
438 ep = &xhci->devs[slot_id]->eps[ep_index];
440 /* A ring has pending URBs if its TD list is not empty */
441 if (!(ep->ep_state & EP_HAS_STREAMS)) {
442 if (ep->ring && !(list_empty(&ep->ring->td_list)))
443 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
447 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
449 struct xhci_stream_info *stream_info = ep->stream_info;
450 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
451 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
457 * Find the segment that trb is in. Start searching in start_seg.
458 * If we must move past a segment that has a link TRB with a toggle cycle state
459 * bit set, then we will toggle the value pointed at by cycle_state.
461 static struct xhci_segment *find_trb_seg(
462 struct xhci_segment *start_seg,
463 union xhci_trb *trb, int *cycle_state)
465 struct xhci_segment *cur_seg = start_seg;
466 struct xhci_generic_trb *generic_trb;
468 while (cur_seg->trbs > trb ||
469 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
470 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
471 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
473 cur_seg = cur_seg->next;
474 if (cur_seg == start_seg)
475 /* Looped over the entire list. Oops! */
482 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
483 unsigned int slot_id, unsigned int ep_index,
484 unsigned int stream_id)
486 struct xhci_virt_ep *ep;
488 ep = &xhci->devs[slot_id]->eps[ep_index];
489 /* Common case: no streams */
490 if (!(ep->ep_state & EP_HAS_STREAMS))
493 if (stream_id == 0) {
495 "WARN: Slot ID %u, ep index %u has streams, "
496 "but URB has no stream ID.\n",
501 if (stream_id < ep->stream_info->num_streams)
502 return ep->stream_info->stream_rings[stream_id];
505 "WARN: Slot ID %u, ep index %u has "
506 "stream IDs 1 to %u allocated, "
507 "but stream ID %u is requested.\n",
509 ep->stream_info->num_streams - 1,
514 /* Get the right ring for the given URB.
515 * If the endpoint supports streams, boundary check the URB's stream ID.
516 * If the endpoint doesn't support streams, return the singular endpoint ring.
518 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
521 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
522 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
526 * Move the xHC's endpoint ring dequeue pointer past cur_td.
527 * Record the new state of the xHC's endpoint ring dequeue segment,
528 * dequeue pointer, and new consumer cycle state in state.
529 * Update our internal representation of the ring's dequeue pointer.
531 * We do this in three jumps:
532 * - First we update our new ring state to be the same as when the xHC stopped.
533 * - Then we traverse the ring to find the segment that contains
534 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
535 * any link TRBs with the toggle cycle bit set.
536 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
537 * if we've moved it past a link TRB with the toggle cycle bit set.
539 * Some of the uses of xhci_generic_trb are grotty, but if they're done
540 * with correct __le32 accesses they should work fine. Only users of this are
543 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
544 unsigned int slot_id, unsigned int ep_index,
545 unsigned int stream_id, struct xhci_td *cur_td,
546 struct xhci_dequeue_state *state)
548 struct xhci_virt_device *dev = xhci->devs[slot_id];
549 struct xhci_virt_ep *ep = &dev->eps[ep_index];
550 struct xhci_ring *ep_ring;
551 struct xhci_generic_trb *trb;
554 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
555 ep_index, stream_id);
557 xhci_warn(xhci, "WARN can't find new dequeue state "
558 "for invalid stream ID %u.\n",
562 state->new_cycle_state = 0;
563 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
564 "Finding segment containing stopped TRB.");
565 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
566 dev->eps[ep_index].stopped_trb,
567 &state->new_cycle_state);
568 if (!state->new_deq_seg) {
573 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
574 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
575 "Finding endpoint context");
576 /* 4.6.9 the css flag is written to the stream context for streams */
577 if (ep->ep_state & EP_HAS_STREAMS) {
578 struct xhci_stream_ctx *ctx =
579 &ep->stream_info->stream_ctx_array[stream_id];
580 state->new_cycle_state = 0x1 & le64_to_cpu(ctx->stream_ring);
582 struct xhci_ep_ctx *ep_ctx
583 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
584 state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
587 state->new_deq_ptr = cur_td->last_trb;
588 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
589 "Finding segment containing last TRB in TD.");
590 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
592 &state->new_cycle_state);
593 if (!state->new_deq_seg) {
598 trb = &state->new_deq_ptr->generic;
599 if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
600 (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
601 state->new_cycle_state ^= 0x1;
602 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
605 * If there is only one segment in a ring, find_trb_seg()'s while loop
606 * will not run, and it will return before it has a chance to see if it
607 * needs to toggle the cycle bit. It can't tell if the stalled transfer
608 * ended just before the link TRB on a one-segment ring, or if the TD
609 * wrapped around the top of the ring, because it doesn't have the TD in
610 * question. Look for the one-segment case where stalled TRB's address
611 * is greater than the new dequeue pointer address.
613 if (ep_ring->first_seg == ep_ring->first_seg->next &&
614 state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
615 state->new_cycle_state ^= 0x1;
616 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
617 "Cycle state = 0x%x", state->new_cycle_state);
619 /* Don't update the ring cycle state for the producer (us). */
620 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
621 "New dequeue segment = %p (virtual)",
623 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
624 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
625 "New dequeue pointer = 0x%llx (DMA)",
626 (unsigned long long) addr);
629 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
630 * (The last TRB actually points to the ring enqueue pointer, which is not part
631 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
633 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
634 struct xhci_td *cur_td, bool flip_cycle)
636 struct xhci_segment *cur_seg;
637 union xhci_trb *cur_trb;
639 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
641 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
642 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
643 /* Unchain any chained Link TRBs, but
644 * leave the pointers intact.
646 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
647 /* Flip the cycle bit (link TRBs can't be the first
651 cur_trb->generic.field[3] ^=
652 cpu_to_le32(TRB_CYCLE);
653 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
654 "Cancel (unchain) link TRB");
655 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
656 "Address = %p (0x%llx dma); "
657 "in seg %p (0x%llx dma)",
659 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
661 (unsigned long long)cur_seg->dma);
663 cur_trb->generic.field[0] = 0;
664 cur_trb->generic.field[1] = 0;
665 cur_trb->generic.field[2] = 0;
666 /* Preserve only the cycle bit of this TRB */
667 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
668 /* Flip the cycle bit except on the first or last TRB */
669 if (flip_cycle && cur_trb != cur_td->first_trb &&
670 cur_trb != cur_td->last_trb)
671 cur_trb->generic.field[3] ^=
672 cpu_to_le32(TRB_CYCLE);
673 cur_trb->generic.field[3] |= cpu_to_le32(
674 TRB_TYPE(TRB_TR_NOOP));
675 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
676 "TRB to noop at offset 0x%llx",
678 xhci_trb_virt_to_dma(cur_seg, cur_trb));
680 if (cur_trb == cur_td->last_trb)
685 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
686 unsigned int ep_index, unsigned int stream_id,
687 struct xhci_segment *deq_seg,
688 union xhci_trb *deq_ptr, u32 cycle_state);
690 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
691 unsigned int slot_id, unsigned int ep_index,
692 unsigned int stream_id,
693 struct xhci_dequeue_state *deq_state)
695 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
697 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
698 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
699 "new deq ptr = %p (0x%llx dma), new cycle = %u",
700 deq_state->new_deq_seg,
701 (unsigned long long)deq_state->new_deq_seg->dma,
702 deq_state->new_deq_ptr,
703 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
704 deq_state->new_cycle_state);
705 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
706 deq_state->new_deq_seg,
707 deq_state->new_deq_ptr,
708 (u32) deq_state->new_cycle_state);
709 /* Stop the TD queueing code from ringing the doorbell until
710 * this command completes. The HC won't set the dequeue pointer
711 * if the ring is running, and ringing the doorbell starts the
714 ep->ep_state |= SET_DEQ_PENDING;
717 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
718 struct xhci_virt_ep *ep)
720 ep->ep_state &= ~EP_HALT_PENDING;
721 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
722 * timer is running on another CPU, we don't decrement stop_cmds_pending
723 * (since we didn't successfully stop the watchdog timer).
725 if (del_timer(&ep->stop_cmd_timer))
726 ep->stop_cmds_pending--;
729 /* Must be called with xhci->lock held in interrupt context */
730 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
731 struct xhci_td *cur_td, int status)
735 struct urb_priv *urb_priv;
738 urb_priv = urb->hcpriv;
740 hcd = bus_to_hcd(urb->dev->bus);
742 /* Only giveback urb when this is the last td in urb */
743 if (urb_priv->td_cnt == urb_priv->length) {
744 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
745 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
746 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
747 if (xhci->quirks & XHCI_AMD_PLL_FIX)
748 usb_amd_quirk_pll_enable();
751 usb_hcd_unlink_urb_from_ep(hcd, urb);
753 spin_unlock(&xhci->lock);
754 usb_hcd_giveback_urb(hcd, urb, status);
755 xhci_urb_free_priv(xhci, urb_priv);
756 spin_lock(&xhci->lock);
761 * When we get a command completion for a Stop Endpoint Command, we need to
762 * unlink any cancelled TDs from the ring. There are two ways to do that:
764 * 1. If the HW was in the middle of processing the TD that needs to be
765 * cancelled, then we must move the ring's dequeue pointer past the last TRB
766 * in the TD with a Set Dequeue Pointer Command.
767 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
768 * bit cleared) so that the HW will skip over them.
770 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
771 union xhci_trb *trb, struct xhci_event_cmd *event)
773 unsigned int ep_index;
774 struct xhci_virt_device *virt_dev;
775 struct xhci_ring *ep_ring;
776 struct xhci_virt_ep *ep;
777 struct list_head *entry;
778 struct xhci_td *cur_td = NULL;
779 struct xhci_td *last_unlinked_td;
781 struct xhci_dequeue_state deq_state;
783 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
784 virt_dev = xhci->devs[slot_id];
786 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
789 xhci_warn(xhci, "Stop endpoint command "
790 "completion for disabled slot %u\n",
795 memset(&deq_state, 0, sizeof(deq_state));
796 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
797 ep = &xhci->devs[slot_id]->eps[ep_index];
799 if (list_empty(&ep->cancelled_td_list)) {
800 xhci_stop_watchdog_timer_in_irq(xhci, ep);
801 ep->stopped_td = NULL;
802 ep->stopped_trb = NULL;
803 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
807 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
808 * We have the xHCI lock, so nothing can modify this list until we drop
809 * it. We're also in the event handler, so we can't get re-interrupted
810 * if another Stop Endpoint command completes
812 list_for_each(entry, &ep->cancelled_td_list) {
813 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
814 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
815 "Removing canceled TD starting at 0x%llx (dma).",
816 (unsigned long long)xhci_trb_virt_to_dma(
817 cur_td->start_seg, cur_td->first_trb));
818 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
820 /* This shouldn't happen unless a driver is mucking
821 * with the stream ID after submission. This will
822 * leave the TD on the hardware ring, and the hardware
823 * will try to execute it, and may access a buffer
824 * that has already been freed. In the best case, the
825 * hardware will execute it, and the event handler will
826 * ignore the completion event for that TD, since it was
827 * removed from the td_list for that endpoint. In
828 * short, don't muck with the stream ID after
831 xhci_warn(xhci, "WARN Cancelled URB %p "
832 "has invalid stream ID %u.\n",
834 cur_td->urb->stream_id);
835 goto remove_finished_td;
838 * If we stopped on the TD we need to cancel, then we have to
839 * move the xHC endpoint ring dequeue pointer past this TD.
841 if (cur_td == ep->stopped_td)
842 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
843 cur_td->urb->stream_id,
846 td_to_noop(xhci, ep_ring, cur_td, false);
849 * The event handler won't see a completion for this TD anymore,
850 * so remove it from the endpoint ring's TD list. Keep it in
851 * the cancelled TD list for URB completion later.
853 list_del_init(&cur_td->td_list);
855 last_unlinked_td = cur_td;
856 xhci_stop_watchdog_timer_in_irq(xhci, ep);
858 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
859 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
860 xhci_queue_new_dequeue_state(xhci,
862 ep->stopped_td->urb->stream_id,
864 xhci_ring_cmd_db(xhci);
866 /* Otherwise ring the doorbell(s) to restart queued transfers */
867 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
870 /* Clear stopped_td and stopped_trb if endpoint is not halted */
871 if (!(ep->ep_state & EP_HALTED)) {
872 ep->stopped_td = NULL;
873 ep->stopped_trb = NULL;
877 * Drop the lock and complete the URBs in the cancelled TD list.
878 * New TDs to be cancelled might be added to the end of the list before
879 * we can complete all the URBs for the TDs we already unlinked.
880 * So stop when we've completed the URB for the last TD we unlinked.
883 cur_td = list_entry(ep->cancelled_td_list.next,
884 struct xhci_td, cancelled_td_list);
885 list_del_init(&cur_td->cancelled_td_list);
887 /* Clean up the cancelled URB */
888 /* Doesn't matter what we pass for status, since the core will
889 * just overwrite it (because the URB has been unlinked).
891 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
893 /* Stop processing the cancelled list if the watchdog timer is
896 if (xhci->xhc_state & XHCI_STATE_DYING)
898 } while (cur_td != last_unlinked_td);
900 /* Return to the event handler with xhci->lock re-acquired */
903 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
905 struct xhci_td *cur_td;
907 while (!list_empty(&ring->td_list)) {
908 cur_td = list_first_entry(&ring->td_list,
909 struct xhci_td, td_list);
910 list_del_init(&cur_td->td_list);
911 if (!list_empty(&cur_td->cancelled_td_list))
912 list_del_init(&cur_td->cancelled_td_list);
913 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
917 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
918 int slot_id, int ep_index)
920 struct xhci_td *cur_td;
921 struct xhci_virt_ep *ep;
922 struct xhci_ring *ring;
924 ep = &xhci->devs[slot_id]->eps[ep_index];
925 if ((ep->ep_state & EP_HAS_STREAMS) ||
926 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
929 for (stream_id = 0; stream_id < ep->stream_info->num_streams;
931 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
932 "Killing URBs for slot ID %u, ep index %u, stream %u",
933 slot_id, ep_index, stream_id + 1);
934 xhci_kill_ring_urbs(xhci,
935 ep->stream_info->stream_rings[stream_id]);
941 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
942 "Killing URBs for slot ID %u, ep index %u",
944 xhci_kill_ring_urbs(xhci, ring);
946 while (!list_empty(&ep->cancelled_td_list)) {
947 cur_td = list_first_entry(&ep->cancelled_td_list,
948 struct xhci_td, cancelled_td_list);
949 list_del_init(&cur_td->cancelled_td_list);
950 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
954 /* Watchdog timer function for when a stop endpoint command fails to complete.
955 * In this case, we assume the host controller is broken or dying or dead. The
956 * host may still be completing some other events, so we have to be careful to
957 * let the event ring handler and the URB dequeueing/enqueueing functions know
958 * through xhci->state.
960 * The timer may also fire if the host takes a very long time to respond to the
961 * command, and the stop endpoint command completion handler cannot delete the
962 * timer before the timer function is called. Another endpoint cancellation may
963 * sneak in before the timer function can grab the lock, and that may queue
964 * another stop endpoint command and add the timer back. So we cannot use a
965 * simple flag to say whether there is a pending stop endpoint command for a
966 * particular endpoint.
968 * Instead we use a combination of that flag and a counter for the number of
969 * pending stop endpoint commands. If the timer is the tail end of the last
970 * stop endpoint command, and the endpoint's command is still pending, we assume
973 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
975 struct xhci_hcd *xhci;
976 struct xhci_virt_ep *ep;
980 ep = (struct xhci_virt_ep *) arg;
983 spin_lock_irqsave(&xhci->lock, flags);
985 ep->stop_cmds_pending--;
986 if (xhci->xhc_state & XHCI_STATE_DYING) {
987 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
988 "Stop EP timer ran, but another timer marked "
989 "xHCI as DYING, exiting.");
990 spin_unlock_irqrestore(&xhci->lock, flags);
993 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
994 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
995 "Stop EP timer ran, but no command pending, "
997 spin_unlock_irqrestore(&xhci->lock, flags);
1001 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
1002 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
1003 /* Oops, HC is dead or dying or at least not responding to the stop
1006 xhci->xhc_state |= XHCI_STATE_DYING;
1007 /* Disable interrupts from the host controller and start halting it */
1009 spin_unlock_irqrestore(&xhci->lock, flags);
1011 ret = xhci_halt(xhci);
1013 spin_lock_irqsave(&xhci->lock, flags);
1015 /* This is bad; the host is not responding to commands and it's
1016 * not allowing itself to be halted. At least interrupts are
1017 * disabled. If we call usb_hc_died(), it will attempt to
1018 * disconnect all device drivers under this host. Those
1019 * disconnect() methods will wait for all URBs to be unlinked,
1020 * so we must complete them.
1022 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
1023 xhci_warn(xhci, "Completing active URBs anyway.\n");
1024 /* We could turn all TDs on the rings to no-ops. This won't
1025 * help if the host has cached part of the ring, and is slow if
1026 * we want to preserve the cycle bit. Skip it and hope the host
1027 * doesn't touch the memory.
1030 for (i = 0; i < MAX_HC_SLOTS; i++) {
1033 for (j = 0; j < 31; j++)
1034 xhci_kill_endpoint_urbs(xhci, i, j);
1036 spin_unlock_irqrestore(&xhci->lock, flags);
1037 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1038 "Calling usb_hc_died()");
1039 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1040 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1041 "xHCI host controller is dead.");
1045 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1046 struct xhci_virt_device *dev,
1047 struct xhci_ring *ep_ring,
1048 unsigned int ep_index)
1050 union xhci_trb *dequeue_temp;
1051 int num_trbs_free_temp;
1052 bool revert = false;
1054 num_trbs_free_temp = ep_ring->num_trbs_free;
1055 dequeue_temp = ep_ring->dequeue;
1057 /* If we get two back-to-back stalls, and the first stalled transfer
1058 * ends just before a link TRB, the dequeue pointer will be left on
1059 * the link TRB by the code in the while loop. So we have to update
1060 * the dequeue pointer one segment further, or we'll jump off
1061 * the segment into la-la-land.
1063 if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
1064 ep_ring->deq_seg = ep_ring->deq_seg->next;
1065 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1068 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1069 /* We have more usable TRBs */
1070 ep_ring->num_trbs_free++;
1072 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
1073 ep_ring->dequeue)) {
1074 if (ep_ring->dequeue ==
1075 dev->eps[ep_index].queued_deq_ptr)
1077 ep_ring->deq_seg = ep_ring->deq_seg->next;
1078 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1080 if (ep_ring->dequeue == dequeue_temp) {
1087 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1088 ep_ring->num_trbs_free = num_trbs_free_temp;
1093 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1094 * we need to clear the set deq pending flag in the endpoint ring state, so that
1095 * the TD queueing code can ring the doorbell again. We also need to ring the
1096 * endpoint doorbell to restart the ring, but only if there aren't more
1097 * cancellations pending.
1099 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1100 union xhci_trb *trb, u32 cmd_comp_code)
1102 unsigned int ep_index;
1103 unsigned int stream_id;
1104 struct xhci_ring *ep_ring;
1105 struct xhci_virt_device *dev;
1106 struct xhci_virt_ep *ep;
1107 struct xhci_ep_ctx *ep_ctx;
1108 struct xhci_slot_ctx *slot_ctx;
1110 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1111 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1112 dev = xhci->devs[slot_id];
1113 ep = &dev->eps[ep_index];
1115 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1117 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1119 /* XXX: Harmless??? */
1120 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1124 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1125 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1127 if (cmd_comp_code != COMP_SUCCESS) {
1128 unsigned int ep_state;
1129 unsigned int slot_state;
1131 switch (cmd_comp_code) {
1133 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1135 case COMP_CTX_STATE:
1136 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1137 ep_state = le32_to_cpu(ep_ctx->ep_info);
1138 ep_state &= EP_STATE_MASK;
1139 slot_state = le32_to_cpu(slot_ctx->dev_state);
1140 slot_state = GET_SLOT_STATE(slot_state);
1141 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1142 "Slot state = %u, EP state = %u",
1143 slot_state, ep_state);
1146 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1150 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1154 /* OK what do we do now? The endpoint state is hosed, and we
1155 * should never get to this point if the synchronization between
1156 * queueing, and endpoint state are correct. This might happen
1157 * if the device gets disconnected after we've finished
1158 * cancelling URBs, which might not be an error...
1162 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1163 if (ep->ep_state & EP_HAS_STREAMS) {
1164 struct xhci_stream_ctx *ctx =
1165 &ep->stream_info->stream_ctx_array[stream_id];
1166 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1168 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1170 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1171 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1172 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1173 ep->queued_deq_ptr) == deq) {
1174 /* Update the ring's dequeue segment and dequeue pointer
1175 * to reflect the new position.
1177 update_ring_for_set_deq_completion(xhci, dev,
1180 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1181 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1182 ep->queued_deq_seg, ep->queued_deq_ptr);
1186 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1187 dev->eps[ep_index].queued_deq_seg = NULL;
1188 dev->eps[ep_index].queued_deq_ptr = NULL;
1189 /* Restart any rings with pending URBs */
1190 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1193 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1194 union xhci_trb *trb, u32 cmd_comp_code)
1196 unsigned int ep_index;
1198 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1199 /* This command will only fail if the endpoint wasn't halted,
1200 * but we don't care.
1202 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1203 "Ignoring reset ep completion code of %u", cmd_comp_code);
1205 /* HW with the reset endpoint quirk needs to have a configure endpoint
1206 * command complete before the endpoint can be used. Queue that here
1207 * because the HW can't handle two commands being queued in a row.
1209 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1210 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1211 "Queueing configure endpoint command");
1212 xhci_queue_configure_endpoint(xhci,
1213 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1215 xhci_ring_cmd_db(xhci);
1217 /* Clear our internal halted state and restart the ring(s) */
1218 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1219 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1223 /* Complete the command and detele it from the devcie's command queue.
1225 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1226 struct xhci_command *command, u32 status)
1228 command->status = status;
1229 list_del(&command->cmd_list);
1230 if (command->completion)
1231 complete(command->completion);
1233 xhci_free_command(xhci, command);
1237 /* Check to see if a command in the device's command queue matches this one.
1238 * Signal the completion or free the command, and return 1. Return 0 if the
1239 * completed command isn't at the head of the command list.
1241 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1242 struct xhci_virt_device *virt_dev,
1243 struct xhci_event_cmd *event)
1245 struct xhci_command *command;
1247 if (list_empty(&virt_dev->cmd_list))
1250 command = list_entry(virt_dev->cmd_list.next,
1251 struct xhci_command, cmd_list);
1252 if (xhci->cmd_ring->dequeue != command->command_trb)
1255 xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1256 GET_COMP_CODE(le32_to_cpu(event->status)));
1261 * Finding the command trb need to be cancelled and modifying it to
1262 * NO OP command. And if the command is in device's command wait
1263 * list, finishing and freeing it.
1265 * If we can't find the command trb, we think it had already been
1268 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1270 struct xhci_segment *cur_seg;
1271 union xhci_trb *cmd_trb;
1274 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1277 /* find the current segment of command ring */
1278 cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1279 xhci->cmd_ring->dequeue, &cycle_state);
1282 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1283 xhci->cmd_ring->dequeue,
1284 (unsigned long long)
1285 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1286 xhci->cmd_ring->dequeue));
1287 xhci_debug_ring(xhci, xhci->cmd_ring);
1288 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1292 /* find the command trb matched by cd from command ring */
1293 for (cmd_trb = xhci->cmd_ring->dequeue;
1294 cmd_trb != xhci->cmd_ring->enqueue;
1295 next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1296 /* If the trb is link trb, continue */
1297 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1300 if (cur_cd->cmd_trb == cmd_trb) {
1302 /* If the command in device's command list, we should
1303 * finish it and free the command structure.
1305 if (cur_cd->command)
1306 xhci_complete_cmd_in_cmd_wait_list(xhci,
1307 cur_cd->command, COMP_CMD_STOP);
1309 /* get cycle state from the origin command trb */
1310 cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1313 /* modify the command trb to NO OP command */
1314 cmd_trb->generic.field[0] = 0;
1315 cmd_trb->generic.field[1] = 0;
1316 cmd_trb->generic.field[2] = 0;
1317 cmd_trb->generic.field[3] = cpu_to_le32(
1318 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1324 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1326 struct xhci_cd *cur_cd, *next_cd;
1328 if (list_empty(&xhci->cancel_cmd_list))
1331 list_for_each_entry_safe(cur_cd, next_cd,
1332 &xhci->cancel_cmd_list, cancel_cmd_list) {
1333 xhci_cmd_to_noop(xhci, cur_cd);
1334 list_del(&cur_cd->cancel_cmd_list);
1340 * traversing the cancel_cmd_list. If the command descriptor according
1341 * to cmd_trb is found, the function free it and return 1, otherwise
1344 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1345 union xhci_trb *cmd_trb)
1347 struct xhci_cd *cur_cd, *next_cd;
1349 if (list_empty(&xhci->cancel_cmd_list))
1352 list_for_each_entry_safe(cur_cd, next_cd,
1353 &xhci->cancel_cmd_list, cancel_cmd_list) {
1354 if (cur_cd->cmd_trb == cmd_trb) {
1355 if (cur_cd->command)
1356 xhci_complete_cmd_in_cmd_wait_list(xhci,
1357 cur_cd->command, COMP_CMD_STOP);
1358 list_del(&cur_cd->cancel_cmd_list);
1368 * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1369 * trb pointed by the command ring dequeue pointer is the trb we want to
1370 * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1371 * traverse the cancel_cmd_list to trun the all of the commands according
1372 * to command descriptor to NO-OP trb.
1374 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1375 int cmd_trb_comp_code)
1377 int cur_trb_is_good = 0;
1379 /* Searching the cmd trb pointed by the command ring dequeue
1380 * pointer in command descriptor list. If it is found, free it.
1382 cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1383 xhci->cmd_ring->dequeue);
1385 if (cmd_trb_comp_code == COMP_CMD_ABORT)
1386 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1387 else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1388 /* traversing the cancel_cmd_list and canceling
1389 * the command according to command descriptor
1391 xhci_cancel_cmd_in_cd_list(xhci);
1393 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1395 * ring command ring doorbell again to restart the
1398 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1399 xhci_ring_cmd_db(xhci);
1401 return cur_trb_is_good;
1404 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1407 if (cmd_comp_code == COMP_SUCCESS)
1408 xhci->slot_id = slot_id;
1411 complete(&xhci->addr_dev);
1414 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1416 struct xhci_virt_device *virt_dev;
1418 virt_dev = xhci->devs[slot_id];
1421 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1422 /* Delete default control endpoint resources */
1423 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1424 xhci_free_virt_device(xhci, slot_id);
1427 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1428 struct xhci_event_cmd *event, u32 cmd_comp_code)
1430 struct xhci_virt_device *virt_dev;
1431 struct xhci_input_control_ctx *ctrl_ctx;
1432 unsigned int ep_index;
1433 unsigned int ep_state;
1434 u32 add_flags, drop_flags;
1436 virt_dev = xhci->devs[slot_id];
1437 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1440 * Configure endpoint commands can come from the USB core
1441 * configuration or alt setting changes, or because the HW
1442 * needed an extra configure endpoint command after a reset
1443 * endpoint command or streams were being configured.
1444 * If the command was for a halted endpoint, the xHCI driver
1445 * is not waiting on the configure endpoint command.
1447 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1449 xhci_warn(xhci, "Could not get input context, bad type.\n");
1453 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1454 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1455 /* Input ctx add_flags are the endpoint index plus one */
1456 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1458 /* A usb_set_interface() call directly after clearing a halted
1459 * condition may race on this quirky hardware. Not worth
1460 * worrying about, since this is prototype hardware. Not sure
1461 * if this will work for streams, but streams support was
1462 * untested on this prototype.
1464 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1465 ep_index != (unsigned int) -1 &&
1466 add_flags - SLOT_FLAG == drop_flags) {
1467 ep_state = virt_dev->eps[ep_index].ep_state;
1468 if (!(ep_state & EP_HALTED))
1469 goto bandwidth_change;
1470 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1471 "Completed config ep cmd - "
1472 "last ep index = %d, state = %d",
1473 ep_index, ep_state);
1474 /* Clear internal halted state and restart ring(s) */
1475 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1476 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1480 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1481 "Completed config ep cmd");
1482 virt_dev->cmd_status = cmd_comp_code;
1483 complete(&virt_dev->cmd_completion);
1487 static void xhci_handle_cmd_eval_ctx(struct xhci_hcd *xhci, int slot_id,
1488 struct xhci_event_cmd *event, u32 cmd_comp_code)
1490 struct xhci_virt_device *virt_dev;
1492 virt_dev = xhci->devs[slot_id];
1493 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1495 virt_dev->cmd_status = cmd_comp_code;
1496 complete(&virt_dev->cmd_completion);
1499 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id,
1502 xhci->devs[slot_id]->cmd_status = cmd_comp_code;
1503 complete(&xhci->addr_dev);
1506 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1507 struct xhci_event_cmd *event)
1509 struct xhci_virt_device *virt_dev;
1511 xhci_dbg(xhci, "Completed reset device command.\n");
1512 virt_dev = xhci->devs[slot_id];
1514 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1516 xhci_warn(xhci, "Reset device command completion "
1517 "for disabled slot %u\n", slot_id);
1520 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1521 struct xhci_event_cmd *event)
1523 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1524 xhci->error_bitmask |= 1 << 6;
1527 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1528 "NEC firmware version %2x.%02x",
1529 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1530 NEC_FW_MINOR(le32_to_cpu(event->status)));
1533 static void handle_cmd_completion(struct xhci_hcd *xhci,
1534 struct xhci_event_cmd *event)
1536 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1538 dma_addr_t cmd_dequeue_dma;
1540 union xhci_trb *cmd_trb;
1543 cmd_dma = le64_to_cpu(event->cmd_trb);
1544 cmd_trb = xhci->cmd_ring->dequeue;
1545 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1547 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1548 if (cmd_dequeue_dma == 0) {
1549 xhci->error_bitmask |= 1 << 4;
1552 /* Does the DMA address match our internal dequeue pointer address? */
1553 if (cmd_dma != (u64) cmd_dequeue_dma) {
1554 xhci->error_bitmask |= 1 << 5;
1558 trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1560 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1561 if (cmd_comp_code == COMP_CMD_ABORT || cmd_comp_code == COMP_CMD_STOP) {
1562 /* If the return value is 0, we think the trb pointed by
1563 * command ring dequeue pointer is a good trb. The good
1564 * trb means we don't want to cancel the trb, but it have
1565 * been stopped by host. So we should handle it normally.
1566 * Otherwise, driver should invoke inc_deq() and return.
1568 if (handle_stopped_cmd_ring(xhci, cmd_comp_code)) {
1569 inc_deq(xhci, xhci->cmd_ring);
1572 /* There is no command to handle if we get a stop event when the
1573 * command ring is empty, event->cmd_trb points to the next
1576 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1580 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1582 case TRB_ENABLE_SLOT:
1583 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1585 case TRB_DISABLE_SLOT:
1586 xhci_handle_cmd_disable_slot(xhci, slot_id);
1589 xhci_handle_cmd_config_ep(xhci, slot_id, event, cmd_comp_code);
1591 case TRB_EVAL_CONTEXT:
1592 xhci_handle_cmd_eval_ctx(xhci, slot_id, event, cmd_comp_code);
1595 xhci_handle_cmd_addr_dev(xhci, slot_id, cmd_comp_code);
1598 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1599 le32_to_cpu(cmd_trb->generic.field[3])));
1600 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1603 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1604 le32_to_cpu(cmd_trb->generic.field[3])));
1605 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1610 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1611 le32_to_cpu(cmd_trb->generic.field[3])));
1612 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1615 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1616 le32_to_cpu(cmd_trb->generic.field[3])));
1617 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1619 case TRB_NEC_GET_FW:
1620 xhci_handle_cmd_nec_get_fw(xhci, event);
1623 /* Skip over unknown commands on the event ring */
1624 xhci->error_bitmask |= 1 << 6;
1627 inc_deq(xhci, xhci->cmd_ring);
1630 static void handle_vendor_event(struct xhci_hcd *xhci,
1631 union xhci_trb *event)
1635 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1636 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1637 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1638 handle_cmd_completion(xhci, &event->event_cmd);
1641 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1642 * port registers -- USB 3.0 and USB 2.0).
1644 * Returns a zero-based port number, which is suitable for indexing into each of
1645 * the split roothubs' port arrays and bus state arrays.
1646 * Add one to it in order to call xhci_find_slot_id_by_port.
1648 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1649 struct xhci_hcd *xhci, u32 port_id)
1652 unsigned int num_similar_speed_ports = 0;
1654 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1655 * and usb2_ports are 0-based indexes. Count the number of similar
1656 * speed ports, up to 1 port before this port.
1658 for (i = 0; i < (port_id - 1); i++) {
1659 u8 port_speed = xhci->port_array[i];
1662 * Skip ports that don't have known speeds, or have duplicate
1663 * Extended Capabilities port speed entries.
1665 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1669 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1670 * 1.1 ports are under the USB 2.0 hub. If the port speed
1671 * matches the device speed, it's a similar speed port.
1673 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1674 num_similar_speed_ports++;
1676 return num_similar_speed_ports;
1679 static void handle_device_notification(struct xhci_hcd *xhci,
1680 union xhci_trb *event)
1683 struct usb_device *udev;
1685 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1686 if (!xhci->devs[slot_id]) {
1687 xhci_warn(xhci, "Device Notification event for "
1688 "unused slot %u\n", slot_id);
1692 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1694 udev = xhci->devs[slot_id]->udev;
1695 if (udev && udev->parent)
1696 usb_wakeup_notification(udev->parent, udev->portnum);
1699 static void handle_port_status(struct xhci_hcd *xhci,
1700 union xhci_trb *event)
1702 struct usb_hcd *hcd;
1707 unsigned int faked_port_index;
1709 struct xhci_bus_state *bus_state;
1710 __le32 __iomem **port_array;
1711 bool bogus_port_status = false;
1713 /* Port status change events always have a successful completion code */
1714 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1715 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1716 xhci->error_bitmask |= 1 << 8;
1718 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1719 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1721 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1722 if ((port_id <= 0) || (port_id > max_ports)) {
1723 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1724 inc_deq(xhci, xhci->event_ring);
1728 /* Figure out which usb_hcd this port is attached to:
1729 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1731 major_revision = xhci->port_array[port_id - 1];
1733 /* Find the right roothub. */
1734 hcd = xhci_to_hcd(xhci);
1735 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1736 hcd = xhci->shared_hcd;
1738 if (major_revision == 0) {
1739 xhci_warn(xhci, "Event for port %u not in "
1740 "Extended Capabilities, ignoring.\n",
1742 bogus_port_status = true;
1745 if (major_revision == DUPLICATE_ENTRY) {
1746 xhci_warn(xhci, "Event for port %u duplicated in"
1747 "Extended Capabilities, ignoring.\n",
1749 bogus_port_status = true;
1754 * Hardware port IDs reported by a Port Status Change Event include USB
1755 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1756 * resume event, but we first need to translate the hardware port ID
1757 * into the index into the ports on the correct split roothub, and the
1758 * correct bus_state structure.
1760 bus_state = &xhci->bus_state[hcd_index(hcd)];
1761 if (hcd->speed == HCD_USB3)
1762 port_array = xhci->usb3_ports;
1764 port_array = xhci->usb2_ports;
1765 /* Find the faked port hub number */
1766 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1769 temp = readl(port_array[faked_port_index]);
1770 if (hcd->state == HC_STATE_SUSPENDED) {
1771 xhci_dbg(xhci, "resume root hub\n");
1772 usb_hcd_resume_root_hub(hcd);
1775 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1776 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1778 temp1 = readl(&xhci->op_regs->command);
1779 if (!(temp1 & CMD_RUN)) {
1780 xhci_warn(xhci, "xHC is not running.\n");
1784 if (DEV_SUPERSPEED(temp)) {
1785 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1786 /* Set a flag to say the port signaled remote wakeup,
1787 * so we can tell the difference between the end of
1788 * device and host initiated resume.
1790 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1791 xhci_test_and_clear_bit(xhci, port_array,
1792 faked_port_index, PORT_PLC);
1793 xhci_set_link_state(xhci, port_array, faked_port_index,
1795 /* Need to wait until the next link state change
1796 * indicates the device is actually in U0.
1798 bogus_port_status = true;
1801 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1802 bus_state->resume_done[faked_port_index] = jiffies +
1803 msecs_to_jiffies(20);
1804 set_bit(faked_port_index, &bus_state->resuming_ports);
1805 mod_timer(&hcd->rh_timer,
1806 bus_state->resume_done[faked_port_index]);
1807 /* Do the rest in GetPortStatus */
1811 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1812 DEV_SUPERSPEED(temp)) {
1813 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1814 /* We've just brought the device into U0 through either the
1815 * Resume state after a device remote wakeup, or through the
1816 * U3Exit state after a host-initiated resume. If it's a device
1817 * initiated remote wake, don't pass up the link state change,
1818 * so the roothub behavior is consistent with external
1819 * USB 3.0 hub behavior.
1821 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1822 faked_port_index + 1);
1823 if (slot_id && xhci->devs[slot_id])
1824 xhci_ring_device(xhci, slot_id);
1825 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1826 bus_state->port_remote_wakeup &=
1827 ~(1 << faked_port_index);
1828 xhci_test_and_clear_bit(xhci, port_array,
1829 faked_port_index, PORT_PLC);
1830 usb_wakeup_notification(hcd->self.root_hub,
1831 faked_port_index + 1);
1832 bogus_port_status = true;
1838 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1839 * RExit to a disconnect state). If so, let the the driver know it's
1840 * out of the RExit state.
1842 if (!DEV_SUPERSPEED(temp) &&
1843 test_and_clear_bit(faked_port_index,
1844 &bus_state->rexit_ports)) {
1845 complete(&bus_state->rexit_done[faked_port_index]);
1846 bogus_port_status = true;
1850 if (hcd->speed != HCD_USB3)
1851 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1855 /* Update event ring dequeue pointer before dropping the lock */
1856 inc_deq(xhci, xhci->event_ring);
1858 /* Don't make the USB core poll the roothub if we got a bad port status
1859 * change event. Besides, at that point we can't tell which roothub
1860 * (USB 2.0 or USB 3.0) to kick.
1862 if (bogus_port_status)
1866 * xHCI port-status-change events occur when the "or" of all the
1867 * status-change bits in the portsc register changes from 0 to 1.
1868 * New status changes won't cause an event if any other change
1869 * bits are still set. When an event occurs, switch over to
1870 * polling to avoid losing status changes.
1872 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1873 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1874 spin_unlock(&xhci->lock);
1875 /* Pass this up to the core */
1876 usb_hcd_poll_rh_status(hcd);
1877 spin_lock(&xhci->lock);
1881 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1882 * at end_trb, which may be in another segment. If the suspect DMA address is a
1883 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1886 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1887 union xhci_trb *start_trb,
1888 union xhci_trb *end_trb,
1889 dma_addr_t suspect_dma)
1891 dma_addr_t start_dma;
1892 dma_addr_t end_seg_dma;
1893 dma_addr_t end_trb_dma;
1894 struct xhci_segment *cur_seg;
1896 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1897 cur_seg = start_seg;
1902 /* We may get an event for a Link TRB in the middle of a TD */
1903 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1904 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1905 /* If the end TRB isn't in this segment, this is set to 0 */
1906 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1908 if (end_trb_dma > 0) {
1909 /* The end TRB is in this segment, so suspect should be here */
1910 if (start_dma <= end_trb_dma) {
1911 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1914 /* Case for one segment with
1915 * a TD wrapped around to the top
1917 if ((suspect_dma >= start_dma &&
1918 suspect_dma <= end_seg_dma) ||
1919 (suspect_dma >= cur_seg->dma &&
1920 suspect_dma <= end_trb_dma))
1925 /* Might still be somewhere in this segment */
1926 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1929 cur_seg = cur_seg->next;
1930 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1931 } while (cur_seg != start_seg);
1936 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1937 unsigned int slot_id, unsigned int ep_index,
1938 unsigned int stream_id,
1939 struct xhci_td *td, union xhci_trb *event_trb)
1941 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1942 ep->ep_state |= EP_HALTED;
1943 ep->stopped_td = td;
1944 ep->stopped_trb = event_trb;
1945 ep->stopped_stream = stream_id;
1947 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1948 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1950 ep->stopped_td = NULL;
1951 ep->stopped_trb = NULL;
1952 ep->stopped_stream = 0;
1954 xhci_ring_cmd_db(xhci);
1957 /* Check if an error has halted the endpoint ring. The class driver will
1958 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1959 * However, a babble and other errors also halt the endpoint ring, and the class
1960 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1961 * Ring Dequeue Pointer command manually.
1963 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1964 struct xhci_ep_ctx *ep_ctx,
1965 unsigned int trb_comp_code)
1967 /* TRB completion codes that may require a manual halt cleanup */
1968 if (trb_comp_code == COMP_TX_ERR ||
1969 trb_comp_code == COMP_BABBLE ||
1970 trb_comp_code == COMP_SPLIT_ERR)
1971 /* The 0.96 spec says a babbling control endpoint
1972 * is not halted. The 0.96 spec says it is. Some HW
1973 * claims to be 0.95 compliant, but it halts the control
1974 * endpoint anyway. Check if a babble halted the
1977 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1978 cpu_to_le32(EP_STATE_HALTED))
1984 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1986 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1987 /* Vendor defined "informational" completion code,
1988 * treat as not-an-error.
1990 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1992 xhci_dbg(xhci, "Treating code as success.\n");
1999 * Finish the td processing, remove the td from td list;
2000 * Return 1 if the urb can be given back.
2002 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
2003 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2004 struct xhci_virt_ep *ep, int *status, bool skip)
2006 struct xhci_virt_device *xdev;
2007 struct xhci_ring *ep_ring;
2008 unsigned int slot_id;
2010 struct urb *urb = NULL;
2011 struct xhci_ep_ctx *ep_ctx;
2013 struct urb_priv *urb_priv;
2016 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2017 xdev = xhci->devs[slot_id];
2018 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2019 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2020 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2021 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2026 if (trb_comp_code == COMP_STOP_INVAL ||
2027 trb_comp_code == COMP_STOP) {
2028 /* The Endpoint Stop Command completion will take care of any
2029 * stopped TDs. A stopped TD may be restarted, so don't update
2030 * the ring dequeue pointer or take this TD off any lists yet.
2032 ep->stopped_td = td;
2033 ep->stopped_trb = event_trb;
2036 if (trb_comp_code == COMP_STALL) {
2037 /* The transfer is completed from the driver's
2038 * perspective, but we need to issue a set dequeue
2039 * command for this stalled endpoint to move the dequeue
2040 * pointer past the TD. We can't do that here because
2041 * the halt condition must be cleared first. Let the
2042 * USB class driver clear the stall later.
2044 ep->stopped_td = td;
2045 ep->stopped_trb = event_trb;
2046 ep->stopped_stream = ep_ring->stream_id;
2047 } else if (xhci_requires_manual_halt_cleanup(xhci,
2048 ep_ctx, trb_comp_code)) {
2049 /* Other types of errors halt the endpoint, but the
2050 * class driver doesn't call usb_reset_endpoint() unless
2051 * the error is -EPIPE. Clear the halted status in the
2052 * xHCI hardware manually.
2054 xhci_cleanup_halted_endpoint(xhci,
2055 slot_id, ep_index, ep_ring->stream_id,
2058 /* Update ring dequeue pointer */
2059 while (ep_ring->dequeue != td->last_trb)
2060 inc_deq(xhci, ep_ring);
2061 inc_deq(xhci, ep_ring);
2065 /* Clean up the endpoint's TD list */
2067 urb_priv = urb->hcpriv;
2069 /* Do one last check of the actual transfer length.
2070 * If the host controller said we transferred more data than
2071 * the buffer length, urb->actual_length will be a very big
2072 * number (since it's unsigned). Play it safe and say we didn't
2073 * transfer anything.
2075 if (urb->actual_length > urb->transfer_buffer_length) {
2076 xhci_warn(xhci, "URB transfer length is wrong, "
2077 "xHC issue? req. len = %u, "
2079 urb->transfer_buffer_length,
2080 urb->actual_length);
2081 urb->actual_length = 0;
2082 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2083 *status = -EREMOTEIO;
2087 list_del_init(&td->td_list);
2088 /* Was this TD slated to be cancelled but completed anyway? */
2089 if (!list_empty(&td->cancelled_td_list))
2090 list_del_init(&td->cancelled_td_list);
2093 /* Giveback the urb when all the tds are completed */
2094 if (urb_priv->td_cnt == urb_priv->length) {
2096 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2097 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
2098 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
2100 if (xhci->quirks & XHCI_AMD_PLL_FIX)
2101 usb_amd_quirk_pll_enable();
2111 * Process control tds, update urb status and actual_length.
2113 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2114 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2115 struct xhci_virt_ep *ep, int *status)
2117 struct xhci_virt_device *xdev;
2118 struct xhci_ring *ep_ring;
2119 unsigned int slot_id;
2121 struct xhci_ep_ctx *ep_ctx;
2124 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2125 xdev = xhci->devs[slot_id];
2126 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2127 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2128 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2129 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2131 switch (trb_comp_code) {
2133 if (event_trb == ep_ring->dequeue) {
2134 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
2135 "without IOC set??\n");
2136 *status = -ESHUTDOWN;
2137 } else if (event_trb != td->last_trb) {
2138 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
2139 "without IOC set??\n");
2140 *status = -ESHUTDOWN;
2146 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2147 *status = -EREMOTEIO;
2151 case COMP_STOP_INVAL:
2153 return finish_td(xhci, td, event_trb, event, ep, status, false);
2155 if (!xhci_requires_manual_halt_cleanup(xhci,
2156 ep_ctx, trb_comp_code))
2158 xhci_dbg(xhci, "TRB error code %u, "
2159 "halted endpoint index = %u\n",
2160 trb_comp_code, ep_index);
2161 /* else fall through */
2163 /* Did we transfer part of the data (middle) phase? */
2164 if (event_trb != ep_ring->dequeue &&
2165 event_trb != td->last_trb)
2166 td->urb->actual_length =
2167 td->urb->transfer_buffer_length -
2168 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2170 td->urb->actual_length = 0;
2172 xhci_cleanup_halted_endpoint(xhci,
2173 slot_id, ep_index, 0, td, event_trb);
2174 return finish_td(xhci, td, event_trb, event, ep, status, true);
2177 * Did we transfer any data, despite the errors that might have
2178 * happened? I.e. did we get past the setup stage?
2180 if (event_trb != ep_ring->dequeue) {
2181 /* The event was for the status stage */
2182 if (event_trb == td->last_trb) {
2183 if (td->urb->actual_length != 0) {
2184 /* Don't overwrite a previously set error code
2186 if ((*status == -EINPROGRESS || *status == 0) &&
2187 (td->urb->transfer_flags
2188 & URB_SHORT_NOT_OK))
2189 /* Did we already see a short data
2191 *status = -EREMOTEIO;
2193 td->urb->actual_length =
2194 td->urb->transfer_buffer_length;
2197 /* Maybe the event was for the data stage? */
2198 td->urb->actual_length =
2199 td->urb->transfer_buffer_length -
2200 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2201 xhci_dbg(xhci, "Waiting for status "
2207 return finish_td(xhci, td, event_trb, event, ep, status, false);
2211 * Process isochronous tds, update urb packet status and actual_length.
2213 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2214 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2215 struct xhci_virt_ep *ep, int *status)
2217 struct xhci_ring *ep_ring;
2218 struct urb_priv *urb_priv;
2221 union xhci_trb *cur_trb;
2222 struct xhci_segment *cur_seg;
2223 struct usb_iso_packet_descriptor *frame;
2225 bool skip_td = false;
2227 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2228 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2229 urb_priv = td->urb->hcpriv;
2230 idx = urb_priv->td_cnt;
2231 frame = &td->urb->iso_frame_desc[idx];
2233 /* handle completion code */
2234 switch (trb_comp_code) {
2236 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2240 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2241 trb_comp_code = COMP_SHORT_TX;
2243 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2247 frame->status = -ECOMM;
2250 case COMP_BUFF_OVER:
2252 frame->status = -EOVERFLOW;
2258 frame->status = -EPROTO;
2262 case COMP_STOP_INVAL:
2269 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2270 frame->actual_length = frame->length;
2271 td->urb->actual_length += frame->length;
2273 for (cur_trb = ep_ring->dequeue,
2274 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2275 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2276 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2277 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2278 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2280 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2281 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2283 if (trb_comp_code != COMP_STOP_INVAL) {
2284 frame->actual_length = len;
2285 td->urb->actual_length += len;
2289 return finish_td(xhci, td, event_trb, event, ep, status, false);
2292 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2293 struct xhci_transfer_event *event,
2294 struct xhci_virt_ep *ep, int *status)
2296 struct xhci_ring *ep_ring;
2297 struct urb_priv *urb_priv;
2298 struct usb_iso_packet_descriptor *frame;
2301 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2302 urb_priv = td->urb->hcpriv;
2303 idx = urb_priv->td_cnt;
2304 frame = &td->urb->iso_frame_desc[idx];
2306 /* The transfer is partly done. */
2307 frame->status = -EXDEV;
2309 /* calc actual length */
2310 frame->actual_length = 0;
2312 /* Update ring dequeue pointer */
2313 while (ep_ring->dequeue != td->last_trb)
2314 inc_deq(xhci, ep_ring);
2315 inc_deq(xhci, ep_ring);
2317 return finish_td(xhci, td, NULL, event, ep, status, true);
2321 * Process bulk and interrupt tds, update urb status and actual_length.
2323 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2324 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2325 struct xhci_virt_ep *ep, int *status)
2327 struct xhci_ring *ep_ring;
2328 union xhci_trb *cur_trb;
2329 struct xhci_segment *cur_seg;
2332 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2333 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2335 switch (trb_comp_code) {
2337 /* Double check that the HW transferred everything. */
2338 if (event_trb != td->last_trb ||
2339 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2340 xhci_warn(xhci, "WARN Successful completion "
2342 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2343 *status = -EREMOTEIO;
2346 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2347 trb_comp_code = COMP_SHORT_TX;
2353 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2354 *status = -EREMOTEIO;
2359 /* Others already handled above */
2362 if (trb_comp_code == COMP_SHORT_TX)
2363 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2364 "%d bytes untransferred\n",
2365 td->urb->ep->desc.bEndpointAddress,
2366 td->urb->transfer_buffer_length,
2367 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2368 /* Fast path - was this the last TRB in the TD for this URB? */
2369 if (event_trb == td->last_trb) {
2370 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2371 td->urb->actual_length =
2372 td->urb->transfer_buffer_length -
2373 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2374 if (td->urb->transfer_buffer_length <
2375 td->urb->actual_length) {
2376 xhci_warn(xhci, "HC gave bad length "
2377 "of %d bytes left\n",
2378 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2379 td->urb->actual_length = 0;
2380 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2381 *status = -EREMOTEIO;
2385 /* Don't overwrite a previously set error code */
2386 if (*status == -EINPROGRESS) {
2387 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2388 *status = -EREMOTEIO;
2393 td->urb->actual_length =
2394 td->urb->transfer_buffer_length;
2395 /* Ignore a short packet completion if the
2396 * untransferred length was zero.
2398 if (*status == -EREMOTEIO)
2402 /* Slow path - walk the list, starting from the dequeue
2403 * pointer, to get the actual length transferred.
2405 td->urb->actual_length = 0;
2406 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2407 cur_trb != event_trb;
2408 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2409 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2410 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2411 td->urb->actual_length +=
2412 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2414 /* If the ring didn't stop on a Link or No-op TRB, add
2415 * in the actual bytes transferred from the Normal TRB
2417 if (trb_comp_code != COMP_STOP_INVAL)
2418 td->urb->actual_length +=
2419 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2420 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2423 return finish_td(xhci, td, event_trb, event, ep, status, false);
2427 * If this function returns an error condition, it means it got a Transfer
2428 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2429 * At this point, the host controller is probably hosed and should be reset.
2431 static int handle_tx_event(struct xhci_hcd *xhci,
2432 struct xhci_transfer_event *event)
2433 __releases(&xhci->lock)
2434 __acquires(&xhci->lock)
2436 struct xhci_virt_device *xdev;
2437 struct xhci_virt_ep *ep;
2438 struct xhci_ring *ep_ring;
2439 unsigned int slot_id;
2441 struct xhci_td *td = NULL;
2442 dma_addr_t event_dma;
2443 struct xhci_segment *event_seg;
2444 union xhci_trb *event_trb;
2445 struct urb *urb = NULL;
2446 int status = -EINPROGRESS;
2447 struct urb_priv *urb_priv;
2448 struct xhci_ep_ctx *ep_ctx;
2449 struct list_head *tmp;
2454 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2455 xdev = xhci->devs[slot_id];
2457 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2458 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2459 (unsigned long long) xhci_trb_virt_to_dma(
2460 xhci->event_ring->deq_seg,
2461 xhci->event_ring->dequeue),
2462 lower_32_bits(le64_to_cpu(event->buffer)),
2463 upper_32_bits(le64_to_cpu(event->buffer)),
2464 le32_to_cpu(event->transfer_len),
2465 le32_to_cpu(event->flags));
2466 xhci_dbg(xhci, "Event ring:\n");
2467 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2471 /* Endpoint ID is 1 based, our index is zero based */
2472 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2473 ep = &xdev->eps[ep_index];
2474 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2475 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2477 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2478 EP_STATE_DISABLED) {
2479 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2480 "or incorrect stream ring\n");
2481 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2482 (unsigned long long) xhci_trb_virt_to_dma(
2483 xhci->event_ring->deq_seg,
2484 xhci->event_ring->dequeue),
2485 lower_32_bits(le64_to_cpu(event->buffer)),
2486 upper_32_bits(le64_to_cpu(event->buffer)),
2487 le32_to_cpu(event->transfer_len),
2488 le32_to_cpu(event->flags));
2489 xhci_dbg(xhci, "Event ring:\n");
2490 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2494 /* Count current td numbers if ep->skip is set */
2496 list_for_each(tmp, &ep_ring->td_list)
2500 event_dma = le64_to_cpu(event->buffer);
2501 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2502 /* Look for common error cases */
2503 switch (trb_comp_code) {
2504 /* Skip codes that require special handling depending on
2508 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2510 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2511 trb_comp_code = COMP_SHORT_TX;
2513 xhci_warn_ratelimited(xhci,
2514 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2518 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2520 case COMP_STOP_INVAL:
2521 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2524 xhci_dbg(xhci, "Stalled endpoint\n");
2525 ep->ep_state |= EP_HALTED;
2529 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2532 case COMP_SPLIT_ERR:
2534 xhci_dbg(xhci, "Transfer error on endpoint\n");
2538 xhci_dbg(xhci, "Babble error on endpoint\n");
2539 status = -EOVERFLOW;
2542 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2546 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2548 case COMP_BUFF_OVER:
2549 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2553 * When the Isoch ring is empty, the xHC will generate
2554 * a Ring Overrun Event for IN Isoch endpoint or Ring
2555 * Underrun Event for OUT Isoch endpoint.
2557 xhci_dbg(xhci, "underrun event on endpoint\n");
2558 if (!list_empty(&ep_ring->td_list))
2559 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2560 "still with TDs queued?\n",
2561 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2565 xhci_dbg(xhci, "overrun event on endpoint\n");
2566 if (!list_empty(&ep_ring->td_list))
2567 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2568 "still with TDs queued?\n",
2569 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2573 xhci_warn(xhci, "WARN: detect an incompatible device");
2576 case COMP_MISSED_INT:
2578 * When encounter missed service error, one or more isoc tds
2579 * may be missed by xHC.
2580 * Set skip flag of the ep_ring; Complete the missed tds as
2581 * short transfer when process the ep_ring next time.
2584 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2587 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2591 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2597 /* This TRB should be in the TD at the head of this ring's
2600 if (list_empty(&ep_ring->td_list)) {
2602 * A stopped endpoint may generate an extra completion
2603 * event if the device was suspended. Don't print
2606 if (!(trb_comp_code == COMP_STOP ||
2607 trb_comp_code == COMP_STOP_INVAL)) {
2608 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2609 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2611 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2612 (le32_to_cpu(event->flags) &
2613 TRB_TYPE_BITMASK)>>10);
2614 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2618 xhci_dbg(xhci, "td_list is empty while skip "
2619 "flag set. Clear skip flag.\n");
2625 /* We've skipped all the TDs on the ep ring when ep->skip set */
2626 if (ep->skip && td_num == 0) {
2628 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2629 "Clear skip flag.\n");
2634 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2638 /* Is this a TRB in the currently executing TD? */
2639 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2640 td->last_trb, event_dma);
2643 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2644 * is not in the current TD pointed by ep_ring->dequeue because
2645 * that the hardware dequeue pointer still at the previous TRB
2646 * of the current TD. The previous TRB maybe a Link TD or the
2647 * last TRB of the previous TD. The command completion handle
2648 * will take care the rest.
2650 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2657 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2658 /* Some host controllers give a spurious
2659 * successful event after a short transfer.
2662 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2663 ep_ring->last_td_was_short) {
2664 ep_ring->last_td_was_short = false;
2668 /* HC is busted, give up! */
2670 "ERROR Transfer event TRB DMA ptr not "
2671 "part of current TD\n");
2675 ret = skip_isoc_td(xhci, td, event, ep, &status);
2678 if (trb_comp_code == COMP_SHORT_TX)
2679 ep_ring->last_td_was_short = true;
2681 ep_ring->last_td_was_short = false;
2684 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2688 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2689 sizeof(*event_trb)];
2691 * No-op TRB should not trigger interrupts.
2692 * If event_trb is a no-op TRB, it means the
2693 * corresponding TD has been cancelled. Just ignore
2696 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2698 "event_trb is a no-op TRB. Skip it\n");
2702 /* Now update the urb's actual_length and give back to
2705 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2706 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2708 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2709 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2712 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2717 * Do not update event ring dequeue pointer if ep->skip is set.
2718 * Will roll back to continue process missed tds.
2720 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2721 inc_deq(xhci, xhci->event_ring);
2726 urb_priv = urb->hcpriv;
2727 /* Leave the TD around for the reset endpoint function
2728 * to use(but only if it's not a control endpoint,
2729 * since we already queued the Set TR dequeue pointer
2730 * command for stalled control endpoints).
2732 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2733 (trb_comp_code != COMP_STALL &&
2734 trb_comp_code != COMP_BABBLE))
2735 xhci_urb_free_priv(xhci, urb_priv);
2739 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2740 if ((urb->actual_length != urb->transfer_buffer_length &&
2741 (urb->transfer_flags &
2742 URB_SHORT_NOT_OK)) ||
2744 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2745 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2746 "expected = %d, status = %d\n",
2747 urb, urb->actual_length,
2748 urb->transfer_buffer_length,
2750 spin_unlock(&xhci->lock);
2751 /* EHCI, UHCI, and OHCI always unconditionally set the
2752 * urb->status of an isochronous endpoint to 0.
2754 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2756 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2757 spin_lock(&xhci->lock);
2761 * If ep->skip is set, it means there are missed tds on the
2762 * endpoint ring need to take care of.
2763 * Process them as short transfer until reach the td pointed by
2766 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2772 * This function handles all OS-owned events on the event ring. It may drop
2773 * xhci->lock between event processing (e.g. to pass up port status changes).
2774 * Returns >0 for "possibly more events to process" (caller should call again),
2775 * otherwise 0 if done. In future, <0 returns should indicate error code.
2777 static int xhci_handle_event(struct xhci_hcd *xhci)
2779 union xhci_trb *event;
2780 int update_ptrs = 1;
2783 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2784 xhci->error_bitmask |= 1 << 1;
2788 event = xhci->event_ring->dequeue;
2789 /* Does the HC or OS own the TRB? */
2790 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2791 xhci->event_ring->cycle_state) {
2792 xhci->error_bitmask |= 1 << 2;
2797 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2798 * speculative reads of the event's flags/data below.
2801 /* FIXME: Handle more event types. */
2802 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2803 case TRB_TYPE(TRB_COMPLETION):
2804 handle_cmd_completion(xhci, &event->event_cmd);
2806 case TRB_TYPE(TRB_PORT_STATUS):
2807 handle_port_status(xhci, event);
2810 case TRB_TYPE(TRB_TRANSFER):
2811 ret = handle_tx_event(xhci, &event->trans_event);
2813 xhci->error_bitmask |= 1 << 9;
2817 case TRB_TYPE(TRB_DEV_NOTE):
2818 handle_device_notification(xhci, event);
2821 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2823 handle_vendor_event(xhci, event);
2825 xhci->error_bitmask |= 1 << 3;
2827 /* Any of the above functions may drop and re-acquire the lock, so check
2828 * to make sure a watchdog timer didn't mark the host as non-responsive.
2830 if (xhci->xhc_state & XHCI_STATE_DYING) {
2831 xhci_dbg(xhci, "xHCI host dying, returning from "
2832 "event handler.\n");
2837 /* Update SW event ring dequeue pointer */
2838 inc_deq(xhci, xhci->event_ring);
2840 /* Are there more items on the event ring? Caller will call us again to
2847 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2848 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2849 * indicators of an event TRB error, but we check the status *first* to be safe.
2851 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2853 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2856 union xhci_trb *event_ring_deq;
2859 spin_lock(&xhci->lock);
2860 /* Check if the xHC generated the interrupt, or the irq is shared */
2861 status = readl(&xhci->op_regs->status);
2862 if (status == 0xffffffff)
2865 if (!(status & STS_EINT)) {
2866 spin_unlock(&xhci->lock);
2869 if (status & STS_FATAL) {
2870 xhci_warn(xhci, "WARNING: Host System Error\n");
2873 spin_unlock(&xhci->lock);
2878 * Clear the op reg interrupt status first,
2879 * so we can receive interrupts from other MSI-X interrupters.
2880 * Write 1 to clear the interrupt status.
2883 writel(status, &xhci->op_regs->status);
2884 /* FIXME when MSI-X is supported and there are multiple vectors */
2885 /* Clear the MSI-X event interrupt status */
2889 /* Acknowledge the PCI interrupt */
2890 irq_pending = readl(&xhci->ir_set->irq_pending);
2891 irq_pending |= IMAN_IP;
2892 writel(irq_pending, &xhci->ir_set->irq_pending);
2895 if (xhci->xhc_state & XHCI_STATE_DYING) {
2896 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2897 "Shouldn't IRQs be disabled?\n");
2898 /* Clear the event handler busy flag (RW1C);
2899 * the event ring should be empty.
2901 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2902 xhci_write_64(xhci, temp_64 | ERST_EHB,
2903 &xhci->ir_set->erst_dequeue);
2904 spin_unlock(&xhci->lock);
2909 event_ring_deq = xhci->event_ring->dequeue;
2910 /* FIXME this should be a delayed service routine
2911 * that clears the EHB.
2913 while (xhci_handle_event(xhci) > 0) {}
2915 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2916 /* If necessary, update the HW's version of the event ring deq ptr. */
2917 if (event_ring_deq != xhci->event_ring->dequeue) {
2918 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2919 xhci->event_ring->dequeue);
2921 xhci_warn(xhci, "WARN something wrong with SW event "
2922 "ring dequeue ptr.\n");
2923 /* Update HC event ring dequeue pointer */
2924 temp_64 &= ERST_PTR_MASK;
2925 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2928 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2929 temp_64 |= ERST_EHB;
2930 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2932 spin_unlock(&xhci->lock);
2937 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2939 return xhci_irq(hcd);
2942 /**** Endpoint Ring Operations ****/
2945 * Generic function for queueing a TRB on a ring.
2946 * The caller must have checked to make sure there's room on the ring.
2948 * @more_trbs_coming: Will you enqueue more TRBs before calling
2949 * prepare_transfer()?
2951 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2952 bool more_trbs_coming,
2953 u32 field1, u32 field2, u32 field3, u32 field4)
2955 struct xhci_generic_trb *trb;
2957 trb = &ring->enqueue->generic;
2958 trb->field[0] = cpu_to_le32(field1);
2959 trb->field[1] = cpu_to_le32(field2);
2960 trb->field[2] = cpu_to_le32(field3);
2961 trb->field[3] = cpu_to_le32(field4);
2962 inc_enq(xhci, ring, more_trbs_coming);
2966 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2967 * FIXME allocate segments if the ring is full.
2969 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2970 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2972 unsigned int num_trbs_needed;
2974 /* Make sure the endpoint has been added to xHC schedule */
2976 case EP_STATE_DISABLED:
2978 * USB core changed config/interfaces without notifying us,
2979 * or hardware is reporting the wrong state.
2981 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2983 case EP_STATE_ERROR:
2984 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2985 /* FIXME event handling code for error needs to clear it */
2986 /* XXX not sure if this should be -ENOENT or not */
2988 case EP_STATE_HALTED:
2989 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2990 case EP_STATE_STOPPED:
2991 case EP_STATE_RUNNING:
2994 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2996 * FIXME issue Configure Endpoint command to try to get the HC
2997 * back into a known state.
3003 if (room_on_ring(xhci, ep_ring, num_trbs))
3006 if (ep_ring == xhci->cmd_ring) {
3007 xhci_err(xhci, "Do not support expand command ring\n");
3011 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3012 "ERROR no room on ep ring, try ring expansion");
3013 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
3014 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
3016 xhci_err(xhci, "Ring expansion failed\n");
3021 if (enqueue_is_link_trb(ep_ring)) {
3022 struct xhci_ring *ring = ep_ring;
3023 union xhci_trb *next;
3025 next = ring->enqueue;
3027 while (last_trb(xhci, ring, ring->enq_seg, next)) {
3028 /* If we're not dealing with 0.95 hardware or isoc rings
3029 * on AMD 0.96 host, clear the chain bit.
3031 if (!xhci_link_trb_quirk(xhci) &&
3032 !(ring->type == TYPE_ISOC &&
3033 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3034 next->link.control &= cpu_to_le32(~TRB_CHAIN);
3036 next->link.control |= cpu_to_le32(TRB_CHAIN);
3039 next->link.control ^= cpu_to_le32(TRB_CYCLE);
3041 /* Toggle the cycle bit after the last ring segment. */
3042 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
3043 ring->cycle_state = (ring->cycle_state ? 0 : 1);
3045 ring->enq_seg = ring->enq_seg->next;
3046 ring->enqueue = ring->enq_seg->trbs;
3047 next = ring->enqueue;
3054 static int prepare_transfer(struct xhci_hcd *xhci,
3055 struct xhci_virt_device *xdev,
3056 unsigned int ep_index,
3057 unsigned int stream_id,
3058 unsigned int num_trbs,
3060 unsigned int td_index,
3064 struct urb_priv *urb_priv;
3066 struct xhci_ring *ep_ring;
3067 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3069 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
3071 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3076 ret = prepare_ring(xhci, ep_ring,
3077 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3078 num_trbs, mem_flags);
3082 urb_priv = urb->hcpriv;
3083 td = urb_priv->td[td_index];
3085 INIT_LIST_HEAD(&td->td_list);
3086 INIT_LIST_HEAD(&td->cancelled_td_list);
3088 if (td_index == 0) {
3089 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3095 /* Add this TD to the tail of the endpoint ring's TD list */
3096 list_add_tail(&td->td_list, &ep_ring->td_list);
3097 td->start_seg = ep_ring->enq_seg;
3098 td->first_trb = ep_ring->enqueue;
3100 urb_priv->td[td_index] = td;
3105 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
3107 int num_sgs, num_trbs, running_total, temp, i;
3108 struct scatterlist *sg;
3111 num_sgs = urb->num_mapped_sgs;
3112 temp = urb->transfer_buffer_length;
3115 for_each_sg(urb->sg, sg, num_sgs, i) {
3116 unsigned int len = sg_dma_len(sg);
3118 /* Scatter gather list entries may cross 64KB boundaries */
3119 running_total = TRB_MAX_BUFF_SIZE -
3120 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
3121 running_total &= TRB_MAX_BUFF_SIZE - 1;
3122 if (running_total != 0)
3125 /* How many more 64KB chunks to transfer, how many more TRBs? */
3126 while (running_total < sg_dma_len(sg) && running_total < temp) {
3128 running_total += TRB_MAX_BUFF_SIZE;
3130 len = min_t(int, len, temp);
3138 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
3141 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
3142 "TRBs, %d left\n", __func__,
3143 urb->ep->desc.bEndpointAddress, num_trbs);
3144 if (running_total != urb->transfer_buffer_length)
3145 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3146 "queued %#x (%d), asked for %#x (%d)\n",
3148 urb->ep->desc.bEndpointAddress,
3149 running_total, running_total,
3150 urb->transfer_buffer_length,
3151 urb->transfer_buffer_length);
3154 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3155 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3156 struct xhci_generic_trb *start_trb)
3159 * Pass all the TRBs to the hardware at once and make sure this write
3164 start_trb->field[3] |= cpu_to_le32(start_cycle);
3166 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3167 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3171 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3172 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3173 * (comprised of sg list entries) can take several service intervals to
3176 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3177 struct urb *urb, int slot_id, unsigned int ep_index)
3179 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3180 xhci->devs[slot_id]->out_ctx, ep_index);
3184 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3185 ep_interval = urb->interval;
3186 /* Convert to microframes */
3187 if (urb->dev->speed == USB_SPEED_LOW ||
3188 urb->dev->speed == USB_SPEED_FULL)
3190 /* FIXME change this to a warning and a suggestion to use the new API
3191 * to set the polling interval (once the API is added).
3193 if (xhci_interval != ep_interval) {
3194 dev_dbg_ratelimited(&urb->dev->dev,
3195 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3196 ep_interval, ep_interval == 1 ? "" : "s",
3197 xhci_interval, xhci_interval == 1 ? "" : "s");
3198 urb->interval = xhci_interval;
3199 /* Convert back to frames for LS/FS devices */
3200 if (urb->dev->speed == USB_SPEED_LOW ||
3201 urb->dev->speed == USB_SPEED_FULL)
3204 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3208 * The TD size is the number of bytes remaining in the TD (including this TRB),
3209 * right shifted by 10.
3210 * It must fit in bits 21:17, so it can't be bigger than 31.
3212 static u32 xhci_td_remainder(unsigned int remainder)
3214 u32 max = (1 << (21 - 17 + 1)) - 1;
3216 if ((remainder >> 10) >= max)
3219 return (remainder >> 10) << 17;
3223 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3224 * packets remaining in the TD (*not* including this TRB).
3226 * Total TD packet count = total_packet_count =
3227 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3229 * Packets transferred up to and including this TRB = packets_transferred =
3230 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3232 * TD size = total_packet_count - packets_transferred
3234 * It must fit in bits 21:17, so it can't be bigger than 31.
3235 * The last TRB in a TD must have the TD size set to zero.
3237 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3238 unsigned int total_packet_count, struct urb *urb,
3239 unsigned int num_trbs_left)
3241 int packets_transferred;
3243 /* One TRB with a zero-length data packet. */
3244 if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3247 /* All the TRB queueing functions don't count the current TRB in
3250 packets_transferred = (running_total + trb_buff_len) /
3251 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3253 if ((total_packet_count - packets_transferred) > 31)
3255 return (total_packet_count - packets_transferred) << 17;
3258 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3259 struct urb *urb, int slot_id, unsigned int ep_index)
3261 struct xhci_ring *ep_ring;
3262 unsigned int num_trbs;
3263 struct urb_priv *urb_priv;
3265 struct scatterlist *sg;
3267 int trb_buff_len, this_sg_len, running_total;
3268 unsigned int total_packet_count;
3271 bool more_trbs_coming;
3273 struct xhci_generic_trb *start_trb;
3276 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3280 num_trbs = count_sg_trbs_needed(xhci, urb);
3281 num_sgs = urb->num_mapped_sgs;
3282 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3283 usb_endpoint_maxp(&urb->ep->desc));
3285 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3286 ep_index, urb->stream_id,
3287 num_trbs, urb, 0, mem_flags);
3288 if (trb_buff_len < 0)
3289 return trb_buff_len;
3291 urb_priv = urb->hcpriv;
3292 td = urb_priv->td[0];
3295 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3296 * until we've finished creating all the other TRBs. The ring's cycle
3297 * state may change as we enqueue the other TRBs, so save it too.
3299 start_trb = &ep_ring->enqueue->generic;
3300 start_cycle = ep_ring->cycle_state;
3304 * How much data is in the first TRB?
3306 * There are three forces at work for TRB buffer pointers and lengths:
3307 * 1. We don't want to walk off the end of this sg-list entry buffer.
3308 * 2. The transfer length that the driver requested may be smaller than
3309 * the amount of memory allocated for this scatter-gather list.
3310 * 3. TRBs buffers can't cross 64KB boundaries.
3313 addr = (u64) sg_dma_address(sg);
3314 this_sg_len = sg_dma_len(sg);
3315 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3316 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3317 if (trb_buff_len > urb->transfer_buffer_length)
3318 trb_buff_len = urb->transfer_buffer_length;
3321 /* Queue the first TRB, even if it's zero-length */
3324 u32 length_field = 0;
3327 /* Don't change the cycle bit of the first TRB until later */
3330 if (start_cycle == 0)
3333 field |= ep_ring->cycle_state;
3335 /* Chain all the TRBs together; clear the chain bit in the last
3336 * TRB to indicate it's the last TRB in the chain.
3341 /* FIXME - add check for ZERO_PACKET flag before this */
3342 td->last_trb = ep_ring->enqueue;
3346 /* Only set interrupt on short packet for IN endpoints */
3347 if (usb_urb_dir_in(urb))
3350 if (TRB_MAX_BUFF_SIZE -
3351 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3352 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3353 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3354 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3355 (unsigned int) addr + trb_buff_len);
3358 /* Set the TRB length, TD size, and interrupter fields. */
3359 if (xhci->hci_version < 0x100) {
3360 remainder = xhci_td_remainder(
3361 urb->transfer_buffer_length -
3364 remainder = xhci_v1_0_td_remainder(running_total,
3365 trb_buff_len, total_packet_count, urb,
3368 length_field = TRB_LEN(trb_buff_len) |
3373 more_trbs_coming = true;
3375 more_trbs_coming = false;
3376 queue_trb(xhci, ep_ring, more_trbs_coming,
3377 lower_32_bits(addr),
3378 upper_32_bits(addr),
3380 field | TRB_TYPE(TRB_NORMAL));
3382 running_total += trb_buff_len;
3384 /* Calculate length for next transfer --
3385 * Are we done queueing all the TRBs for this sg entry?
3387 this_sg_len -= trb_buff_len;
3388 if (this_sg_len == 0) {
3393 addr = (u64) sg_dma_address(sg);
3394 this_sg_len = sg_dma_len(sg);
3396 addr += trb_buff_len;
3399 trb_buff_len = TRB_MAX_BUFF_SIZE -
3400 (addr & (TRB_MAX_BUFF_SIZE - 1));
3401 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3402 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3404 urb->transfer_buffer_length - running_total;
3405 } while (running_total < urb->transfer_buffer_length);
3407 check_trb_math(urb, num_trbs, running_total);
3408 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3409 start_cycle, start_trb);
3413 /* This is very similar to what ehci-q.c qtd_fill() does */
3414 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3415 struct urb *urb, int slot_id, unsigned int ep_index)
3417 struct xhci_ring *ep_ring;
3418 struct urb_priv *urb_priv;
3421 struct xhci_generic_trb *start_trb;
3423 bool more_trbs_coming;
3425 u32 field, length_field;
3427 int running_total, trb_buff_len, ret;
3428 unsigned int total_packet_count;
3432 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3434 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3439 /* How much data is (potentially) left before the 64KB boundary? */
3440 running_total = TRB_MAX_BUFF_SIZE -
3441 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3442 running_total &= TRB_MAX_BUFF_SIZE - 1;
3444 /* If there's some data on this 64KB chunk, or we have to send a
3445 * zero-length transfer, we need at least one TRB
3447 if (running_total != 0 || urb->transfer_buffer_length == 0)
3449 /* How many more 64KB chunks to transfer, how many more TRBs? */
3450 while (running_total < urb->transfer_buffer_length) {
3452 running_total += TRB_MAX_BUFF_SIZE;
3454 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3456 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3457 ep_index, urb->stream_id,
3458 num_trbs, urb, 0, mem_flags);
3462 urb_priv = urb->hcpriv;
3463 td = urb_priv->td[0];
3466 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3467 * until we've finished creating all the other TRBs. The ring's cycle
3468 * state may change as we enqueue the other TRBs, so save it too.
3470 start_trb = &ep_ring->enqueue->generic;
3471 start_cycle = ep_ring->cycle_state;
3474 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3475 usb_endpoint_maxp(&urb->ep->desc));
3476 /* How much data is in the first TRB? */
3477 addr = (u64) urb->transfer_dma;
3478 trb_buff_len = TRB_MAX_BUFF_SIZE -
3479 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3480 if (trb_buff_len > urb->transfer_buffer_length)
3481 trb_buff_len = urb->transfer_buffer_length;
3485 /* Queue the first TRB, even if it's zero-length */
3490 /* Don't change the cycle bit of the first TRB until later */
3493 if (start_cycle == 0)
3496 field |= ep_ring->cycle_state;
3498 /* Chain all the TRBs together; clear the chain bit in the last
3499 * TRB to indicate it's the last TRB in the chain.
3504 /* FIXME - add check for ZERO_PACKET flag before this */
3505 td->last_trb = ep_ring->enqueue;
3509 /* Only set interrupt on short packet for IN endpoints */
3510 if (usb_urb_dir_in(urb))
3513 /* Set the TRB length, TD size, and interrupter fields. */
3514 if (xhci->hci_version < 0x100) {
3515 remainder = xhci_td_remainder(
3516 urb->transfer_buffer_length -
3519 remainder = xhci_v1_0_td_remainder(running_total,
3520 trb_buff_len, total_packet_count, urb,
3523 length_field = TRB_LEN(trb_buff_len) |
3528 more_trbs_coming = true;
3530 more_trbs_coming = false;
3531 queue_trb(xhci, ep_ring, more_trbs_coming,
3532 lower_32_bits(addr),
3533 upper_32_bits(addr),
3535 field | TRB_TYPE(TRB_NORMAL));
3537 running_total += trb_buff_len;
3539 /* Calculate length for next transfer */
3540 addr += trb_buff_len;
3541 trb_buff_len = urb->transfer_buffer_length - running_total;
3542 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3543 trb_buff_len = TRB_MAX_BUFF_SIZE;
3544 } while (running_total < urb->transfer_buffer_length);
3546 check_trb_math(urb, num_trbs, running_total);
3547 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3548 start_cycle, start_trb);
3552 /* Caller must have locked xhci->lock */
3553 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3554 struct urb *urb, int slot_id, unsigned int ep_index)
3556 struct xhci_ring *ep_ring;
3559 struct usb_ctrlrequest *setup;
3560 struct xhci_generic_trb *start_trb;
3562 u32 field, length_field;
3563 struct urb_priv *urb_priv;
3566 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3571 * Need to copy setup packet into setup TRB, so we can't use the setup
3574 if (!urb->setup_packet)
3577 /* 1 TRB for setup, 1 for status */
3580 * Don't need to check if we need additional event data and normal TRBs,
3581 * since data in control transfers will never get bigger than 16MB
3582 * XXX: can we get a buffer that crosses 64KB boundaries?
3584 if (urb->transfer_buffer_length > 0)
3586 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3587 ep_index, urb->stream_id,
3588 num_trbs, urb, 0, mem_flags);
3592 urb_priv = urb->hcpriv;
3593 td = urb_priv->td[0];
3596 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3597 * until we've finished creating all the other TRBs. The ring's cycle
3598 * state may change as we enqueue the other TRBs, so save it too.
3600 start_trb = &ep_ring->enqueue->generic;
3601 start_cycle = ep_ring->cycle_state;
3603 /* Queue setup TRB - see section 6.4.1.2.1 */
3604 /* FIXME better way to translate setup_packet into two u32 fields? */
3605 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3607 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3608 if (start_cycle == 0)
3611 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3612 if (xhci->hci_version == 0x100) {
3613 if (urb->transfer_buffer_length > 0) {
3614 if (setup->bRequestType & USB_DIR_IN)
3615 field |= TRB_TX_TYPE(TRB_DATA_IN);
3617 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3621 queue_trb(xhci, ep_ring, true,
3622 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3623 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3624 TRB_LEN(8) | TRB_INTR_TARGET(0),
3625 /* Immediate data in pointer */
3628 /* If there's data, queue data TRBs */
3629 /* Only set interrupt on short packet for IN endpoints */
3630 if (usb_urb_dir_in(urb))
3631 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3633 field = TRB_TYPE(TRB_DATA);
3635 length_field = TRB_LEN(urb->transfer_buffer_length) |
3636 xhci_td_remainder(urb->transfer_buffer_length) |
3638 if (urb->transfer_buffer_length > 0) {
3639 if (setup->bRequestType & USB_DIR_IN)
3640 field |= TRB_DIR_IN;
3641 queue_trb(xhci, ep_ring, true,
3642 lower_32_bits(urb->transfer_dma),
3643 upper_32_bits(urb->transfer_dma),
3645 field | ep_ring->cycle_state);
3648 /* Save the DMA address of the last TRB in the TD */
3649 td->last_trb = ep_ring->enqueue;
3651 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3652 /* If the device sent data, the status stage is an OUT transfer */
3653 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3657 queue_trb(xhci, ep_ring, false,
3661 /* Event on completion */
3662 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3664 giveback_first_trb(xhci, slot_id, ep_index, 0,
3665 start_cycle, start_trb);
3669 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3670 struct urb *urb, int i)
3675 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3676 td_len = urb->iso_frame_desc[i].length;
3678 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3687 * The transfer burst count field of the isochronous TRB defines the number of
3688 * bursts that are required to move all packets in this TD. Only SuperSpeed
3689 * devices can burst up to bMaxBurst number of packets per service interval.
3690 * This field is zero based, meaning a value of zero in the field means one
3691 * burst. Basically, for everything but SuperSpeed devices, this field will be
3692 * zero. Only xHCI 1.0 host controllers support this field.
3694 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3695 struct usb_device *udev,
3696 struct urb *urb, unsigned int total_packet_count)
3698 unsigned int max_burst;
3700 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3703 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3704 return roundup(total_packet_count, max_burst + 1) - 1;
3708 * Returns the number of packets in the last "burst" of packets. This field is
3709 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3710 * the last burst packet count is equal to the total number of packets in the
3711 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3712 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3713 * contain 1 to (bMaxBurst + 1) packets.
3715 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3716 struct usb_device *udev,
3717 struct urb *urb, unsigned int total_packet_count)
3719 unsigned int max_burst;
3720 unsigned int residue;
3722 if (xhci->hci_version < 0x100)
3725 switch (udev->speed) {
3726 case USB_SPEED_SUPER:
3727 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3728 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3729 residue = total_packet_count % (max_burst + 1);
3730 /* If residue is zero, the last burst contains (max_burst + 1)
3731 * number of packets, but the TLBPC field is zero-based.
3737 if (total_packet_count == 0)
3739 return total_packet_count - 1;
3743 /* This is for isoc transfer */
3744 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3745 struct urb *urb, int slot_id, unsigned int ep_index)
3747 struct xhci_ring *ep_ring;
3748 struct urb_priv *urb_priv;
3750 int num_tds, trbs_per_td;
3751 struct xhci_generic_trb *start_trb;
3754 u32 field, length_field;
3755 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3756 u64 start_addr, addr;
3758 bool more_trbs_coming;
3760 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3762 num_tds = urb->number_of_packets;
3764 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3768 start_addr = (u64) urb->transfer_dma;
3769 start_trb = &ep_ring->enqueue->generic;
3770 start_cycle = ep_ring->cycle_state;
3772 urb_priv = urb->hcpriv;
3773 /* Queue the first TRB, even if it's zero-length */
3774 for (i = 0; i < num_tds; i++) {
3775 unsigned int total_packet_count;
3776 unsigned int burst_count;
3777 unsigned int residue;
3781 addr = start_addr + urb->iso_frame_desc[i].offset;
3782 td_len = urb->iso_frame_desc[i].length;
3783 td_remain_len = td_len;
3784 total_packet_count = DIV_ROUND_UP(td_len,
3786 usb_endpoint_maxp(&urb->ep->desc)));
3787 /* A zero-length transfer still involves at least one packet. */
3788 if (total_packet_count == 0)
3789 total_packet_count++;
3790 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3791 total_packet_count);
3792 residue = xhci_get_last_burst_packet_count(xhci,
3793 urb->dev, urb, total_packet_count);
3795 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3797 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3798 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3805 td = urb_priv->td[i];
3806 for (j = 0; j < trbs_per_td; j++) {
3811 field = TRB_TBC(burst_count) |
3813 /* Queue the isoc TRB */
3814 field |= TRB_TYPE(TRB_ISOC);
3815 /* Assume URB_ISO_ASAP is set */
3818 if (start_cycle == 0)
3821 field |= ep_ring->cycle_state;
3824 /* Queue other normal TRBs */
3825 field |= TRB_TYPE(TRB_NORMAL);
3826 field |= ep_ring->cycle_state;
3829 /* Only set interrupt on short packet for IN EPs */
3830 if (usb_urb_dir_in(urb))
3833 /* Chain all the TRBs together; clear the chain bit in
3834 * the last TRB to indicate it's the last TRB in the
3837 if (j < trbs_per_td - 1) {
3839 more_trbs_coming = true;
3841 td->last_trb = ep_ring->enqueue;
3843 if (xhci->hci_version == 0x100 &&
3846 /* Set BEI bit except for the last td */
3847 if (i < num_tds - 1)
3850 more_trbs_coming = false;
3853 /* Calculate TRB length */
3854 trb_buff_len = TRB_MAX_BUFF_SIZE -
3855 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3856 if (trb_buff_len > td_remain_len)
3857 trb_buff_len = td_remain_len;
3859 /* Set the TRB length, TD size, & interrupter fields. */
3860 if (xhci->hci_version < 0x100) {
3861 remainder = xhci_td_remainder(
3862 td_len - running_total);
3864 remainder = xhci_v1_0_td_remainder(
3865 running_total, trb_buff_len,
3866 total_packet_count, urb,
3867 (trbs_per_td - j - 1));
3869 length_field = TRB_LEN(trb_buff_len) |
3873 queue_trb(xhci, ep_ring, more_trbs_coming,
3874 lower_32_bits(addr),
3875 upper_32_bits(addr),
3878 running_total += trb_buff_len;
3880 addr += trb_buff_len;
3881 td_remain_len -= trb_buff_len;
3884 /* Check TD length */
3885 if (running_total != td_len) {
3886 xhci_err(xhci, "ISOC TD length unmatch\n");
3892 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3893 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3894 usb_amd_quirk_pll_disable();
3896 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3898 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3899 start_cycle, start_trb);
3902 /* Clean up a partially enqueued isoc transfer. */
3904 for (i--; i >= 0; i--)
3905 list_del_init(&urb_priv->td[i]->td_list);
3907 /* Use the first TD as a temporary variable to turn the TDs we've queued
3908 * into No-ops with a software-owned cycle bit. That way the hardware
3909 * won't accidentally start executing bogus TDs when we partially
3910 * overwrite them. td->first_trb and td->start_seg are already set.
3912 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3913 /* Every TRB except the first & last will have its cycle bit flipped. */
3914 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3916 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3917 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3918 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3919 ep_ring->cycle_state = start_cycle;
3920 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3921 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3926 * Check transfer ring to guarantee there is enough room for the urb.
3927 * Update ISO URB start_frame and interval.
3928 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3929 * update the urb->start_frame by now.
3930 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3932 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3933 struct urb *urb, int slot_id, unsigned int ep_index)
3935 struct xhci_virt_device *xdev;
3936 struct xhci_ring *ep_ring;
3937 struct xhci_ep_ctx *ep_ctx;
3941 int num_tds, num_trbs, i;
3944 xdev = xhci->devs[slot_id];
3945 ep_ring = xdev->eps[ep_index].ring;
3946 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3949 num_tds = urb->number_of_packets;
3950 for (i = 0; i < num_tds; i++)
3951 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3953 /* Check the ring to guarantee there is enough room for the whole urb.
3954 * Do not insert any td of the urb to the ring if the check failed.
3956 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3957 num_trbs, mem_flags);
3961 start_frame = readl(&xhci->run_regs->microframe_index);
3962 start_frame &= 0x3fff;
3964 urb->start_frame = start_frame;
3965 if (urb->dev->speed == USB_SPEED_LOW ||
3966 urb->dev->speed == USB_SPEED_FULL)
3967 urb->start_frame >>= 3;
3969 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3970 ep_interval = urb->interval;
3971 /* Convert to microframes */
3972 if (urb->dev->speed == USB_SPEED_LOW ||
3973 urb->dev->speed == USB_SPEED_FULL)
3975 /* FIXME change this to a warning and a suggestion to use the new API
3976 * to set the polling interval (once the API is added).
3978 if (xhci_interval != ep_interval) {
3979 dev_dbg_ratelimited(&urb->dev->dev,
3980 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3981 ep_interval, ep_interval == 1 ? "" : "s",
3982 xhci_interval, xhci_interval == 1 ? "" : "s");
3983 urb->interval = xhci_interval;
3984 /* Convert back to frames for LS/FS devices */
3985 if (urb->dev->speed == USB_SPEED_LOW ||
3986 urb->dev->speed == USB_SPEED_FULL)
3989 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3991 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3994 /**** Command Ring Operations ****/
3996 /* Generic function for queueing a command TRB on the command ring.
3997 * Check to make sure there's room on the command ring for one command TRB.
3998 * Also check that there's room reserved for commands that must not fail.
3999 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4000 * then only check for the number of reserved spots.
4001 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4002 * because the command event handler may want to resubmit a failed command.
4004 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
4005 u32 field3, u32 field4, bool command_must_succeed)
4007 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4010 if (!command_must_succeed)
4013 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4014 reserved_trbs, GFP_ATOMIC);
4016 xhci_err(xhci, "ERR: No room for command on command ring\n");
4017 if (command_must_succeed)
4018 xhci_err(xhci, "ERR: Reserved TRB counting for "
4019 "unfailable commands failed.\n");
4022 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4023 field4 | xhci->cmd_ring->cycle_state);
4027 /* Queue a slot enable or disable request on the command ring */
4028 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
4030 return queue_command(xhci, 0, 0, 0,
4031 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4034 /* Queue an address device command TRB */
4035 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4036 u32 slot_id, enum xhci_setup_dev setup)
4038 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4039 upper_32_bits(in_ctx_ptr), 0,
4040 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4041 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4044 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
4045 u32 field1, u32 field2, u32 field3, u32 field4)
4047 return queue_command(xhci, field1, field2, field3, field4, false);
4050 /* Queue a reset device command TRB */
4051 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
4053 return queue_command(xhci, 0, 0, 0,
4054 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4058 /* Queue a configure endpoint command TRB */
4059 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4060 u32 slot_id, bool command_must_succeed)
4062 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4063 upper_32_bits(in_ctx_ptr), 0,
4064 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4065 command_must_succeed);
4068 /* Queue an evaluate context command TRB */
4069 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4070 u32 slot_id, bool command_must_succeed)
4072 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4073 upper_32_bits(in_ctx_ptr), 0,
4074 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4075 command_must_succeed);
4079 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4080 * activity on an endpoint that is about to be suspended.
4082 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
4083 unsigned int ep_index, int suspend)
4085 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4086 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4087 u32 type = TRB_TYPE(TRB_STOP_RING);
4088 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4090 return queue_command(xhci, 0, 0, 0,
4091 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4094 /* Set Transfer Ring Dequeue Pointer command.
4095 * This should not be used for endpoints that have streams enabled.
4097 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
4098 unsigned int ep_index, unsigned int stream_id,
4099 struct xhci_segment *deq_seg,
4100 union xhci_trb *deq_ptr, u32 cycle_state)
4103 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4104 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4105 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4107 u32 type = TRB_TYPE(TRB_SET_DEQ);
4108 struct xhci_virt_ep *ep;
4110 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
4112 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4113 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4117 ep = &xhci->devs[slot_id]->eps[ep_index];
4118 if ((ep->ep_state & SET_DEQ_PENDING)) {
4119 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4120 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4123 ep->queued_deq_seg = deq_seg;
4124 ep->queued_deq_ptr = deq_ptr;
4126 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4127 return queue_command(xhci, lower_32_bits(addr) | trb_sct | cycle_state,
4128 upper_32_bits(addr), trb_stream_id,
4129 trb_slot_id | trb_ep_index | type, false);
4132 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
4133 unsigned int ep_index)
4135 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4136 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4137 u32 type = TRB_TYPE(TRB_RESET_EP);
4139 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,