2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72 struct xhci_virt_device *virt_dev,
73 struct xhci_event_cmd *event);
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
82 unsigned long segment_offset;
84 if (!seg || !trb || trb < seg->trbs)
87 segment_offset = trb - seg->trbs;
88 if (segment_offset > TRBS_PER_SEGMENT)
90 return seg->dma + (segment_offset * sizeof(*trb));
93 /* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
97 struct xhci_segment *seg, union xhci_trb *trb)
99 if (ring == xhci->event_ring)
100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101 (seg->next == xhci->event_ring->first_seg);
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
111 struct xhci_segment *seg, union xhci_trb *trb)
113 if (ring == xhci->event_ring)
114 return trb == &seg->trbs[TRBS_PER_SEGMENT];
116 return TRB_TYPE_LINK_LE32(trb->link.control);
119 static int enqueue_is_link_trb(struct xhci_ring *ring)
121 struct xhci_link_trb *link = &ring->enqueue->link;
122 return TRB_TYPE_LINK_LE32(link->control);
125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
129 static void next_trb(struct xhci_hcd *xhci,
130 struct xhci_ring *ring,
131 struct xhci_segment **seg,
132 union xhci_trb **trb)
134 if (last_trb(xhci, ring, *seg, *trb)) {
136 *trb = ((*seg)->trbs);
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
148 union xhci_trb *next = ++(ring->dequeue);
149 unsigned long long addr;
152 /* Update the dequeue pointer further if that was a link TRB or we're at
153 * the end of an event ring segment (which doesn't have link TRBS)
155 while (last_trb(xhci, ring, ring->deq_seg, next)) {
156 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
157 ring->cycle_state = (ring->cycle_state ? 0 : 1);
159 ring->deq_seg = ring->deq_seg->next;
160 ring->dequeue = ring->deq_seg->trbs;
161 next = ring->dequeue;
163 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
167 * See Cycle bit rules. SW is the consumer for the event ring only.
168 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
170 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
171 * chain bit is set), then set the chain bit in all the following link TRBs.
172 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
173 * have their chain bit cleared (so that each Link TRB is a separate TD).
175 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
176 * set, but other sections talk about dealing with the chain bit set. This was
177 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
178 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
180 * @more_trbs_coming: Will you enqueue more TRBs before calling
181 * prepare_transfer()?
183 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
184 bool consumer, bool more_trbs_coming, bool isoc)
187 union xhci_trb *next;
188 unsigned long long addr;
190 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
191 next = ++(ring->enqueue);
194 /* Update the dequeue pointer further if that was a link TRB or we're at
195 * the end of an event ring segment (which doesn't have link TRBS)
197 while (last_trb(xhci, ring, ring->enq_seg, next)) {
199 if (ring != xhci->event_ring) {
201 * If the caller doesn't plan on enqueueing more
202 * TDs before ringing the doorbell, then we
203 * don't want to give the link TRB to the
204 * hardware just yet. We'll give the link TRB
205 * back in prepare_ring() just before we enqueue
206 * the TD at the top of the ring.
208 if (!chain && !more_trbs_coming)
211 /* If we're not dealing with 0.95 hardware or
212 * isoc rings on AMD 0.96 host,
213 * carry over the chain bit of the previous TRB
214 * (which may mean the chain bit is cleared).
216 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
217 && !xhci_link_trb_quirk(xhci)) {
218 next->link.control &=
219 cpu_to_le32(~TRB_CHAIN);
220 next->link.control |=
223 /* Give this link TRB to the hardware */
225 next->link.control ^= cpu_to_le32(TRB_CYCLE);
227 /* Toggle the cycle bit after the last ring segment. */
228 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
229 ring->cycle_state = (ring->cycle_state ? 0 : 1);
232 ring->enq_seg = ring->enq_seg->next;
233 ring->enqueue = ring->enq_seg->trbs;
234 next = ring->enqueue;
236 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
240 * Check to see if there's room to enqueue num_trbs on the ring. See rules
242 * FIXME: this would be simpler and faster if we just kept track of the number
243 * of free TRBs in a ring.
245 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
246 unsigned int num_trbs)
249 union xhci_trb *enq = ring->enqueue;
250 struct xhci_segment *enq_seg = ring->enq_seg;
251 struct xhci_segment *cur_seg;
252 unsigned int left_on_ring;
254 /* If we are currently pointing to a link TRB, advance the
255 * enqueue pointer before checking for space */
256 while (last_trb(xhci, ring, enq_seg, enq)) {
257 enq_seg = enq_seg->next;
261 /* Check if ring is empty */
262 if (enq == ring->dequeue) {
263 /* Can't use link trbs */
264 left_on_ring = TRBS_PER_SEGMENT - 1;
265 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
266 cur_seg = cur_seg->next)
267 left_on_ring += TRBS_PER_SEGMENT - 1;
269 /* Always need one TRB free in the ring. */
271 if (num_trbs > left_on_ring) {
272 xhci_warn(xhci, "Not enough room on ring; "
273 "need %u TRBs, %u TRBs left\n",
274 num_trbs, left_on_ring);
279 /* Make sure there's an extra empty TRB available */
280 for (i = 0; i <= num_trbs; ++i) {
281 if (enq == ring->dequeue)
284 while (last_trb(xhci, ring, enq_seg, enq)) {
285 enq_seg = enq_seg->next;
292 /* Ring the host controller doorbell after placing a command on the ring */
293 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
295 xhci_dbg(xhci, "// Ding dong!\n");
296 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
297 /* Flush PCI posted writes */
298 xhci_readl(xhci, &xhci->dba->doorbell[0]);
301 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
302 unsigned int slot_id,
303 unsigned int ep_index,
304 unsigned int stream_id)
306 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
307 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
308 unsigned int ep_state = ep->ep_state;
310 /* Don't ring the doorbell for this endpoint if there are pending
311 * cancellations because we don't want to interrupt processing.
312 * We don't want to restart any stream rings if there's a set dequeue
313 * pointer command pending because the device can choose to start any
314 * stream once the endpoint is on the HW schedule.
315 * FIXME - check all the stream rings for pending cancellations.
317 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
318 (ep_state & EP_HALTED))
320 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
321 /* The CPU has better things to do at this point than wait for a
322 * write-posting flush. It'll get there soon enough.
326 /* Ring the doorbell for any rings with pending URBs */
327 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
328 unsigned int slot_id,
329 unsigned int ep_index)
331 unsigned int stream_id;
332 struct xhci_virt_ep *ep;
334 ep = &xhci->devs[slot_id]->eps[ep_index];
336 /* A ring has pending URBs if its TD list is not empty */
337 if (!(ep->ep_state & EP_HAS_STREAMS)) {
338 if (!(list_empty(&ep->ring->td_list)))
339 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
343 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
345 struct xhci_stream_info *stream_info = ep->stream_info;
346 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
347 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
353 * Find the segment that trb is in. Start searching in start_seg.
354 * If we must move past a segment that has a link TRB with a toggle cycle state
355 * bit set, then we will toggle the value pointed at by cycle_state.
357 static struct xhci_segment *find_trb_seg(
358 struct xhci_segment *start_seg,
359 union xhci_trb *trb, int *cycle_state)
361 struct xhci_segment *cur_seg = start_seg;
362 struct xhci_generic_trb *generic_trb;
364 while (cur_seg->trbs > trb ||
365 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
366 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
367 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
369 cur_seg = cur_seg->next;
370 if (cur_seg == start_seg)
371 /* Looped over the entire list. Oops! */
378 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
379 unsigned int slot_id, unsigned int ep_index,
380 unsigned int stream_id)
382 struct xhci_virt_ep *ep;
384 ep = &xhci->devs[slot_id]->eps[ep_index];
385 /* Common case: no streams */
386 if (!(ep->ep_state & EP_HAS_STREAMS))
389 if (stream_id == 0) {
391 "WARN: Slot ID %u, ep index %u has streams, "
392 "but URB has no stream ID.\n",
397 if (stream_id < ep->stream_info->num_streams)
398 return ep->stream_info->stream_rings[stream_id];
401 "WARN: Slot ID %u, ep index %u has "
402 "stream IDs 1 to %u allocated, "
403 "but stream ID %u is requested.\n",
405 ep->stream_info->num_streams - 1,
410 /* Get the right ring for the given URB.
411 * If the endpoint supports streams, boundary check the URB's stream ID.
412 * If the endpoint doesn't support streams, return the singular endpoint ring.
414 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
417 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
418 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
422 * Move the xHC's endpoint ring dequeue pointer past cur_td.
423 * Record the new state of the xHC's endpoint ring dequeue segment,
424 * dequeue pointer, and new consumer cycle state in state.
425 * Update our internal representation of the ring's dequeue pointer.
427 * We do this in three jumps:
428 * - First we update our new ring state to be the same as when the xHC stopped.
429 * - Then we traverse the ring to find the segment that contains
430 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
431 * any link TRBs with the toggle cycle bit set.
432 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
433 * if we've moved it past a link TRB with the toggle cycle bit set.
435 * Some of the uses of xhci_generic_trb are grotty, but if they're done
436 * with correct __le32 accesses they should work fine. Only users of this are
439 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
440 unsigned int slot_id, unsigned int ep_index,
441 unsigned int stream_id, struct xhci_td *cur_td,
442 struct xhci_dequeue_state *state)
444 struct xhci_virt_device *dev = xhci->devs[slot_id];
445 struct xhci_ring *ep_ring;
446 struct xhci_generic_trb *trb;
447 struct xhci_ep_ctx *ep_ctx;
450 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
451 ep_index, stream_id);
453 xhci_warn(xhci, "WARN can't find new dequeue state "
454 "for invalid stream ID %u.\n",
458 state->new_cycle_state = 0;
459 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
460 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
461 dev->eps[ep_index].stopped_trb,
462 &state->new_cycle_state);
463 if (!state->new_deq_seg) {
468 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
469 xhci_dbg(xhci, "Finding endpoint context\n");
470 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
471 state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
473 state->new_deq_ptr = cur_td->last_trb;
474 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
475 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
477 &state->new_cycle_state);
478 if (!state->new_deq_seg) {
483 trb = &state->new_deq_ptr->generic;
484 if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
485 (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
486 state->new_cycle_state ^= 0x1;
487 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
490 * If there is only one segment in a ring, find_trb_seg()'s while loop
491 * will not run, and it will return before it has a chance to see if it
492 * needs to toggle the cycle bit. It can't tell if the stalled transfer
493 * ended just before the link TRB on a one-segment ring, or if the TD
494 * wrapped around the top of the ring, because it doesn't have the TD in
495 * question. Look for the one-segment case where stalled TRB's address
496 * is greater than the new dequeue pointer address.
498 if (ep_ring->first_seg == ep_ring->first_seg->next &&
499 state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
500 state->new_cycle_state ^= 0x1;
501 xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
503 /* Don't update the ring cycle state for the producer (us). */
504 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
506 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
507 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
508 (unsigned long long) addr);
511 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
512 * (The last TRB actually points to the ring enqueue pointer, which is not part
513 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
515 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
516 struct xhci_td *cur_td, bool flip_cycle)
518 struct xhci_segment *cur_seg;
519 union xhci_trb *cur_trb;
521 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
523 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
524 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
525 /* Unchain any chained Link TRBs, but
526 * leave the pointers intact.
528 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
529 /* Flip the cycle bit (link TRBs can't be the first
533 cur_trb->generic.field[3] ^=
534 cpu_to_le32(TRB_CYCLE);
535 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
536 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
537 "in seg %p (0x%llx dma)\n",
539 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
541 (unsigned long long)cur_seg->dma);
543 cur_trb->generic.field[0] = 0;
544 cur_trb->generic.field[1] = 0;
545 cur_trb->generic.field[2] = 0;
546 /* Preserve only the cycle bit of this TRB */
547 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
548 /* Flip the cycle bit except on the first or last TRB */
549 if (flip_cycle && cur_trb != cur_td->first_trb &&
550 cur_trb != cur_td->last_trb)
551 cur_trb->generic.field[3] ^=
552 cpu_to_le32(TRB_CYCLE);
553 cur_trb->generic.field[3] |= cpu_to_le32(
554 TRB_TYPE(TRB_TR_NOOP));
555 xhci_dbg(xhci, "TRB to noop at offset 0x%llx\n",
557 xhci_trb_virt_to_dma(cur_seg, cur_trb));
559 if (cur_trb == cur_td->last_trb)
564 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
565 unsigned int ep_index, unsigned int stream_id,
566 struct xhci_segment *deq_seg,
567 union xhci_trb *deq_ptr, u32 cycle_state);
569 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
570 unsigned int slot_id, unsigned int ep_index,
571 unsigned int stream_id,
572 struct xhci_dequeue_state *deq_state)
574 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
576 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
577 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
578 deq_state->new_deq_seg,
579 (unsigned long long)deq_state->new_deq_seg->dma,
580 deq_state->new_deq_ptr,
581 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
582 deq_state->new_cycle_state);
583 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
584 deq_state->new_deq_seg,
585 deq_state->new_deq_ptr,
586 (u32) deq_state->new_cycle_state);
587 /* Stop the TD queueing code from ringing the doorbell until
588 * this command completes. The HC won't set the dequeue pointer
589 * if the ring is running, and ringing the doorbell starts the
592 ep->ep_state |= SET_DEQ_PENDING;
595 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
596 struct xhci_virt_ep *ep)
598 ep->ep_state &= ~EP_HALT_PENDING;
599 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
600 * timer is running on another CPU, we don't decrement stop_cmds_pending
601 * (since we didn't successfully stop the watchdog timer).
603 if (del_timer(&ep->stop_cmd_timer))
604 ep->stop_cmds_pending--;
607 /* Must be called with xhci->lock held in interrupt context */
608 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
609 struct xhci_td *cur_td, int status, char *adjective)
613 struct urb_priv *urb_priv;
616 urb_priv = urb->hcpriv;
618 hcd = bus_to_hcd(urb->dev->bus);
620 /* Only giveback urb when this is the last td in urb */
621 if (urb_priv->td_cnt == urb_priv->length) {
622 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
623 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
624 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
625 if (xhci->quirks & XHCI_AMD_PLL_FIX)
626 usb_amd_quirk_pll_enable();
629 usb_hcd_unlink_urb_from_ep(hcd, urb);
631 spin_unlock(&xhci->lock);
632 usb_hcd_giveback_urb(hcd, urb, status);
633 xhci_urb_free_priv(xhci, urb_priv);
634 spin_lock(&xhci->lock);
639 * When we get a command completion for a Stop Endpoint Command, we need to
640 * unlink any cancelled TDs from the ring. There are two ways to do that:
642 * 1. If the HW was in the middle of processing the TD that needs to be
643 * cancelled, then we must move the ring's dequeue pointer past the last TRB
644 * in the TD with a Set Dequeue Pointer Command.
645 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
646 * bit cleared) so that the HW will skip over them.
648 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
649 union xhci_trb *trb, struct xhci_event_cmd *event)
651 unsigned int slot_id;
652 unsigned int ep_index;
653 struct xhci_virt_device *virt_dev;
654 struct xhci_ring *ep_ring;
655 struct xhci_virt_ep *ep;
656 struct list_head *entry;
657 struct xhci_td *cur_td = NULL;
658 struct xhci_td *last_unlinked_td;
660 struct xhci_dequeue_state deq_state;
662 if (unlikely(TRB_TO_SUSPEND_PORT(
663 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
664 slot_id = TRB_TO_SLOT_ID(
665 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
666 virt_dev = xhci->devs[slot_id];
668 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
671 xhci_warn(xhci, "Stop endpoint command "
672 "completion for disabled slot %u\n",
677 memset(&deq_state, 0, sizeof(deq_state));
678 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
679 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
680 ep = &xhci->devs[slot_id]->eps[ep_index];
682 if (list_empty(&ep->cancelled_td_list)) {
683 xhci_stop_watchdog_timer_in_irq(xhci, ep);
684 ep->stopped_td = NULL;
685 ep->stopped_trb = NULL;
686 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
690 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
691 * We have the xHCI lock, so nothing can modify this list until we drop
692 * it. We're also in the event handler, so we can't get re-interrupted
693 * if another Stop Endpoint command completes
695 list_for_each(entry, &ep->cancelled_td_list) {
696 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
697 xhci_dbg(xhci, "Removing canceled TD starting at 0x%llx (dma).\n",
698 (unsigned long long)xhci_trb_virt_to_dma(
699 cur_td->start_seg, cur_td->first_trb));
700 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
702 /* This shouldn't happen unless a driver is mucking
703 * with the stream ID after submission. This will
704 * leave the TD on the hardware ring, and the hardware
705 * will try to execute it, and may access a buffer
706 * that has already been freed. In the best case, the
707 * hardware will execute it, and the event handler will
708 * ignore the completion event for that TD, since it was
709 * removed from the td_list for that endpoint. In
710 * short, don't muck with the stream ID after
713 xhci_warn(xhci, "WARN Cancelled URB %p "
714 "has invalid stream ID %u.\n",
716 cur_td->urb->stream_id);
717 goto remove_finished_td;
720 * If we stopped on the TD we need to cancel, then we have to
721 * move the xHC endpoint ring dequeue pointer past this TD.
723 if (cur_td == ep->stopped_td)
724 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
725 cur_td->urb->stream_id,
728 td_to_noop(xhci, ep_ring, cur_td, false);
731 * The event handler won't see a completion for this TD anymore,
732 * so remove it from the endpoint ring's TD list. Keep it in
733 * the cancelled TD list for URB completion later.
735 list_del_init(&cur_td->td_list);
737 last_unlinked_td = cur_td;
738 xhci_stop_watchdog_timer_in_irq(xhci, ep);
740 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
741 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
742 xhci_queue_new_dequeue_state(xhci,
744 ep->stopped_td->urb->stream_id,
746 xhci_ring_cmd_db(xhci);
748 /* Otherwise ring the doorbell(s) to restart queued transfers */
749 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
751 ep->stopped_td = NULL;
752 ep->stopped_trb = NULL;
755 * Drop the lock and complete the URBs in the cancelled TD list.
756 * New TDs to be cancelled might be added to the end of the list before
757 * we can complete all the URBs for the TDs we already unlinked.
758 * So stop when we've completed the URB for the last TD we unlinked.
761 cur_td = list_entry(ep->cancelled_td_list.next,
762 struct xhci_td, cancelled_td_list);
763 list_del_init(&cur_td->cancelled_td_list);
765 /* Clean up the cancelled URB */
766 /* Doesn't matter what we pass for status, since the core will
767 * just overwrite it (because the URB has been unlinked).
769 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
771 /* Stop processing the cancelled list if the watchdog timer is
774 if (xhci->xhc_state & XHCI_STATE_DYING)
776 } while (cur_td != last_unlinked_td);
778 /* Return to the event handler with xhci->lock re-acquired */
781 /* Watchdog timer function for when a stop endpoint command fails to complete.
782 * In this case, we assume the host controller is broken or dying or dead. The
783 * host may still be completing some other events, so we have to be careful to
784 * let the event ring handler and the URB dequeueing/enqueueing functions know
785 * through xhci->state.
787 * The timer may also fire if the host takes a very long time to respond to the
788 * command, and the stop endpoint command completion handler cannot delete the
789 * timer before the timer function is called. Another endpoint cancellation may
790 * sneak in before the timer function can grab the lock, and that may queue
791 * another stop endpoint command and add the timer back. So we cannot use a
792 * simple flag to say whether there is a pending stop endpoint command for a
793 * particular endpoint.
795 * Instead we use a combination of that flag and a counter for the number of
796 * pending stop endpoint commands. If the timer is the tail end of the last
797 * stop endpoint command, and the endpoint's command is still pending, we assume
800 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
802 struct xhci_hcd *xhci;
803 struct xhci_virt_ep *ep;
804 struct xhci_virt_ep *temp_ep;
805 struct xhci_ring *ring;
806 struct xhci_td *cur_td;
810 ep = (struct xhci_virt_ep *) arg;
813 spin_lock_irqsave(&xhci->lock, flags);
815 ep->stop_cmds_pending--;
816 if (xhci->xhc_state & XHCI_STATE_DYING) {
817 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
818 "xHCI as DYING, exiting.\n");
819 spin_unlock_irqrestore(&xhci->lock, flags);
822 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
823 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
825 spin_unlock_irqrestore(&xhci->lock, flags);
829 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
830 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
831 /* Oops, HC is dead or dying or at least not responding to the stop
834 xhci->xhc_state |= XHCI_STATE_DYING;
835 /* Disable interrupts from the host controller and start halting it */
837 spin_unlock_irqrestore(&xhci->lock, flags);
839 ret = xhci_halt(xhci);
841 spin_lock_irqsave(&xhci->lock, flags);
843 /* This is bad; the host is not responding to commands and it's
844 * not allowing itself to be halted. At least interrupts are
845 * disabled. If we call usb_hc_died(), it will attempt to
846 * disconnect all device drivers under this host. Those
847 * disconnect() methods will wait for all URBs to be unlinked,
848 * so we must complete them.
850 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
851 xhci_warn(xhci, "Completing active URBs anyway.\n");
852 /* We could turn all TDs on the rings to no-ops. This won't
853 * help if the host has cached part of the ring, and is slow if
854 * we want to preserve the cycle bit. Skip it and hope the host
855 * doesn't touch the memory.
858 for (i = 0; i < MAX_HC_SLOTS; i++) {
861 for (j = 0; j < 31; j++) {
862 temp_ep = &xhci->devs[i]->eps[j];
863 ring = temp_ep->ring;
866 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
867 "ep index %u\n", i, j);
868 while (!list_empty(&ring->td_list)) {
869 cur_td = list_first_entry(&ring->td_list,
872 list_del_init(&cur_td->td_list);
873 if (!list_empty(&cur_td->cancelled_td_list))
874 list_del_init(&cur_td->cancelled_td_list);
875 xhci_giveback_urb_in_irq(xhci, cur_td,
876 -ESHUTDOWN, "killed");
878 while (!list_empty(&temp_ep->cancelled_td_list)) {
879 cur_td = list_first_entry(
880 &temp_ep->cancelled_td_list,
883 list_del_init(&cur_td->cancelled_td_list);
884 xhci_giveback_urb_in_irq(xhci, cur_td,
885 -ESHUTDOWN, "killed");
889 spin_unlock_irqrestore(&xhci->lock, flags);
890 xhci_dbg(xhci, "Calling usb_hc_died()\n");
891 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
892 xhci_dbg(xhci, "xHCI host controller is dead.\n");
896 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
897 * we need to clear the set deq pending flag in the endpoint ring state, so that
898 * the TD queueing code can ring the doorbell again. We also need to ring the
899 * endpoint doorbell to restart the ring, but only if there aren't more
900 * cancellations pending.
902 static void handle_set_deq_completion(struct xhci_hcd *xhci,
903 struct xhci_event_cmd *event,
906 unsigned int slot_id;
907 unsigned int ep_index;
908 unsigned int stream_id;
909 struct xhci_ring *ep_ring;
910 struct xhci_virt_device *dev;
911 struct xhci_ep_ctx *ep_ctx;
912 struct xhci_slot_ctx *slot_ctx;
914 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
915 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
916 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
917 dev = xhci->devs[slot_id];
919 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
921 xhci_warn(xhci, "WARN Set TR deq ptr command for "
922 "freed stream ID %u\n",
924 /* XXX: Harmless??? */
925 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
929 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
930 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
932 if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
933 unsigned int ep_state;
934 unsigned int slot_state;
936 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
938 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
939 "of stream ID configuration\n");
942 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
943 "to incorrect slot or ep state.\n");
944 ep_state = le32_to_cpu(ep_ctx->ep_info);
945 ep_state &= EP_STATE_MASK;
946 slot_state = le32_to_cpu(slot_ctx->dev_state);
947 slot_state = GET_SLOT_STATE(slot_state);
948 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
949 slot_state, ep_state);
952 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
953 "slot %u was not enabled.\n", slot_id);
956 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
957 "completion code of %u.\n",
958 GET_COMP_CODE(le32_to_cpu(event->status)));
961 /* OK what do we do now? The endpoint state is hosed, and we
962 * should never get to this point if the synchronization between
963 * queueing, and endpoint state are correct. This might happen
964 * if the device gets disconnected after we've finished
965 * cancelling URBs, which might not be an error...
968 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
969 le64_to_cpu(ep_ctx->deq));
970 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
971 dev->eps[ep_index].queued_deq_ptr) ==
972 (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
973 /* Update the ring's dequeue segment and dequeue pointer
974 * to reflect the new position.
976 ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
977 ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
979 xhci_warn(xhci, "Mismatch between completed Set TR Deq "
980 "Ptr command & xHCI internal state.\n");
981 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
982 dev->eps[ep_index].queued_deq_seg,
983 dev->eps[ep_index].queued_deq_ptr);
987 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
988 dev->eps[ep_index].queued_deq_seg = NULL;
989 dev->eps[ep_index].queued_deq_ptr = NULL;
990 /* Restart any rings with pending URBs */
991 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
994 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
995 struct xhci_event_cmd *event,
999 unsigned int ep_index;
1001 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1002 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1003 /* This command will only fail if the endpoint wasn't halted,
1004 * but we don't care.
1006 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1007 GET_COMP_CODE(le32_to_cpu(event->status)));
1009 /* HW with the reset endpoint quirk needs to have a configure endpoint
1010 * command complete before the endpoint can be used. Queue that here
1011 * because the HW can't handle two commands being queued in a row.
1013 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1014 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1015 xhci_queue_configure_endpoint(xhci,
1016 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1018 xhci_ring_cmd_db(xhci);
1020 /* Clear our internal halted state and restart the ring(s) */
1021 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1022 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1026 /* Check to see if a command in the device's command queue matches this one.
1027 * Signal the completion or free the command, and return 1. Return 0 if the
1028 * completed command isn't at the head of the command list.
1030 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1031 struct xhci_virt_device *virt_dev,
1032 struct xhci_event_cmd *event)
1034 struct xhci_command *command;
1036 if (list_empty(&virt_dev->cmd_list))
1039 command = list_entry(virt_dev->cmd_list.next,
1040 struct xhci_command, cmd_list);
1041 if (xhci->cmd_ring->dequeue != command->command_trb)
1044 command->status = GET_COMP_CODE(le32_to_cpu(event->status));
1045 list_del(&command->cmd_list);
1046 if (command->completion)
1047 complete(command->completion);
1049 xhci_free_command(xhci, command);
1053 static void handle_cmd_completion(struct xhci_hcd *xhci,
1054 struct xhci_event_cmd *event)
1056 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1058 dma_addr_t cmd_dequeue_dma;
1059 struct xhci_input_control_ctx *ctrl_ctx;
1060 struct xhci_virt_device *virt_dev;
1061 unsigned int ep_index;
1062 struct xhci_ring *ep_ring;
1063 unsigned int ep_state;
1065 cmd_dma = le64_to_cpu(event->cmd_trb);
1066 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1067 xhci->cmd_ring->dequeue);
1068 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1069 if (cmd_dequeue_dma == 0) {
1070 xhci->error_bitmask |= 1 << 4;
1073 /* Does the DMA address match our internal dequeue pointer address? */
1074 if (cmd_dma != (u64) cmd_dequeue_dma) {
1075 xhci->error_bitmask |= 1 << 5;
1078 switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1079 & TRB_TYPE_BITMASK) {
1080 case TRB_TYPE(TRB_ENABLE_SLOT):
1081 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1082 xhci->slot_id = slot_id;
1085 complete(&xhci->addr_dev);
1087 case TRB_TYPE(TRB_DISABLE_SLOT):
1088 if (xhci->devs[slot_id]) {
1089 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1090 /* Delete default control endpoint resources */
1091 xhci_free_device_endpoint_resources(xhci,
1092 xhci->devs[slot_id], true);
1093 xhci_free_virt_device(xhci, slot_id);
1096 case TRB_TYPE(TRB_CONFIG_EP):
1097 virt_dev = xhci->devs[slot_id];
1098 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1101 * Configure endpoint commands can come from the USB core
1102 * configuration or alt setting changes, or because the HW
1103 * needed an extra configure endpoint command after a reset
1104 * endpoint command or streams were being configured.
1105 * If the command was for a halted endpoint, the xHCI driver
1106 * is not waiting on the configure endpoint command.
1108 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1110 /* Input ctx add_flags are the endpoint index plus one */
1111 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1112 /* A usb_set_interface() call directly after clearing a halted
1113 * condition may race on this quirky hardware. Not worth
1114 * worrying about, since this is prototype hardware. Not sure
1115 * if this will work for streams, but streams support was
1116 * untested on this prototype.
1118 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1119 ep_index != (unsigned int) -1 &&
1120 le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1121 le32_to_cpu(ctrl_ctx->drop_flags)) {
1122 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1123 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1124 if (!(ep_state & EP_HALTED))
1125 goto bandwidth_change;
1126 xhci_dbg(xhci, "Completed config ep cmd - "
1127 "last ep index = %d, state = %d\n",
1128 ep_index, ep_state);
1129 /* Clear internal halted state and restart ring(s) */
1130 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1132 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1136 xhci_dbg(xhci, "Completed config ep cmd\n");
1137 xhci->devs[slot_id]->cmd_status =
1138 GET_COMP_CODE(le32_to_cpu(event->status));
1139 complete(&xhci->devs[slot_id]->cmd_completion);
1141 case TRB_TYPE(TRB_EVAL_CONTEXT):
1142 virt_dev = xhci->devs[slot_id];
1143 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1145 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1146 complete(&xhci->devs[slot_id]->cmd_completion);
1148 case TRB_TYPE(TRB_ADDR_DEV):
1149 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1150 complete(&xhci->addr_dev);
1152 case TRB_TYPE(TRB_STOP_RING):
1153 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1155 case TRB_TYPE(TRB_SET_DEQ):
1156 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1158 case TRB_TYPE(TRB_CMD_NOOP):
1160 case TRB_TYPE(TRB_RESET_EP):
1161 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1163 case TRB_TYPE(TRB_RESET_DEV):
1164 xhci_dbg(xhci, "Completed reset device command.\n");
1165 slot_id = TRB_TO_SLOT_ID(
1166 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1167 virt_dev = xhci->devs[slot_id];
1169 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1171 xhci_warn(xhci, "Reset device command completion "
1172 "for disabled slot %u\n", slot_id);
1174 case TRB_TYPE(TRB_NEC_GET_FW):
1175 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1176 xhci->error_bitmask |= 1 << 6;
1179 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1180 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1181 NEC_FW_MINOR(le32_to_cpu(event->status)));
1184 /* Skip over unknown commands on the event ring */
1185 xhci->error_bitmask |= 1 << 6;
1188 inc_deq(xhci, xhci->cmd_ring, false);
1191 static void handle_vendor_event(struct xhci_hcd *xhci,
1192 union xhci_trb *event)
1196 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1197 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1198 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1199 handle_cmd_completion(xhci, &event->event_cmd);
1202 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1203 * port registers -- USB 3.0 and USB 2.0).
1205 * Returns a zero-based port number, which is suitable for indexing into each of
1206 * the split roothubs' port arrays and bus state arrays.
1208 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1209 struct xhci_hcd *xhci, u32 port_id)
1212 unsigned int num_similar_speed_ports = 0;
1214 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1215 * and usb2_ports are 0-based indexes. Count the number of similar
1216 * speed ports, up to 1 port before this port.
1218 for (i = 0; i < (port_id - 1); i++) {
1219 u8 port_speed = xhci->port_array[i];
1222 * Skip ports that don't have known speeds, or have duplicate
1223 * Extended Capabilities port speed entries.
1225 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1229 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1230 * 1.1 ports are under the USB 2.0 hub. If the port speed
1231 * matches the device speed, it's a similar speed port.
1233 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1234 num_similar_speed_ports++;
1236 return num_similar_speed_ports;
1239 static void handle_port_status(struct xhci_hcd *xhci,
1240 union xhci_trb *event)
1242 struct usb_hcd *hcd;
1247 unsigned int faked_port_index;
1249 struct xhci_bus_state *bus_state;
1250 __le32 __iomem **port_array;
1251 bool bogus_port_status = false;
1253 /* Port status change events always have a successful completion code */
1254 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1255 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1256 xhci->error_bitmask |= 1 << 8;
1258 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1259 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1261 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1262 if ((port_id <= 0) || (port_id > max_ports)) {
1263 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1264 bogus_port_status = true;
1268 /* Figure out which usb_hcd this port is attached to:
1269 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1271 major_revision = xhci->port_array[port_id - 1];
1272 if (major_revision == 0) {
1273 xhci_warn(xhci, "Event for port %u not in "
1274 "Extended Capabilities, ignoring.\n",
1276 bogus_port_status = true;
1279 if (major_revision == DUPLICATE_ENTRY) {
1280 xhci_warn(xhci, "Event for port %u duplicated in"
1281 "Extended Capabilities, ignoring.\n",
1283 bogus_port_status = true;
1288 * Hardware port IDs reported by a Port Status Change Event include USB
1289 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1290 * resume event, but we first need to translate the hardware port ID
1291 * into the index into the ports on the correct split roothub, and the
1292 * correct bus_state structure.
1294 /* Find the right roothub. */
1295 hcd = xhci_to_hcd(xhci);
1296 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1297 hcd = xhci->shared_hcd;
1298 bus_state = &xhci->bus_state[hcd_index(hcd)];
1299 if (hcd->speed == HCD_USB3)
1300 port_array = xhci->usb3_ports;
1302 port_array = xhci->usb2_ports;
1303 /* Find the faked port hub number */
1304 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1307 temp = xhci_readl(xhci, port_array[faked_port_index]);
1308 if (hcd->state == HC_STATE_SUSPENDED) {
1309 xhci_dbg(xhci, "resume root hub\n");
1310 usb_hcd_resume_root_hub(hcd);
1313 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1314 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1316 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1317 if (!(temp1 & CMD_RUN)) {
1318 xhci_warn(xhci, "xHC is not running.\n");
1322 if (DEV_SUPERSPEED(temp)) {
1323 xhci_dbg(xhci, "resume SS port %d\n", port_id);
1324 xhci_set_link_state(xhci, port_array, faked_port_index,
1326 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1329 xhci_dbg(xhci, "slot_id is zero\n");
1332 xhci_ring_device(xhci, slot_id);
1333 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1334 /* Clear PORT_PLC */
1335 xhci_test_and_clear_bit(xhci, port_array,
1336 faked_port_index, PORT_PLC);
1338 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1339 bus_state->resume_done[faked_port_index] = jiffies +
1340 msecs_to_jiffies(20);
1341 mod_timer(&hcd->rh_timer,
1342 bus_state->resume_done[faked_port_index]);
1343 /* Do the rest in GetPortStatus */
1347 if (hcd->speed != HCD_USB3)
1348 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1352 /* Update event ring dequeue pointer before dropping the lock */
1353 inc_deq(xhci, xhci->event_ring, true);
1355 /* Don't make the USB core poll the roothub if we got a bad port status
1356 * change event. Besides, at that point we can't tell which roothub
1357 * (USB 2.0 or USB 3.0) to kick.
1359 if (bogus_port_status)
1362 spin_unlock(&xhci->lock);
1363 /* Pass this up to the core */
1364 usb_hcd_poll_rh_status(hcd);
1365 spin_lock(&xhci->lock);
1369 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1370 * at end_trb, which may be in another segment. If the suspect DMA address is a
1371 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1374 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1375 union xhci_trb *start_trb,
1376 union xhci_trb *end_trb,
1377 dma_addr_t suspect_dma)
1379 dma_addr_t start_dma;
1380 dma_addr_t end_seg_dma;
1381 dma_addr_t end_trb_dma;
1382 struct xhci_segment *cur_seg;
1384 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1385 cur_seg = start_seg;
1390 /* We may get an event for a Link TRB in the middle of a TD */
1391 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1392 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1393 /* If the end TRB isn't in this segment, this is set to 0 */
1394 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1396 if (end_trb_dma > 0) {
1397 /* The end TRB is in this segment, so suspect should be here */
1398 if (start_dma <= end_trb_dma) {
1399 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1402 /* Case for one segment with
1403 * a TD wrapped around to the top
1405 if ((suspect_dma >= start_dma &&
1406 suspect_dma <= end_seg_dma) ||
1407 (suspect_dma >= cur_seg->dma &&
1408 suspect_dma <= end_trb_dma))
1413 /* Might still be somewhere in this segment */
1414 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1417 cur_seg = cur_seg->next;
1418 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1419 } while (cur_seg != start_seg);
1424 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1425 unsigned int slot_id, unsigned int ep_index,
1426 unsigned int stream_id,
1427 struct xhci_td *td, union xhci_trb *event_trb)
1429 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1430 ep->ep_state |= EP_HALTED;
1431 ep->stopped_td = td;
1432 ep->stopped_trb = event_trb;
1433 ep->stopped_stream = stream_id;
1435 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1436 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1438 ep->stopped_td = NULL;
1439 ep->stopped_trb = NULL;
1440 ep->stopped_stream = 0;
1442 xhci_ring_cmd_db(xhci);
1445 /* Check if an error has halted the endpoint ring. The class driver will
1446 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1447 * However, a babble and other errors also halt the endpoint ring, and the class
1448 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1449 * Ring Dequeue Pointer command manually.
1451 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1452 struct xhci_ep_ctx *ep_ctx,
1453 unsigned int trb_comp_code)
1455 /* TRB completion codes that may require a manual halt cleanup */
1456 if (trb_comp_code == COMP_TX_ERR ||
1457 trb_comp_code == COMP_BABBLE ||
1458 trb_comp_code == COMP_SPLIT_ERR)
1459 /* The 0.96 spec says a babbling control endpoint
1460 * is not halted. The 0.96 spec says it is. Some HW
1461 * claims to be 0.95 compliant, but it halts the control
1462 * endpoint anyway. Check if a babble halted the
1465 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1466 cpu_to_le32(EP_STATE_HALTED))
1472 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1474 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1475 /* Vendor defined "informational" completion code,
1476 * treat as not-an-error.
1478 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1480 xhci_dbg(xhci, "Treating code as success.\n");
1487 * Finish the td processing, remove the td from td list;
1488 * Return 1 if the urb can be given back.
1490 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1491 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1492 struct xhci_virt_ep *ep, int *status, bool skip)
1494 struct xhci_virt_device *xdev;
1495 struct xhci_ring *ep_ring;
1496 unsigned int slot_id;
1498 struct urb *urb = NULL;
1499 struct xhci_ep_ctx *ep_ctx;
1501 struct urb_priv *urb_priv;
1504 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1505 xdev = xhci->devs[slot_id];
1506 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1507 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1508 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1509 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1514 if (trb_comp_code == COMP_STOP_INVAL ||
1515 trb_comp_code == COMP_STOP) {
1516 /* The Endpoint Stop Command completion will take care of any
1517 * stopped TDs. A stopped TD may be restarted, so don't update
1518 * the ring dequeue pointer or take this TD off any lists yet.
1520 ep->stopped_td = td;
1521 ep->stopped_trb = event_trb;
1524 if (trb_comp_code == COMP_STALL) {
1525 /* The transfer is completed from the driver's
1526 * perspective, but we need to issue a set dequeue
1527 * command for this stalled endpoint to move the dequeue
1528 * pointer past the TD. We can't do that here because
1529 * the halt condition must be cleared first. Let the
1530 * USB class driver clear the stall later.
1532 ep->stopped_td = td;
1533 ep->stopped_trb = event_trb;
1534 ep->stopped_stream = ep_ring->stream_id;
1535 } else if (xhci_requires_manual_halt_cleanup(xhci,
1536 ep_ctx, trb_comp_code)) {
1537 /* Other types of errors halt the endpoint, but the
1538 * class driver doesn't call usb_reset_endpoint() unless
1539 * the error is -EPIPE. Clear the halted status in the
1540 * xHCI hardware manually.
1542 xhci_cleanup_halted_endpoint(xhci,
1543 slot_id, ep_index, ep_ring->stream_id,
1546 /* Update ring dequeue pointer */
1547 while (ep_ring->dequeue != td->last_trb)
1548 inc_deq(xhci, ep_ring, false);
1549 inc_deq(xhci, ep_ring, false);
1553 /* Clean up the endpoint's TD list */
1555 urb_priv = urb->hcpriv;
1557 /* Do one last check of the actual transfer length.
1558 * If the host controller said we transferred more data than
1559 * the buffer length, urb->actual_length will be a very big
1560 * number (since it's unsigned). Play it safe and say we didn't
1561 * transfer anything.
1563 if (urb->actual_length > urb->transfer_buffer_length) {
1564 xhci_warn(xhci, "URB transfer length is wrong, "
1565 "xHC issue? req. len = %u, "
1567 urb->transfer_buffer_length,
1568 urb->actual_length);
1569 urb->actual_length = 0;
1570 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1571 *status = -EREMOTEIO;
1575 list_del_init(&td->td_list);
1576 /* Was this TD slated to be cancelled but completed anyway? */
1577 if (!list_empty(&td->cancelled_td_list))
1578 list_del_init(&td->cancelled_td_list);
1581 /* Giveback the urb when all the tds are completed */
1582 if (urb_priv->td_cnt == urb_priv->length) {
1584 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1585 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1586 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1588 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1589 usb_amd_quirk_pll_enable();
1599 * Process control tds, update urb status and actual_length.
1601 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1602 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1603 struct xhci_virt_ep *ep, int *status)
1605 struct xhci_virt_device *xdev;
1606 struct xhci_ring *ep_ring;
1607 unsigned int slot_id;
1609 struct xhci_ep_ctx *ep_ctx;
1612 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1613 xdev = xhci->devs[slot_id];
1614 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1615 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1616 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1617 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1619 switch (trb_comp_code) {
1621 if (event_trb == ep_ring->dequeue) {
1622 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1623 "without IOC set??\n");
1624 *status = -ESHUTDOWN;
1625 } else if (event_trb != td->last_trb) {
1626 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1627 "without IOC set??\n");
1628 *status = -ESHUTDOWN;
1634 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1635 *status = -EREMOTEIO;
1639 case COMP_STOP_INVAL:
1641 return finish_td(xhci, td, event_trb, event, ep, status, false);
1643 if (!xhci_requires_manual_halt_cleanup(xhci,
1644 ep_ctx, trb_comp_code))
1646 xhci_dbg(xhci, "TRB error code %u, "
1647 "halted endpoint index = %u\n",
1648 trb_comp_code, ep_index);
1649 /* else fall through */
1651 /* Did we transfer part of the data (middle) phase? */
1652 if (event_trb != ep_ring->dequeue &&
1653 event_trb != td->last_trb)
1654 td->urb->actual_length =
1655 td->urb->transfer_buffer_length
1656 - TRB_LEN(le32_to_cpu(event->transfer_len));
1658 td->urb->actual_length = 0;
1660 xhci_cleanup_halted_endpoint(xhci,
1661 slot_id, ep_index, 0, td, event_trb);
1662 return finish_td(xhci, td, event_trb, event, ep, status, true);
1665 * Did we transfer any data, despite the errors that might have
1666 * happened? I.e. did we get past the setup stage?
1668 if (event_trb != ep_ring->dequeue) {
1669 /* The event was for the status stage */
1670 if (event_trb == td->last_trb) {
1671 if (td->urb->actual_length != 0) {
1672 /* Don't overwrite a previously set error code
1674 if ((*status == -EINPROGRESS || *status == 0) &&
1675 (td->urb->transfer_flags
1676 & URB_SHORT_NOT_OK))
1677 /* Did we already see a short data
1679 *status = -EREMOTEIO;
1681 td->urb->actual_length =
1682 td->urb->transfer_buffer_length;
1685 /* Maybe the event was for the data stage? */
1686 td->urb->actual_length =
1687 td->urb->transfer_buffer_length -
1688 TRB_LEN(le32_to_cpu(event->transfer_len));
1689 xhci_dbg(xhci, "Waiting for status "
1695 return finish_td(xhci, td, event_trb, event, ep, status, false);
1699 * Process isochronous tds, update urb packet status and actual_length.
1701 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1702 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1703 struct xhci_virt_ep *ep, int *status)
1705 struct xhci_ring *ep_ring;
1706 struct urb_priv *urb_priv;
1709 union xhci_trb *cur_trb;
1710 struct xhci_segment *cur_seg;
1711 struct usb_iso_packet_descriptor *frame;
1713 bool skip_td = false;
1715 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1716 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1717 urb_priv = td->urb->hcpriv;
1718 idx = urb_priv->td_cnt;
1719 frame = &td->urb->iso_frame_desc[idx];
1721 /* handle completion code */
1722 switch (trb_comp_code) {
1727 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1731 frame->status = -ECOMM;
1734 case COMP_BUFF_OVER:
1736 frame->status = -EOVERFLOW;
1741 frame->status = -EPROTO;
1745 case COMP_STOP_INVAL:
1752 if (trb_comp_code == COMP_SUCCESS || skip_td) {
1753 frame->actual_length = frame->length;
1754 td->urb->actual_length += frame->length;
1756 for (cur_trb = ep_ring->dequeue,
1757 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1758 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1759 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1760 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1761 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1763 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1764 TRB_LEN(le32_to_cpu(event->transfer_len));
1766 if (trb_comp_code != COMP_STOP_INVAL) {
1767 frame->actual_length = len;
1768 td->urb->actual_length += len;
1772 return finish_td(xhci, td, event_trb, event, ep, status, false);
1775 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1776 struct xhci_transfer_event *event,
1777 struct xhci_virt_ep *ep, int *status)
1779 struct xhci_ring *ep_ring;
1780 struct urb_priv *urb_priv;
1781 struct usb_iso_packet_descriptor *frame;
1784 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1785 urb_priv = td->urb->hcpriv;
1786 idx = urb_priv->td_cnt;
1787 frame = &td->urb->iso_frame_desc[idx];
1789 /* The transfer is partly done. */
1790 frame->status = -EXDEV;
1792 /* calc actual length */
1793 frame->actual_length = 0;
1795 /* Update ring dequeue pointer */
1796 while (ep_ring->dequeue != td->last_trb)
1797 inc_deq(xhci, ep_ring, false);
1798 inc_deq(xhci, ep_ring, false);
1800 return finish_td(xhci, td, NULL, event, ep, status, true);
1804 * Process bulk and interrupt tds, update urb status and actual_length.
1806 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1807 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1808 struct xhci_virt_ep *ep, int *status)
1810 struct xhci_ring *ep_ring;
1811 union xhci_trb *cur_trb;
1812 struct xhci_segment *cur_seg;
1815 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1816 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1818 switch (trb_comp_code) {
1820 /* Double check that the HW transferred everything. */
1821 if (event_trb != td->last_trb) {
1822 xhci_warn(xhci, "WARN Successful completion "
1824 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1825 *status = -EREMOTEIO;
1833 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1834 *status = -EREMOTEIO;
1839 /* Others already handled above */
1842 if (trb_comp_code == COMP_SHORT_TX)
1843 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1844 "%d bytes untransferred\n",
1845 td->urb->ep->desc.bEndpointAddress,
1846 td->urb->transfer_buffer_length,
1847 TRB_LEN(le32_to_cpu(event->transfer_len)));
1848 /* Fast path - was this the last TRB in the TD for this URB? */
1849 if (event_trb == td->last_trb) {
1850 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1851 td->urb->actual_length =
1852 td->urb->transfer_buffer_length -
1853 TRB_LEN(le32_to_cpu(event->transfer_len));
1854 if (td->urb->transfer_buffer_length <
1855 td->urb->actual_length) {
1856 xhci_warn(xhci, "HC gave bad length "
1857 "of %d bytes left\n",
1858 TRB_LEN(le32_to_cpu(event->transfer_len)));
1859 td->urb->actual_length = 0;
1860 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1861 *status = -EREMOTEIO;
1865 /* Don't overwrite a previously set error code */
1866 if (*status == -EINPROGRESS) {
1867 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1868 *status = -EREMOTEIO;
1873 td->urb->actual_length =
1874 td->urb->transfer_buffer_length;
1875 /* Ignore a short packet completion if the
1876 * untransferred length was zero.
1878 if (*status == -EREMOTEIO)
1882 /* Slow path - walk the list, starting from the dequeue
1883 * pointer, to get the actual length transferred.
1885 td->urb->actual_length = 0;
1886 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1887 cur_trb != event_trb;
1888 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1889 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1890 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1891 td->urb->actual_length +=
1892 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1894 /* If the ring didn't stop on a Link or No-op TRB, add
1895 * in the actual bytes transferred from the Normal TRB
1897 if (trb_comp_code != COMP_STOP_INVAL)
1898 td->urb->actual_length +=
1899 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1900 TRB_LEN(le32_to_cpu(event->transfer_len));
1903 return finish_td(xhci, td, event_trb, event, ep, status, false);
1907 * If this function returns an error condition, it means it got a Transfer
1908 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1909 * At this point, the host controller is probably hosed and should be reset.
1911 static int handle_tx_event(struct xhci_hcd *xhci,
1912 struct xhci_transfer_event *event)
1914 struct xhci_virt_device *xdev;
1915 struct xhci_virt_ep *ep;
1916 struct xhci_ring *ep_ring;
1917 unsigned int slot_id;
1919 struct xhci_td *td = NULL;
1920 dma_addr_t event_dma;
1921 struct xhci_segment *event_seg;
1922 union xhci_trb *event_trb;
1923 struct urb *urb = NULL;
1924 int status = -EINPROGRESS;
1925 struct urb_priv *urb_priv;
1926 struct xhci_ep_ctx *ep_ctx;
1927 struct list_head *tmp;
1932 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1933 xdev = xhci->devs[slot_id];
1935 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1936 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
1937 (unsigned long long) xhci_trb_virt_to_dma(
1938 xhci->event_ring->deq_seg,
1939 xhci->event_ring->dequeue),
1940 lower_32_bits(le64_to_cpu(event->buffer)),
1941 upper_32_bits(le64_to_cpu(event->buffer)),
1942 le32_to_cpu(event->transfer_len),
1943 le32_to_cpu(event->flags));
1944 xhci_dbg(xhci, "Event ring:\n");
1945 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
1949 /* Endpoint ID is 1 based, our index is zero based */
1950 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1951 ep = &xdev->eps[ep_index];
1952 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1953 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1955 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
1956 EP_STATE_DISABLED) {
1957 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1958 "or incorrect stream ring\n");
1959 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
1960 (unsigned long long) xhci_trb_virt_to_dma(
1961 xhci->event_ring->deq_seg,
1962 xhci->event_ring->dequeue),
1963 lower_32_bits(le64_to_cpu(event->buffer)),
1964 upper_32_bits(le64_to_cpu(event->buffer)),
1965 le32_to_cpu(event->transfer_len),
1966 le32_to_cpu(event->flags));
1967 xhci_dbg(xhci, "Event ring:\n");
1968 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
1972 /* Count current td numbers if ep->skip is set */
1974 list_for_each(tmp, &ep_ring->td_list)
1978 event_dma = le64_to_cpu(event->buffer);
1979 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1980 /* Look for common error cases */
1981 switch (trb_comp_code) {
1982 /* Skip codes that require special handling depending on
1989 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1991 case COMP_STOP_INVAL:
1992 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1995 xhci_dbg(xhci, "Stalled endpoint\n");
1996 ep->ep_state |= EP_HALTED;
2000 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2003 case COMP_SPLIT_ERR:
2005 xhci_dbg(xhci, "Transfer error on endpoint\n");
2009 xhci_dbg(xhci, "Babble error on endpoint\n");
2010 status = -EOVERFLOW;
2013 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2017 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2019 case COMP_BUFF_OVER:
2020 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2024 * When the Isoch ring is empty, the xHC will generate
2025 * a Ring Overrun Event for IN Isoch endpoint or Ring
2026 * Underrun Event for OUT Isoch endpoint.
2028 xhci_dbg(xhci, "underrun event on endpoint\n");
2029 if (!list_empty(&ep_ring->td_list))
2030 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2031 "still with TDs queued?\n",
2032 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2036 xhci_dbg(xhci, "overrun event on endpoint\n");
2037 if (!list_empty(&ep_ring->td_list))
2038 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2039 "still with TDs queued?\n",
2040 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2044 xhci_warn(xhci, "WARN: detect an incompatible device");
2047 case COMP_MISSED_INT:
2049 * When encounter missed service error, one or more isoc tds
2050 * may be missed by xHC.
2051 * Set skip flag of the ep_ring; Complete the missed tds as
2052 * short transfer when process the ep_ring next time.
2055 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2058 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2062 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2068 /* This TRB should be in the TD at the head of this ring's
2071 if (list_empty(&ep_ring->td_list)) {
2072 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2073 "with no TDs queued?\n",
2074 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2076 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2077 (le32_to_cpu(event->flags) &
2078 TRB_TYPE_BITMASK)>>10);
2079 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2082 xhci_dbg(xhci, "td_list is empty while skip "
2083 "flag set. Clear skip flag.\n");
2089 /* We've skipped all the TDs on the ep ring when ep->skip set */
2090 if (ep->skip && td_num == 0) {
2092 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2093 "Clear skip flag.\n");
2098 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2102 /* Is this a TRB in the currently executing TD? */
2103 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2104 td->last_trb, event_dma);
2107 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2108 * is not in the current TD pointed by ep_ring->dequeue because
2109 * that the hardware dequeue pointer still at the previous TRB
2110 * of the current TD. The previous TRB maybe a Link TD or the
2111 * last TRB of the previous TD. The command completion handle
2112 * will take care the rest.
2114 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2121 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2122 /* Some host controllers give a spurious
2123 * successful event after a short transfer.
2126 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2127 ep_ring->last_td_was_short) {
2128 ep_ring->last_td_was_short = false;
2132 /* HC is busted, give up! */
2134 "ERROR Transfer event TRB DMA ptr not "
2135 "part of current TD\n");
2139 ret = skip_isoc_td(xhci, td, event, ep, &status);
2142 if (trb_comp_code == COMP_SHORT_TX)
2143 ep_ring->last_td_was_short = true;
2145 ep_ring->last_td_was_short = false;
2148 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2152 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2153 sizeof(*event_trb)];
2155 * No-op TRB should not trigger interrupts.
2156 * If event_trb is a no-op TRB, it means the
2157 * corresponding TD has been cancelled. Just ignore
2160 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2162 "event_trb is a no-op TRB. Skip it\n");
2166 /* Now update the urb's actual_length and give back to
2169 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2170 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2172 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2173 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2176 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2181 * Do not update event ring dequeue pointer if ep->skip is set.
2182 * Will roll back to continue process missed tds.
2184 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2185 inc_deq(xhci, xhci->event_ring, true);
2190 urb_priv = urb->hcpriv;
2191 /* Leave the TD around for the reset endpoint function
2192 * to use(but only if it's not a control endpoint,
2193 * since we already queued the Set TR dequeue pointer
2194 * command for stalled control endpoints).
2196 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2197 (trb_comp_code != COMP_STALL &&
2198 trb_comp_code != COMP_BABBLE))
2199 xhci_urb_free_priv(xhci, urb_priv);
2201 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2202 if ((urb->actual_length != urb->transfer_buffer_length &&
2203 (urb->transfer_flags &
2204 URB_SHORT_NOT_OK)) ||
2206 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2207 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2208 "expected = %x, status = %d\n",
2209 urb, urb->actual_length,
2210 urb->transfer_buffer_length,
2212 spin_unlock(&xhci->lock);
2213 /* EHCI, UHCI, and OHCI always unconditionally set the
2214 * urb->status of an isochronous endpoint to 0.
2216 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2218 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2219 spin_lock(&xhci->lock);
2223 * If ep->skip is set, it means there are missed tds on the
2224 * endpoint ring need to take care of.
2225 * Process them as short transfer until reach the td pointed by
2228 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2234 * This function handles all OS-owned events on the event ring. It may drop
2235 * xhci->lock between event processing (e.g. to pass up port status changes).
2236 * Returns >0 for "possibly more events to process" (caller should call again),
2237 * otherwise 0 if done. In future, <0 returns should indicate error code.
2239 static int xhci_handle_event(struct xhci_hcd *xhci)
2241 union xhci_trb *event;
2242 int update_ptrs = 1;
2245 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2246 xhci->error_bitmask |= 1 << 1;
2250 event = xhci->event_ring->dequeue;
2251 /* Does the HC or OS own the TRB? */
2252 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2253 xhci->event_ring->cycle_state) {
2254 xhci->error_bitmask |= 1 << 2;
2259 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2260 * speculative reads of the event's flags/data below.
2263 /* FIXME: Handle more event types. */
2264 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2265 case TRB_TYPE(TRB_COMPLETION):
2266 handle_cmd_completion(xhci, &event->event_cmd);
2268 case TRB_TYPE(TRB_PORT_STATUS):
2269 handle_port_status(xhci, event);
2272 case TRB_TYPE(TRB_TRANSFER):
2273 ret = handle_tx_event(xhci, &event->trans_event);
2275 xhci->error_bitmask |= 1 << 9;
2280 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2282 handle_vendor_event(xhci, event);
2284 xhci->error_bitmask |= 1 << 3;
2286 /* Any of the above functions may drop and re-acquire the lock, so check
2287 * to make sure a watchdog timer didn't mark the host as non-responsive.
2289 if (xhci->xhc_state & XHCI_STATE_DYING) {
2290 xhci_dbg(xhci, "xHCI host dying, returning from "
2291 "event handler.\n");
2296 /* Update SW event ring dequeue pointer */
2297 inc_deq(xhci, xhci->event_ring, true);
2299 /* Are there more items on the event ring? Caller will call us again to
2306 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2307 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2308 * indicators of an event TRB error, but we check the status *first* to be safe.
2310 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2312 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2314 union xhci_trb *trb;
2316 union xhci_trb *event_ring_deq;
2319 spin_lock(&xhci->lock);
2320 trb = xhci->event_ring->dequeue;
2321 /* Check if the xHC generated the interrupt, or the irq is shared */
2322 status = xhci_readl(xhci, &xhci->op_regs->status);
2323 if (status == 0xffffffff)
2326 if (!(status & STS_EINT)) {
2327 spin_unlock(&xhci->lock);
2330 if (status & STS_FATAL) {
2331 xhci_warn(xhci, "WARNING: Host System Error\n");
2334 spin_unlock(&xhci->lock);
2339 * Clear the op reg interrupt status first,
2340 * so we can receive interrupts from other MSI-X interrupters.
2341 * Write 1 to clear the interrupt status.
2344 xhci_writel(xhci, status, &xhci->op_regs->status);
2345 /* FIXME when MSI-X is supported and there are multiple vectors */
2346 /* Clear the MSI-X event interrupt status */
2348 if (hcd->irq != -1) {
2350 /* Acknowledge the PCI interrupt */
2351 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2353 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2356 if (xhci->xhc_state & XHCI_STATE_DYING) {
2357 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2358 "Shouldn't IRQs be disabled?\n");
2359 /* Clear the event handler busy flag (RW1C);
2360 * the event ring should be empty.
2362 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2363 xhci_write_64(xhci, temp_64 | ERST_EHB,
2364 &xhci->ir_set->erst_dequeue);
2365 spin_unlock(&xhci->lock);
2370 event_ring_deq = xhci->event_ring->dequeue;
2371 /* FIXME this should be a delayed service routine
2372 * that clears the EHB.
2374 while (xhci_handle_event(xhci) > 0) {}
2376 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2377 /* If necessary, update the HW's version of the event ring deq ptr. */
2378 if (event_ring_deq != xhci->event_ring->dequeue) {
2379 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2380 xhci->event_ring->dequeue);
2382 xhci_warn(xhci, "WARN something wrong with SW event "
2383 "ring dequeue ptr.\n");
2384 /* Update HC event ring dequeue pointer */
2385 temp_64 &= ERST_PTR_MASK;
2386 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2389 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2390 temp_64 |= ERST_EHB;
2391 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2393 spin_unlock(&xhci->lock);
2398 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2400 return xhci_irq(hcd);
2403 /**** Endpoint Ring Operations ****/
2406 * Generic function for queueing a TRB on a ring.
2407 * The caller must have checked to make sure there's room on the ring.
2409 * @more_trbs_coming: Will you enqueue more TRBs before calling
2410 * prepare_transfer()?
2412 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2413 bool consumer, bool more_trbs_coming, bool isoc,
2414 u32 field1, u32 field2, u32 field3, u32 field4)
2416 struct xhci_generic_trb *trb;
2418 trb = &ring->enqueue->generic;
2419 trb->field[0] = cpu_to_le32(field1);
2420 trb->field[1] = cpu_to_le32(field2);
2421 trb->field[2] = cpu_to_le32(field3);
2422 trb->field[3] = cpu_to_le32(field4);
2423 inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2427 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2428 * FIXME allocate segments if the ring is full.
2430 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2431 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2433 /* Make sure the endpoint has been added to xHC schedule */
2435 case EP_STATE_DISABLED:
2437 * USB core changed config/interfaces without notifying us,
2438 * or hardware is reporting the wrong state.
2440 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2442 case EP_STATE_ERROR:
2443 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2444 /* FIXME event handling code for error needs to clear it */
2445 /* XXX not sure if this should be -ENOENT or not */
2447 case EP_STATE_HALTED:
2448 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2449 case EP_STATE_STOPPED:
2450 case EP_STATE_RUNNING:
2453 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2455 * FIXME issue Configure Endpoint command to try to get the HC
2456 * back into a known state.
2460 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2461 /* FIXME allocate more room */
2462 xhci_err(xhci, "ERROR no room on ep ring\n");
2466 if (enqueue_is_link_trb(ep_ring)) {
2467 struct xhci_ring *ring = ep_ring;
2468 union xhci_trb *next;
2470 next = ring->enqueue;
2472 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2473 /* If we're not dealing with 0.95 hardware or isoc rings
2474 * on AMD 0.96 host, clear the chain bit.
2476 if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2477 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2478 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2480 next->link.control |= cpu_to_le32(TRB_CHAIN);
2483 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2485 /* Toggle the cycle bit after the last ring segment. */
2486 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2487 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2489 ring->enq_seg = ring->enq_seg->next;
2490 ring->enqueue = ring->enq_seg->trbs;
2491 next = ring->enqueue;
2498 static int prepare_transfer(struct xhci_hcd *xhci,
2499 struct xhci_virt_device *xdev,
2500 unsigned int ep_index,
2501 unsigned int stream_id,
2502 unsigned int num_trbs,
2504 unsigned int td_index,
2509 struct urb_priv *urb_priv;
2511 struct xhci_ring *ep_ring;
2512 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2514 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2516 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2521 ret = prepare_ring(xhci, ep_ring,
2522 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2523 num_trbs, isoc, mem_flags);
2527 urb_priv = urb->hcpriv;
2528 td = urb_priv->td[td_index];
2530 INIT_LIST_HEAD(&td->td_list);
2531 INIT_LIST_HEAD(&td->cancelled_td_list);
2533 if (td_index == 0) {
2534 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2540 /* Add this TD to the tail of the endpoint ring's TD list */
2541 list_add_tail(&td->td_list, &ep_ring->td_list);
2542 td->start_seg = ep_ring->enq_seg;
2543 td->first_trb = ep_ring->enqueue;
2545 urb_priv->td[td_index] = td;
2550 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2552 int num_sgs, num_trbs, running_total, temp, i;
2553 struct scatterlist *sg;
2556 num_sgs = urb->num_mapped_sgs;
2557 temp = urb->transfer_buffer_length;
2560 for_each_sg(urb->sg, sg, num_sgs, i) {
2561 unsigned int len = sg_dma_len(sg);
2563 /* Scatter gather list entries may cross 64KB boundaries */
2564 running_total = TRB_MAX_BUFF_SIZE -
2565 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2566 running_total &= TRB_MAX_BUFF_SIZE - 1;
2567 if (running_total != 0)
2570 /* How many more 64KB chunks to transfer, how many more TRBs? */
2571 while (running_total < sg_dma_len(sg) && running_total < temp) {
2573 running_total += TRB_MAX_BUFF_SIZE;
2575 len = min_t(int, len, temp);
2583 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2586 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2587 "TRBs, %d left\n", __func__,
2588 urb->ep->desc.bEndpointAddress, num_trbs);
2589 if (running_total != urb->transfer_buffer_length)
2590 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2591 "queued %#x (%d), asked for %#x (%d)\n",
2593 urb->ep->desc.bEndpointAddress,
2594 running_total, running_total,
2595 urb->transfer_buffer_length,
2596 urb->transfer_buffer_length);
2599 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2600 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2601 struct xhci_generic_trb *start_trb)
2604 * Pass all the TRBs to the hardware at once and make sure this write
2609 start_trb->field[3] |= cpu_to_le32(start_cycle);
2611 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2612 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2616 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2617 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2618 * (comprised of sg list entries) can take several service intervals to
2621 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2622 struct urb *urb, int slot_id, unsigned int ep_index)
2624 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2625 xhci->devs[slot_id]->out_ctx, ep_index);
2629 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2630 ep_interval = urb->interval;
2631 /* Convert to microframes */
2632 if (urb->dev->speed == USB_SPEED_LOW ||
2633 urb->dev->speed == USB_SPEED_FULL)
2635 /* FIXME change this to a warning and a suggestion to use the new API
2636 * to set the polling interval (once the API is added).
2638 if (xhci_interval != ep_interval) {
2639 if (printk_ratelimit())
2640 dev_dbg(&urb->dev->dev, "Driver uses different interval"
2641 " (%d microframe%s) than xHCI "
2642 "(%d microframe%s)\n",
2644 ep_interval == 1 ? "" : "s",
2646 xhci_interval == 1 ? "" : "s");
2647 urb->interval = xhci_interval;
2648 /* Convert back to frames for LS/FS devices */
2649 if (urb->dev->speed == USB_SPEED_LOW ||
2650 urb->dev->speed == USB_SPEED_FULL)
2653 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2657 * The TD size is the number of bytes remaining in the TD (including this TRB),
2658 * right shifted by 10.
2659 * It must fit in bits 21:17, so it can't be bigger than 31.
2661 static u32 xhci_td_remainder(unsigned int remainder)
2663 u32 max = (1 << (21 - 17 + 1)) - 1;
2665 if ((remainder >> 10) >= max)
2668 return (remainder >> 10) << 17;
2672 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2673 * the TD (*not* including this TRB).
2675 * Total TD packet count = total_packet_count =
2676 * roundup(TD size in bytes / wMaxPacketSize)
2678 * Packets transferred up to and including this TRB = packets_transferred =
2679 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2681 * TD size = total_packet_count - packets_transferred
2683 * It must fit in bits 21:17, so it can't be bigger than 31.
2686 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
2687 unsigned int total_packet_count, struct urb *urb)
2689 int packets_transferred;
2691 /* One TRB with a zero-length data packet. */
2692 if (running_total == 0 && trb_buff_len == 0)
2695 /* All the TRB queueing functions don't count the current TRB in
2698 packets_transferred = (running_total + trb_buff_len) /
2699 usb_endpoint_maxp(&urb->ep->desc);
2701 return xhci_td_remainder(total_packet_count - packets_transferred);
2704 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2705 struct urb *urb, int slot_id, unsigned int ep_index)
2707 struct xhci_ring *ep_ring;
2708 unsigned int num_trbs;
2709 struct urb_priv *urb_priv;
2711 struct scatterlist *sg;
2713 int trb_buff_len, this_sg_len, running_total;
2714 unsigned int total_packet_count;
2717 bool more_trbs_coming;
2719 struct xhci_generic_trb *start_trb;
2722 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2726 num_trbs = count_sg_trbs_needed(xhci, urb);
2727 num_sgs = urb->num_mapped_sgs;
2728 total_packet_count = roundup(urb->transfer_buffer_length,
2729 usb_endpoint_maxp(&urb->ep->desc));
2731 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2732 ep_index, urb->stream_id,
2733 num_trbs, urb, 0, false, mem_flags);
2734 if (trb_buff_len < 0)
2735 return trb_buff_len;
2737 urb_priv = urb->hcpriv;
2738 td = urb_priv->td[0];
2741 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2742 * until we've finished creating all the other TRBs. The ring's cycle
2743 * state may change as we enqueue the other TRBs, so save it too.
2745 start_trb = &ep_ring->enqueue->generic;
2746 start_cycle = ep_ring->cycle_state;
2750 * How much data is in the first TRB?
2752 * There are three forces at work for TRB buffer pointers and lengths:
2753 * 1. We don't want to walk off the end of this sg-list entry buffer.
2754 * 2. The transfer length that the driver requested may be smaller than
2755 * the amount of memory allocated for this scatter-gather list.
2756 * 3. TRBs buffers can't cross 64KB boundaries.
2759 addr = (u64) sg_dma_address(sg);
2760 this_sg_len = sg_dma_len(sg);
2761 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2762 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2763 if (trb_buff_len > urb->transfer_buffer_length)
2764 trb_buff_len = urb->transfer_buffer_length;
2767 /* Queue the first TRB, even if it's zero-length */
2770 u32 length_field = 0;
2773 /* Don't change the cycle bit of the first TRB until later */
2776 if (start_cycle == 0)
2779 field |= ep_ring->cycle_state;
2781 /* Chain all the TRBs together; clear the chain bit in the last
2782 * TRB to indicate it's the last TRB in the chain.
2787 /* FIXME - add check for ZERO_PACKET flag before this */
2788 td->last_trb = ep_ring->enqueue;
2792 /* Only set interrupt on short packet for IN endpoints */
2793 if (usb_urb_dir_in(urb))
2796 if (TRB_MAX_BUFF_SIZE -
2797 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2798 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2799 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2800 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2801 (unsigned int) addr + trb_buff_len);
2804 /* Set the TRB length, TD size, and interrupter fields. */
2805 if (xhci->hci_version < 0x100) {
2806 remainder = xhci_td_remainder(
2807 urb->transfer_buffer_length -
2810 remainder = xhci_v1_0_td_remainder(running_total,
2811 trb_buff_len, total_packet_count, urb);
2813 length_field = TRB_LEN(trb_buff_len) |
2818 more_trbs_coming = true;
2820 more_trbs_coming = false;
2821 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
2822 lower_32_bits(addr),
2823 upper_32_bits(addr),
2825 field | TRB_TYPE(TRB_NORMAL));
2827 running_total += trb_buff_len;
2829 /* Calculate length for next transfer --
2830 * Are we done queueing all the TRBs for this sg entry?
2832 this_sg_len -= trb_buff_len;
2833 if (this_sg_len == 0) {
2838 addr = (u64) sg_dma_address(sg);
2839 this_sg_len = sg_dma_len(sg);
2841 addr += trb_buff_len;
2844 trb_buff_len = TRB_MAX_BUFF_SIZE -
2845 (addr & (TRB_MAX_BUFF_SIZE - 1));
2846 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2847 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2849 urb->transfer_buffer_length - running_total;
2850 } while (running_total < urb->transfer_buffer_length);
2852 check_trb_math(urb, num_trbs, running_total);
2853 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2854 start_cycle, start_trb);
2858 /* This is very similar to what ehci-q.c qtd_fill() does */
2859 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2860 struct urb *urb, int slot_id, unsigned int ep_index)
2862 struct xhci_ring *ep_ring;
2863 struct urb_priv *urb_priv;
2866 struct xhci_generic_trb *start_trb;
2868 bool more_trbs_coming;
2870 u32 field, length_field;
2872 int running_total, trb_buff_len, ret;
2873 unsigned int total_packet_count;
2877 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2879 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2884 /* How much data is (potentially) left before the 64KB boundary? */
2885 running_total = TRB_MAX_BUFF_SIZE -
2886 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2887 running_total &= TRB_MAX_BUFF_SIZE - 1;
2889 /* If there's some data on this 64KB chunk, or we have to send a
2890 * zero-length transfer, we need at least one TRB
2892 if (running_total != 0 || urb->transfer_buffer_length == 0)
2894 /* How many more 64KB chunks to transfer, how many more TRBs? */
2895 while (running_total < urb->transfer_buffer_length) {
2897 running_total += TRB_MAX_BUFF_SIZE;
2899 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2901 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2902 ep_index, urb->stream_id,
2903 num_trbs, urb, 0, false, mem_flags);
2907 urb_priv = urb->hcpriv;
2908 td = urb_priv->td[0];
2911 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2912 * until we've finished creating all the other TRBs. The ring's cycle
2913 * state may change as we enqueue the other TRBs, so save it too.
2915 start_trb = &ep_ring->enqueue->generic;
2916 start_cycle = ep_ring->cycle_state;
2919 total_packet_count = roundup(urb->transfer_buffer_length,
2920 usb_endpoint_maxp(&urb->ep->desc));
2921 /* How much data is in the first TRB? */
2922 addr = (u64) urb->transfer_dma;
2923 trb_buff_len = TRB_MAX_BUFF_SIZE -
2924 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2925 if (trb_buff_len > urb->transfer_buffer_length)
2926 trb_buff_len = urb->transfer_buffer_length;
2930 /* Queue the first TRB, even if it's zero-length */
2935 /* Don't change the cycle bit of the first TRB until later */
2938 if (start_cycle == 0)
2941 field |= ep_ring->cycle_state;
2943 /* Chain all the TRBs together; clear the chain bit in the last
2944 * TRB to indicate it's the last TRB in the chain.
2949 /* FIXME - add check for ZERO_PACKET flag before this */
2950 td->last_trb = ep_ring->enqueue;
2954 /* Only set interrupt on short packet for IN endpoints */
2955 if (usb_urb_dir_in(urb))
2958 /* Set the TRB length, TD size, and interrupter fields. */
2959 if (xhci->hci_version < 0x100) {
2960 remainder = xhci_td_remainder(
2961 urb->transfer_buffer_length -
2964 remainder = xhci_v1_0_td_remainder(running_total,
2965 trb_buff_len, total_packet_count, urb);
2967 length_field = TRB_LEN(trb_buff_len) |
2972 more_trbs_coming = true;
2974 more_trbs_coming = false;
2975 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
2976 lower_32_bits(addr),
2977 upper_32_bits(addr),
2979 field | TRB_TYPE(TRB_NORMAL));
2981 running_total += trb_buff_len;
2983 /* Calculate length for next transfer */
2984 addr += trb_buff_len;
2985 trb_buff_len = urb->transfer_buffer_length - running_total;
2986 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2987 trb_buff_len = TRB_MAX_BUFF_SIZE;
2988 } while (running_total < urb->transfer_buffer_length);
2990 check_trb_math(urb, num_trbs, running_total);
2991 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2992 start_cycle, start_trb);
2996 /* Caller must have locked xhci->lock */
2997 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2998 struct urb *urb, int slot_id, unsigned int ep_index)
3000 struct xhci_ring *ep_ring;
3003 struct usb_ctrlrequest *setup;
3004 struct xhci_generic_trb *start_trb;
3006 u32 field, length_field;
3007 struct urb_priv *urb_priv;
3010 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3015 * Need to copy setup packet into setup TRB, so we can't use the setup
3018 if (!urb->setup_packet)
3021 /* 1 TRB for setup, 1 for status */
3024 * Don't need to check if we need additional event data and normal TRBs,
3025 * since data in control transfers will never get bigger than 16MB
3026 * XXX: can we get a buffer that crosses 64KB boundaries?
3028 if (urb->transfer_buffer_length > 0)
3030 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3031 ep_index, urb->stream_id,
3032 num_trbs, urb, 0, false, mem_flags);
3036 urb_priv = urb->hcpriv;
3037 td = urb_priv->td[0];
3040 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3041 * until we've finished creating all the other TRBs. The ring's cycle
3042 * state may change as we enqueue the other TRBs, so save it too.
3044 start_trb = &ep_ring->enqueue->generic;
3045 start_cycle = ep_ring->cycle_state;
3047 /* Queue setup TRB - see section 6.4.1.2.1 */
3048 /* FIXME better way to translate setup_packet into two u32 fields? */
3049 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3051 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3052 if (start_cycle == 0)
3055 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3056 if (xhci->hci_version == 0x100) {
3057 if (urb->transfer_buffer_length > 0) {
3058 if (setup->bRequestType & USB_DIR_IN)
3059 field |= TRB_TX_TYPE(TRB_DATA_IN);
3061 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3065 queue_trb(xhci, ep_ring, false, true, false,
3066 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3067 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3068 TRB_LEN(8) | TRB_INTR_TARGET(0),
3069 /* Immediate data in pointer */
3072 /* If there's data, queue data TRBs */
3073 /* Only set interrupt on short packet for IN endpoints */
3074 if (usb_urb_dir_in(urb))
3075 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3077 field = TRB_TYPE(TRB_DATA);
3079 length_field = TRB_LEN(urb->transfer_buffer_length) |
3080 xhci_td_remainder(urb->transfer_buffer_length) |
3082 if (urb->transfer_buffer_length > 0) {
3083 if (setup->bRequestType & USB_DIR_IN)
3084 field |= TRB_DIR_IN;
3085 queue_trb(xhci, ep_ring, false, true, false,
3086 lower_32_bits(urb->transfer_dma),
3087 upper_32_bits(urb->transfer_dma),
3089 field | ep_ring->cycle_state);
3092 /* Save the DMA address of the last TRB in the TD */
3093 td->last_trb = ep_ring->enqueue;
3095 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3096 /* If the device sent data, the status stage is an OUT transfer */
3097 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3101 queue_trb(xhci, ep_ring, false, false, false,
3105 /* Event on completion */
3106 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3108 giveback_first_trb(xhci, slot_id, ep_index, 0,
3109 start_cycle, start_trb);
3113 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3114 struct urb *urb, int i)
3119 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3120 td_len = urb->iso_frame_desc[i].length;
3122 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3131 * The transfer burst count field of the isochronous TRB defines the number of
3132 * bursts that are required to move all packets in this TD. Only SuperSpeed
3133 * devices can burst up to bMaxBurst number of packets per service interval.
3134 * This field is zero based, meaning a value of zero in the field means one
3135 * burst. Basically, for everything but SuperSpeed devices, this field will be
3136 * zero. Only xHCI 1.0 host controllers support this field.
3138 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3139 struct usb_device *udev,
3140 struct urb *urb, unsigned int total_packet_count)
3142 unsigned int max_burst;
3144 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3147 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3148 return roundup(total_packet_count, max_burst + 1) - 1;
3152 * Returns the number of packets in the last "burst" of packets. This field is
3153 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3154 * the last burst packet count is equal to the total number of packets in the
3155 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3156 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3157 * contain 1 to (bMaxBurst + 1) packets.
3159 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3160 struct usb_device *udev,
3161 struct urb *urb, unsigned int total_packet_count)
3163 unsigned int max_burst;
3164 unsigned int residue;
3166 if (xhci->hci_version < 0x100)
3169 switch (udev->speed) {
3170 case USB_SPEED_SUPER:
3171 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3172 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3173 residue = total_packet_count % (max_burst + 1);
3174 /* If residue is zero, the last burst contains (max_burst + 1)
3175 * number of packets, but the TLBPC field is zero-based.
3181 if (total_packet_count == 0)
3183 return total_packet_count - 1;
3187 /* This is for isoc transfer */
3188 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3189 struct urb *urb, int slot_id, unsigned int ep_index)
3191 struct xhci_ring *ep_ring;
3192 struct urb_priv *urb_priv;
3194 int num_tds, trbs_per_td;
3195 struct xhci_generic_trb *start_trb;
3198 u32 field, length_field;
3199 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3200 u64 start_addr, addr;
3202 bool more_trbs_coming;
3204 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3206 num_tds = urb->number_of_packets;
3208 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3212 start_addr = (u64) urb->transfer_dma;
3213 start_trb = &ep_ring->enqueue->generic;
3214 start_cycle = ep_ring->cycle_state;
3216 urb_priv = urb->hcpriv;
3217 /* Queue the first TRB, even if it's zero-length */
3218 for (i = 0; i < num_tds; i++) {
3219 unsigned int total_packet_count;
3220 unsigned int burst_count;
3221 unsigned int residue;
3225 addr = start_addr + urb->iso_frame_desc[i].offset;
3226 td_len = urb->iso_frame_desc[i].length;
3227 td_remain_len = td_len;
3228 total_packet_count = roundup(td_len,
3229 usb_endpoint_maxp(&urb->ep->desc));
3230 /* A zero-length transfer still involves at least one packet. */
3231 if (total_packet_count == 0)
3232 total_packet_count++;
3233 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3234 total_packet_count);
3235 residue = xhci_get_last_burst_packet_count(xhci,
3236 urb->dev, urb, total_packet_count);
3238 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3240 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3241 urb->stream_id, trbs_per_td, urb, i, true,
3249 td = urb_priv->td[i];
3250 for (j = 0; j < trbs_per_td; j++) {
3252 field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
3255 /* Queue the isoc TRB */
3256 field |= TRB_TYPE(TRB_ISOC);
3257 /* Assume URB_ISO_ASAP is set */
3260 if (start_cycle == 0)
3263 field |= ep_ring->cycle_state;
3266 /* Queue other normal TRBs */
3267 field |= TRB_TYPE(TRB_NORMAL);
3268 field |= ep_ring->cycle_state;
3271 /* Only set interrupt on short packet for IN EPs */
3272 if (usb_urb_dir_in(urb))
3275 /* Chain all the TRBs together; clear the chain bit in
3276 * the last TRB to indicate it's the last TRB in the
3279 if (j < trbs_per_td - 1) {
3281 more_trbs_coming = true;
3283 td->last_trb = ep_ring->enqueue;
3285 if (xhci->hci_version == 0x100) {
3286 /* Set BEI bit except for the last td */
3287 if (i < num_tds - 1)
3290 more_trbs_coming = false;
3293 /* Calculate TRB length */
3294 trb_buff_len = TRB_MAX_BUFF_SIZE -
3295 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3296 if (trb_buff_len > td_remain_len)
3297 trb_buff_len = td_remain_len;
3299 /* Set the TRB length, TD size, & interrupter fields. */
3300 if (xhci->hci_version < 0x100) {
3301 remainder = xhci_td_remainder(
3302 td_len - running_total);
3304 remainder = xhci_v1_0_td_remainder(
3305 running_total, trb_buff_len,
3306 total_packet_count, urb);
3308 length_field = TRB_LEN(trb_buff_len) |
3312 queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3313 lower_32_bits(addr),
3314 upper_32_bits(addr),
3317 running_total += trb_buff_len;
3319 addr += trb_buff_len;
3320 td_remain_len -= trb_buff_len;
3323 /* Check TD length */
3324 if (running_total != td_len) {
3325 xhci_err(xhci, "ISOC TD length unmatch\n");
3330 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3331 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3332 usb_amd_quirk_pll_disable();
3334 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3336 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3337 start_cycle, start_trb);
3340 /* Clean up a partially enqueued isoc transfer. */
3342 for (i--; i >= 0; i--)
3343 list_del_init(&urb_priv->td[i]->td_list);
3345 /* Use the first TD as a temporary variable to turn the TDs we've queued
3346 * into No-ops with a software-owned cycle bit. That way the hardware
3347 * won't accidentally start executing bogus TDs when we partially
3348 * overwrite them. td->first_trb and td->start_seg are already set.
3350 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3351 /* Every TRB except the first & last will have its cycle bit flipped. */
3352 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3354 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3355 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3356 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3357 ep_ring->cycle_state = start_cycle;
3358 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3363 * Check transfer ring to guarantee there is enough room for the urb.
3364 * Update ISO URB start_frame and interval.
3365 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3366 * update the urb->start_frame by now.
3367 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3369 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3370 struct urb *urb, int slot_id, unsigned int ep_index)
3372 struct xhci_virt_device *xdev;
3373 struct xhci_ring *ep_ring;
3374 struct xhci_ep_ctx *ep_ctx;
3378 int num_tds, num_trbs, i;
3381 xdev = xhci->devs[slot_id];
3382 ep_ring = xdev->eps[ep_index].ring;
3383 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3386 num_tds = urb->number_of_packets;
3387 for (i = 0; i < num_tds; i++)
3388 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3390 /* Check the ring to guarantee there is enough room for the whole urb.
3391 * Do not insert any td of the urb to the ring if the check failed.
3393 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3394 num_trbs, true, mem_flags);
3398 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3399 start_frame &= 0x3fff;
3401 urb->start_frame = start_frame;
3402 if (urb->dev->speed == USB_SPEED_LOW ||
3403 urb->dev->speed == USB_SPEED_FULL)
3404 urb->start_frame >>= 3;
3406 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3407 ep_interval = urb->interval;
3408 /* Convert to microframes */
3409 if (urb->dev->speed == USB_SPEED_LOW ||
3410 urb->dev->speed == USB_SPEED_FULL)
3412 /* FIXME change this to a warning and a suggestion to use the new API
3413 * to set the polling interval (once the API is added).
3415 if (xhci_interval != ep_interval) {
3416 if (printk_ratelimit())
3417 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3418 " (%d microframe%s) than xHCI "
3419 "(%d microframe%s)\n",
3421 ep_interval == 1 ? "" : "s",
3423 xhci_interval == 1 ? "" : "s");
3424 urb->interval = xhci_interval;
3425 /* Convert back to frames for LS/FS devices */
3426 if (urb->dev->speed == USB_SPEED_LOW ||
3427 urb->dev->speed == USB_SPEED_FULL)
3430 return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3433 /**** Command Ring Operations ****/
3435 /* Generic function for queueing a command TRB on the command ring.
3436 * Check to make sure there's room on the command ring for one command TRB.
3437 * Also check that there's room reserved for commands that must not fail.
3438 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3439 * then only check for the number of reserved spots.
3440 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3441 * because the command event handler may want to resubmit a failed command.
3443 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3444 u32 field3, u32 field4, bool command_must_succeed)
3446 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3449 if (!command_must_succeed)
3452 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3453 reserved_trbs, false, GFP_ATOMIC);
3455 xhci_err(xhci, "ERR: No room for command on command ring\n");
3456 if (command_must_succeed)
3457 xhci_err(xhci, "ERR: Reserved TRB counting for "
3458 "unfailable commands failed.\n");
3461 queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3462 field3, field4 | xhci->cmd_ring->cycle_state);
3466 /* Queue a slot enable or disable request on the command ring */
3467 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3469 return queue_command(xhci, 0, 0, 0,
3470 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3473 /* Queue an address device command TRB */
3474 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3477 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3478 upper_32_bits(in_ctx_ptr), 0,
3479 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3483 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3484 u32 field1, u32 field2, u32 field3, u32 field4)
3486 return queue_command(xhci, field1, field2, field3, field4, false);
3489 /* Queue a reset device command TRB */
3490 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3492 return queue_command(xhci, 0, 0, 0,
3493 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3497 /* Queue a configure endpoint command TRB */
3498 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3499 u32 slot_id, bool command_must_succeed)
3501 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3502 upper_32_bits(in_ctx_ptr), 0,
3503 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3504 command_must_succeed);
3507 /* Queue an evaluate context command TRB */
3508 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3511 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3512 upper_32_bits(in_ctx_ptr), 0,
3513 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3518 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3519 * activity on an endpoint that is about to be suspended.
3521 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3522 unsigned int ep_index, int suspend)
3524 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3525 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3526 u32 type = TRB_TYPE(TRB_STOP_RING);
3527 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3529 return queue_command(xhci, 0, 0, 0,
3530 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3533 /* Set Transfer Ring Dequeue Pointer command.
3534 * This should not be used for endpoints that have streams enabled.
3536 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3537 unsigned int ep_index, unsigned int stream_id,
3538 struct xhci_segment *deq_seg,
3539 union xhci_trb *deq_ptr, u32 cycle_state)
3542 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3543 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3544 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3545 u32 type = TRB_TYPE(TRB_SET_DEQ);
3546 struct xhci_virt_ep *ep;
3548 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3550 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3551 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3555 ep = &xhci->devs[slot_id]->eps[ep_index];
3556 if ((ep->ep_state & SET_DEQ_PENDING)) {
3557 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3558 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3561 ep->queued_deq_seg = deq_seg;
3562 ep->queued_deq_ptr = deq_ptr;
3563 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3564 upper_32_bits(addr), trb_stream_id,
3565 trb_slot_id | trb_ep_index | type, false);
3568 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3569 unsigned int ep_index)
3571 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3572 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3573 u32 type = TRB_TYPE(TRB_RESET_EP);
3575 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,