2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
70 #include "xhci-trace.h"
73 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
76 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
79 unsigned long segment_offset;
81 if (!seg || !trb || trb < seg->trbs)
84 segment_offset = trb - seg->trbs;
85 if (segment_offset >= TRBS_PER_SEGMENT)
87 return seg->dma + (segment_offset * sizeof(*trb));
90 /* Does this link TRB point to the first segment in a ring,
91 * or was the previous TRB the last TRB on the last segment in the ERST?
93 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
94 struct xhci_segment *seg, union xhci_trb *trb)
96 if (ring == xhci->event_ring)
97 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
98 (seg->next == xhci->event_ring->first_seg);
100 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
103 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
104 * segment? I.e. would the updated event TRB pointer step off the end of the
107 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
108 struct xhci_segment *seg, union xhci_trb *trb)
110 if (ring == xhci->event_ring)
111 return trb == &seg->trbs[TRBS_PER_SEGMENT];
113 return TRB_TYPE_LINK_LE32(trb->link.control);
116 static int enqueue_is_link_trb(struct xhci_ring *ring)
118 struct xhci_link_trb *link = &ring->enqueue->link;
119 return TRB_TYPE_LINK_LE32(link->control);
122 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
123 * TRB is in a new segment. This does not skip over link TRBs, and it does not
124 * effect the ring dequeue or enqueue pointers.
126 static void next_trb(struct xhci_hcd *xhci,
127 struct xhci_ring *ring,
128 struct xhci_segment **seg,
129 union xhci_trb **trb)
131 if (last_trb(xhci, ring, *seg, *trb)) {
133 *trb = ((*seg)->trbs);
140 * See Cycle bit rules. SW is the consumer for the event ring only.
141 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
143 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
148 * If this is not event ring, and the dequeue pointer
149 * is not on a link TRB, there is one more usable TRB
151 if (ring->type != TYPE_EVENT &&
152 !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
153 ring->num_trbs_free++;
157 * Update the dequeue pointer further if that was a link TRB or
158 * we're at the end of an event ring segment (which doesn't have
161 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
162 if (ring->type == TYPE_EVENT &&
163 last_trb_on_last_seg(xhci, ring,
164 ring->deq_seg, ring->dequeue)) {
165 ring->cycle_state ^= 1;
167 ring->deq_seg = ring->deq_seg->next;
168 ring->dequeue = ring->deq_seg->trbs;
172 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
176 * See Cycle bit rules. SW is the consumer for the event ring only.
177 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
179 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
180 * chain bit is set), then set the chain bit in all the following link TRBs.
181 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
182 * have their chain bit cleared (so that each Link TRB is a separate TD).
184 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
185 * set, but other sections talk about dealing with the chain bit set. This was
186 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
187 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
189 * @more_trbs_coming: Will you enqueue more TRBs before calling
190 * prepare_transfer()?
192 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
193 bool more_trbs_coming)
196 union xhci_trb *next;
198 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
199 /* If this is not event ring, there is one less usable TRB */
200 if (ring->type != TYPE_EVENT &&
201 !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
202 ring->num_trbs_free--;
203 next = ++(ring->enqueue);
206 /* Update the dequeue pointer further if that was a link TRB or we're at
207 * the end of an event ring segment (which doesn't have link TRBS)
209 while (last_trb(xhci, ring, ring->enq_seg, next)) {
210 if (ring->type != TYPE_EVENT) {
212 * If the caller doesn't plan on enqueueing more
213 * TDs before ringing the doorbell, then we
214 * don't want to give the link TRB to the
215 * hardware just yet. We'll give the link TRB
216 * back in prepare_ring() just before we enqueue
217 * the TD at the top of the ring.
219 if (!chain && !more_trbs_coming)
222 /* If we're not dealing with 0.95 hardware or
223 * isoc rings on AMD 0.96 host,
224 * carry over the chain bit of the previous TRB
225 * (which may mean the chain bit is cleared).
227 if (!(ring->type == TYPE_ISOC &&
228 (xhci->quirks & XHCI_AMD_0x96_HOST))
229 && !xhci_link_trb_quirk(xhci)) {
230 next->link.control &=
231 cpu_to_le32(~TRB_CHAIN);
232 next->link.control |=
235 /* Give this link TRB to the hardware */
237 next->link.control ^= cpu_to_le32(TRB_CYCLE);
239 /* Toggle the cycle bit after the last ring segment. */
240 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
241 ring->cycle_state ^= 1;
244 ring->enq_seg = ring->enq_seg->next;
245 ring->enqueue = ring->enq_seg->trbs;
246 next = ring->enqueue;
251 * Check to see if there's room to enqueue num_trbs on the ring and make sure
252 * enqueue pointer will not advance into dequeue segment. See rules above.
254 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
255 unsigned int num_trbs)
257 int num_trbs_in_deq_seg;
259 if (ring->num_trbs_free < num_trbs)
262 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
263 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
264 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
271 /* Ring the host controller doorbell after placing a command on the ring */
272 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
274 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
277 xhci_dbg(xhci, "// Ding dong!\n");
278 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
279 /* Flush PCI posted writes */
280 readl(&xhci->dba->doorbell[0]);
283 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
288 xhci_dbg(xhci, "Abort command ring\n");
290 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
291 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
292 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
293 &xhci->op_regs->cmd_ring);
295 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
296 * time the completion od all xHCI commands, including
297 * the Command Abort operation. If software doesn't see
298 * CRR negated in a timely manner (e.g. longer than 5
299 * seconds), then it should assume that the there are
300 * larger problems with the xHC and assert HCRST.
302 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
303 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
305 /* we are about to kill xhci, give it one more chance */
306 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
307 &xhci->op_regs->cmd_ring);
309 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
310 CMD_RING_RUNNING, 0, 3 * 1000 * 1000);
314 xhci_err(xhci, "Stopped the command ring failed, "
315 "maybe the host is dead\n");
316 xhci->xhc_state |= XHCI_STATE_DYING;
325 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
326 unsigned int slot_id,
327 unsigned int ep_index,
328 unsigned int stream_id)
330 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
331 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
332 unsigned int ep_state = ep->ep_state;
334 /* Don't ring the doorbell for this endpoint if there are pending
335 * cancellations because we don't want to interrupt processing.
336 * We don't want to restart any stream rings if there's a set dequeue
337 * pointer command pending because the device can choose to start any
338 * stream once the endpoint is on the HW schedule.
340 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
341 (ep_state & EP_HALTED))
343 writel(DB_VALUE(ep_index, stream_id), db_addr);
344 /* The CPU has better things to do at this point than wait for a
345 * write-posting flush. It'll get there soon enough.
349 /* Ring the doorbell for any rings with pending URBs */
350 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
351 unsigned int slot_id,
352 unsigned int ep_index)
354 unsigned int stream_id;
355 struct xhci_virt_ep *ep;
357 ep = &xhci->devs[slot_id]->eps[ep_index];
359 /* A ring has pending URBs if its TD list is not empty */
360 if (!(ep->ep_state & EP_HAS_STREAMS)) {
361 if (ep->ring && !(list_empty(&ep->ring->td_list)))
362 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
366 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
368 struct xhci_stream_info *stream_info = ep->stream_info;
369 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
370 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
375 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
376 unsigned int slot_id, unsigned int ep_index,
377 unsigned int stream_id)
379 struct xhci_virt_ep *ep;
381 ep = &xhci->devs[slot_id]->eps[ep_index];
382 /* Common case: no streams */
383 if (!(ep->ep_state & EP_HAS_STREAMS))
386 if (stream_id == 0) {
388 "WARN: Slot ID %u, ep index %u has streams, "
389 "but URB has no stream ID.\n",
394 if (stream_id < ep->stream_info->num_streams)
395 return ep->stream_info->stream_rings[stream_id];
398 "WARN: Slot ID %u, ep index %u has "
399 "stream IDs 1 to %u allocated, "
400 "but stream ID %u is requested.\n",
402 ep->stream_info->num_streams - 1,
407 /* Get the right ring for the given URB.
408 * If the endpoint supports streams, boundary check the URB's stream ID.
409 * If the endpoint doesn't support streams, return the singular endpoint ring.
411 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
414 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
415 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
419 * Move the xHC's endpoint ring dequeue pointer past cur_td.
420 * Record the new state of the xHC's endpoint ring dequeue segment,
421 * dequeue pointer, and new consumer cycle state in state.
422 * Update our internal representation of the ring's dequeue pointer.
424 * We do this in three jumps:
425 * - First we update our new ring state to be the same as when the xHC stopped.
426 * - Then we traverse the ring to find the segment that contains
427 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
428 * any link TRBs with the toggle cycle bit set.
429 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
430 * if we've moved it past a link TRB with the toggle cycle bit set.
432 * Some of the uses of xhci_generic_trb are grotty, but if they're done
433 * with correct __le32 accesses they should work fine. Only users of this are
436 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
437 unsigned int slot_id, unsigned int ep_index,
438 unsigned int stream_id, struct xhci_td *cur_td,
439 struct xhci_dequeue_state *state)
441 struct xhci_virt_device *dev = xhci->devs[slot_id];
442 struct xhci_virt_ep *ep = &dev->eps[ep_index];
443 struct xhci_ring *ep_ring;
444 struct xhci_segment *new_seg;
445 union xhci_trb *new_deq;
448 bool cycle_found = false;
449 bool td_last_trb_found = false;
451 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
452 ep_index, stream_id);
454 xhci_warn(xhci, "WARN can't find new dequeue state "
455 "for invalid stream ID %u.\n",
460 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
461 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
462 "Finding endpoint context");
463 /* 4.6.9 the css flag is written to the stream context for streams */
464 if (ep->ep_state & EP_HAS_STREAMS) {
465 struct xhci_stream_ctx *ctx =
466 &ep->stream_info->stream_ctx_array[stream_id];
467 hw_dequeue = le64_to_cpu(ctx->stream_ring);
469 struct xhci_ep_ctx *ep_ctx
470 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
471 hw_dequeue = le64_to_cpu(ep_ctx->deq);
474 new_seg = ep_ring->deq_seg;
475 new_deq = ep_ring->dequeue;
476 state->new_cycle_state = hw_dequeue & 0x1;
479 * We want to find the pointer, segment and cycle state of the new trb
480 * (the one after current TD's last_trb). We know the cycle state at
481 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
485 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
486 == (dma_addr_t)(hw_dequeue & ~0xf)) {
488 if (td_last_trb_found)
491 if (new_deq == cur_td->last_trb)
492 td_last_trb_found = true;
495 TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) &&
496 new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE))
497 state->new_cycle_state ^= 0x1;
499 next_trb(xhci, ep_ring, &new_seg, &new_deq);
501 /* Search wrapped around, bail out */
502 if (new_deq == ep->ring->dequeue) {
503 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
504 state->new_deq_seg = NULL;
505 state->new_deq_ptr = NULL;
509 } while (!cycle_found || !td_last_trb_found);
511 state->new_deq_seg = new_seg;
512 state->new_deq_ptr = new_deq;
514 /* Don't update the ring cycle state for the producer (us). */
515 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
516 "Cycle state = 0x%x", state->new_cycle_state);
518 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
519 "New dequeue segment = %p (virtual)",
521 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
522 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
523 "New dequeue pointer = 0x%llx (DMA)",
524 (unsigned long long) addr);
527 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
528 * (The last TRB actually points to the ring enqueue pointer, which is not part
529 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
531 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
532 struct xhci_td *cur_td, bool flip_cycle)
534 struct xhci_segment *cur_seg;
535 union xhci_trb *cur_trb;
537 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
539 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
540 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
541 /* Unchain any chained Link TRBs, but
542 * leave the pointers intact.
544 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
545 /* Flip the cycle bit (link TRBs can't be the first
549 cur_trb->generic.field[3] ^=
550 cpu_to_le32(TRB_CYCLE);
551 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
552 "Cancel (unchain) link TRB");
553 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
554 "Address = %p (0x%llx dma); "
555 "in seg %p (0x%llx dma)",
557 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
559 (unsigned long long)cur_seg->dma);
561 cur_trb->generic.field[0] = 0;
562 cur_trb->generic.field[1] = 0;
563 cur_trb->generic.field[2] = 0;
564 /* Preserve only the cycle bit of this TRB */
565 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
566 /* Flip the cycle bit except on the first or last TRB */
567 if (flip_cycle && cur_trb != cur_td->first_trb &&
568 cur_trb != cur_td->last_trb)
569 cur_trb->generic.field[3] ^=
570 cpu_to_le32(TRB_CYCLE);
571 cur_trb->generic.field[3] |= cpu_to_le32(
572 TRB_TYPE(TRB_TR_NOOP));
573 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
574 "TRB to noop at offset 0x%llx",
576 xhci_trb_virt_to_dma(cur_seg, cur_trb));
578 if (cur_trb == cur_td->last_trb)
583 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
584 struct xhci_virt_ep *ep)
586 ep->ep_state &= ~EP_HALT_PENDING;
587 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
588 * timer is running on another CPU, we don't decrement stop_cmds_pending
589 * (since we didn't successfully stop the watchdog timer).
591 if (del_timer(&ep->stop_cmd_timer))
592 ep->stop_cmds_pending--;
595 /* Must be called with xhci->lock held in interrupt context */
596 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
597 struct xhci_td *cur_td, int status)
601 struct urb_priv *urb_priv;
604 urb_priv = urb->hcpriv;
606 hcd = bus_to_hcd(urb->dev->bus);
608 /* Only giveback urb when this is the last td in urb */
609 if (urb_priv->td_cnt == urb_priv->length) {
610 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
611 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
612 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
613 if (xhci->quirks & XHCI_AMD_PLL_FIX)
614 usb_amd_quirk_pll_enable();
617 usb_hcd_unlink_urb_from_ep(hcd, urb);
619 spin_unlock(&xhci->lock);
620 usb_hcd_giveback_urb(hcd, urb, status);
621 xhci_urb_free_priv(urb_priv);
622 spin_lock(&xhci->lock);
627 * When we get a command completion for a Stop Endpoint Command, we need to
628 * unlink any cancelled TDs from the ring. There are two ways to do that:
630 * 1. If the HW was in the middle of processing the TD that needs to be
631 * cancelled, then we must move the ring's dequeue pointer past the last TRB
632 * in the TD with a Set Dequeue Pointer Command.
633 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
634 * bit cleared) so that the HW will skip over them.
636 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
637 union xhci_trb *trb, struct xhci_event_cmd *event)
639 unsigned int ep_index;
640 struct xhci_ring *ep_ring;
641 struct xhci_virt_ep *ep;
642 struct list_head *entry;
643 struct xhci_td *cur_td = NULL;
644 struct xhci_td *last_unlinked_td;
646 struct xhci_dequeue_state deq_state;
648 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
649 if (!xhci->devs[slot_id])
650 xhci_warn(xhci, "Stop endpoint command "
651 "completion for disabled slot %u\n",
656 memset(&deq_state, 0, sizeof(deq_state));
657 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
658 ep = &xhci->devs[slot_id]->eps[ep_index];
660 if (list_empty(&ep->cancelled_td_list)) {
661 xhci_stop_watchdog_timer_in_irq(xhci, ep);
662 ep->stopped_td = NULL;
663 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
667 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
668 * We have the xHCI lock, so nothing can modify this list until we drop
669 * it. We're also in the event handler, so we can't get re-interrupted
670 * if another Stop Endpoint command completes
672 list_for_each(entry, &ep->cancelled_td_list) {
673 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
674 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
675 "Removing canceled TD starting at 0x%llx (dma).",
676 (unsigned long long)xhci_trb_virt_to_dma(
677 cur_td->start_seg, cur_td->first_trb));
678 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
680 /* This shouldn't happen unless a driver is mucking
681 * with the stream ID after submission. This will
682 * leave the TD on the hardware ring, and the hardware
683 * will try to execute it, and may access a buffer
684 * that has already been freed. In the best case, the
685 * hardware will execute it, and the event handler will
686 * ignore the completion event for that TD, since it was
687 * removed from the td_list for that endpoint. In
688 * short, don't muck with the stream ID after
691 xhci_warn(xhci, "WARN Cancelled URB %p "
692 "has invalid stream ID %u.\n",
694 cur_td->urb->stream_id);
695 goto remove_finished_td;
698 * If we stopped on the TD we need to cancel, then we have to
699 * move the xHC endpoint ring dequeue pointer past this TD.
701 if (cur_td == ep->stopped_td)
702 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
703 cur_td->urb->stream_id,
706 td_to_noop(xhci, ep_ring, cur_td, false);
709 * The event handler won't see a completion for this TD anymore,
710 * so remove it from the endpoint ring's TD list. Keep it in
711 * the cancelled TD list for URB completion later.
713 list_del_init(&cur_td->td_list);
715 last_unlinked_td = cur_td;
716 xhci_stop_watchdog_timer_in_irq(xhci, ep);
718 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
719 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
720 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
721 ep->stopped_td->urb->stream_id, &deq_state);
722 xhci_ring_cmd_db(xhci);
724 /* Otherwise ring the doorbell(s) to restart queued transfers */
725 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
728 ep->stopped_td = NULL;
731 * Drop the lock and complete the URBs in the cancelled TD list.
732 * New TDs to be cancelled might be added to the end of the list before
733 * we can complete all the URBs for the TDs we already unlinked.
734 * So stop when we've completed the URB for the last TD we unlinked.
737 cur_td = list_entry(ep->cancelled_td_list.next,
738 struct xhci_td, cancelled_td_list);
739 list_del_init(&cur_td->cancelled_td_list);
741 /* Clean up the cancelled URB */
742 /* Doesn't matter what we pass for status, since the core will
743 * just overwrite it (because the URB has been unlinked).
745 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
747 /* Stop processing the cancelled list if the watchdog timer is
750 if (xhci->xhc_state & XHCI_STATE_DYING)
752 } while (cur_td != last_unlinked_td);
754 /* Return to the event handler with xhci->lock re-acquired */
757 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
759 struct xhci_td *cur_td;
761 while (!list_empty(&ring->td_list)) {
762 cur_td = list_first_entry(&ring->td_list,
763 struct xhci_td, td_list);
764 list_del_init(&cur_td->td_list);
765 if (!list_empty(&cur_td->cancelled_td_list))
766 list_del_init(&cur_td->cancelled_td_list);
767 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
771 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
772 int slot_id, int ep_index)
774 struct xhci_td *cur_td;
775 struct xhci_virt_ep *ep;
776 struct xhci_ring *ring;
778 ep = &xhci->devs[slot_id]->eps[ep_index];
779 if ((ep->ep_state & EP_HAS_STREAMS) ||
780 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
783 for (stream_id = 0; stream_id < ep->stream_info->num_streams;
785 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
786 "Killing URBs for slot ID %u, ep index %u, stream %u",
787 slot_id, ep_index, stream_id + 1);
788 xhci_kill_ring_urbs(xhci,
789 ep->stream_info->stream_rings[stream_id]);
795 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
796 "Killing URBs for slot ID %u, ep index %u",
798 xhci_kill_ring_urbs(xhci, ring);
800 while (!list_empty(&ep->cancelled_td_list)) {
801 cur_td = list_first_entry(&ep->cancelled_td_list,
802 struct xhci_td, cancelled_td_list);
803 list_del_init(&cur_td->cancelled_td_list);
804 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
808 /* Watchdog timer function for when a stop endpoint command fails to complete.
809 * In this case, we assume the host controller is broken or dying or dead. The
810 * host may still be completing some other events, so we have to be careful to
811 * let the event ring handler and the URB dequeueing/enqueueing functions know
812 * through xhci->state.
814 * The timer may also fire if the host takes a very long time to respond to the
815 * command, and the stop endpoint command completion handler cannot delete the
816 * timer before the timer function is called. Another endpoint cancellation may
817 * sneak in before the timer function can grab the lock, and that may queue
818 * another stop endpoint command and add the timer back. So we cannot use a
819 * simple flag to say whether there is a pending stop endpoint command for a
820 * particular endpoint.
822 * Instead we use a combination of that flag and a counter for the number of
823 * pending stop endpoint commands. If the timer is the tail end of the last
824 * stop endpoint command, and the endpoint's command is still pending, we assume
827 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
829 struct xhci_hcd *xhci;
830 struct xhci_virt_ep *ep;
834 ep = (struct xhci_virt_ep *) arg;
837 spin_lock_irqsave(&xhci->lock, flags);
839 ep->stop_cmds_pending--;
840 if (xhci->xhc_state & XHCI_STATE_DYING) {
841 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
842 "Stop EP timer ran, but another timer marked "
843 "xHCI as DYING, exiting.");
844 spin_unlock_irqrestore(&xhci->lock, flags);
847 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
848 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
849 "Stop EP timer ran, but no command pending, "
851 spin_unlock_irqrestore(&xhci->lock, flags);
855 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
856 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
857 /* Oops, HC is dead or dying or at least not responding to the stop
860 xhci->xhc_state |= XHCI_STATE_DYING;
861 /* Disable interrupts from the host controller and start halting it */
863 spin_unlock_irqrestore(&xhci->lock, flags);
865 ret = xhci_halt(xhci);
867 spin_lock_irqsave(&xhci->lock, flags);
869 /* This is bad; the host is not responding to commands and it's
870 * not allowing itself to be halted. At least interrupts are
871 * disabled. If we call usb_hc_died(), it will attempt to
872 * disconnect all device drivers under this host. Those
873 * disconnect() methods will wait for all URBs to be unlinked,
874 * so we must complete them.
876 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
877 xhci_warn(xhci, "Completing active URBs anyway.\n");
878 /* We could turn all TDs on the rings to no-ops. This won't
879 * help if the host has cached part of the ring, and is slow if
880 * we want to preserve the cycle bit. Skip it and hope the host
881 * doesn't touch the memory.
884 for (i = 0; i < MAX_HC_SLOTS; i++) {
887 for (j = 0; j < 31; j++)
888 xhci_kill_endpoint_urbs(xhci, i, j);
890 spin_unlock_irqrestore(&xhci->lock, flags);
891 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
892 "Calling usb_hc_died()");
893 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
894 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
895 "xHCI host controller is dead.");
899 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
900 struct xhci_virt_device *dev,
901 struct xhci_ring *ep_ring,
902 unsigned int ep_index)
904 union xhci_trb *dequeue_temp;
905 int num_trbs_free_temp;
908 num_trbs_free_temp = ep_ring->num_trbs_free;
909 dequeue_temp = ep_ring->dequeue;
911 /* If we get two back-to-back stalls, and the first stalled transfer
912 * ends just before a link TRB, the dequeue pointer will be left on
913 * the link TRB by the code in the while loop. So we have to update
914 * the dequeue pointer one segment further, or we'll jump off
915 * the segment into la-la-land.
917 if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
918 ep_ring->deq_seg = ep_ring->deq_seg->next;
919 ep_ring->dequeue = ep_ring->deq_seg->trbs;
922 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
923 /* We have more usable TRBs */
924 ep_ring->num_trbs_free++;
926 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
928 if (ep_ring->dequeue ==
929 dev->eps[ep_index].queued_deq_ptr)
931 ep_ring->deq_seg = ep_ring->deq_seg->next;
932 ep_ring->dequeue = ep_ring->deq_seg->trbs;
934 if (ep_ring->dequeue == dequeue_temp) {
941 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
942 ep_ring->num_trbs_free = num_trbs_free_temp;
947 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
948 * we need to clear the set deq pending flag in the endpoint ring state, so that
949 * the TD queueing code can ring the doorbell again. We also need to ring the
950 * endpoint doorbell to restart the ring, but only if there aren't more
951 * cancellations pending.
953 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
954 union xhci_trb *trb, u32 cmd_comp_code)
956 unsigned int ep_index;
957 unsigned int stream_id;
958 struct xhci_ring *ep_ring;
959 struct xhci_virt_device *dev;
960 struct xhci_virt_ep *ep;
961 struct xhci_ep_ctx *ep_ctx;
962 struct xhci_slot_ctx *slot_ctx;
964 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
965 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
966 dev = xhci->devs[slot_id];
967 ep = &dev->eps[ep_index];
969 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
971 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
973 /* XXX: Harmless??? */
977 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
978 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
980 if (cmd_comp_code != COMP_SUCCESS) {
981 unsigned int ep_state;
982 unsigned int slot_state;
984 switch (cmd_comp_code) {
986 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
989 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
990 ep_state = le32_to_cpu(ep_ctx->ep_info);
991 ep_state &= EP_STATE_MASK;
992 slot_state = le32_to_cpu(slot_ctx->dev_state);
993 slot_state = GET_SLOT_STATE(slot_state);
994 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
995 "Slot state = %u, EP state = %u",
996 slot_state, ep_state);
999 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1003 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1007 /* OK what do we do now? The endpoint state is hosed, and we
1008 * should never get to this point if the synchronization between
1009 * queueing, and endpoint state are correct. This might happen
1010 * if the device gets disconnected after we've finished
1011 * cancelling URBs, which might not be an error...
1015 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1016 if (ep->ep_state & EP_HAS_STREAMS) {
1017 struct xhci_stream_ctx *ctx =
1018 &ep->stream_info->stream_ctx_array[stream_id];
1019 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1021 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1023 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1024 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1025 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1026 ep->queued_deq_ptr) == deq) {
1027 /* Update the ring's dequeue segment and dequeue pointer
1028 * to reflect the new position.
1030 update_ring_for_set_deq_completion(xhci, dev,
1033 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1034 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1035 ep->queued_deq_seg, ep->queued_deq_ptr);
1040 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1041 dev->eps[ep_index].queued_deq_seg = NULL;
1042 dev->eps[ep_index].queued_deq_ptr = NULL;
1043 /* Restart any rings with pending URBs */
1044 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1047 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1048 union xhci_trb *trb, u32 cmd_comp_code)
1050 unsigned int ep_index;
1052 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1053 /* This command will only fail if the endpoint wasn't halted,
1054 * but we don't care.
1056 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1057 "Ignoring reset ep completion code of %u", cmd_comp_code);
1059 /* HW with the reset endpoint quirk needs to have a configure endpoint
1060 * command complete before the endpoint can be used. Queue that here
1061 * because the HW can't handle two commands being queued in a row.
1063 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1064 struct xhci_command *command;
1065 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1067 xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n");
1070 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1071 "Queueing configure endpoint command");
1072 xhci_queue_configure_endpoint(xhci, command,
1073 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1075 xhci_ring_cmd_db(xhci);
1077 /* Clear our internal halted state */
1078 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1082 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1085 if (cmd_comp_code == COMP_SUCCESS)
1086 xhci->slot_id = slot_id;
1091 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1093 struct xhci_virt_device *virt_dev;
1095 virt_dev = xhci->devs[slot_id];
1098 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1099 /* Delete default control endpoint resources */
1100 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1101 xhci_free_virt_device(xhci, slot_id);
1104 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1105 struct xhci_event_cmd *event, u32 cmd_comp_code)
1107 struct xhci_virt_device *virt_dev;
1108 struct xhci_input_control_ctx *ctrl_ctx;
1109 unsigned int ep_index;
1110 unsigned int ep_state;
1111 u32 add_flags, drop_flags;
1114 * Configure endpoint commands can come from the USB core
1115 * configuration or alt setting changes, or because the HW
1116 * needed an extra configure endpoint command after a reset
1117 * endpoint command or streams were being configured.
1118 * If the command was for a halted endpoint, the xHCI driver
1119 * is not waiting on the configure endpoint command.
1121 virt_dev = xhci->devs[slot_id];
1122 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1124 xhci_warn(xhci, "Could not get input context, bad type.\n");
1128 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1129 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1130 /* Input ctx add_flags are the endpoint index plus one */
1131 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1133 /* A usb_set_interface() call directly after clearing a halted
1134 * condition may race on this quirky hardware. Not worth
1135 * worrying about, since this is prototype hardware. Not sure
1136 * if this will work for streams, but streams support was
1137 * untested on this prototype.
1139 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1140 ep_index != (unsigned int) -1 &&
1141 add_flags - SLOT_FLAG == drop_flags) {
1142 ep_state = virt_dev->eps[ep_index].ep_state;
1143 if (!(ep_state & EP_HALTED))
1145 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1146 "Completed config ep cmd - "
1147 "last ep index = %d, state = %d",
1148 ep_index, ep_state);
1149 /* Clear internal halted state and restart ring(s) */
1150 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1151 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1157 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1158 struct xhci_event_cmd *event)
1160 xhci_dbg(xhci, "Completed reset device command.\n");
1161 if (!xhci->devs[slot_id])
1162 xhci_warn(xhci, "Reset device command completion "
1163 "for disabled slot %u\n", slot_id);
1166 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1167 struct xhci_event_cmd *event)
1169 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1170 xhci->error_bitmask |= 1 << 6;
1173 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1174 "NEC firmware version %2x.%02x",
1175 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1176 NEC_FW_MINOR(le32_to_cpu(event->status)));
1179 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1181 list_del(&cmd->cmd_list);
1183 if (cmd->completion) {
1184 cmd->status = status;
1185 complete(cmd->completion);
1191 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1193 struct xhci_command *cur_cmd, *tmp_cmd;
1194 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1195 xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT);
1199 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
1200 * If there are other commands waiting then restart the ring and kick the timer.
1201 * This must be called with command ring stopped and xhci->lock held.
1203 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1204 struct xhci_command *cur_cmd)
1206 struct xhci_command *i_cmd, *tmp_cmd;
1209 /* Turn all aborted commands in list to no-ops, then restart */
1210 list_for_each_entry_safe(i_cmd, tmp_cmd, &xhci->cmd_list,
1213 if (i_cmd->status != COMP_CMD_ABORT)
1216 i_cmd->status = COMP_CMD_STOP;
1218 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
1219 i_cmd->command_trb);
1220 /* get cycle state from the original cmd trb */
1221 cycle_state = le32_to_cpu(
1222 i_cmd->command_trb->generic.field[3]) & TRB_CYCLE;
1223 /* modify the command trb to no-op command */
1224 i_cmd->command_trb->generic.field[0] = 0;
1225 i_cmd->command_trb->generic.field[1] = 0;
1226 i_cmd->command_trb->generic.field[2] = 0;
1227 i_cmd->command_trb->generic.field[3] = cpu_to_le32(
1228 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1231 * caller waiting for completion is called when command
1232 * completion event is received for these no-op commands
1236 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1238 /* ring command ring doorbell to restart the command ring */
1239 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
1240 !(xhci->xhc_state & XHCI_STATE_DYING)) {
1241 xhci->current_cmd = cur_cmd;
1242 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1243 xhci_ring_cmd_db(xhci);
1249 void xhci_handle_command_timeout(unsigned long data)
1251 struct xhci_hcd *xhci;
1253 unsigned long flags;
1255 struct xhci_command *cur_cmd = NULL;
1256 xhci = (struct xhci_hcd *) data;
1258 /* mark this command to be cancelled */
1259 spin_lock_irqsave(&xhci->lock, flags);
1260 if (xhci->current_cmd) {
1261 cur_cmd = xhci->current_cmd;
1262 cur_cmd->status = COMP_CMD_ABORT;
1266 /* Make sure command ring is running before aborting it */
1267 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1268 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1269 (hw_ring_state & CMD_RING_RUNNING)) {
1271 spin_unlock_irqrestore(&xhci->lock, flags);
1272 xhci_dbg(xhci, "Command timeout\n");
1273 ret = xhci_abort_cmd_ring(xhci);
1274 if (unlikely(ret == -ESHUTDOWN)) {
1275 xhci_err(xhci, "Abort command ring failed\n");
1276 xhci_cleanup_command_queue(xhci);
1277 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1278 xhci_dbg(xhci, "xHCI host controller is dead.\n");
1282 /* command timeout on stopped ring, ring can't be aborted */
1283 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1284 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1285 spin_unlock_irqrestore(&xhci->lock, flags);
1289 static void handle_cmd_completion(struct xhci_hcd *xhci,
1290 struct xhci_event_cmd *event)
1292 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1294 dma_addr_t cmd_dequeue_dma;
1296 union xhci_trb *cmd_trb;
1297 struct xhci_command *cmd;
1300 cmd_dma = le64_to_cpu(event->cmd_trb);
1301 cmd_trb = xhci->cmd_ring->dequeue;
1302 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1304 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1305 if (cmd_dequeue_dma == 0) {
1306 xhci->error_bitmask |= 1 << 4;
1309 /* Does the DMA address match our internal dequeue pointer address? */
1310 if (cmd_dma != (u64) cmd_dequeue_dma) {
1311 xhci->error_bitmask |= 1 << 5;
1315 cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list);
1317 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1319 "Command completion event does not match command\n");
1323 del_timer(&xhci->cmd_timer);
1325 trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1327 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1329 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1330 if (cmd_comp_code == COMP_CMD_STOP) {
1331 xhci_handle_stopped_cmd_ring(xhci, cmd);
1335 * Host aborted the command ring, check if the current command was
1336 * supposed to be aborted, otherwise continue normally.
1337 * The command ring is stopped now, but the xHC will issue a Command
1338 * Ring Stopped event which will cause us to restart it.
1340 if (cmd_comp_code == COMP_CMD_ABORT) {
1341 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1342 if (cmd->status == COMP_CMD_ABORT)
1346 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1348 case TRB_ENABLE_SLOT:
1349 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1351 case TRB_DISABLE_SLOT:
1352 xhci_handle_cmd_disable_slot(xhci, slot_id);
1355 if (!cmd->completion)
1356 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1359 case TRB_EVAL_CONTEXT:
1364 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1365 le32_to_cpu(cmd_trb->generic.field[3])));
1366 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1369 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1370 le32_to_cpu(cmd_trb->generic.field[3])));
1371 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1374 /* Is this an aborted command turned to NO-OP? */
1375 if (cmd->status == COMP_CMD_STOP)
1376 cmd_comp_code = COMP_CMD_STOP;
1379 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1380 le32_to_cpu(cmd_trb->generic.field[3])));
1381 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1384 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1385 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1387 slot_id = TRB_TO_SLOT_ID(
1388 le32_to_cpu(cmd_trb->generic.field[3]));
1389 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1391 case TRB_NEC_GET_FW:
1392 xhci_handle_cmd_nec_get_fw(xhci, event);
1395 /* Skip over unknown commands on the event ring */
1396 xhci->error_bitmask |= 1 << 6;
1400 /* restart timer if this wasn't the last command */
1401 if (cmd->cmd_list.next != &xhci->cmd_list) {
1402 xhci->current_cmd = list_entry(cmd->cmd_list.next,
1403 struct xhci_command, cmd_list);
1404 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1408 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1410 inc_deq(xhci, xhci->cmd_ring);
1413 static void handle_vendor_event(struct xhci_hcd *xhci,
1414 union xhci_trb *event)
1418 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1419 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1420 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1421 handle_cmd_completion(xhci, &event->event_cmd);
1424 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1425 * port registers -- USB 3.0 and USB 2.0).
1427 * Returns a zero-based port number, which is suitable for indexing into each of
1428 * the split roothubs' port arrays and bus state arrays.
1429 * Add one to it in order to call xhci_find_slot_id_by_port.
1431 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1432 struct xhci_hcd *xhci, u32 port_id)
1435 unsigned int num_similar_speed_ports = 0;
1437 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1438 * and usb2_ports are 0-based indexes. Count the number of similar
1439 * speed ports, up to 1 port before this port.
1441 for (i = 0; i < (port_id - 1); i++) {
1442 u8 port_speed = xhci->port_array[i];
1445 * Skip ports that don't have known speeds, or have duplicate
1446 * Extended Capabilities port speed entries.
1448 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1452 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1453 * 1.1 ports are under the USB 2.0 hub. If the port speed
1454 * matches the device speed, it's a similar speed port.
1456 if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3))
1457 num_similar_speed_ports++;
1459 return num_similar_speed_ports;
1462 static void handle_device_notification(struct xhci_hcd *xhci,
1463 union xhci_trb *event)
1466 struct usb_device *udev;
1468 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1469 if (!xhci->devs[slot_id]) {
1470 xhci_warn(xhci, "Device Notification event for "
1471 "unused slot %u\n", slot_id);
1475 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1477 udev = xhci->devs[slot_id]->udev;
1478 if (udev && udev->parent)
1479 usb_wakeup_notification(udev->parent, udev->portnum);
1482 static void handle_port_status(struct xhci_hcd *xhci,
1483 union xhci_trb *event)
1485 struct usb_hcd *hcd;
1490 unsigned int faked_port_index;
1492 struct xhci_bus_state *bus_state;
1493 __le32 __iomem **port_array;
1494 bool bogus_port_status = false;
1496 /* Port status change events always have a successful completion code */
1497 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1498 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1499 xhci->error_bitmask |= 1 << 8;
1501 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1502 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1504 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1505 if ((port_id <= 0) || (port_id > max_ports)) {
1506 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1507 inc_deq(xhci, xhci->event_ring);
1511 /* Figure out which usb_hcd this port is attached to:
1512 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1514 major_revision = xhci->port_array[port_id - 1];
1516 /* Find the right roothub. */
1517 hcd = xhci_to_hcd(xhci);
1518 if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3))
1519 hcd = xhci->shared_hcd;
1521 if (major_revision == 0) {
1522 xhci_warn(xhci, "Event for port %u not in "
1523 "Extended Capabilities, ignoring.\n",
1525 bogus_port_status = true;
1528 if (major_revision == DUPLICATE_ENTRY) {
1529 xhci_warn(xhci, "Event for port %u duplicated in"
1530 "Extended Capabilities, ignoring.\n",
1532 bogus_port_status = true;
1537 * Hardware port IDs reported by a Port Status Change Event include USB
1538 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1539 * resume event, but we first need to translate the hardware port ID
1540 * into the index into the ports on the correct split roothub, and the
1541 * correct bus_state structure.
1543 bus_state = &xhci->bus_state[hcd_index(hcd)];
1544 if (hcd->speed >= HCD_USB3)
1545 port_array = xhci->usb3_ports;
1547 port_array = xhci->usb2_ports;
1548 /* Find the faked port hub number */
1549 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1552 temp = readl(port_array[faked_port_index]);
1553 if (hcd->state == HC_STATE_SUSPENDED) {
1554 xhci_dbg(xhci, "resume root hub\n");
1555 usb_hcd_resume_root_hub(hcd);
1558 if (hcd->speed >= HCD_USB3 && (temp & PORT_PLS_MASK) == XDEV_INACTIVE)
1559 bus_state->port_remote_wakeup &= ~(1 << faked_port_index);
1561 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1562 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1564 temp1 = readl(&xhci->op_regs->command);
1565 if (!(temp1 & CMD_RUN)) {
1566 xhci_warn(xhci, "xHC is not running.\n");
1570 if (DEV_SUPERSPEED_ANY(temp)) {
1571 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1572 /* Set a flag to say the port signaled remote wakeup,
1573 * so we can tell the difference between the end of
1574 * device and host initiated resume.
1576 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1577 xhci_test_and_clear_bit(xhci, port_array,
1578 faked_port_index, PORT_PLC);
1579 xhci_set_link_state(xhci, port_array, faked_port_index,
1581 /* Need to wait until the next link state change
1582 * indicates the device is actually in U0.
1584 bogus_port_status = true;
1587 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1588 bus_state->resume_done[faked_port_index] = jiffies +
1589 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1590 set_bit(faked_port_index, &bus_state->resuming_ports);
1591 mod_timer(&hcd->rh_timer,
1592 bus_state->resume_done[faked_port_index]);
1593 /* Do the rest in GetPortStatus */
1597 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1598 DEV_SUPERSPEED_ANY(temp)) {
1599 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1600 /* We've just brought the device into U0 through either the
1601 * Resume state after a device remote wakeup, or through the
1602 * U3Exit state after a host-initiated resume. If it's a device
1603 * initiated remote wake, don't pass up the link state change,
1604 * so the roothub behavior is consistent with external
1605 * USB 3.0 hub behavior.
1607 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1608 faked_port_index + 1);
1609 if (slot_id && xhci->devs[slot_id])
1610 xhci_ring_device(xhci, slot_id);
1611 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1612 bus_state->port_remote_wakeup &=
1613 ~(1 << faked_port_index);
1614 xhci_test_and_clear_bit(xhci, port_array,
1615 faked_port_index, PORT_PLC);
1616 usb_wakeup_notification(hcd->self.root_hub,
1617 faked_port_index + 1);
1618 bogus_port_status = true;
1624 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1625 * RExit to a disconnect state). If so, let the the driver know it's
1626 * out of the RExit state.
1628 if (!DEV_SUPERSPEED_ANY(temp) &&
1629 test_and_clear_bit(faked_port_index,
1630 &bus_state->rexit_ports)) {
1631 complete(&bus_state->rexit_done[faked_port_index]);
1632 bogus_port_status = true;
1636 if (hcd->speed < HCD_USB3)
1637 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1641 /* Update event ring dequeue pointer before dropping the lock */
1642 inc_deq(xhci, xhci->event_ring);
1644 /* Don't make the USB core poll the roothub if we got a bad port status
1645 * change event. Besides, at that point we can't tell which roothub
1646 * (USB 2.0 or USB 3.0) to kick.
1648 if (bogus_port_status)
1652 * xHCI port-status-change events occur when the "or" of all the
1653 * status-change bits in the portsc register changes from 0 to 1.
1654 * New status changes won't cause an event if any other change
1655 * bits are still set. When an event occurs, switch over to
1656 * polling to avoid losing status changes.
1658 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1659 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1660 spin_unlock(&xhci->lock);
1661 /* Pass this up to the core */
1662 usb_hcd_poll_rh_status(hcd);
1663 spin_lock(&xhci->lock);
1667 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1668 * at end_trb, which may be in another segment. If the suspect DMA address is a
1669 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1672 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1673 struct xhci_segment *start_seg,
1674 union xhci_trb *start_trb,
1675 union xhci_trb *end_trb,
1676 dma_addr_t suspect_dma,
1679 dma_addr_t start_dma;
1680 dma_addr_t end_seg_dma;
1681 dma_addr_t end_trb_dma;
1682 struct xhci_segment *cur_seg;
1684 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1685 cur_seg = start_seg;
1690 /* We may get an event for a Link TRB in the middle of a TD */
1691 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1692 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1693 /* If the end TRB isn't in this segment, this is set to 0 */
1694 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1698 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1699 (unsigned long long)suspect_dma,
1700 (unsigned long long)start_dma,
1701 (unsigned long long)end_trb_dma,
1702 (unsigned long long)cur_seg->dma,
1703 (unsigned long long)end_seg_dma);
1705 if (end_trb_dma > 0) {
1706 /* The end TRB is in this segment, so suspect should be here */
1707 if (start_dma <= end_trb_dma) {
1708 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1711 /* Case for one segment with
1712 * a TD wrapped around to the top
1714 if ((suspect_dma >= start_dma &&
1715 suspect_dma <= end_seg_dma) ||
1716 (suspect_dma >= cur_seg->dma &&
1717 suspect_dma <= end_trb_dma))
1722 /* Might still be somewhere in this segment */
1723 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1726 cur_seg = cur_seg->next;
1727 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1728 } while (cur_seg != start_seg);
1733 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1734 unsigned int slot_id, unsigned int ep_index,
1735 unsigned int stream_id,
1736 struct xhci_td *td, union xhci_trb *event_trb)
1738 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1739 struct xhci_command *command;
1740 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1744 ep->ep_state |= EP_HALTED;
1745 ep->stopped_stream = stream_id;
1747 xhci_queue_reset_ep(xhci, command, slot_id, ep_index);
1748 xhci_cleanup_stalled_ring(xhci, ep_index, td);
1750 ep->stopped_stream = 0;
1752 xhci_ring_cmd_db(xhci);
1755 /* Check if an error has halted the endpoint ring. The class driver will
1756 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1757 * However, a babble and other errors also halt the endpoint ring, and the class
1758 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1759 * Ring Dequeue Pointer command manually.
1761 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1762 struct xhci_ep_ctx *ep_ctx,
1763 unsigned int trb_comp_code)
1765 /* TRB completion codes that may require a manual halt cleanup */
1766 if (trb_comp_code == COMP_TX_ERR ||
1767 trb_comp_code == COMP_BABBLE ||
1768 trb_comp_code == COMP_SPLIT_ERR)
1769 /* The 0.96 spec says a babbling control endpoint
1770 * is not halted. The 0.96 spec says it is. Some HW
1771 * claims to be 0.95 compliant, but it halts the control
1772 * endpoint anyway. Check if a babble halted the
1775 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1776 cpu_to_le32(EP_STATE_HALTED))
1782 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1784 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1785 /* Vendor defined "informational" completion code,
1786 * treat as not-an-error.
1788 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1790 xhci_dbg(xhci, "Treating code as success.\n");
1797 * Finish the td processing, remove the td from td list;
1798 * Return 1 if the urb can be given back.
1800 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1801 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1802 struct xhci_virt_ep *ep, int *status, bool skip)
1804 struct xhci_virt_device *xdev;
1805 struct xhci_ring *ep_ring;
1806 unsigned int slot_id;
1808 struct urb *urb = NULL;
1809 struct xhci_ep_ctx *ep_ctx;
1811 struct urb_priv *urb_priv;
1814 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1815 xdev = xhci->devs[slot_id];
1816 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1817 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1818 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1819 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1824 if (trb_comp_code == COMP_STOP_INVAL ||
1825 trb_comp_code == COMP_STOP ||
1826 trb_comp_code == COMP_STOP_SHORT) {
1827 /* The Endpoint Stop Command completion will take care of any
1828 * stopped TDs. A stopped TD may be restarted, so don't update
1829 * the ring dequeue pointer or take this TD off any lists yet.
1831 ep->stopped_td = td;
1834 if (trb_comp_code == COMP_STALL ||
1835 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1837 /* Issue a reset endpoint command to clear the host side
1838 * halt, followed by a set dequeue command to move the
1839 * dequeue pointer past the TD.
1840 * The class driver clears the device side halt later.
1842 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1843 ep_ring->stream_id, td, event_trb);
1845 /* Update ring dequeue pointer */
1846 while (ep_ring->dequeue != td->last_trb)
1847 inc_deq(xhci, ep_ring);
1848 inc_deq(xhci, ep_ring);
1852 /* Clean up the endpoint's TD list */
1854 urb_priv = urb->hcpriv;
1856 /* Do one last check of the actual transfer length.
1857 * If the host controller said we transferred more data than the buffer
1858 * length, urb->actual_length will be a very big number (since it's
1859 * unsigned). Play it safe and say we didn't transfer anything.
1861 if (urb->actual_length > urb->transfer_buffer_length) {
1862 xhci_warn(xhci, "URB transfer length is wrong, xHC issue? req. len = %u, act. len = %u\n",
1863 urb->transfer_buffer_length,
1864 urb->actual_length);
1865 urb->actual_length = 0;
1866 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1867 *status = -EREMOTEIO;
1871 list_del_init(&td->td_list);
1872 /* Was this TD slated to be cancelled but completed anyway? */
1873 if (!list_empty(&td->cancelled_td_list))
1874 list_del_init(&td->cancelled_td_list);
1877 /* Giveback the urb when all the tds are completed */
1878 if (urb_priv->td_cnt == urb_priv->length) {
1880 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1881 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1882 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
1883 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1884 usb_amd_quirk_pll_enable();
1893 * Process control tds, update urb status and actual_length.
1895 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1896 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1897 struct xhci_virt_ep *ep, int *status)
1899 struct xhci_virt_device *xdev;
1900 struct xhci_ring *ep_ring;
1901 unsigned int slot_id;
1903 struct xhci_ep_ctx *ep_ctx;
1906 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1907 xdev = xhci->devs[slot_id];
1908 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1909 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1910 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1911 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1913 switch (trb_comp_code) {
1915 if (event_trb == ep_ring->dequeue) {
1916 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1917 "without IOC set??\n");
1918 *status = -ESHUTDOWN;
1919 } else if (event_trb != td->last_trb) {
1920 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1921 "without IOC set??\n");
1922 *status = -ESHUTDOWN;
1928 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1929 *status = -EREMOTEIO;
1933 case COMP_STOP_SHORT:
1934 if (event_trb == ep_ring->dequeue || event_trb == td->last_trb)
1935 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
1937 td->urb->actual_length =
1938 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1940 return finish_td(xhci, td, event_trb, event, ep, status, false);
1942 /* Did we stop at data stage? */
1943 if (event_trb != ep_ring->dequeue && event_trb != td->last_trb)
1944 td->urb->actual_length =
1945 td->urb->transfer_buffer_length -
1946 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1948 case COMP_STOP_INVAL:
1949 return finish_td(xhci, td, event_trb, event, ep, status, false);
1951 if (!xhci_requires_manual_halt_cleanup(xhci,
1952 ep_ctx, trb_comp_code))
1954 xhci_dbg(xhci, "TRB error code %u, "
1955 "halted endpoint index = %u\n",
1956 trb_comp_code, ep_index);
1957 /* else fall through */
1959 /* Did we transfer part of the data (middle) phase? */
1960 if (event_trb != ep_ring->dequeue &&
1961 event_trb != td->last_trb)
1962 td->urb->actual_length =
1963 td->urb->transfer_buffer_length -
1964 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1965 else if (!td->urb_length_set)
1966 td->urb->actual_length = 0;
1968 return finish_td(xhci, td, event_trb, event, ep, status, false);
1971 * Did we transfer any data, despite the errors that might have
1972 * happened? I.e. did we get past the setup stage?
1974 if (event_trb != ep_ring->dequeue) {
1975 /* The event was for the status stage */
1976 if (event_trb == td->last_trb) {
1977 if (td->urb_length_set) {
1978 /* Don't overwrite a previously set error code
1980 if ((*status == -EINPROGRESS || *status == 0) &&
1981 (td->urb->transfer_flags
1982 & URB_SHORT_NOT_OK))
1983 /* Did we already see a short data
1985 *status = -EREMOTEIO;
1987 td->urb->actual_length =
1988 td->urb->transfer_buffer_length;
1992 * Maybe the event was for the data stage? If so, update
1993 * already the actual_length of the URB and flag it as
1994 * set, so that it is not overwritten in the event for
1997 td->urb_length_set = true;
1998 td->urb->actual_length =
1999 td->urb->transfer_buffer_length -
2000 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2001 xhci_dbg(xhci, "Waiting for status "
2007 return finish_td(xhci, td, event_trb, event, ep, status, false);
2011 * Process isochronous tds, update urb packet status and actual_length.
2013 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2014 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2015 struct xhci_virt_ep *ep, int *status)
2017 struct xhci_ring *ep_ring;
2018 struct urb_priv *urb_priv;
2021 union xhci_trb *cur_trb;
2022 struct xhci_segment *cur_seg;
2023 struct usb_iso_packet_descriptor *frame;
2025 bool skip_td = false;
2027 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2028 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2029 urb_priv = td->urb->hcpriv;
2030 idx = urb_priv->td_cnt;
2031 frame = &td->urb->iso_frame_desc[idx];
2033 /* handle completion code */
2034 switch (trb_comp_code) {
2036 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2040 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2041 trb_comp_code = COMP_SHORT_TX;
2043 case COMP_STOP_SHORT:
2045 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2049 frame->status = -ECOMM;
2052 case COMP_BUFF_OVER:
2054 frame->status = -EOVERFLOW;
2059 frame->status = -EPROTO;
2063 frame->status = -EPROTO;
2064 if (event_trb != td->last_trb)
2069 case COMP_STOP_INVAL:
2076 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2077 frame->actual_length = frame->length;
2078 td->urb->actual_length += frame->length;
2079 } else if (trb_comp_code == COMP_STOP_SHORT) {
2080 frame->actual_length =
2081 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2082 td->urb->actual_length += frame->actual_length;
2084 for (cur_trb = ep_ring->dequeue,
2085 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2086 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2087 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2088 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2089 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2091 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2092 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2094 if (trb_comp_code != COMP_STOP_INVAL) {
2095 frame->actual_length = len;
2096 td->urb->actual_length += len;
2100 return finish_td(xhci, td, event_trb, event, ep, status, false);
2103 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2104 struct xhci_transfer_event *event,
2105 struct xhci_virt_ep *ep, int *status)
2107 struct xhci_ring *ep_ring;
2108 struct urb_priv *urb_priv;
2109 struct usb_iso_packet_descriptor *frame;
2112 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2113 urb_priv = td->urb->hcpriv;
2114 idx = urb_priv->td_cnt;
2115 frame = &td->urb->iso_frame_desc[idx];
2117 /* The transfer is partly done. */
2118 frame->status = -EXDEV;
2120 /* calc actual length */
2121 frame->actual_length = 0;
2123 /* Update ring dequeue pointer */
2124 while (ep_ring->dequeue != td->last_trb)
2125 inc_deq(xhci, ep_ring);
2126 inc_deq(xhci, ep_ring);
2128 return finish_td(xhci, td, NULL, event, ep, status, true);
2132 * Process bulk and interrupt tds, update urb status and actual_length.
2134 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2135 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2136 struct xhci_virt_ep *ep, int *status)
2138 struct xhci_ring *ep_ring;
2139 union xhci_trb *cur_trb;
2140 struct xhci_segment *cur_seg;
2143 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2144 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2146 switch (trb_comp_code) {
2148 /* Double check that the HW transferred everything. */
2149 if (event_trb != td->last_trb ||
2150 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2151 xhci_warn(xhci, "WARN Successful completion "
2153 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2154 *status = -EREMOTEIO;
2157 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2158 trb_comp_code = COMP_SHORT_TX;
2163 case COMP_STOP_SHORT:
2165 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2166 *status = -EREMOTEIO;
2171 /* Others already handled above */
2174 if (trb_comp_code == COMP_SHORT_TX)
2175 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2176 "%d bytes untransferred\n",
2177 td->urb->ep->desc.bEndpointAddress,
2178 td->urb->transfer_buffer_length,
2179 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2180 /* Stopped - short packet completion */
2181 if (trb_comp_code == COMP_STOP_SHORT) {
2182 td->urb->actual_length =
2183 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2185 if (td->urb->transfer_buffer_length <
2186 td->urb->actual_length) {
2187 xhci_warn(xhci, "HC gave bad length of %d bytes txed\n",
2188 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2189 td->urb->actual_length = 0;
2190 /* status will be set by usb core for canceled urbs */
2192 /* Fast path - was this the last TRB in the TD for this URB? */
2193 } else if (event_trb == td->last_trb) {
2194 if (td->urb_length_set && trb_comp_code == COMP_SHORT_TX)
2195 return finish_td(xhci, td, event_trb, event, ep,
2198 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2199 td->urb->actual_length =
2200 td->urb->transfer_buffer_length -
2201 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2202 if (td->urb->transfer_buffer_length <
2203 td->urb->actual_length) {
2204 xhci_warn(xhci, "HC gave bad length "
2205 "of %d bytes left\n",
2206 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2207 td->urb->actual_length = 0;
2208 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2209 *status = -EREMOTEIO;
2213 /* Don't overwrite a previously set error code */
2214 if (*status == -EINPROGRESS) {
2215 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2216 *status = -EREMOTEIO;
2221 td->urb->actual_length =
2222 td->urb->transfer_buffer_length;
2223 /* Ignore a short packet completion if the
2224 * untransferred length was zero.
2226 if (*status == -EREMOTEIO)
2230 /* Slow path - walk the list, starting from the dequeue
2231 * pointer, to get the actual length transferred.
2233 td->urb->actual_length = 0;
2234 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2235 cur_trb != event_trb;
2236 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2237 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2238 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2239 td->urb->actual_length +=
2240 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2242 /* If the ring didn't stop on a Link or No-op TRB, add
2243 * in the actual bytes transferred from the Normal TRB
2245 if (trb_comp_code != COMP_STOP_INVAL)
2246 td->urb->actual_length +=
2247 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2248 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2250 if (trb_comp_code == COMP_SHORT_TX) {
2251 xhci_dbg(xhci, "mid bulk/intr SP, wait for last TRB event\n");
2252 td->urb_length_set = true;
2257 return finish_td(xhci, td, event_trb, event, ep, status, false);
2261 * If this function returns an error condition, it means it got a Transfer
2262 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2263 * At this point, the host controller is probably hosed and should be reset.
2265 static int handle_tx_event(struct xhci_hcd *xhci,
2266 struct xhci_transfer_event *event)
2267 __releases(&xhci->lock)
2268 __acquires(&xhci->lock)
2270 struct xhci_virt_device *xdev;
2271 struct xhci_virt_ep *ep;
2272 struct xhci_ring *ep_ring;
2273 unsigned int slot_id;
2275 struct xhci_td *td = NULL;
2276 dma_addr_t event_dma;
2277 struct xhci_segment *event_seg;
2278 union xhci_trb *event_trb;
2279 struct urb *urb = NULL;
2280 int status = -EINPROGRESS;
2281 struct urb_priv *urb_priv;
2282 struct xhci_ep_ctx *ep_ctx;
2283 struct list_head *tmp;
2287 bool handling_skipped_tds = false;
2289 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2290 xdev = xhci->devs[slot_id];
2292 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2293 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2294 (unsigned long long) xhci_trb_virt_to_dma(
2295 xhci->event_ring->deq_seg,
2296 xhci->event_ring->dequeue),
2297 lower_32_bits(le64_to_cpu(event->buffer)),
2298 upper_32_bits(le64_to_cpu(event->buffer)),
2299 le32_to_cpu(event->transfer_len),
2300 le32_to_cpu(event->flags));
2301 xhci_dbg(xhci, "Event ring:\n");
2302 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2306 /* Endpoint ID is 1 based, our index is zero based */
2307 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2308 ep = &xdev->eps[ep_index];
2309 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2310 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2312 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2313 EP_STATE_DISABLED) {
2314 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2315 "or incorrect stream ring\n");
2316 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2317 (unsigned long long) xhci_trb_virt_to_dma(
2318 xhci->event_ring->deq_seg,
2319 xhci->event_ring->dequeue),
2320 lower_32_bits(le64_to_cpu(event->buffer)),
2321 upper_32_bits(le64_to_cpu(event->buffer)),
2322 le32_to_cpu(event->transfer_len),
2323 le32_to_cpu(event->flags));
2324 xhci_dbg(xhci, "Event ring:\n");
2325 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2329 /* Count current td numbers if ep->skip is set */
2331 list_for_each(tmp, &ep_ring->td_list)
2335 event_dma = le64_to_cpu(event->buffer);
2336 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2337 /* Look for common error cases */
2338 switch (trb_comp_code) {
2339 /* Skip codes that require special handling depending on
2343 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2345 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2346 trb_comp_code = COMP_SHORT_TX;
2348 xhci_warn_ratelimited(xhci,
2349 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2353 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2355 case COMP_STOP_INVAL:
2356 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2358 case COMP_STOP_SHORT:
2359 xhci_dbg(xhci, "Stopped with short packet transfer detected\n");
2362 xhci_dbg(xhci, "Stalled endpoint\n");
2363 ep->ep_state |= EP_HALTED;
2367 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2370 case COMP_SPLIT_ERR:
2372 xhci_dbg(xhci, "Transfer error on endpoint\n");
2376 xhci_dbg(xhci, "Babble error on endpoint\n");
2377 status = -EOVERFLOW;
2380 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2384 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2386 case COMP_BUFF_OVER:
2387 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2391 * When the Isoch ring is empty, the xHC will generate
2392 * a Ring Overrun Event for IN Isoch endpoint or Ring
2393 * Underrun Event for OUT Isoch endpoint.
2395 xhci_dbg(xhci, "underrun event on endpoint\n");
2396 if (!list_empty(&ep_ring->td_list))
2397 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2398 "still with TDs queued?\n",
2399 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2403 xhci_dbg(xhci, "overrun event on endpoint\n");
2404 if (!list_empty(&ep_ring->td_list))
2405 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2406 "still with TDs queued?\n",
2407 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2411 xhci_warn(xhci, "WARN: detect an incompatible device");
2414 case COMP_MISSED_INT:
2416 * When encounter missed service error, one or more isoc tds
2417 * may be missed by xHC.
2418 * Set skip flag of the ep_ring; Complete the missed tds as
2419 * short transfer when process the ep_ring next time.
2422 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2426 xhci_dbg(xhci, "No Ping response error, Skip one Isoc TD\n");
2429 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2433 xhci_warn(xhci, "ERROR Unknown event condition %u, HC probably busted\n",
2439 /* This TRB should be in the TD at the head of this ring's
2442 if (list_empty(&ep_ring->td_list)) {
2444 * A stopped endpoint may generate an extra completion
2445 * event if the device was suspended. Don't print
2448 if (!(trb_comp_code == COMP_STOP ||
2449 trb_comp_code == COMP_STOP_INVAL)) {
2450 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2451 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2453 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2454 (le32_to_cpu(event->flags) &
2455 TRB_TYPE_BITMASK)>>10);
2456 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2460 xhci_dbg(xhci, "td_list is empty while skip "
2461 "flag set. Clear skip flag.\n");
2467 /* We've skipped all the TDs on the ep ring when ep->skip set */
2468 if (ep->skip && td_num == 0) {
2470 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2471 "Clear skip flag.\n");
2476 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2480 /* Is this a TRB in the currently executing TD? */
2481 event_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2482 td->last_trb, event_dma, false);
2485 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2486 * is not in the current TD pointed by ep_ring->dequeue because
2487 * that the hardware dequeue pointer still at the previous TRB
2488 * of the current TD. The previous TRB maybe a Link TD or the
2489 * last TRB of the previous TD. The command completion handle
2490 * will take care the rest.
2492 if (!event_seg && (trb_comp_code == COMP_STOP ||
2493 trb_comp_code == COMP_STOP_INVAL)) {
2500 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2501 /* Some host controllers give a spurious
2502 * successful event after a short transfer.
2505 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2506 ep_ring->last_td_was_short) {
2507 ep_ring->last_td_was_short = false;
2511 /* HC is busted, give up! */
2513 "ERROR Transfer event TRB DMA ptr not "
2514 "part of current TD ep_index %d "
2515 "comp_code %u\n", ep_index,
2517 trb_in_td(xhci, ep_ring->deq_seg,
2518 ep_ring->dequeue, td->last_trb,
2523 ret = skip_isoc_td(xhci, td, event, ep, &status);
2526 if (trb_comp_code == COMP_SHORT_TX)
2527 ep_ring->last_td_was_short = true;
2529 ep_ring->last_td_was_short = false;
2532 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2536 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2537 sizeof(*event_trb)];
2539 * No-op TRB should not trigger interrupts.
2540 * If event_trb is a no-op TRB, it means the
2541 * corresponding TD has been cancelled. Just ignore
2544 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2546 "event_trb is a no-op TRB. Skip it\n");
2550 /* Now update the urb's actual_length and give back to
2553 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2554 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2556 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2557 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2560 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2566 handling_skipped_tds = ep->skip &&
2567 trb_comp_code != COMP_MISSED_INT &&
2568 trb_comp_code != COMP_PING_ERR;
2571 * Do not update event ring dequeue pointer if we're in a loop
2572 * processing missed tds.
2574 if (!handling_skipped_tds)
2575 inc_deq(xhci, xhci->event_ring);
2579 urb_priv = urb->hcpriv;
2581 xhci_urb_free_priv(urb_priv);
2583 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2584 if ((urb->actual_length != urb->transfer_buffer_length &&
2585 (urb->transfer_flags &
2586 URB_SHORT_NOT_OK)) ||
2588 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2589 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2590 "expected = %d, status = %d\n",
2591 urb, urb->actual_length,
2592 urb->transfer_buffer_length,
2594 spin_unlock(&xhci->lock);
2595 /* EHCI, UHCI, and OHCI always unconditionally set the
2596 * urb->status of an isochronous endpoint to 0.
2598 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2600 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2601 spin_lock(&xhci->lock);
2605 * If ep->skip is set, it means there are missed tds on the
2606 * endpoint ring need to take care of.
2607 * Process them as short transfer until reach the td pointed by
2610 } while (handling_skipped_tds);
2616 * This function handles all OS-owned events on the event ring. It may drop
2617 * xhci->lock between event processing (e.g. to pass up port status changes).
2618 * Returns >0 for "possibly more events to process" (caller should call again),
2619 * otherwise 0 if done. In future, <0 returns should indicate error code.
2621 static int xhci_handle_event(struct xhci_hcd *xhci)
2623 union xhci_trb *event;
2624 int update_ptrs = 1;
2627 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2628 xhci->error_bitmask |= 1 << 1;
2632 event = xhci->event_ring->dequeue;
2633 /* Does the HC or OS own the TRB? */
2634 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2635 xhci->event_ring->cycle_state) {
2636 xhci->error_bitmask |= 1 << 2;
2641 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2642 * speculative reads of the event's flags/data below.
2645 /* FIXME: Handle more event types. */
2646 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2647 case TRB_TYPE(TRB_COMPLETION):
2648 handle_cmd_completion(xhci, &event->event_cmd);
2650 case TRB_TYPE(TRB_PORT_STATUS):
2651 handle_port_status(xhci, event);
2654 case TRB_TYPE(TRB_TRANSFER):
2655 ret = handle_tx_event(xhci, &event->trans_event);
2657 xhci->error_bitmask |= 1 << 9;
2661 case TRB_TYPE(TRB_DEV_NOTE):
2662 handle_device_notification(xhci, event);
2665 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2667 handle_vendor_event(xhci, event);
2669 xhci->error_bitmask |= 1 << 3;
2671 /* Any of the above functions may drop and re-acquire the lock, so check
2672 * to make sure a watchdog timer didn't mark the host as non-responsive.
2674 if (xhci->xhc_state & XHCI_STATE_DYING) {
2675 xhci_dbg(xhci, "xHCI host dying, returning from "
2676 "event handler.\n");
2681 /* Update SW event ring dequeue pointer */
2682 inc_deq(xhci, xhci->event_ring);
2684 /* Are there more items on the event ring? Caller will call us again to
2691 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2692 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2693 * indicators of an event TRB error, but we check the status *first* to be safe.
2695 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2697 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2700 union xhci_trb *event_ring_deq;
2703 spin_lock(&xhci->lock);
2704 /* Check if the xHC generated the interrupt, or the irq is shared */
2705 status = readl(&xhci->op_regs->status);
2706 if (status == 0xffffffff)
2709 if (!(status & STS_EINT)) {
2710 spin_unlock(&xhci->lock);
2713 if (status & STS_FATAL) {
2714 xhci_warn(xhci, "WARNING: Host System Error\n");
2717 spin_unlock(&xhci->lock);
2722 * Clear the op reg interrupt status first,
2723 * so we can receive interrupts from other MSI-X interrupters.
2724 * Write 1 to clear the interrupt status.
2727 writel(status, &xhci->op_regs->status);
2728 /* FIXME when MSI-X is supported and there are multiple vectors */
2729 /* Clear the MSI-X event interrupt status */
2733 /* Acknowledge the PCI interrupt */
2734 irq_pending = readl(&xhci->ir_set->irq_pending);
2735 irq_pending |= IMAN_IP;
2736 writel(irq_pending, &xhci->ir_set->irq_pending);
2739 if (xhci->xhc_state & XHCI_STATE_DYING) {
2740 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2741 "Shouldn't IRQs be disabled?\n");
2742 /* Clear the event handler busy flag (RW1C);
2743 * the event ring should be empty.
2745 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2746 xhci_write_64(xhci, temp_64 | ERST_EHB,
2747 &xhci->ir_set->erst_dequeue);
2748 spin_unlock(&xhci->lock);
2753 event_ring_deq = xhci->event_ring->dequeue;
2754 /* FIXME this should be a delayed service routine
2755 * that clears the EHB.
2757 while (xhci_handle_event(xhci) > 0) {}
2759 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2760 /* If necessary, update the HW's version of the event ring deq ptr. */
2761 if (event_ring_deq != xhci->event_ring->dequeue) {
2762 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2763 xhci->event_ring->dequeue);
2765 xhci_warn(xhci, "WARN something wrong with SW event "
2766 "ring dequeue ptr.\n");
2767 /* Update HC event ring dequeue pointer */
2768 temp_64 &= ERST_PTR_MASK;
2769 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2772 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2773 temp_64 |= ERST_EHB;
2774 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2776 spin_unlock(&xhci->lock);
2781 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2783 return xhci_irq(hcd);
2786 /**** Endpoint Ring Operations ****/
2789 * Generic function for queueing a TRB on a ring.
2790 * The caller must have checked to make sure there's room on the ring.
2792 * @more_trbs_coming: Will you enqueue more TRBs before calling
2793 * prepare_transfer()?
2795 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2796 bool more_trbs_coming,
2797 u32 field1, u32 field2, u32 field3, u32 field4)
2799 struct xhci_generic_trb *trb;
2801 trb = &ring->enqueue->generic;
2802 trb->field[0] = cpu_to_le32(field1);
2803 trb->field[1] = cpu_to_le32(field2);
2804 trb->field[2] = cpu_to_le32(field3);
2805 trb->field[3] = cpu_to_le32(field4);
2806 inc_enq(xhci, ring, more_trbs_coming);
2810 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2811 * FIXME allocate segments if the ring is full.
2813 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2814 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2816 unsigned int num_trbs_needed;
2818 /* Make sure the endpoint has been added to xHC schedule */
2820 case EP_STATE_DISABLED:
2822 * USB core changed config/interfaces without notifying us,
2823 * or hardware is reporting the wrong state.
2825 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2827 case EP_STATE_ERROR:
2828 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2829 /* FIXME event handling code for error needs to clear it */
2830 /* XXX not sure if this should be -ENOENT or not */
2832 case EP_STATE_HALTED:
2833 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2834 case EP_STATE_STOPPED:
2835 case EP_STATE_RUNNING:
2838 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2840 * FIXME issue Configure Endpoint command to try to get the HC
2841 * back into a known state.
2847 if (room_on_ring(xhci, ep_ring, num_trbs))
2850 if (ep_ring == xhci->cmd_ring) {
2851 xhci_err(xhci, "Do not support expand command ring\n");
2855 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2856 "ERROR no room on ep ring, try ring expansion");
2857 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2858 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2860 xhci_err(xhci, "Ring expansion failed\n");
2865 if (enqueue_is_link_trb(ep_ring)) {
2866 struct xhci_ring *ring = ep_ring;
2867 union xhci_trb *next;
2869 next = ring->enqueue;
2871 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2872 /* If we're not dealing with 0.95 hardware or isoc rings
2873 * on AMD 0.96 host, clear the chain bit.
2875 if (!xhci_link_trb_quirk(xhci) &&
2876 !(ring->type == TYPE_ISOC &&
2877 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2878 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2880 next->link.control |= cpu_to_le32(TRB_CHAIN);
2883 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2885 /* Toggle the cycle bit after the last ring segment. */
2886 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2887 ring->cycle_state ^= 1;
2889 ring->enq_seg = ring->enq_seg->next;
2890 ring->enqueue = ring->enq_seg->trbs;
2891 next = ring->enqueue;
2898 static int prepare_transfer(struct xhci_hcd *xhci,
2899 struct xhci_virt_device *xdev,
2900 unsigned int ep_index,
2901 unsigned int stream_id,
2902 unsigned int num_trbs,
2904 unsigned int td_index,
2908 struct urb_priv *urb_priv;
2910 struct xhci_ring *ep_ring;
2911 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2913 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2915 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2920 ret = prepare_ring(xhci, ep_ring,
2921 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2922 num_trbs, mem_flags);
2926 urb_priv = urb->hcpriv;
2927 td = urb_priv->td[td_index];
2929 INIT_LIST_HEAD(&td->td_list);
2930 INIT_LIST_HEAD(&td->cancelled_td_list);
2932 if (td_index == 0) {
2933 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2939 /* Add this TD to the tail of the endpoint ring's TD list */
2940 list_add_tail(&td->td_list, &ep_ring->td_list);
2941 td->start_seg = ep_ring->enq_seg;
2942 td->first_trb = ep_ring->enqueue;
2944 urb_priv->td[td_index] = td;
2949 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2951 int num_sgs, num_trbs, running_total, temp, i;
2952 struct scatterlist *sg;
2955 num_sgs = urb->num_mapped_sgs;
2956 temp = urb->transfer_buffer_length;
2959 for_each_sg(urb->sg, sg, num_sgs, i) {
2960 unsigned int len = sg_dma_len(sg);
2962 /* Scatter gather list entries may cross 64KB boundaries */
2963 running_total = TRB_MAX_BUFF_SIZE -
2964 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2965 running_total &= TRB_MAX_BUFF_SIZE - 1;
2966 if (running_total != 0)
2969 /* How many more 64KB chunks to transfer, how many more TRBs? */
2970 while (running_total < sg_dma_len(sg) && running_total < temp) {
2972 running_total += TRB_MAX_BUFF_SIZE;
2974 len = min_t(int, len, temp);
2982 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2985 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2986 "TRBs, %d left\n", __func__,
2987 urb->ep->desc.bEndpointAddress, num_trbs);
2988 if (running_total != urb->transfer_buffer_length)
2989 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2990 "queued %#x (%d), asked for %#x (%d)\n",
2992 urb->ep->desc.bEndpointAddress,
2993 running_total, running_total,
2994 urb->transfer_buffer_length,
2995 urb->transfer_buffer_length);
2998 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2999 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3000 struct xhci_generic_trb *start_trb)
3003 * Pass all the TRBs to the hardware at once and make sure this write
3008 start_trb->field[3] |= cpu_to_le32(start_cycle);
3010 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3011 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3015 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3016 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3017 * (comprised of sg list entries) can take several service intervals to
3020 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3021 struct urb *urb, int slot_id, unsigned int ep_index)
3023 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3024 xhci->devs[slot_id]->out_ctx, ep_index);
3028 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3029 ep_interval = urb->interval;
3030 /* Convert to microframes */
3031 if (urb->dev->speed == USB_SPEED_LOW ||
3032 urb->dev->speed == USB_SPEED_FULL)
3034 /* FIXME change this to a warning and a suggestion to use the new API
3035 * to set the polling interval (once the API is added).
3037 if (xhci_interval != ep_interval) {
3038 dev_dbg_ratelimited(&urb->dev->dev,
3039 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3040 ep_interval, ep_interval == 1 ? "" : "s",
3041 xhci_interval, xhci_interval == 1 ? "" : "s");
3042 urb->interval = xhci_interval;
3043 /* Convert back to frames for LS/FS devices */
3044 if (urb->dev->speed == USB_SPEED_LOW ||
3045 urb->dev->speed == USB_SPEED_FULL)
3048 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3052 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3053 * packets remaining in the TD (*not* including this TRB).
3055 * Total TD packet count = total_packet_count =
3056 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3058 * Packets transferred up to and including this TRB = packets_transferred =
3059 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3061 * TD size = total_packet_count - packets_transferred
3063 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3064 * including this TRB, right shifted by 10
3066 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3067 * This is taken care of in the TRB_TD_SIZE() macro
3069 * The last TRB in a TD must have the TD size set to zero.
3071 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3072 int trb_buff_len, unsigned int td_total_len,
3073 struct urb *urb, unsigned int num_trbs_left)
3075 u32 maxp, total_packet_count;
3077 if (xhci->hci_version < 0x100)
3078 return ((td_total_len - transferred) >> 10);
3080 maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3081 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3083 /* One TRB with a zero-length data packet. */
3084 if (num_trbs_left == 0 || (transferred == 0 && trb_buff_len == 0) ||
3085 trb_buff_len == td_total_len)
3088 /* Queueing functions don't count the current TRB into transferred */
3089 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3093 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3094 struct urb *urb, int slot_id, unsigned int ep_index)
3096 struct xhci_ring *ep_ring;
3097 unsigned int num_trbs;
3098 struct urb_priv *urb_priv;
3100 struct scatterlist *sg;
3102 int trb_buff_len, this_sg_len, running_total, ret;
3103 unsigned int total_packet_count;
3104 bool zero_length_needed;
3108 bool more_trbs_coming;
3110 struct xhci_generic_trb *start_trb;
3113 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3117 num_trbs = count_sg_trbs_needed(xhci, urb);
3118 num_sgs = urb->num_mapped_sgs;
3119 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3120 usb_endpoint_maxp(&urb->ep->desc));
3122 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3123 ep_index, urb->stream_id,
3124 num_trbs, urb, 0, mem_flags);
3128 urb_priv = urb->hcpriv;
3130 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3131 zero_length_needed = urb->transfer_flags & URB_ZERO_PACKET &&
3132 urb_priv->length == 2;
3133 if (zero_length_needed) {
3135 xhci_dbg(xhci, "Creating zero length td.\n");
3136 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3137 ep_index, urb->stream_id,
3138 1, urb, 1, mem_flags);
3143 td = urb_priv->td[0];
3146 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3147 * until we've finished creating all the other TRBs. The ring's cycle
3148 * state may change as we enqueue the other TRBs, so save it too.
3150 start_trb = &ep_ring->enqueue->generic;
3151 start_cycle = ep_ring->cycle_state;
3155 * How much data is in the first TRB?
3157 * There are three forces at work for TRB buffer pointers and lengths:
3158 * 1. We don't want to walk off the end of this sg-list entry buffer.
3159 * 2. The transfer length that the driver requested may be smaller than
3160 * the amount of memory allocated for this scatter-gather list.
3161 * 3. TRBs buffers can't cross 64KB boundaries.
3164 addr = (u64) sg_dma_address(sg);
3165 this_sg_len = sg_dma_len(sg);
3166 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3167 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3168 if (trb_buff_len > urb->transfer_buffer_length)
3169 trb_buff_len = urb->transfer_buffer_length;
3172 last_trb_num = zero_length_needed ? 2 : 1;
3173 /* Queue the first TRB, even if it's zero-length */
3176 u32 length_field = 0;
3179 /* Don't change the cycle bit of the first TRB until later */
3182 if (start_cycle == 0)
3185 field |= ep_ring->cycle_state;
3187 /* Chain all the TRBs together; clear the chain bit in the last
3188 * TRB to indicate it's the last TRB in the chain.
3190 if (num_trbs > last_trb_num) {
3192 } else if (num_trbs == last_trb_num) {
3193 td->last_trb = ep_ring->enqueue;
3195 } else if (zero_length_needed && num_trbs == 1) {
3197 urb_priv->td[1]->last_trb = ep_ring->enqueue;
3201 /* Only set interrupt on short packet for IN endpoints */
3202 if (usb_urb_dir_in(urb))
3205 if (TRB_MAX_BUFF_SIZE -
3206 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3207 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3208 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3209 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3210 (unsigned int) addr + trb_buff_len);
3213 /* Set the TRB length, TD size, and interrupter fields. */
3214 remainder = xhci_td_remainder(xhci, running_total, trb_buff_len,
3215 urb->transfer_buffer_length,
3218 length_field = TRB_LEN(trb_buff_len) |
3219 TRB_TD_SIZE(remainder) |
3223 more_trbs_coming = true;
3225 more_trbs_coming = false;
3226 queue_trb(xhci, ep_ring, more_trbs_coming,
3227 lower_32_bits(addr),
3228 upper_32_bits(addr),
3230 field | TRB_TYPE(TRB_NORMAL));
3232 running_total += trb_buff_len;
3234 /* Calculate length for next transfer --
3235 * Are we done queueing all the TRBs for this sg entry?
3237 this_sg_len -= trb_buff_len;
3238 if (this_sg_len == 0) {
3243 addr = (u64) sg_dma_address(sg);
3244 this_sg_len = sg_dma_len(sg);
3246 addr += trb_buff_len;
3249 trb_buff_len = TRB_MAX_BUFF_SIZE -
3250 (addr & (TRB_MAX_BUFF_SIZE - 1));
3251 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3252 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3254 urb->transfer_buffer_length - running_total;
3255 } while (num_trbs > 0);
3257 check_trb_math(urb, num_trbs, running_total);
3258 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3259 start_cycle, start_trb);
3263 /* This is very similar to what ehci-q.c qtd_fill() does */
3264 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3265 struct urb *urb, int slot_id, unsigned int ep_index)
3267 struct xhci_ring *ep_ring;
3268 struct urb_priv *urb_priv;
3271 struct xhci_generic_trb *start_trb;
3274 bool more_trbs_coming;
3275 bool zero_length_needed;
3277 u32 field, length_field;
3279 int running_total, trb_buff_len, ret;
3280 unsigned int total_packet_count;
3284 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3286 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3291 /* How much data is (potentially) left before the 64KB boundary? */
3292 running_total = TRB_MAX_BUFF_SIZE -
3293 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3294 running_total &= TRB_MAX_BUFF_SIZE - 1;
3296 /* If there's some data on this 64KB chunk, or we have to send a
3297 * zero-length transfer, we need at least one TRB
3299 if (running_total != 0 || urb->transfer_buffer_length == 0)
3301 /* How many more 64KB chunks to transfer, how many more TRBs? */
3302 while (running_total < urb->transfer_buffer_length) {
3304 running_total += TRB_MAX_BUFF_SIZE;
3307 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3308 ep_index, urb->stream_id,
3309 num_trbs, urb, 0, mem_flags);
3313 urb_priv = urb->hcpriv;
3315 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3316 zero_length_needed = urb->transfer_flags & URB_ZERO_PACKET &&
3317 urb_priv->length == 2;
3318 if (zero_length_needed) {
3320 xhci_dbg(xhci, "Creating zero length td.\n");
3321 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3322 ep_index, urb->stream_id,
3323 1, urb, 1, mem_flags);
3328 td = urb_priv->td[0];
3331 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3332 * until we've finished creating all the other TRBs. The ring's cycle
3333 * state may change as we enqueue the other TRBs, so save it too.
3335 start_trb = &ep_ring->enqueue->generic;
3336 start_cycle = ep_ring->cycle_state;
3339 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3340 usb_endpoint_maxp(&urb->ep->desc));
3341 /* How much data is in the first TRB? */
3342 addr = (u64) urb->transfer_dma;
3343 trb_buff_len = TRB_MAX_BUFF_SIZE -
3344 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3345 if (trb_buff_len > urb->transfer_buffer_length)
3346 trb_buff_len = urb->transfer_buffer_length;
3349 last_trb_num = zero_length_needed ? 2 : 1;
3350 /* Queue the first TRB, even if it's zero-length */
3355 /* Don't change the cycle bit of the first TRB until later */
3358 if (start_cycle == 0)
3361 field |= ep_ring->cycle_state;
3363 /* Chain all the TRBs together; clear the chain bit in the last
3364 * TRB to indicate it's the last TRB in the chain.
3366 if (num_trbs > last_trb_num) {
3368 } else if (num_trbs == last_trb_num) {
3369 td->last_trb = ep_ring->enqueue;
3371 } else if (zero_length_needed && num_trbs == 1) {
3373 urb_priv->td[1]->last_trb = ep_ring->enqueue;
3377 /* Only set interrupt on short packet for IN endpoints */
3378 if (usb_urb_dir_in(urb))
3381 /* Set the TRB length, TD size, and interrupter fields. */
3382 remainder = xhci_td_remainder(xhci, running_total, trb_buff_len,
3383 urb->transfer_buffer_length,
3386 length_field = TRB_LEN(trb_buff_len) |
3387 TRB_TD_SIZE(remainder) |
3391 more_trbs_coming = true;
3393 more_trbs_coming = false;
3394 queue_trb(xhci, ep_ring, more_trbs_coming,
3395 lower_32_bits(addr),
3396 upper_32_bits(addr),
3398 field | TRB_TYPE(TRB_NORMAL));
3400 running_total += trb_buff_len;
3402 /* Calculate length for next transfer */
3403 addr += trb_buff_len;
3404 trb_buff_len = urb->transfer_buffer_length - running_total;
3405 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3406 trb_buff_len = TRB_MAX_BUFF_SIZE;
3407 } while (num_trbs > 0);
3409 check_trb_math(urb, num_trbs, running_total);
3410 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3411 start_cycle, start_trb);
3415 /* Caller must have locked xhci->lock */
3416 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3417 struct urb *urb, int slot_id, unsigned int ep_index)
3419 struct xhci_ring *ep_ring;
3422 struct usb_ctrlrequest *setup;
3423 struct xhci_generic_trb *start_trb;
3425 u32 field, length_field, remainder;
3426 struct urb_priv *urb_priv;
3429 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3434 * Need to copy setup packet into setup TRB, so we can't use the setup
3437 if (!urb->setup_packet)
3440 /* 1 TRB for setup, 1 for status */
3443 * Don't need to check if we need additional event data and normal TRBs,
3444 * since data in control transfers will never get bigger than 16MB
3445 * XXX: can we get a buffer that crosses 64KB boundaries?
3447 if (urb->transfer_buffer_length > 0)
3449 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3450 ep_index, urb->stream_id,
3451 num_trbs, urb, 0, mem_flags);
3455 urb_priv = urb->hcpriv;
3456 td = urb_priv->td[0];
3459 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3460 * until we've finished creating all the other TRBs. The ring's cycle
3461 * state may change as we enqueue the other TRBs, so save it too.
3463 start_trb = &ep_ring->enqueue->generic;
3464 start_cycle = ep_ring->cycle_state;
3466 /* Queue setup TRB - see section 6.4.1.2.1 */
3467 /* FIXME better way to translate setup_packet into two u32 fields? */
3468 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3470 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3471 if (start_cycle == 0)
3474 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3475 if (xhci->hci_version >= 0x100) {
3476 if (urb->transfer_buffer_length > 0) {
3477 if (setup->bRequestType & USB_DIR_IN)
3478 field |= TRB_TX_TYPE(TRB_DATA_IN);
3480 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3484 queue_trb(xhci, ep_ring, true,
3485 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3486 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3487 TRB_LEN(8) | TRB_INTR_TARGET(0),
3488 /* Immediate data in pointer */
3491 /* If there's data, queue data TRBs */
3492 /* Only set interrupt on short packet for IN endpoints */
3493 if (usb_urb_dir_in(urb))
3494 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3496 field = TRB_TYPE(TRB_DATA);
3498 remainder = xhci_td_remainder(xhci, 0,
3499 urb->transfer_buffer_length,
3500 urb->transfer_buffer_length,
3503 length_field = TRB_LEN(urb->transfer_buffer_length) |
3504 TRB_TD_SIZE(remainder) |
3507 if (urb->transfer_buffer_length > 0) {
3508 if (setup->bRequestType & USB_DIR_IN)
3509 field |= TRB_DIR_IN;
3510 queue_trb(xhci, ep_ring, true,
3511 lower_32_bits(urb->transfer_dma),
3512 upper_32_bits(urb->transfer_dma),
3514 field | ep_ring->cycle_state);
3517 /* Save the DMA address of the last TRB in the TD */
3518 td->last_trb = ep_ring->enqueue;
3520 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3521 /* If the device sent data, the status stage is an OUT transfer */
3522 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3526 queue_trb(xhci, ep_ring, false,
3530 /* Event on completion */
3531 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3533 giveback_first_trb(xhci, slot_id, ep_index, 0,
3534 start_cycle, start_trb);
3538 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3539 struct urb *urb, int i)
3544 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3545 td_len = urb->iso_frame_desc[i].length;
3547 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3556 * The transfer burst count field of the isochronous TRB defines the number of
3557 * bursts that are required to move all packets in this TD. Only SuperSpeed
3558 * devices can burst up to bMaxBurst number of packets per service interval.
3559 * This field is zero based, meaning a value of zero in the field means one
3560 * burst. Basically, for everything but SuperSpeed devices, this field will be
3561 * zero. Only xHCI 1.0 host controllers support this field.
3563 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3564 struct usb_device *udev,
3565 struct urb *urb, unsigned int total_packet_count)
3567 unsigned int max_burst;
3569 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3572 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3573 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3577 * Returns the number of packets in the last "burst" of packets. This field is
3578 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3579 * the last burst packet count is equal to the total number of packets in the
3580 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3581 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3582 * contain 1 to (bMaxBurst + 1) packets.
3584 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3585 struct usb_device *udev,
3586 struct urb *urb, unsigned int total_packet_count)
3588 unsigned int max_burst;
3589 unsigned int residue;
3591 if (xhci->hci_version < 0x100)
3594 switch (udev->speed) {
3595 case USB_SPEED_SUPER:
3596 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3597 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3598 residue = total_packet_count % (max_burst + 1);
3599 /* If residue is zero, the last burst contains (max_burst + 1)
3600 * number of packets, but the TLBPC field is zero-based.
3606 if (total_packet_count == 0)
3608 return total_packet_count - 1;
3613 * Calculates Frame ID field of the isochronous TRB identifies the
3614 * target frame that the Interval associated with this Isochronous
3615 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3617 * Returns actual frame id on success, negative value on error.
3619 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3620 struct urb *urb, int index)
3622 int start_frame, ist, ret = 0;
3623 int start_frame_id, end_frame_id, current_frame_id;
3625 if (urb->dev->speed == USB_SPEED_LOW ||
3626 urb->dev->speed == USB_SPEED_FULL)
3627 start_frame = urb->start_frame + index * urb->interval;
3629 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3631 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3633 * If bit [3] of IST is cleared to '0', software can add a TRB no
3634 * later than IST[2:0] Microframes before that TRB is scheduled to
3636 * If bit [3] of IST is set to '1', software can add a TRB no later
3637 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3639 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3640 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3643 /* Software shall not schedule an Isoch TD with a Frame ID value that
3644 * is less than the Start Frame ID or greater than the End Frame ID,
3647 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3648 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3650 * Both the End Frame ID and Start Frame ID values are calculated
3651 * in microframes. When software determines the valid Frame ID value;
3652 * The End Frame ID value should be rounded down to the nearest Frame
3653 * boundary, and the Start Frame ID value should be rounded up to the
3654 * nearest Frame boundary.
3656 current_frame_id = readl(&xhci->run_regs->microframe_index);
3657 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3658 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3660 start_frame &= 0x7ff;
3661 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3662 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3664 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3665 __func__, index, readl(&xhci->run_regs->microframe_index),
3666 start_frame_id, end_frame_id, start_frame);
3668 if (start_frame_id < end_frame_id) {
3669 if (start_frame > end_frame_id ||
3670 start_frame < start_frame_id)
3672 } else if (start_frame_id > end_frame_id) {
3673 if ((start_frame > end_frame_id &&
3674 start_frame < start_frame_id))
3681 if (ret == -EINVAL || start_frame == start_frame_id) {
3682 start_frame = start_frame_id + 1;
3683 if (urb->dev->speed == USB_SPEED_LOW ||
3684 urb->dev->speed == USB_SPEED_FULL)
3685 urb->start_frame = start_frame;
3687 urb->start_frame = start_frame << 3;
3693 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3694 start_frame, current_frame_id, index,
3695 start_frame_id, end_frame_id);
3696 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3703 /* This is for isoc transfer */
3704 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3705 struct urb *urb, int slot_id, unsigned int ep_index)
3707 struct xhci_ring *ep_ring;
3708 struct urb_priv *urb_priv;
3710 int num_tds, trbs_per_td;
3711 struct xhci_generic_trb *start_trb;
3714 u32 field, length_field;
3715 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3716 u64 start_addr, addr;
3718 bool more_trbs_coming;
3719 struct xhci_virt_ep *xep;
3721 xep = &xhci->devs[slot_id]->eps[ep_index];
3722 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3724 num_tds = urb->number_of_packets;
3726 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3730 start_addr = (u64) urb->transfer_dma;
3731 start_trb = &ep_ring->enqueue->generic;
3732 start_cycle = ep_ring->cycle_state;
3734 urb_priv = urb->hcpriv;
3735 /* Queue the first TRB, even if it's zero-length */
3736 for (i = 0; i < num_tds; i++) {
3737 unsigned int total_packet_count;
3738 unsigned int burst_count;
3739 unsigned int residue;
3743 addr = start_addr + urb->iso_frame_desc[i].offset;
3744 td_len = urb->iso_frame_desc[i].length;
3745 td_remain_len = td_len;
3746 total_packet_count = DIV_ROUND_UP(td_len,
3748 usb_endpoint_maxp(&urb->ep->desc)));
3749 /* A zero-length transfer still involves at least one packet. */
3750 if (total_packet_count == 0)
3751 total_packet_count++;
3752 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3753 total_packet_count);
3754 residue = xhci_get_last_burst_packet_count(xhci,
3755 urb->dev, urb, total_packet_count);
3757 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3759 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3760 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3767 td = urb_priv->td[i];
3768 for (j = 0; j < trbs_per_td; j++) {
3774 field = TRB_TBC(burst_count) |
3776 /* Queue the isoc TRB */
3777 field |= TRB_TYPE(TRB_ISOC);
3779 /* Calculate Frame ID and SIA fields */
3780 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3781 HCC_CFC(xhci->hcc_params)) {
3782 frame_id = xhci_get_isoc_frame_id(xhci,
3786 field |= TRB_FRAME_ID(frame_id);
3793 if (start_cycle == 0)
3796 field |= ep_ring->cycle_state;
3799 /* Queue other normal TRBs */
3800 field |= TRB_TYPE(TRB_NORMAL);
3801 field |= ep_ring->cycle_state;
3804 /* Only set interrupt on short packet for IN EPs */
3805 if (usb_urb_dir_in(urb))
3808 /* Chain all the TRBs together; clear the chain bit in
3809 * the last TRB to indicate it's the last TRB in the
3812 if (j < trbs_per_td - 1) {
3814 more_trbs_coming = true;
3816 td->last_trb = ep_ring->enqueue;
3818 if (xhci->hci_version == 0x100 &&
3821 /* Set BEI bit except for the last td */
3822 if (i < num_tds - 1)
3825 more_trbs_coming = false;
3828 /* Calculate TRB length */
3829 trb_buff_len = TRB_MAX_BUFF_SIZE -
3830 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3831 if (trb_buff_len > td_remain_len)
3832 trb_buff_len = td_remain_len;
3834 /* Set the TRB length, TD size, & interrupter fields. */
3835 remainder = xhci_td_remainder(xhci, running_total,
3836 trb_buff_len, td_len,
3837 urb, trbs_per_td - j - 1);
3839 length_field = TRB_LEN(trb_buff_len) |
3840 TRB_TD_SIZE(remainder) |
3843 queue_trb(xhci, ep_ring, more_trbs_coming,
3844 lower_32_bits(addr),
3845 upper_32_bits(addr),
3848 running_total += trb_buff_len;
3850 addr += trb_buff_len;
3851 td_remain_len -= trb_buff_len;
3854 /* Check TD length */
3855 if (running_total != td_len) {
3856 xhci_err(xhci, "ISOC TD length unmatch\n");
3862 /* store the next frame id */
3863 if (HCC_CFC(xhci->hcc_params))
3864 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3866 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3867 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3868 usb_amd_quirk_pll_disable();
3870 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3872 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3873 start_cycle, start_trb);
3876 /* Clean up a partially enqueued isoc transfer. */
3878 for (i--; i >= 0; i--)
3879 list_del_init(&urb_priv->td[i]->td_list);
3881 /* Use the first TD as a temporary variable to turn the TDs we've queued
3882 * into No-ops with a software-owned cycle bit. That way the hardware
3883 * won't accidentally start executing bogus TDs when we partially
3884 * overwrite them. td->first_trb and td->start_seg are already set.
3886 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3887 /* Every TRB except the first & last will have its cycle bit flipped. */
3888 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3890 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3891 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3892 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3893 ep_ring->cycle_state = start_cycle;
3894 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3895 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3900 * Check transfer ring to guarantee there is enough room for the urb.
3901 * Update ISO URB start_frame and interval.
3902 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3903 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3904 * Contiguous Frame ID is not supported by HC.
3906 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3907 struct urb *urb, int slot_id, unsigned int ep_index)
3909 struct xhci_virt_device *xdev;
3910 struct xhci_ring *ep_ring;
3911 struct xhci_ep_ctx *ep_ctx;
3915 int num_tds, num_trbs, i;
3917 struct xhci_virt_ep *xep;
3920 xdev = xhci->devs[slot_id];
3921 xep = &xhci->devs[slot_id]->eps[ep_index];
3922 ep_ring = xdev->eps[ep_index].ring;
3923 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3926 num_tds = urb->number_of_packets;
3927 for (i = 0; i < num_tds; i++)
3928 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3930 /* Check the ring to guarantee there is enough room for the whole urb.
3931 * Do not insert any td of the urb to the ring if the check failed.
3933 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3934 num_trbs, mem_flags);
3939 * Check interval value. This should be done before we start to
3940 * calculate the start frame value.
3942 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3943 ep_interval = urb->interval;
3944 /* Convert to microframes */
3945 if (urb->dev->speed == USB_SPEED_LOW ||
3946 urb->dev->speed == USB_SPEED_FULL)
3948 /* FIXME change this to a warning and a suggestion to use the new API
3949 * to set the polling interval (once the API is added).
3951 if (xhci_interval != ep_interval) {
3952 dev_dbg_ratelimited(&urb->dev->dev,
3953 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3954 ep_interval, ep_interval == 1 ? "" : "s",
3955 xhci_interval, xhci_interval == 1 ? "" : "s");
3956 urb->interval = xhci_interval;
3957 /* Convert back to frames for LS/FS devices */
3958 if (urb->dev->speed == USB_SPEED_LOW ||
3959 urb->dev->speed == USB_SPEED_FULL)
3963 /* Calculate the start frame and put it in urb->start_frame. */
3964 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3965 if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
3967 urb->start_frame = xep->next_frame_id;
3968 goto skip_start_over;
3972 start_frame = readl(&xhci->run_regs->microframe_index);
3973 start_frame &= 0x3fff;
3975 * Round up to the next frame and consider the time before trb really
3976 * gets scheduled by hardare.
3978 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3979 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3981 start_frame += ist + XHCI_CFC_DELAY;
3982 start_frame = roundup(start_frame, 8);
3985 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
3986 * is greate than 8 microframes.
3988 if (urb->dev->speed == USB_SPEED_LOW ||
3989 urb->dev->speed == USB_SPEED_FULL) {
3990 start_frame = roundup(start_frame, urb->interval << 3);
3991 urb->start_frame = start_frame >> 3;
3993 start_frame = roundup(start_frame, urb->interval);
3994 urb->start_frame = start_frame;
3998 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4000 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4003 /**** Command Ring Operations ****/
4005 /* Generic function for queueing a command TRB on the command ring.
4006 * Check to make sure there's room on the command ring for one command TRB.
4007 * Also check that there's room reserved for commands that must not fail.
4008 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4009 * then only check for the number of reserved spots.
4010 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4011 * because the command event handler may want to resubmit a failed command.
4013 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4014 u32 field1, u32 field2,
4015 u32 field3, u32 field4, bool command_must_succeed)
4017 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4020 if (xhci->xhc_state) {
4021 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4025 if (!command_must_succeed)
4028 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4029 reserved_trbs, GFP_ATOMIC);
4031 xhci_err(xhci, "ERR: No room for command on command ring\n");
4032 if (command_must_succeed)
4033 xhci_err(xhci, "ERR: Reserved TRB counting for "
4034 "unfailable commands failed.\n");
4038 cmd->command_trb = xhci->cmd_ring->enqueue;
4039 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4041 /* if there are no other commands queued we start the timeout timer */
4042 if (xhci->cmd_list.next == &cmd->cmd_list &&
4043 !timer_pending(&xhci->cmd_timer)) {
4044 xhci->current_cmd = cmd;
4045 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
4048 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4049 field4 | xhci->cmd_ring->cycle_state);
4053 /* Queue a slot enable or disable request on the command ring */
4054 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4055 u32 trb_type, u32 slot_id)
4057 return queue_command(xhci, cmd, 0, 0, 0,
4058 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4061 /* Queue an address device command TRB */
4062 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4063 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4065 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4066 upper_32_bits(in_ctx_ptr), 0,
4067 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4068 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4071 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4072 u32 field1, u32 field2, u32 field3, u32 field4)
4074 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4077 /* Queue a reset device command TRB */
4078 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4081 return queue_command(xhci, cmd, 0, 0, 0,
4082 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4086 /* Queue a configure endpoint command TRB */
4087 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4088 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4089 u32 slot_id, bool command_must_succeed)
4091 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4092 upper_32_bits(in_ctx_ptr), 0,
4093 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4094 command_must_succeed);
4097 /* Queue an evaluate context command TRB */
4098 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4099 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4101 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4102 upper_32_bits(in_ctx_ptr), 0,
4103 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4104 command_must_succeed);
4108 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4109 * activity on an endpoint that is about to be suspended.
4111 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4112 int slot_id, unsigned int ep_index, int suspend)
4114 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4115 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4116 u32 type = TRB_TYPE(TRB_STOP_RING);
4117 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4119 return queue_command(xhci, cmd, 0, 0, 0,
4120 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4123 /* Set Transfer Ring Dequeue Pointer command */
4124 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4125 unsigned int slot_id, unsigned int ep_index,
4126 unsigned int stream_id,
4127 struct xhci_dequeue_state *deq_state)
4130 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4131 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4132 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4134 u32 type = TRB_TYPE(TRB_SET_DEQ);
4135 struct xhci_virt_ep *ep;
4136 struct xhci_command *cmd;
4139 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4140 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4141 deq_state->new_deq_seg,
4142 (unsigned long long)deq_state->new_deq_seg->dma,
4143 deq_state->new_deq_ptr,
4144 (unsigned long long)xhci_trb_virt_to_dma(
4145 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4146 deq_state->new_cycle_state);
4148 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4149 deq_state->new_deq_ptr);
4151 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4152 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4153 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4156 ep = &xhci->devs[slot_id]->eps[ep_index];
4157 if ((ep->ep_state & SET_DEQ_PENDING)) {
4158 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4159 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4163 /* This function gets called from contexts where it cannot sleep */
4164 cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
4166 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n");
4170 ep->queued_deq_seg = deq_state->new_deq_seg;
4171 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4173 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4174 ret = queue_command(xhci, cmd,
4175 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4176 upper_32_bits(addr), trb_stream_id,
4177 trb_slot_id | trb_ep_index | type, false);
4179 xhci_free_command(xhci, cmd);
4183 /* Stop the TD queueing code from ringing the doorbell until
4184 * this command completes. The HC won't set the dequeue pointer
4185 * if the ring is running, and ringing the doorbell starts the
4188 ep->ep_state |= SET_DEQ_PENDING;
4191 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4192 int slot_id, unsigned int ep_index)
4194 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4195 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4196 u32 type = TRB_TYPE(TRB_RESET_EP);
4198 return queue_command(xhci, cmd, 0, 0, 0,
4199 trb_slot_id | trb_ep_index | type, false);