2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
70 #include "xhci-trace.h"
73 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
76 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
79 unsigned long segment_offset;
81 if (!seg || !trb || trb < seg->trbs)
84 segment_offset = trb - seg->trbs;
85 if (segment_offset >= TRBS_PER_SEGMENT)
87 return seg->dma + (segment_offset * sizeof(*trb));
90 /* Does this link TRB point to the first segment in a ring,
91 * or was the previous TRB the last TRB on the last segment in the ERST?
93 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
94 struct xhci_segment *seg, union xhci_trb *trb)
96 if (ring == xhci->event_ring)
97 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
98 (seg->next == xhci->event_ring->first_seg);
100 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
103 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
104 * segment? I.e. would the updated event TRB pointer step off the end of the
107 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
108 struct xhci_segment *seg, union xhci_trb *trb)
110 if (ring == xhci->event_ring)
111 return trb == &seg->trbs[TRBS_PER_SEGMENT];
113 return TRB_TYPE_LINK_LE32(trb->link.control);
116 static int enqueue_is_link_trb(struct xhci_ring *ring)
118 struct xhci_link_trb *link = &ring->enqueue->link;
119 return TRB_TYPE_LINK_LE32(link->control);
122 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
123 * TRB is in a new segment. This does not skip over link TRBs, and it does not
124 * effect the ring dequeue or enqueue pointers.
126 static void next_trb(struct xhci_hcd *xhci,
127 struct xhci_ring *ring,
128 struct xhci_segment **seg,
129 union xhci_trb **trb)
131 if (last_trb(xhci, ring, *seg, *trb)) {
133 *trb = ((*seg)->trbs);
140 * See Cycle bit rules. SW is the consumer for the event ring only.
141 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
143 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
148 * If this is not event ring, and the dequeue pointer
149 * is not on a link TRB, there is one more usable TRB
151 if (ring->type != TYPE_EVENT &&
152 !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
153 ring->num_trbs_free++;
157 * Update the dequeue pointer further if that was a link TRB or
158 * we're at the end of an event ring segment (which doesn't have
161 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
162 if (ring->type == TYPE_EVENT &&
163 last_trb_on_last_seg(xhci, ring,
164 ring->deq_seg, ring->dequeue)) {
165 ring->cycle_state ^= 1;
167 ring->deq_seg = ring->deq_seg->next;
168 ring->dequeue = ring->deq_seg->trbs;
172 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
176 * See Cycle bit rules. SW is the consumer for the event ring only.
177 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
179 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
180 * chain bit is set), then set the chain bit in all the following link TRBs.
181 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
182 * have their chain bit cleared (so that each Link TRB is a separate TD).
184 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
185 * set, but other sections talk about dealing with the chain bit set. This was
186 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
187 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
189 * @more_trbs_coming: Will you enqueue more TRBs before calling
190 * prepare_transfer()?
192 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
193 bool more_trbs_coming)
196 union xhci_trb *next;
198 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
199 /* If this is not event ring, there is one less usable TRB */
200 if (ring->type != TYPE_EVENT &&
201 !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
202 ring->num_trbs_free--;
203 next = ++(ring->enqueue);
206 /* Update the dequeue pointer further if that was a link TRB or we're at
207 * the end of an event ring segment (which doesn't have link TRBS)
209 while (last_trb(xhci, ring, ring->enq_seg, next)) {
210 if (ring->type != TYPE_EVENT) {
212 * If the caller doesn't plan on enqueueing more
213 * TDs before ringing the doorbell, then we
214 * don't want to give the link TRB to the
215 * hardware just yet. We'll give the link TRB
216 * back in prepare_ring() just before we enqueue
217 * the TD at the top of the ring.
219 if (!chain && !more_trbs_coming)
222 /* If we're not dealing with 0.95 hardware or
223 * isoc rings on AMD 0.96 host,
224 * carry over the chain bit of the previous TRB
225 * (which may mean the chain bit is cleared).
227 if (!(ring->type == TYPE_ISOC &&
228 (xhci->quirks & XHCI_AMD_0x96_HOST))
229 && !xhci_link_trb_quirk(xhci)) {
230 next->link.control &=
231 cpu_to_le32(~TRB_CHAIN);
232 next->link.control |=
235 /* Give this link TRB to the hardware */
237 next->link.control ^= cpu_to_le32(TRB_CYCLE);
239 /* Toggle the cycle bit after the last ring segment. */
240 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
241 ring->cycle_state ^= 1;
244 ring->enq_seg = ring->enq_seg->next;
245 ring->enqueue = ring->enq_seg->trbs;
246 next = ring->enqueue;
251 * Check to see if there's room to enqueue num_trbs on the ring and make sure
252 * enqueue pointer will not advance into dequeue segment. See rules above.
254 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
255 unsigned int num_trbs)
257 int num_trbs_in_deq_seg;
259 if (ring->num_trbs_free < num_trbs)
262 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
263 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
264 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
271 /* Ring the host controller doorbell after placing a command on the ring */
272 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
274 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
277 xhci_dbg(xhci, "// Ding dong!\n");
278 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
279 /* Flush PCI posted writes */
280 readl(&xhci->dba->doorbell[0]);
283 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
288 xhci_dbg(xhci, "Abort command ring\n");
290 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
291 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
294 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
295 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
296 * but the completion event in never sent. Use the cmd timeout timer to
297 * handle those cases. Use twice the time to cover the bit polling retry
299 mod_timer(&xhci->cmd_timer, jiffies + (2 * XHCI_CMD_DEFAULT_TIMEOUT));
300 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
301 &xhci->op_regs->cmd_ring);
303 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
304 * time the completion od all xHCI commands, including
305 * the Command Abort operation. If software doesn't see
306 * CRR negated in a timely manner (e.g. longer than 5
307 * seconds), then it should assume that the there are
308 * larger problems with the xHC and assert HCRST.
310 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
311 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
313 /* we are about to kill xhci, give it one more chance */
314 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
315 &xhci->op_regs->cmd_ring);
317 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
318 CMD_RING_RUNNING, 0, 3 * 1000 * 1000);
322 xhci_err(xhci, "Stopped the command ring failed, "
323 "maybe the host is dead\n");
324 del_timer(&xhci->cmd_timer);
325 xhci->xhc_state |= XHCI_STATE_DYING;
334 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
335 unsigned int slot_id,
336 unsigned int ep_index,
337 unsigned int stream_id)
339 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
340 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
341 unsigned int ep_state = ep->ep_state;
343 /* Don't ring the doorbell for this endpoint if there are pending
344 * cancellations because we don't want to interrupt processing.
345 * We don't want to restart any stream rings if there's a set dequeue
346 * pointer command pending because the device can choose to start any
347 * stream once the endpoint is on the HW schedule.
349 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
350 (ep_state & EP_HALTED))
352 writel(DB_VALUE(ep_index, stream_id), db_addr);
353 /* The CPU has better things to do at this point than wait for a
354 * write-posting flush. It'll get there soon enough.
358 /* Ring the doorbell for any rings with pending URBs */
359 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
360 unsigned int slot_id,
361 unsigned int ep_index)
363 unsigned int stream_id;
364 struct xhci_virt_ep *ep;
366 ep = &xhci->devs[slot_id]->eps[ep_index];
368 /* A ring has pending URBs if its TD list is not empty */
369 if (!(ep->ep_state & EP_HAS_STREAMS)) {
370 if (ep->ring && !(list_empty(&ep->ring->td_list)))
371 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
375 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
377 struct xhci_stream_info *stream_info = ep->stream_info;
378 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
379 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
384 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
385 unsigned int slot_id, unsigned int ep_index,
386 unsigned int stream_id)
388 struct xhci_virt_ep *ep;
390 ep = &xhci->devs[slot_id]->eps[ep_index];
391 /* Common case: no streams */
392 if (!(ep->ep_state & EP_HAS_STREAMS))
395 if (stream_id == 0) {
397 "WARN: Slot ID %u, ep index %u has streams, "
398 "but URB has no stream ID.\n",
403 if (stream_id < ep->stream_info->num_streams)
404 return ep->stream_info->stream_rings[stream_id];
407 "WARN: Slot ID %u, ep index %u has "
408 "stream IDs 1 to %u allocated, "
409 "but stream ID %u is requested.\n",
411 ep->stream_info->num_streams - 1,
416 /* Get the right ring for the given URB.
417 * If the endpoint supports streams, boundary check the URB's stream ID.
418 * If the endpoint doesn't support streams, return the singular endpoint ring.
420 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
423 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
424 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
428 * Move the xHC's endpoint ring dequeue pointer past cur_td.
429 * Record the new state of the xHC's endpoint ring dequeue segment,
430 * dequeue pointer, and new consumer cycle state in state.
431 * Update our internal representation of the ring's dequeue pointer.
433 * We do this in three jumps:
434 * - First we update our new ring state to be the same as when the xHC stopped.
435 * - Then we traverse the ring to find the segment that contains
436 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
437 * any link TRBs with the toggle cycle bit set.
438 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
439 * if we've moved it past a link TRB with the toggle cycle bit set.
441 * Some of the uses of xhci_generic_trb are grotty, but if they're done
442 * with correct __le32 accesses they should work fine. Only users of this are
445 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
446 unsigned int slot_id, unsigned int ep_index,
447 unsigned int stream_id, struct xhci_td *cur_td,
448 struct xhci_dequeue_state *state)
450 struct xhci_virt_device *dev = xhci->devs[slot_id];
451 struct xhci_virt_ep *ep = &dev->eps[ep_index];
452 struct xhci_ring *ep_ring;
453 struct xhci_segment *new_seg;
454 union xhci_trb *new_deq;
457 bool cycle_found = false;
458 bool td_last_trb_found = false;
460 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
461 ep_index, stream_id);
463 xhci_warn(xhci, "WARN can't find new dequeue state "
464 "for invalid stream ID %u.\n",
469 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
470 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
471 "Finding endpoint context");
472 /* 4.6.9 the css flag is written to the stream context for streams */
473 if (ep->ep_state & EP_HAS_STREAMS) {
474 struct xhci_stream_ctx *ctx =
475 &ep->stream_info->stream_ctx_array[stream_id];
476 hw_dequeue = le64_to_cpu(ctx->stream_ring);
478 struct xhci_ep_ctx *ep_ctx
479 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
480 hw_dequeue = le64_to_cpu(ep_ctx->deq);
483 new_seg = ep_ring->deq_seg;
484 new_deq = ep_ring->dequeue;
485 state->new_cycle_state = hw_dequeue & 0x1;
488 * We want to find the pointer, segment and cycle state of the new trb
489 * (the one after current TD's last_trb). We know the cycle state at
490 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
494 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
495 == (dma_addr_t)(hw_dequeue & ~0xf)) {
497 if (td_last_trb_found)
500 if (new_deq == cur_td->last_trb)
501 td_last_trb_found = true;
504 TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) &&
505 new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE))
506 state->new_cycle_state ^= 0x1;
508 next_trb(xhci, ep_ring, &new_seg, &new_deq);
510 /* Search wrapped around, bail out */
511 if (new_deq == ep->ring->dequeue) {
512 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
513 state->new_deq_seg = NULL;
514 state->new_deq_ptr = NULL;
518 } while (!cycle_found || !td_last_trb_found);
520 state->new_deq_seg = new_seg;
521 state->new_deq_ptr = new_deq;
523 /* Don't update the ring cycle state for the producer (us). */
524 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
525 "Cycle state = 0x%x", state->new_cycle_state);
527 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
528 "New dequeue segment = %p (virtual)",
530 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
531 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
532 "New dequeue pointer = 0x%llx (DMA)",
533 (unsigned long long) addr);
536 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
537 * (The last TRB actually points to the ring enqueue pointer, which is not part
538 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
540 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
541 struct xhci_td *cur_td, bool flip_cycle)
543 struct xhci_segment *cur_seg;
544 union xhci_trb *cur_trb;
546 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
548 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
549 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
550 /* Unchain any chained Link TRBs, but
551 * leave the pointers intact.
553 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
554 /* Flip the cycle bit (link TRBs can't be the first
558 cur_trb->generic.field[3] ^=
559 cpu_to_le32(TRB_CYCLE);
560 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
561 "Cancel (unchain) link TRB");
562 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
563 "Address = %p (0x%llx dma); "
564 "in seg %p (0x%llx dma)",
566 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
568 (unsigned long long)cur_seg->dma);
570 cur_trb->generic.field[0] = 0;
571 cur_trb->generic.field[1] = 0;
572 cur_trb->generic.field[2] = 0;
573 /* Preserve only the cycle bit of this TRB */
574 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
575 /* Flip the cycle bit except on the first or last TRB */
576 if (flip_cycle && cur_trb != cur_td->first_trb &&
577 cur_trb != cur_td->last_trb)
578 cur_trb->generic.field[3] ^=
579 cpu_to_le32(TRB_CYCLE);
580 cur_trb->generic.field[3] |= cpu_to_le32(
581 TRB_TYPE(TRB_TR_NOOP));
582 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
583 "TRB to noop at offset 0x%llx",
585 xhci_trb_virt_to_dma(cur_seg, cur_trb));
587 if (cur_trb == cur_td->last_trb)
592 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
593 struct xhci_virt_ep *ep)
595 ep->ep_state &= ~EP_HALT_PENDING;
596 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
597 * timer is running on another CPU, we don't decrement stop_cmds_pending
598 * (since we didn't successfully stop the watchdog timer).
600 if (del_timer(&ep->stop_cmd_timer))
601 ep->stop_cmds_pending--;
604 /* Must be called with xhci->lock held in interrupt context */
605 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
606 struct xhci_td *cur_td, int status)
610 struct urb_priv *urb_priv;
613 urb_priv = urb->hcpriv;
615 hcd = bus_to_hcd(urb->dev->bus);
617 /* Only giveback urb when this is the last td in urb */
618 if (urb_priv->td_cnt == urb_priv->length) {
619 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
620 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
621 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
622 if (xhci->quirks & XHCI_AMD_PLL_FIX)
623 usb_amd_quirk_pll_enable();
626 usb_hcd_unlink_urb_from_ep(hcd, urb);
628 spin_unlock(&xhci->lock);
629 usb_hcd_giveback_urb(hcd, urb, status);
630 xhci_urb_free_priv(urb_priv);
631 spin_lock(&xhci->lock);
636 * When we get a command completion for a Stop Endpoint Command, we need to
637 * unlink any cancelled TDs from the ring. There are two ways to do that:
639 * 1. If the HW was in the middle of processing the TD that needs to be
640 * cancelled, then we must move the ring's dequeue pointer past the last TRB
641 * in the TD with a Set Dequeue Pointer Command.
642 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
643 * bit cleared) so that the HW will skip over them.
645 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
646 union xhci_trb *trb, struct xhci_event_cmd *event)
648 unsigned int ep_index;
649 struct xhci_ring *ep_ring;
650 struct xhci_virt_ep *ep;
651 struct list_head *entry;
652 struct xhci_td *cur_td = NULL;
653 struct xhci_td *last_unlinked_td;
655 struct xhci_dequeue_state deq_state;
657 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
658 if (!xhci->devs[slot_id])
659 xhci_warn(xhci, "Stop endpoint command "
660 "completion for disabled slot %u\n",
665 memset(&deq_state, 0, sizeof(deq_state));
666 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
667 ep = &xhci->devs[slot_id]->eps[ep_index];
669 if (list_empty(&ep->cancelled_td_list)) {
670 xhci_stop_watchdog_timer_in_irq(xhci, ep);
671 ep->stopped_td = NULL;
672 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
676 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
677 * We have the xHCI lock, so nothing can modify this list until we drop
678 * it. We're also in the event handler, so we can't get re-interrupted
679 * if another Stop Endpoint command completes
681 list_for_each(entry, &ep->cancelled_td_list) {
682 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
683 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
684 "Removing canceled TD starting at 0x%llx (dma).",
685 (unsigned long long)xhci_trb_virt_to_dma(
686 cur_td->start_seg, cur_td->first_trb));
687 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
689 /* This shouldn't happen unless a driver is mucking
690 * with the stream ID after submission. This will
691 * leave the TD on the hardware ring, and the hardware
692 * will try to execute it, and may access a buffer
693 * that has already been freed. In the best case, the
694 * hardware will execute it, and the event handler will
695 * ignore the completion event for that TD, since it was
696 * removed from the td_list for that endpoint. In
697 * short, don't muck with the stream ID after
700 xhci_warn(xhci, "WARN Cancelled URB %p "
701 "has invalid stream ID %u.\n",
703 cur_td->urb->stream_id);
704 goto remove_finished_td;
707 * If we stopped on the TD we need to cancel, then we have to
708 * move the xHC endpoint ring dequeue pointer past this TD.
710 if (cur_td == ep->stopped_td)
711 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
712 cur_td->urb->stream_id,
715 td_to_noop(xhci, ep_ring, cur_td, false);
718 * The event handler won't see a completion for this TD anymore,
719 * so remove it from the endpoint ring's TD list. Keep it in
720 * the cancelled TD list for URB completion later.
722 list_del_init(&cur_td->td_list);
724 last_unlinked_td = cur_td;
725 xhci_stop_watchdog_timer_in_irq(xhci, ep);
727 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
728 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
729 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
730 ep->stopped_td->urb->stream_id, &deq_state);
731 xhci_ring_cmd_db(xhci);
733 /* Otherwise ring the doorbell(s) to restart queued transfers */
734 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
737 ep->stopped_td = NULL;
740 * Drop the lock and complete the URBs in the cancelled TD list.
741 * New TDs to be cancelled might be added to the end of the list before
742 * we can complete all the URBs for the TDs we already unlinked.
743 * So stop when we've completed the URB for the last TD we unlinked.
746 cur_td = list_entry(ep->cancelled_td_list.next,
747 struct xhci_td, cancelled_td_list);
748 list_del_init(&cur_td->cancelled_td_list);
750 /* Clean up the cancelled URB */
751 /* Doesn't matter what we pass for status, since the core will
752 * just overwrite it (because the URB has been unlinked).
754 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
756 /* Stop processing the cancelled list if the watchdog timer is
759 if (xhci->xhc_state & XHCI_STATE_DYING)
761 } while (cur_td != last_unlinked_td);
763 /* Return to the event handler with xhci->lock re-acquired */
766 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
768 struct xhci_td *cur_td;
770 while (!list_empty(&ring->td_list)) {
771 cur_td = list_first_entry(&ring->td_list,
772 struct xhci_td, td_list);
773 list_del_init(&cur_td->td_list);
774 if (!list_empty(&cur_td->cancelled_td_list))
775 list_del_init(&cur_td->cancelled_td_list);
776 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
780 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
781 int slot_id, int ep_index)
783 struct xhci_td *cur_td;
784 struct xhci_virt_ep *ep;
785 struct xhci_ring *ring;
787 ep = &xhci->devs[slot_id]->eps[ep_index];
788 if ((ep->ep_state & EP_HAS_STREAMS) ||
789 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
792 for (stream_id = 0; stream_id < ep->stream_info->num_streams;
794 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
795 "Killing URBs for slot ID %u, ep index %u, stream %u",
796 slot_id, ep_index, stream_id + 1);
797 xhci_kill_ring_urbs(xhci,
798 ep->stream_info->stream_rings[stream_id]);
804 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
805 "Killing URBs for slot ID %u, ep index %u",
807 xhci_kill_ring_urbs(xhci, ring);
809 while (!list_empty(&ep->cancelled_td_list)) {
810 cur_td = list_first_entry(&ep->cancelled_td_list,
811 struct xhci_td, cancelled_td_list);
812 list_del_init(&cur_td->cancelled_td_list);
813 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
817 /* Watchdog timer function for when a stop endpoint command fails to complete.
818 * In this case, we assume the host controller is broken or dying or dead. The
819 * host may still be completing some other events, so we have to be careful to
820 * let the event ring handler and the URB dequeueing/enqueueing functions know
821 * through xhci->state.
823 * The timer may also fire if the host takes a very long time to respond to the
824 * command, and the stop endpoint command completion handler cannot delete the
825 * timer before the timer function is called. Another endpoint cancellation may
826 * sneak in before the timer function can grab the lock, and that may queue
827 * another stop endpoint command and add the timer back. So we cannot use a
828 * simple flag to say whether there is a pending stop endpoint command for a
829 * particular endpoint.
831 * Instead we use a combination of that flag and a counter for the number of
832 * pending stop endpoint commands. If the timer is the tail end of the last
833 * stop endpoint command, and the endpoint's command is still pending, we assume
836 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
838 struct xhci_hcd *xhci;
839 struct xhci_virt_ep *ep;
843 ep = (struct xhci_virt_ep *) arg;
846 spin_lock_irqsave(&xhci->lock, flags);
848 ep->stop_cmds_pending--;
849 if (xhci->xhc_state & XHCI_STATE_DYING) {
850 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
851 "Stop EP timer ran, but another timer marked "
852 "xHCI as DYING, exiting.");
853 spin_unlock_irqrestore(&xhci->lock, flags);
856 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
857 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
858 "Stop EP timer ran, but no command pending, "
860 spin_unlock_irqrestore(&xhci->lock, flags);
864 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
865 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
866 /* Oops, HC is dead or dying or at least not responding to the stop
869 xhci->xhc_state |= XHCI_STATE_DYING;
870 /* Disable interrupts from the host controller and start halting it */
872 spin_unlock_irqrestore(&xhci->lock, flags);
874 ret = xhci_halt(xhci);
876 spin_lock_irqsave(&xhci->lock, flags);
878 /* This is bad; the host is not responding to commands and it's
879 * not allowing itself to be halted. At least interrupts are
880 * disabled. If we call usb_hc_died(), it will attempt to
881 * disconnect all device drivers under this host. Those
882 * disconnect() methods will wait for all URBs to be unlinked,
883 * so we must complete them.
885 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
886 xhci_warn(xhci, "Completing active URBs anyway.\n");
887 /* We could turn all TDs on the rings to no-ops. This won't
888 * help if the host has cached part of the ring, and is slow if
889 * we want to preserve the cycle bit. Skip it and hope the host
890 * doesn't touch the memory.
893 for (i = 0; i < MAX_HC_SLOTS; i++) {
896 for (j = 0; j < 31; j++)
897 xhci_kill_endpoint_urbs(xhci, i, j);
899 spin_unlock_irqrestore(&xhci->lock, flags);
900 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
901 "Calling usb_hc_died()");
902 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
903 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
904 "xHCI host controller is dead.");
908 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
909 struct xhci_virt_device *dev,
910 struct xhci_ring *ep_ring,
911 unsigned int ep_index)
913 union xhci_trb *dequeue_temp;
914 int num_trbs_free_temp;
917 num_trbs_free_temp = ep_ring->num_trbs_free;
918 dequeue_temp = ep_ring->dequeue;
920 /* If we get two back-to-back stalls, and the first stalled transfer
921 * ends just before a link TRB, the dequeue pointer will be left on
922 * the link TRB by the code in the while loop. So we have to update
923 * the dequeue pointer one segment further, or we'll jump off
924 * the segment into la-la-land.
926 if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
927 ep_ring->deq_seg = ep_ring->deq_seg->next;
928 ep_ring->dequeue = ep_ring->deq_seg->trbs;
931 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
932 /* We have more usable TRBs */
933 ep_ring->num_trbs_free++;
935 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
937 if (ep_ring->dequeue ==
938 dev->eps[ep_index].queued_deq_ptr)
940 ep_ring->deq_seg = ep_ring->deq_seg->next;
941 ep_ring->dequeue = ep_ring->deq_seg->trbs;
943 if (ep_ring->dequeue == dequeue_temp) {
950 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
951 ep_ring->num_trbs_free = num_trbs_free_temp;
956 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
957 * we need to clear the set deq pending flag in the endpoint ring state, so that
958 * the TD queueing code can ring the doorbell again. We also need to ring the
959 * endpoint doorbell to restart the ring, but only if there aren't more
960 * cancellations pending.
962 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
963 union xhci_trb *trb, u32 cmd_comp_code)
965 unsigned int ep_index;
966 unsigned int stream_id;
967 struct xhci_ring *ep_ring;
968 struct xhci_virt_device *dev;
969 struct xhci_virt_ep *ep;
970 struct xhci_ep_ctx *ep_ctx;
971 struct xhci_slot_ctx *slot_ctx;
973 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
974 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
975 dev = xhci->devs[slot_id];
976 ep = &dev->eps[ep_index];
978 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
980 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
982 /* XXX: Harmless??? */
986 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
987 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
989 if (cmd_comp_code != COMP_SUCCESS) {
990 unsigned int ep_state;
991 unsigned int slot_state;
993 switch (cmd_comp_code) {
995 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
998 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
999 ep_state = le32_to_cpu(ep_ctx->ep_info);
1000 ep_state &= EP_STATE_MASK;
1001 slot_state = le32_to_cpu(slot_ctx->dev_state);
1002 slot_state = GET_SLOT_STATE(slot_state);
1003 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1004 "Slot state = %u, EP state = %u",
1005 slot_state, ep_state);
1008 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1012 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1016 /* OK what do we do now? The endpoint state is hosed, and we
1017 * should never get to this point if the synchronization between
1018 * queueing, and endpoint state are correct. This might happen
1019 * if the device gets disconnected after we've finished
1020 * cancelling URBs, which might not be an error...
1024 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1025 if (ep->ep_state & EP_HAS_STREAMS) {
1026 struct xhci_stream_ctx *ctx =
1027 &ep->stream_info->stream_ctx_array[stream_id];
1028 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1030 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1032 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1033 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1034 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1035 ep->queued_deq_ptr) == deq) {
1036 /* Update the ring's dequeue segment and dequeue pointer
1037 * to reflect the new position.
1039 update_ring_for_set_deq_completion(xhci, dev,
1042 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1043 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1044 ep->queued_deq_seg, ep->queued_deq_ptr);
1049 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1050 dev->eps[ep_index].queued_deq_seg = NULL;
1051 dev->eps[ep_index].queued_deq_ptr = NULL;
1052 /* Restart any rings with pending URBs */
1053 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1056 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1057 union xhci_trb *trb, u32 cmd_comp_code)
1059 unsigned int ep_index;
1061 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1062 /* This command will only fail if the endpoint wasn't halted,
1063 * but we don't care.
1065 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1066 "Ignoring reset ep completion code of %u", cmd_comp_code);
1068 /* HW with the reset endpoint quirk needs to have a configure endpoint
1069 * command complete before the endpoint can be used. Queue that here
1070 * because the HW can't handle two commands being queued in a row.
1072 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1073 struct xhci_command *command;
1074 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1076 xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n");
1079 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1080 "Queueing configure endpoint command");
1081 xhci_queue_configure_endpoint(xhci, command,
1082 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1084 xhci_ring_cmd_db(xhci);
1086 /* Clear our internal halted state */
1087 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1091 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1094 if (cmd_comp_code == COMP_SUCCESS)
1095 xhci->slot_id = slot_id;
1100 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1102 struct xhci_virt_device *virt_dev;
1104 virt_dev = xhci->devs[slot_id];
1107 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1108 /* Delete default control endpoint resources */
1109 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1110 xhci_free_virt_device(xhci, slot_id);
1113 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1114 struct xhci_event_cmd *event, u32 cmd_comp_code)
1116 struct xhci_virt_device *virt_dev;
1117 struct xhci_input_control_ctx *ctrl_ctx;
1118 unsigned int ep_index;
1119 unsigned int ep_state;
1120 u32 add_flags, drop_flags;
1123 * Configure endpoint commands can come from the USB core
1124 * configuration or alt setting changes, or because the HW
1125 * needed an extra configure endpoint command after a reset
1126 * endpoint command or streams were being configured.
1127 * If the command was for a halted endpoint, the xHCI driver
1128 * is not waiting on the configure endpoint command.
1130 virt_dev = xhci->devs[slot_id];
1131 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1133 xhci_warn(xhci, "Could not get input context, bad type.\n");
1137 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1138 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1139 /* Input ctx add_flags are the endpoint index plus one */
1140 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1142 /* A usb_set_interface() call directly after clearing a halted
1143 * condition may race on this quirky hardware. Not worth
1144 * worrying about, since this is prototype hardware. Not sure
1145 * if this will work for streams, but streams support was
1146 * untested on this prototype.
1148 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1149 ep_index != (unsigned int) -1 &&
1150 add_flags - SLOT_FLAG == drop_flags) {
1151 ep_state = virt_dev->eps[ep_index].ep_state;
1152 if (!(ep_state & EP_HALTED))
1154 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1155 "Completed config ep cmd - "
1156 "last ep index = %d, state = %d",
1157 ep_index, ep_state);
1158 /* Clear internal halted state and restart ring(s) */
1159 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1160 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1166 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1167 struct xhci_event_cmd *event)
1169 xhci_dbg(xhci, "Completed reset device command.\n");
1170 if (!xhci->devs[slot_id])
1171 xhci_warn(xhci, "Reset device command completion "
1172 "for disabled slot %u\n", slot_id);
1175 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1176 struct xhci_event_cmd *event)
1178 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1179 xhci->error_bitmask |= 1 << 6;
1182 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1183 "NEC firmware version %2x.%02x",
1184 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1185 NEC_FW_MINOR(le32_to_cpu(event->status)));
1188 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1190 list_del(&cmd->cmd_list);
1192 if (cmd->completion) {
1193 cmd->status = status;
1194 complete(cmd->completion);
1200 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1202 struct xhci_command *cur_cmd, *tmp_cmd;
1203 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1204 xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT);
1208 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
1209 * If there are other commands waiting then restart the ring and kick the timer.
1210 * This must be called with command ring stopped and xhci->lock held.
1212 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1213 struct xhci_command *cur_cmd)
1215 struct xhci_command *i_cmd, *tmp_cmd;
1218 /* Turn all aborted commands in list to no-ops, then restart */
1219 list_for_each_entry_safe(i_cmd, tmp_cmd, &xhci->cmd_list,
1222 if (i_cmd->status != COMP_CMD_ABORT)
1225 i_cmd->status = COMP_CMD_STOP;
1227 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
1228 i_cmd->command_trb);
1229 /* get cycle state from the original cmd trb */
1230 cycle_state = le32_to_cpu(
1231 i_cmd->command_trb->generic.field[3]) & TRB_CYCLE;
1232 /* modify the command trb to no-op command */
1233 i_cmd->command_trb->generic.field[0] = 0;
1234 i_cmd->command_trb->generic.field[1] = 0;
1235 i_cmd->command_trb->generic.field[2] = 0;
1236 i_cmd->command_trb->generic.field[3] = cpu_to_le32(
1237 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1240 * caller waiting for completion is called when command
1241 * completion event is received for these no-op commands
1245 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1247 /* ring command ring doorbell to restart the command ring */
1248 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
1249 !(xhci->xhc_state & XHCI_STATE_DYING)) {
1250 xhci->current_cmd = cur_cmd;
1251 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1252 xhci_ring_cmd_db(xhci);
1258 void xhci_handle_command_timeout(unsigned long data)
1260 struct xhci_hcd *xhci;
1262 unsigned long flags;
1264 bool second_timeout = false;
1265 xhci = (struct xhci_hcd *) data;
1267 /* mark this command to be cancelled */
1268 spin_lock_irqsave(&xhci->lock, flags);
1269 if (xhci->current_cmd) {
1270 if (xhci->current_cmd->status == COMP_CMD_ABORT)
1271 second_timeout = true;
1272 xhci->current_cmd->status = COMP_CMD_ABORT;
1275 /* Make sure command ring is running before aborting it */
1276 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1277 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1278 (hw_ring_state & CMD_RING_RUNNING)) {
1279 spin_unlock_irqrestore(&xhci->lock, flags);
1280 xhci_dbg(xhci, "Command timeout\n");
1281 ret = xhci_abort_cmd_ring(xhci);
1282 if (unlikely(ret == -ESHUTDOWN)) {
1283 xhci_err(xhci, "Abort command ring failed\n");
1284 xhci_cleanup_command_queue(xhci);
1285 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1286 xhci_dbg(xhci, "xHCI host controller is dead.\n");
1291 /* command ring failed to restart, or host removed. Bail out */
1292 if (second_timeout || xhci->xhc_state & XHCI_STATE_REMOVING) {
1293 spin_unlock_irqrestore(&xhci->lock, flags);
1294 xhci_dbg(xhci, "command timed out twice, ring start fail?\n");
1295 xhci_cleanup_command_queue(xhci);
1299 /* command timeout on stopped ring, ring can't be aborted */
1300 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1301 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1302 spin_unlock_irqrestore(&xhci->lock, flags);
1306 static void handle_cmd_completion(struct xhci_hcd *xhci,
1307 struct xhci_event_cmd *event)
1309 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1311 dma_addr_t cmd_dequeue_dma;
1313 union xhci_trb *cmd_trb;
1314 struct xhci_command *cmd;
1317 cmd_dma = le64_to_cpu(event->cmd_trb);
1318 cmd_trb = xhci->cmd_ring->dequeue;
1319 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1321 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1322 if (cmd_dequeue_dma == 0) {
1323 xhci->error_bitmask |= 1 << 4;
1326 /* Does the DMA address match our internal dequeue pointer address? */
1327 if (cmd_dma != (u64) cmd_dequeue_dma) {
1328 xhci->error_bitmask |= 1 << 5;
1332 cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list);
1334 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1336 "Command completion event does not match command\n");
1340 del_timer(&xhci->cmd_timer);
1342 trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1344 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1346 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1347 if (cmd_comp_code == COMP_CMD_STOP) {
1348 xhci_handle_stopped_cmd_ring(xhci, cmd);
1352 * Host aborted the command ring, check if the current command was
1353 * supposed to be aborted, otherwise continue normally.
1354 * The command ring is stopped now, but the xHC will issue a Command
1355 * Ring Stopped event which will cause us to restart it.
1357 if (cmd_comp_code == COMP_CMD_ABORT) {
1358 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1359 if (cmd->status == COMP_CMD_ABORT)
1363 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1365 case TRB_ENABLE_SLOT:
1366 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1368 case TRB_DISABLE_SLOT:
1369 xhci_handle_cmd_disable_slot(xhci, slot_id);
1372 if (!cmd->completion)
1373 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1376 case TRB_EVAL_CONTEXT:
1381 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1382 le32_to_cpu(cmd_trb->generic.field[3])));
1383 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1386 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1387 le32_to_cpu(cmd_trb->generic.field[3])));
1388 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1391 /* Is this an aborted command turned to NO-OP? */
1392 if (cmd->status == COMP_CMD_STOP)
1393 cmd_comp_code = COMP_CMD_STOP;
1396 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1397 le32_to_cpu(cmd_trb->generic.field[3])));
1398 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1401 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1402 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1404 slot_id = TRB_TO_SLOT_ID(
1405 le32_to_cpu(cmd_trb->generic.field[3]));
1406 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1408 case TRB_NEC_GET_FW:
1409 xhci_handle_cmd_nec_get_fw(xhci, event);
1412 /* Skip over unknown commands on the event ring */
1413 xhci->error_bitmask |= 1 << 6;
1417 /* restart timer if this wasn't the last command */
1418 if (cmd->cmd_list.next != &xhci->cmd_list) {
1419 xhci->current_cmd = list_entry(cmd->cmd_list.next,
1420 struct xhci_command, cmd_list);
1421 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1425 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1427 inc_deq(xhci, xhci->cmd_ring);
1430 static void handle_vendor_event(struct xhci_hcd *xhci,
1431 union xhci_trb *event)
1435 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1436 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1437 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1438 handle_cmd_completion(xhci, &event->event_cmd);
1441 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1442 * port registers -- USB 3.0 and USB 2.0).
1444 * Returns a zero-based port number, which is suitable for indexing into each of
1445 * the split roothubs' port arrays and bus state arrays.
1446 * Add one to it in order to call xhci_find_slot_id_by_port.
1448 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1449 struct xhci_hcd *xhci, u32 port_id)
1452 unsigned int num_similar_speed_ports = 0;
1454 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1455 * and usb2_ports are 0-based indexes. Count the number of similar
1456 * speed ports, up to 1 port before this port.
1458 for (i = 0; i < (port_id - 1); i++) {
1459 u8 port_speed = xhci->port_array[i];
1462 * Skip ports that don't have known speeds, or have duplicate
1463 * Extended Capabilities port speed entries.
1465 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1469 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1470 * 1.1 ports are under the USB 2.0 hub. If the port speed
1471 * matches the device speed, it's a similar speed port.
1473 if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3))
1474 num_similar_speed_ports++;
1476 return num_similar_speed_ports;
1479 static void handle_device_notification(struct xhci_hcd *xhci,
1480 union xhci_trb *event)
1483 struct usb_device *udev;
1485 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1486 if (!xhci->devs[slot_id]) {
1487 xhci_warn(xhci, "Device Notification event for "
1488 "unused slot %u\n", slot_id);
1492 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1494 udev = xhci->devs[slot_id]->udev;
1495 if (udev && udev->parent)
1496 usb_wakeup_notification(udev->parent, udev->portnum);
1499 static void handle_port_status(struct xhci_hcd *xhci,
1500 union xhci_trb *event)
1502 struct usb_hcd *hcd;
1507 unsigned int faked_port_index;
1509 struct xhci_bus_state *bus_state;
1510 __le32 __iomem **port_array;
1511 bool bogus_port_status = false;
1513 /* Port status change events always have a successful completion code */
1514 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1515 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1516 xhci->error_bitmask |= 1 << 8;
1518 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1519 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1521 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1522 if ((port_id <= 0) || (port_id > max_ports)) {
1523 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1524 inc_deq(xhci, xhci->event_ring);
1528 /* Figure out which usb_hcd this port is attached to:
1529 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1531 major_revision = xhci->port_array[port_id - 1];
1533 /* Find the right roothub. */
1534 hcd = xhci_to_hcd(xhci);
1535 if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3))
1536 hcd = xhci->shared_hcd;
1538 if (major_revision == 0) {
1539 xhci_warn(xhci, "Event for port %u not in "
1540 "Extended Capabilities, ignoring.\n",
1542 bogus_port_status = true;
1545 if (major_revision == DUPLICATE_ENTRY) {
1546 xhci_warn(xhci, "Event for port %u duplicated in"
1547 "Extended Capabilities, ignoring.\n",
1549 bogus_port_status = true;
1554 * Hardware port IDs reported by a Port Status Change Event include USB
1555 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1556 * resume event, but we first need to translate the hardware port ID
1557 * into the index into the ports on the correct split roothub, and the
1558 * correct bus_state structure.
1560 bus_state = &xhci->bus_state[hcd_index(hcd)];
1561 if (hcd->speed >= HCD_USB3)
1562 port_array = xhci->usb3_ports;
1564 port_array = xhci->usb2_ports;
1565 /* Find the faked port hub number */
1566 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1569 temp = readl(port_array[faked_port_index]);
1570 if (hcd->state == HC_STATE_SUSPENDED) {
1571 xhci_dbg(xhci, "resume root hub\n");
1572 usb_hcd_resume_root_hub(hcd);
1575 if (hcd->speed >= HCD_USB3 && (temp & PORT_PLS_MASK) == XDEV_INACTIVE)
1576 bus_state->port_remote_wakeup &= ~(1 << faked_port_index);
1578 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1579 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1581 temp1 = readl(&xhci->op_regs->command);
1582 if (!(temp1 & CMD_RUN)) {
1583 xhci_warn(xhci, "xHC is not running.\n");
1587 if (DEV_SUPERSPEED_ANY(temp)) {
1588 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1589 /* Set a flag to say the port signaled remote wakeup,
1590 * so we can tell the difference between the end of
1591 * device and host initiated resume.
1593 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1594 xhci_test_and_clear_bit(xhci, port_array,
1595 faked_port_index, PORT_PLC);
1596 xhci_set_link_state(xhci, port_array, faked_port_index,
1598 /* Need to wait until the next link state change
1599 * indicates the device is actually in U0.
1601 bogus_port_status = true;
1603 } else if (!test_bit(faked_port_index,
1604 &bus_state->resuming_ports)) {
1605 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1606 bus_state->resume_done[faked_port_index] = jiffies +
1607 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1608 set_bit(faked_port_index, &bus_state->resuming_ports);
1609 mod_timer(&hcd->rh_timer,
1610 bus_state->resume_done[faked_port_index]);
1611 /* Do the rest in GetPortStatus */
1615 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1616 DEV_SUPERSPEED_ANY(temp)) {
1617 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1618 /* We've just brought the device into U0 through either the
1619 * Resume state after a device remote wakeup, or through the
1620 * U3Exit state after a host-initiated resume. If it's a device
1621 * initiated remote wake, don't pass up the link state change,
1622 * so the roothub behavior is consistent with external
1623 * USB 3.0 hub behavior.
1625 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1626 faked_port_index + 1);
1627 if (slot_id && xhci->devs[slot_id])
1628 xhci_ring_device(xhci, slot_id);
1629 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1630 bus_state->port_remote_wakeup &=
1631 ~(1 << faked_port_index);
1632 xhci_test_and_clear_bit(xhci, port_array,
1633 faked_port_index, PORT_PLC);
1634 usb_wakeup_notification(hcd->self.root_hub,
1635 faked_port_index + 1);
1636 bogus_port_status = true;
1642 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1643 * RExit to a disconnect state). If so, let the the driver know it's
1644 * out of the RExit state.
1646 if (!DEV_SUPERSPEED_ANY(temp) &&
1647 test_and_clear_bit(faked_port_index,
1648 &bus_state->rexit_ports)) {
1649 complete(&bus_state->rexit_done[faked_port_index]);
1650 bogus_port_status = true;
1654 if (hcd->speed < HCD_USB3)
1655 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1659 /* Update event ring dequeue pointer before dropping the lock */
1660 inc_deq(xhci, xhci->event_ring);
1662 /* Don't make the USB core poll the roothub if we got a bad port status
1663 * change event. Besides, at that point we can't tell which roothub
1664 * (USB 2.0 or USB 3.0) to kick.
1666 if (bogus_port_status)
1670 * xHCI port-status-change events occur when the "or" of all the
1671 * status-change bits in the portsc register changes from 0 to 1.
1672 * New status changes won't cause an event if any other change
1673 * bits are still set. When an event occurs, switch over to
1674 * polling to avoid losing status changes.
1676 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1677 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1678 spin_unlock(&xhci->lock);
1679 /* Pass this up to the core */
1680 usb_hcd_poll_rh_status(hcd);
1681 spin_lock(&xhci->lock);
1685 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1686 * at end_trb, which may be in another segment. If the suspect DMA address is a
1687 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1690 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1691 struct xhci_segment *start_seg,
1692 union xhci_trb *start_trb,
1693 union xhci_trb *end_trb,
1694 dma_addr_t suspect_dma,
1697 dma_addr_t start_dma;
1698 dma_addr_t end_seg_dma;
1699 dma_addr_t end_trb_dma;
1700 struct xhci_segment *cur_seg;
1702 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1703 cur_seg = start_seg;
1708 /* We may get an event for a Link TRB in the middle of a TD */
1709 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1710 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1711 /* If the end TRB isn't in this segment, this is set to 0 */
1712 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1716 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1717 (unsigned long long)suspect_dma,
1718 (unsigned long long)start_dma,
1719 (unsigned long long)end_trb_dma,
1720 (unsigned long long)cur_seg->dma,
1721 (unsigned long long)end_seg_dma);
1723 if (end_trb_dma > 0) {
1724 /* The end TRB is in this segment, so suspect should be here */
1725 if (start_dma <= end_trb_dma) {
1726 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1729 /* Case for one segment with
1730 * a TD wrapped around to the top
1732 if ((suspect_dma >= start_dma &&
1733 suspect_dma <= end_seg_dma) ||
1734 (suspect_dma >= cur_seg->dma &&
1735 suspect_dma <= end_trb_dma))
1740 /* Might still be somewhere in this segment */
1741 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1744 cur_seg = cur_seg->next;
1745 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1746 } while (cur_seg != start_seg);
1751 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1752 unsigned int slot_id, unsigned int ep_index,
1753 unsigned int stream_id,
1754 struct xhci_td *td, union xhci_trb *event_trb)
1756 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1757 struct xhci_command *command;
1758 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1762 ep->ep_state |= EP_HALTED;
1763 ep->stopped_stream = stream_id;
1765 xhci_queue_reset_ep(xhci, command, slot_id, ep_index);
1766 xhci_cleanup_stalled_ring(xhci, ep_index, td);
1768 ep->stopped_stream = 0;
1770 xhci_ring_cmd_db(xhci);
1773 /* Check if an error has halted the endpoint ring. The class driver will
1774 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1775 * However, a babble and other errors also halt the endpoint ring, and the class
1776 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1777 * Ring Dequeue Pointer command manually.
1779 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1780 struct xhci_ep_ctx *ep_ctx,
1781 unsigned int trb_comp_code)
1783 /* TRB completion codes that may require a manual halt cleanup */
1784 if (trb_comp_code == COMP_TX_ERR ||
1785 trb_comp_code == COMP_BABBLE ||
1786 trb_comp_code == COMP_SPLIT_ERR)
1787 /* The 0.96 spec says a babbling control endpoint
1788 * is not halted. The 0.96 spec says it is. Some HW
1789 * claims to be 0.95 compliant, but it halts the control
1790 * endpoint anyway. Check if a babble halted the
1793 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1794 cpu_to_le32(EP_STATE_HALTED))
1800 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1802 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1803 /* Vendor defined "informational" completion code,
1804 * treat as not-an-error.
1806 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1808 xhci_dbg(xhci, "Treating code as success.\n");
1815 * Finish the td processing, remove the td from td list;
1816 * Return 1 if the urb can be given back.
1818 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1819 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1820 struct xhci_virt_ep *ep, int *status, bool skip)
1822 struct xhci_virt_device *xdev;
1823 struct xhci_ring *ep_ring;
1824 unsigned int slot_id;
1826 struct urb *urb = NULL;
1827 struct xhci_ep_ctx *ep_ctx;
1829 struct urb_priv *urb_priv;
1832 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1833 xdev = xhci->devs[slot_id];
1834 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1835 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1836 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1837 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1842 if (trb_comp_code == COMP_STOP_INVAL ||
1843 trb_comp_code == COMP_STOP ||
1844 trb_comp_code == COMP_STOP_SHORT) {
1845 /* The Endpoint Stop Command completion will take care of any
1846 * stopped TDs. A stopped TD may be restarted, so don't update
1847 * the ring dequeue pointer or take this TD off any lists yet.
1849 ep->stopped_td = td;
1852 if (trb_comp_code == COMP_STALL ||
1853 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1855 /* Issue a reset endpoint command to clear the host side
1856 * halt, followed by a set dequeue command to move the
1857 * dequeue pointer past the TD.
1858 * The class driver clears the device side halt later.
1860 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1861 ep_ring->stream_id, td, event_trb);
1863 /* Update ring dequeue pointer */
1864 while (ep_ring->dequeue != td->last_trb)
1865 inc_deq(xhci, ep_ring);
1866 inc_deq(xhci, ep_ring);
1870 /* Clean up the endpoint's TD list */
1872 urb_priv = urb->hcpriv;
1874 /* Do one last check of the actual transfer length.
1875 * If the host controller said we transferred more data than the buffer
1876 * length, urb->actual_length will be a very big number (since it's
1877 * unsigned). Play it safe and say we didn't transfer anything.
1879 if (urb->actual_length > urb->transfer_buffer_length) {
1880 xhci_warn(xhci, "URB transfer length is wrong, xHC issue? req. len = %u, act. len = %u\n",
1881 urb->transfer_buffer_length,
1882 urb->actual_length);
1883 urb->actual_length = 0;
1884 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1885 *status = -EREMOTEIO;
1889 list_del_init(&td->td_list);
1890 /* Was this TD slated to be cancelled but completed anyway? */
1891 if (!list_empty(&td->cancelled_td_list))
1892 list_del_init(&td->cancelled_td_list);
1895 /* Giveback the urb when all the tds are completed */
1896 if (urb_priv->td_cnt == urb_priv->length) {
1898 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1899 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1900 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
1901 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1902 usb_amd_quirk_pll_enable();
1911 * Process control tds, update urb status and actual_length.
1913 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1914 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1915 struct xhci_virt_ep *ep, int *status)
1917 struct xhci_virt_device *xdev;
1918 struct xhci_ring *ep_ring;
1919 unsigned int slot_id;
1921 struct xhci_ep_ctx *ep_ctx;
1924 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1925 xdev = xhci->devs[slot_id];
1926 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1927 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1928 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1929 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1931 switch (trb_comp_code) {
1933 if (event_trb == ep_ring->dequeue) {
1934 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1935 "without IOC set??\n");
1936 *status = -ESHUTDOWN;
1937 } else if (event_trb != td->last_trb) {
1938 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1939 "without IOC set??\n");
1940 *status = -ESHUTDOWN;
1946 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1947 *status = -EREMOTEIO;
1951 case COMP_STOP_SHORT:
1952 if (event_trb == ep_ring->dequeue || event_trb == td->last_trb)
1953 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
1955 td->urb->actual_length =
1956 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1958 return finish_td(xhci, td, event_trb, event, ep, status, false);
1960 /* Did we stop at data stage? */
1961 if (event_trb != ep_ring->dequeue && event_trb != td->last_trb)
1962 td->urb->actual_length =
1963 td->urb->transfer_buffer_length -
1964 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1966 case COMP_STOP_INVAL:
1967 return finish_td(xhci, td, event_trb, event, ep, status, false);
1969 if (!xhci_requires_manual_halt_cleanup(xhci,
1970 ep_ctx, trb_comp_code))
1972 xhci_dbg(xhci, "TRB error code %u, "
1973 "halted endpoint index = %u\n",
1974 trb_comp_code, ep_index);
1975 /* else fall through */
1977 /* Did we transfer part of the data (middle) phase? */
1978 if (event_trb != ep_ring->dequeue &&
1979 event_trb != td->last_trb)
1980 td->urb->actual_length =
1981 td->urb->transfer_buffer_length -
1982 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1983 else if (!td->urb_length_set)
1984 td->urb->actual_length = 0;
1986 return finish_td(xhci, td, event_trb, event, ep, status, false);
1989 * Did we transfer any data, despite the errors that might have
1990 * happened? I.e. did we get past the setup stage?
1992 if (event_trb != ep_ring->dequeue) {
1993 /* The event was for the status stage */
1994 if (event_trb == td->last_trb) {
1995 if (td->urb_length_set) {
1996 /* Don't overwrite a previously set error code
1998 if ((*status == -EINPROGRESS || *status == 0) &&
1999 (td->urb->transfer_flags
2000 & URB_SHORT_NOT_OK))
2001 /* Did we already see a short data
2003 *status = -EREMOTEIO;
2005 td->urb->actual_length =
2006 td->urb->transfer_buffer_length;
2010 * Maybe the event was for the data stage? If so, update
2011 * already the actual_length of the URB and flag it as
2012 * set, so that it is not overwritten in the event for
2015 td->urb_length_set = true;
2016 td->urb->actual_length =
2017 td->urb->transfer_buffer_length -
2018 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2019 xhci_dbg(xhci, "Waiting for status "
2025 return finish_td(xhci, td, event_trb, event, ep, status, false);
2029 * Process isochronous tds, update urb packet status and actual_length.
2031 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2032 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2033 struct xhci_virt_ep *ep, int *status)
2035 struct xhci_ring *ep_ring;
2036 struct urb_priv *urb_priv;
2039 union xhci_trb *cur_trb;
2040 struct xhci_segment *cur_seg;
2041 struct usb_iso_packet_descriptor *frame;
2043 bool skip_td = false;
2045 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2046 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2047 urb_priv = td->urb->hcpriv;
2048 idx = urb_priv->td_cnt;
2049 frame = &td->urb->iso_frame_desc[idx];
2051 /* handle completion code */
2052 switch (trb_comp_code) {
2054 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2058 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2059 trb_comp_code = COMP_SHORT_TX;
2061 case COMP_STOP_SHORT:
2063 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2067 frame->status = -ECOMM;
2070 case COMP_BUFF_OVER:
2072 frame->status = -EOVERFLOW;
2077 frame->status = -EPROTO;
2081 frame->status = -EPROTO;
2082 if (event_trb != td->last_trb)
2087 case COMP_STOP_INVAL:
2094 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2095 frame->actual_length = frame->length;
2096 td->urb->actual_length += frame->length;
2097 } else if (trb_comp_code == COMP_STOP_SHORT) {
2098 frame->actual_length =
2099 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2100 td->urb->actual_length += frame->actual_length;
2102 for (cur_trb = ep_ring->dequeue,
2103 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2104 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2105 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2106 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2107 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2109 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2110 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2112 if (trb_comp_code != COMP_STOP_INVAL) {
2113 frame->actual_length = len;
2114 td->urb->actual_length += len;
2118 return finish_td(xhci, td, event_trb, event, ep, status, false);
2121 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2122 struct xhci_transfer_event *event,
2123 struct xhci_virt_ep *ep, int *status)
2125 struct xhci_ring *ep_ring;
2126 struct urb_priv *urb_priv;
2127 struct usb_iso_packet_descriptor *frame;
2130 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2131 urb_priv = td->urb->hcpriv;
2132 idx = urb_priv->td_cnt;
2133 frame = &td->urb->iso_frame_desc[idx];
2135 /* The transfer is partly done. */
2136 frame->status = -EXDEV;
2138 /* calc actual length */
2139 frame->actual_length = 0;
2141 /* Update ring dequeue pointer */
2142 while (ep_ring->dequeue != td->last_trb)
2143 inc_deq(xhci, ep_ring);
2144 inc_deq(xhci, ep_ring);
2146 return finish_td(xhci, td, NULL, event, ep, status, true);
2150 * Process bulk and interrupt tds, update urb status and actual_length.
2152 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2153 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2154 struct xhci_virt_ep *ep, int *status)
2156 struct xhci_ring *ep_ring;
2157 union xhci_trb *cur_trb;
2158 struct xhci_segment *cur_seg;
2161 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2162 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2164 switch (trb_comp_code) {
2166 /* Double check that the HW transferred everything. */
2167 if (event_trb != td->last_trb ||
2168 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2169 xhci_warn(xhci, "WARN Successful completion "
2171 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2172 *status = -EREMOTEIO;
2175 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2176 trb_comp_code = COMP_SHORT_TX;
2181 case COMP_STOP_SHORT:
2183 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2184 *status = -EREMOTEIO;
2189 /* Others already handled above */
2192 if (trb_comp_code == COMP_SHORT_TX)
2193 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2194 "%d bytes untransferred\n",
2195 td->urb->ep->desc.bEndpointAddress,
2196 td->urb->transfer_buffer_length,
2197 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2198 /* Stopped - short packet completion */
2199 if (trb_comp_code == COMP_STOP_SHORT) {
2200 td->urb->actual_length =
2201 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2203 if (td->urb->transfer_buffer_length <
2204 td->urb->actual_length) {
2205 xhci_warn(xhci, "HC gave bad length of %d bytes txed\n",
2206 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2207 td->urb->actual_length = 0;
2208 /* status will be set by usb core for canceled urbs */
2210 /* Fast path - was this the last TRB in the TD for this URB? */
2211 } else if (event_trb == td->last_trb) {
2212 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2213 td->urb->actual_length =
2214 td->urb->transfer_buffer_length -
2215 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2216 if (td->urb->transfer_buffer_length <
2217 td->urb->actual_length) {
2218 xhci_warn(xhci, "HC gave bad length "
2219 "of %d bytes left\n",
2220 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2221 td->urb->actual_length = 0;
2222 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2223 *status = -EREMOTEIO;
2227 /* Don't overwrite a previously set error code */
2228 if (*status == -EINPROGRESS) {
2229 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2230 *status = -EREMOTEIO;
2235 td->urb->actual_length =
2236 td->urb->transfer_buffer_length;
2237 /* Ignore a short packet completion if the
2238 * untransferred length was zero.
2240 if (*status == -EREMOTEIO)
2244 /* Slow path - walk the list, starting from the dequeue
2245 * pointer, to get the actual length transferred.
2247 td->urb->actual_length = 0;
2248 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2249 cur_trb != event_trb;
2250 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2251 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2252 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2253 td->urb->actual_length +=
2254 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2256 /* If the ring didn't stop on a Link or No-op TRB, add
2257 * in the actual bytes transferred from the Normal TRB
2259 if (trb_comp_code != COMP_STOP_INVAL)
2260 td->urb->actual_length +=
2261 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2262 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2265 return finish_td(xhci, td, event_trb, event, ep, status, false);
2269 * If this function returns an error condition, it means it got a Transfer
2270 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2271 * At this point, the host controller is probably hosed and should be reset.
2273 static int handle_tx_event(struct xhci_hcd *xhci,
2274 struct xhci_transfer_event *event)
2275 __releases(&xhci->lock)
2276 __acquires(&xhci->lock)
2278 struct xhci_virt_device *xdev;
2279 struct xhci_virt_ep *ep;
2280 struct xhci_ring *ep_ring;
2281 unsigned int slot_id;
2283 struct xhci_td *td = NULL;
2284 dma_addr_t event_dma;
2285 struct xhci_segment *event_seg;
2286 union xhci_trb *event_trb;
2287 struct urb *urb = NULL;
2288 int status = -EINPROGRESS;
2289 struct urb_priv *urb_priv;
2290 struct xhci_ep_ctx *ep_ctx;
2291 struct list_head *tmp;
2295 bool handling_skipped_tds = false;
2297 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2298 xdev = xhci->devs[slot_id];
2300 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2301 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2302 (unsigned long long) xhci_trb_virt_to_dma(
2303 xhci->event_ring->deq_seg,
2304 xhci->event_ring->dequeue),
2305 lower_32_bits(le64_to_cpu(event->buffer)),
2306 upper_32_bits(le64_to_cpu(event->buffer)),
2307 le32_to_cpu(event->transfer_len),
2308 le32_to_cpu(event->flags));
2309 xhci_dbg(xhci, "Event ring:\n");
2310 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2314 /* Endpoint ID is 1 based, our index is zero based */
2315 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2316 ep = &xdev->eps[ep_index];
2317 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2318 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2320 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2321 EP_STATE_DISABLED) {
2322 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2323 "or incorrect stream ring\n");
2324 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2325 (unsigned long long) xhci_trb_virt_to_dma(
2326 xhci->event_ring->deq_seg,
2327 xhci->event_ring->dequeue),
2328 lower_32_bits(le64_to_cpu(event->buffer)),
2329 upper_32_bits(le64_to_cpu(event->buffer)),
2330 le32_to_cpu(event->transfer_len),
2331 le32_to_cpu(event->flags));
2332 xhci_dbg(xhci, "Event ring:\n");
2333 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2337 /* Count current td numbers if ep->skip is set */
2339 list_for_each(tmp, &ep_ring->td_list)
2343 event_dma = le64_to_cpu(event->buffer);
2344 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2345 /* Look for common error cases */
2346 switch (trb_comp_code) {
2347 /* Skip codes that require special handling depending on
2351 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2353 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2354 trb_comp_code = COMP_SHORT_TX;
2356 xhci_warn_ratelimited(xhci,
2357 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2361 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2363 case COMP_STOP_INVAL:
2364 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2366 case COMP_STOP_SHORT:
2367 xhci_dbg(xhci, "Stopped with short packet transfer detected\n");
2370 xhci_dbg(xhci, "Stalled endpoint\n");
2371 ep->ep_state |= EP_HALTED;
2375 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2378 case COMP_SPLIT_ERR:
2380 xhci_dbg(xhci, "Transfer error on endpoint\n");
2384 xhci_dbg(xhci, "Babble error on endpoint\n");
2385 status = -EOVERFLOW;
2388 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2392 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2394 case COMP_BUFF_OVER:
2395 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2399 * When the Isoch ring is empty, the xHC will generate
2400 * a Ring Overrun Event for IN Isoch endpoint or Ring
2401 * Underrun Event for OUT Isoch endpoint.
2403 xhci_dbg(xhci, "underrun event on endpoint\n");
2404 if (!list_empty(&ep_ring->td_list))
2405 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2406 "still with TDs queued?\n",
2407 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2411 xhci_dbg(xhci, "overrun event on endpoint\n");
2412 if (!list_empty(&ep_ring->td_list))
2413 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2414 "still with TDs queued?\n",
2415 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2419 xhci_warn(xhci, "WARN: detect an incompatible device");
2422 case COMP_MISSED_INT:
2424 * When encounter missed service error, one or more isoc tds
2425 * may be missed by xHC.
2426 * Set skip flag of the ep_ring; Complete the missed tds as
2427 * short transfer when process the ep_ring next time.
2430 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2434 xhci_dbg(xhci, "No Ping response error, Skip one Isoc TD\n");
2437 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2441 xhci_warn(xhci, "ERROR Unknown event condition %u, HC probably busted\n",
2447 /* This TRB should be in the TD at the head of this ring's
2450 if (list_empty(&ep_ring->td_list)) {
2452 * A stopped endpoint may generate an extra completion
2453 * event if the device was suspended. Don't print
2456 if (!(trb_comp_code == COMP_STOP ||
2457 trb_comp_code == COMP_STOP_INVAL)) {
2458 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2459 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2461 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2462 (le32_to_cpu(event->flags) &
2463 TRB_TYPE_BITMASK)>>10);
2464 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2468 xhci_dbg(xhci, "td_list is empty while skip "
2469 "flag set. Clear skip flag.\n");
2475 /* We've skipped all the TDs on the ep ring when ep->skip set */
2476 if (ep->skip && td_num == 0) {
2478 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2479 "Clear skip flag.\n");
2484 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2488 /* Is this a TRB in the currently executing TD? */
2489 event_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2490 td->last_trb, event_dma, false);
2493 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2494 * is not in the current TD pointed by ep_ring->dequeue because
2495 * that the hardware dequeue pointer still at the previous TRB
2496 * of the current TD. The previous TRB maybe a Link TD or the
2497 * last TRB of the previous TD. The command completion handle
2498 * will take care the rest.
2500 if (!event_seg && (trb_comp_code == COMP_STOP ||
2501 trb_comp_code == COMP_STOP_INVAL)) {
2508 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2509 /* Some host controllers give a spurious
2510 * successful event after a short transfer.
2513 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2514 ep_ring->last_td_was_short) {
2515 ep_ring->last_td_was_short = false;
2519 /* HC is busted, give up! */
2521 "ERROR Transfer event TRB DMA ptr not "
2522 "part of current TD ep_index %d "
2523 "comp_code %u\n", ep_index,
2525 trb_in_td(xhci, ep_ring->deq_seg,
2526 ep_ring->dequeue, td->last_trb,
2531 ret = skip_isoc_td(xhci, td, event, ep, &status);
2534 if (trb_comp_code == COMP_SHORT_TX)
2535 ep_ring->last_td_was_short = true;
2537 ep_ring->last_td_was_short = false;
2540 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2544 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2545 sizeof(*event_trb)];
2547 * No-op TRB should not trigger interrupts.
2548 * If event_trb is a no-op TRB, it means the
2549 * corresponding TD has been cancelled. Just ignore
2552 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2554 "event_trb is a no-op TRB. Skip it\n");
2558 /* Now update the urb's actual_length and give back to
2561 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2562 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2564 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2565 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2568 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2574 handling_skipped_tds = ep->skip &&
2575 trb_comp_code != COMP_MISSED_INT &&
2576 trb_comp_code != COMP_PING_ERR;
2579 * Do not update event ring dequeue pointer if we're in a loop
2580 * processing missed tds.
2582 if (!handling_skipped_tds)
2583 inc_deq(xhci, xhci->event_ring);
2587 urb_priv = urb->hcpriv;
2589 xhci_urb_free_priv(urb_priv);
2591 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2592 if ((urb->actual_length != urb->transfer_buffer_length &&
2593 (urb->transfer_flags &
2594 URB_SHORT_NOT_OK)) ||
2596 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2597 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2598 "expected = %d, status = %d\n",
2599 urb, urb->actual_length,
2600 urb->transfer_buffer_length,
2602 spin_unlock(&xhci->lock);
2603 /* EHCI, UHCI, and OHCI always unconditionally set the
2604 * urb->status of an isochronous endpoint to 0.
2606 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2608 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2609 spin_lock(&xhci->lock);
2613 * If ep->skip is set, it means there are missed tds on the
2614 * endpoint ring need to take care of.
2615 * Process them as short transfer until reach the td pointed by
2618 } while (handling_skipped_tds);
2624 * This function handles all OS-owned events on the event ring. It may drop
2625 * xhci->lock between event processing (e.g. to pass up port status changes).
2626 * Returns >0 for "possibly more events to process" (caller should call again),
2627 * otherwise 0 if done. In future, <0 returns should indicate error code.
2629 static int xhci_handle_event(struct xhci_hcd *xhci)
2631 union xhci_trb *event;
2632 int update_ptrs = 1;
2635 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2636 xhci->error_bitmask |= 1 << 1;
2640 event = xhci->event_ring->dequeue;
2641 /* Does the HC or OS own the TRB? */
2642 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2643 xhci->event_ring->cycle_state) {
2644 xhci->error_bitmask |= 1 << 2;
2649 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2650 * speculative reads of the event's flags/data below.
2653 /* FIXME: Handle more event types. */
2654 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2655 case TRB_TYPE(TRB_COMPLETION):
2656 handle_cmd_completion(xhci, &event->event_cmd);
2658 case TRB_TYPE(TRB_PORT_STATUS):
2659 handle_port_status(xhci, event);
2662 case TRB_TYPE(TRB_TRANSFER):
2663 ret = handle_tx_event(xhci, &event->trans_event);
2665 xhci->error_bitmask |= 1 << 9;
2669 case TRB_TYPE(TRB_DEV_NOTE):
2670 handle_device_notification(xhci, event);
2673 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2675 handle_vendor_event(xhci, event);
2677 xhci->error_bitmask |= 1 << 3;
2679 /* Any of the above functions may drop and re-acquire the lock, so check
2680 * to make sure a watchdog timer didn't mark the host as non-responsive.
2682 if (xhci->xhc_state & XHCI_STATE_DYING) {
2683 xhci_dbg(xhci, "xHCI host dying, returning from "
2684 "event handler.\n");
2689 /* Update SW event ring dequeue pointer */
2690 inc_deq(xhci, xhci->event_ring);
2692 /* Are there more items on the event ring? Caller will call us again to
2699 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2700 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2701 * indicators of an event TRB error, but we check the status *first* to be safe.
2703 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2705 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2708 union xhci_trb *event_ring_deq;
2711 spin_lock(&xhci->lock);
2712 /* Check if the xHC generated the interrupt, or the irq is shared */
2713 status = readl(&xhci->op_regs->status);
2714 if (status == 0xffffffff)
2717 if (!(status & STS_EINT)) {
2718 spin_unlock(&xhci->lock);
2721 if (status & STS_FATAL) {
2722 xhci_warn(xhci, "WARNING: Host System Error\n");
2725 spin_unlock(&xhci->lock);
2730 * Clear the op reg interrupt status first,
2731 * so we can receive interrupts from other MSI-X interrupters.
2732 * Write 1 to clear the interrupt status.
2735 writel(status, &xhci->op_regs->status);
2736 /* FIXME when MSI-X is supported and there are multiple vectors */
2737 /* Clear the MSI-X event interrupt status */
2741 /* Acknowledge the PCI interrupt */
2742 irq_pending = readl(&xhci->ir_set->irq_pending);
2743 irq_pending |= IMAN_IP;
2744 writel(irq_pending, &xhci->ir_set->irq_pending);
2747 if (xhci->xhc_state & XHCI_STATE_DYING ||
2748 xhci->xhc_state & XHCI_STATE_HALTED) {
2749 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2750 "Shouldn't IRQs be disabled?\n");
2751 /* Clear the event handler busy flag (RW1C);
2752 * the event ring should be empty.
2754 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2755 xhci_write_64(xhci, temp_64 | ERST_EHB,
2756 &xhci->ir_set->erst_dequeue);
2757 spin_unlock(&xhci->lock);
2762 event_ring_deq = xhci->event_ring->dequeue;
2763 /* FIXME this should be a delayed service routine
2764 * that clears the EHB.
2766 while (xhci_handle_event(xhci) > 0) {}
2768 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2769 /* If necessary, update the HW's version of the event ring deq ptr. */
2770 if (event_ring_deq != xhci->event_ring->dequeue) {
2771 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2772 xhci->event_ring->dequeue);
2774 xhci_warn(xhci, "WARN something wrong with SW event "
2775 "ring dequeue ptr.\n");
2776 /* Update HC event ring dequeue pointer */
2777 temp_64 &= ERST_PTR_MASK;
2778 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2781 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2782 temp_64 |= ERST_EHB;
2783 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2785 spin_unlock(&xhci->lock);
2790 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2792 return xhci_irq(hcd);
2795 /**** Endpoint Ring Operations ****/
2798 * Generic function for queueing a TRB on a ring.
2799 * The caller must have checked to make sure there's room on the ring.
2801 * @more_trbs_coming: Will you enqueue more TRBs before calling
2802 * prepare_transfer()?
2804 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2805 bool more_trbs_coming,
2806 u32 field1, u32 field2, u32 field3, u32 field4)
2808 struct xhci_generic_trb *trb;
2810 trb = &ring->enqueue->generic;
2811 trb->field[0] = cpu_to_le32(field1);
2812 trb->field[1] = cpu_to_le32(field2);
2813 trb->field[2] = cpu_to_le32(field3);
2814 trb->field[3] = cpu_to_le32(field4);
2815 inc_enq(xhci, ring, more_trbs_coming);
2819 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2820 * FIXME allocate segments if the ring is full.
2822 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2823 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2825 unsigned int num_trbs_needed;
2827 /* Make sure the endpoint has been added to xHC schedule */
2829 case EP_STATE_DISABLED:
2831 * USB core changed config/interfaces without notifying us,
2832 * or hardware is reporting the wrong state.
2834 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2836 case EP_STATE_ERROR:
2837 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2838 /* FIXME event handling code for error needs to clear it */
2839 /* XXX not sure if this should be -ENOENT or not */
2841 case EP_STATE_HALTED:
2842 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2843 case EP_STATE_STOPPED:
2844 case EP_STATE_RUNNING:
2847 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2849 * FIXME issue Configure Endpoint command to try to get the HC
2850 * back into a known state.
2856 if (room_on_ring(xhci, ep_ring, num_trbs))
2859 if (ep_ring == xhci->cmd_ring) {
2860 xhci_err(xhci, "Do not support expand command ring\n");
2864 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2865 "ERROR no room on ep ring, try ring expansion");
2866 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2867 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2869 xhci_err(xhci, "Ring expansion failed\n");
2874 if (enqueue_is_link_trb(ep_ring)) {
2875 struct xhci_ring *ring = ep_ring;
2876 union xhci_trb *next;
2878 next = ring->enqueue;
2880 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2881 /* If we're not dealing with 0.95 hardware or isoc rings
2882 * on AMD 0.96 host, clear the chain bit.
2884 if (!xhci_link_trb_quirk(xhci) &&
2885 !(ring->type == TYPE_ISOC &&
2886 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2887 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2889 next->link.control |= cpu_to_le32(TRB_CHAIN);
2892 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2894 /* Toggle the cycle bit after the last ring segment. */
2895 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2896 ring->cycle_state ^= 1;
2898 ring->enq_seg = ring->enq_seg->next;
2899 ring->enqueue = ring->enq_seg->trbs;
2900 next = ring->enqueue;
2907 static int prepare_transfer(struct xhci_hcd *xhci,
2908 struct xhci_virt_device *xdev,
2909 unsigned int ep_index,
2910 unsigned int stream_id,
2911 unsigned int num_trbs,
2913 unsigned int td_index,
2917 struct urb_priv *urb_priv;
2919 struct xhci_ring *ep_ring;
2920 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2922 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2924 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2929 ret = prepare_ring(xhci, ep_ring,
2930 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2931 num_trbs, mem_flags);
2935 urb_priv = urb->hcpriv;
2936 td = urb_priv->td[td_index];
2938 INIT_LIST_HEAD(&td->td_list);
2939 INIT_LIST_HEAD(&td->cancelled_td_list);
2941 if (td_index == 0) {
2942 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2948 /* Add this TD to the tail of the endpoint ring's TD list */
2949 list_add_tail(&td->td_list, &ep_ring->td_list);
2950 td->start_seg = ep_ring->enq_seg;
2951 td->first_trb = ep_ring->enqueue;
2953 urb_priv->td[td_index] = td;
2958 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2960 int num_sgs, num_trbs, running_total, temp, i;
2961 struct scatterlist *sg;
2964 num_sgs = urb->num_mapped_sgs;
2965 temp = urb->transfer_buffer_length;
2968 for_each_sg(urb->sg, sg, num_sgs, i) {
2969 unsigned int len = sg_dma_len(sg);
2971 /* Scatter gather list entries may cross 64KB boundaries */
2972 running_total = TRB_MAX_BUFF_SIZE -
2973 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2974 running_total &= TRB_MAX_BUFF_SIZE - 1;
2975 if (running_total != 0)
2978 /* How many more 64KB chunks to transfer, how many more TRBs? */
2979 while (running_total < sg_dma_len(sg) && running_total < temp) {
2981 running_total += TRB_MAX_BUFF_SIZE;
2983 len = min_t(int, len, temp);
2991 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2994 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2995 "TRBs, %d left\n", __func__,
2996 urb->ep->desc.bEndpointAddress, num_trbs);
2997 if (running_total != urb->transfer_buffer_length)
2998 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2999 "queued %#x (%d), asked for %#x (%d)\n",
3001 urb->ep->desc.bEndpointAddress,
3002 running_total, running_total,
3003 urb->transfer_buffer_length,
3004 urb->transfer_buffer_length);
3007 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3008 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3009 struct xhci_generic_trb *start_trb)
3012 * Pass all the TRBs to the hardware at once and make sure this write
3017 start_trb->field[3] |= cpu_to_le32(start_cycle);
3019 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3020 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3024 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3025 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3026 * (comprised of sg list entries) can take several service intervals to
3029 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3030 struct urb *urb, int slot_id, unsigned int ep_index)
3032 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3033 xhci->devs[slot_id]->out_ctx, ep_index);
3037 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3038 ep_interval = urb->interval;
3039 /* Convert to microframes */
3040 if (urb->dev->speed == USB_SPEED_LOW ||
3041 urb->dev->speed == USB_SPEED_FULL)
3043 /* FIXME change this to a warning and a suggestion to use the new API
3044 * to set the polling interval (once the API is added).
3046 if (xhci_interval != ep_interval) {
3047 dev_dbg_ratelimited(&urb->dev->dev,
3048 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3049 ep_interval, ep_interval == 1 ? "" : "s",
3050 xhci_interval, xhci_interval == 1 ? "" : "s");
3051 urb->interval = xhci_interval;
3052 /* Convert back to frames for LS/FS devices */
3053 if (urb->dev->speed == USB_SPEED_LOW ||
3054 urb->dev->speed == USB_SPEED_FULL)
3057 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3061 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3062 * packets remaining in the TD (*not* including this TRB).
3064 * Total TD packet count = total_packet_count =
3065 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3067 * Packets transferred up to and including this TRB = packets_transferred =
3068 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3070 * TD size = total_packet_count - packets_transferred
3072 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3073 * including this TRB, right shifted by 10
3075 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3076 * This is taken care of in the TRB_TD_SIZE() macro
3078 * The last TRB in a TD must have the TD size set to zero.
3080 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3081 int trb_buff_len, unsigned int td_total_len,
3082 struct urb *urb, unsigned int num_trbs_left)
3084 u32 maxp, total_packet_count;
3086 if (xhci->hci_version < 0x100)
3087 return ((td_total_len - transferred) >> 10);
3089 maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3090 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3092 /* One TRB with a zero-length data packet. */
3093 if (num_trbs_left == 0 || (transferred == 0 && trb_buff_len == 0) ||
3094 trb_buff_len == td_total_len)
3097 /* Queueing functions don't count the current TRB into transferred */
3098 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3102 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3103 struct urb *urb, int slot_id, unsigned int ep_index)
3105 struct xhci_ring *ep_ring;
3106 unsigned int num_trbs;
3107 struct urb_priv *urb_priv;
3109 struct scatterlist *sg;
3111 int trb_buff_len, this_sg_len, running_total, ret;
3112 unsigned int total_packet_count;
3113 bool zero_length_needed;
3117 bool more_trbs_coming;
3119 struct xhci_generic_trb *start_trb;
3122 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3126 num_trbs = count_sg_trbs_needed(xhci, urb);
3127 num_sgs = urb->num_mapped_sgs;
3128 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3129 usb_endpoint_maxp(&urb->ep->desc));
3131 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3132 ep_index, urb->stream_id,
3133 num_trbs, urb, 0, mem_flags);
3137 urb_priv = urb->hcpriv;
3139 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3140 zero_length_needed = urb->transfer_flags & URB_ZERO_PACKET &&
3141 urb_priv->length == 2;
3142 if (zero_length_needed) {
3144 xhci_dbg(xhci, "Creating zero length td.\n");
3145 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3146 ep_index, urb->stream_id,
3147 1, urb, 1, mem_flags);
3152 td = urb_priv->td[0];
3155 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3156 * until we've finished creating all the other TRBs. The ring's cycle
3157 * state may change as we enqueue the other TRBs, so save it too.
3159 start_trb = &ep_ring->enqueue->generic;
3160 start_cycle = ep_ring->cycle_state;
3164 * How much data is in the first TRB?
3166 * There are three forces at work for TRB buffer pointers and lengths:
3167 * 1. We don't want to walk off the end of this sg-list entry buffer.
3168 * 2. The transfer length that the driver requested may be smaller than
3169 * the amount of memory allocated for this scatter-gather list.
3170 * 3. TRBs buffers can't cross 64KB boundaries.
3173 addr = (u64) sg_dma_address(sg);
3174 this_sg_len = sg_dma_len(sg);
3175 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3176 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3177 if (trb_buff_len > urb->transfer_buffer_length)
3178 trb_buff_len = urb->transfer_buffer_length;
3181 last_trb_num = zero_length_needed ? 2 : 1;
3182 /* Queue the first TRB, even if it's zero-length */
3185 u32 length_field = 0;
3188 /* Don't change the cycle bit of the first TRB until later */
3191 if (start_cycle == 0)
3194 field |= ep_ring->cycle_state;
3196 /* Chain all the TRBs together; clear the chain bit in the last
3197 * TRB to indicate it's the last TRB in the chain.
3199 if (num_trbs > last_trb_num) {
3201 } else if (num_trbs == last_trb_num) {
3202 td->last_trb = ep_ring->enqueue;
3204 } else if (zero_length_needed && num_trbs == 1) {
3206 urb_priv->td[1]->last_trb = ep_ring->enqueue;
3210 /* Only set interrupt on short packet for IN endpoints */
3211 if (usb_urb_dir_in(urb))
3214 if (TRB_MAX_BUFF_SIZE -
3215 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3216 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3217 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3218 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3219 (unsigned int) addr + trb_buff_len);
3222 /* Set the TRB length, TD size, and interrupter fields. */
3223 remainder = xhci_td_remainder(xhci, running_total, trb_buff_len,
3224 urb->transfer_buffer_length,
3227 length_field = TRB_LEN(trb_buff_len) |
3228 TRB_TD_SIZE(remainder) |
3232 more_trbs_coming = true;
3234 more_trbs_coming = false;
3235 queue_trb(xhci, ep_ring, more_trbs_coming,
3236 lower_32_bits(addr),
3237 upper_32_bits(addr),
3239 field | TRB_TYPE(TRB_NORMAL));
3241 running_total += trb_buff_len;
3243 /* Calculate length for next transfer --
3244 * Are we done queueing all the TRBs for this sg entry?
3246 this_sg_len -= trb_buff_len;
3247 if (this_sg_len == 0) {
3252 addr = (u64) sg_dma_address(sg);
3253 this_sg_len = sg_dma_len(sg);
3255 addr += trb_buff_len;
3258 trb_buff_len = TRB_MAX_BUFF_SIZE -
3259 (addr & (TRB_MAX_BUFF_SIZE - 1));
3260 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3261 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3263 urb->transfer_buffer_length - running_total;
3264 } while (num_trbs > 0);
3266 check_trb_math(urb, num_trbs, running_total);
3267 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3268 start_cycle, start_trb);
3272 /* This is very similar to what ehci-q.c qtd_fill() does */
3273 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3274 struct urb *urb, int slot_id, unsigned int ep_index)
3276 struct xhci_ring *ep_ring;
3277 struct urb_priv *urb_priv;
3280 struct xhci_generic_trb *start_trb;
3283 bool more_trbs_coming;
3284 bool zero_length_needed;
3286 u32 field, length_field;
3288 int running_total, trb_buff_len, ret;
3289 unsigned int total_packet_count;
3293 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3295 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3300 /* How much data is (potentially) left before the 64KB boundary? */
3301 running_total = TRB_MAX_BUFF_SIZE -
3302 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3303 running_total &= TRB_MAX_BUFF_SIZE - 1;
3305 /* If there's some data on this 64KB chunk, or we have to send a
3306 * zero-length transfer, we need at least one TRB
3308 if (running_total != 0 || urb->transfer_buffer_length == 0)
3310 /* How many more 64KB chunks to transfer, how many more TRBs? */
3311 while (running_total < urb->transfer_buffer_length) {
3313 running_total += TRB_MAX_BUFF_SIZE;
3316 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3317 ep_index, urb->stream_id,
3318 num_trbs, urb, 0, mem_flags);
3322 urb_priv = urb->hcpriv;
3324 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3325 zero_length_needed = urb->transfer_flags & URB_ZERO_PACKET &&
3326 urb_priv->length == 2;
3327 if (zero_length_needed) {
3329 xhci_dbg(xhci, "Creating zero length td.\n");
3330 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3331 ep_index, urb->stream_id,
3332 1, urb, 1, mem_flags);
3337 td = urb_priv->td[0];
3340 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3341 * until we've finished creating all the other TRBs. The ring's cycle
3342 * state may change as we enqueue the other TRBs, so save it too.
3344 start_trb = &ep_ring->enqueue->generic;
3345 start_cycle = ep_ring->cycle_state;
3348 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3349 usb_endpoint_maxp(&urb->ep->desc));
3350 /* How much data is in the first TRB? */
3351 addr = (u64) urb->transfer_dma;
3352 trb_buff_len = TRB_MAX_BUFF_SIZE -
3353 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3354 if (trb_buff_len > urb->transfer_buffer_length)
3355 trb_buff_len = urb->transfer_buffer_length;
3358 last_trb_num = zero_length_needed ? 2 : 1;
3359 /* Queue the first TRB, even if it's zero-length */
3364 /* Don't change the cycle bit of the first TRB until later */
3367 if (start_cycle == 0)
3370 field |= ep_ring->cycle_state;
3372 /* Chain all the TRBs together; clear the chain bit in the last
3373 * TRB to indicate it's the last TRB in the chain.
3375 if (num_trbs > last_trb_num) {
3377 } else if (num_trbs == last_trb_num) {
3378 td->last_trb = ep_ring->enqueue;
3380 } else if (zero_length_needed && num_trbs == 1) {
3382 urb_priv->td[1]->last_trb = ep_ring->enqueue;
3386 /* Only set interrupt on short packet for IN endpoints */
3387 if (usb_urb_dir_in(urb))
3390 /* Set the TRB length, TD size, and interrupter fields. */
3391 remainder = xhci_td_remainder(xhci, running_total, trb_buff_len,
3392 urb->transfer_buffer_length,
3395 length_field = TRB_LEN(trb_buff_len) |
3396 TRB_TD_SIZE(remainder) |
3400 more_trbs_coming = true;
3402 more_trbs_coming = false;
3403 queue_trb(xhci, ep_ring, more_trbs_coming,
3404 lower_32_bits(addr),
3405 upper_32_bits(addr),
3407 field | TRB_TYPE(TRB_NORMAL));
3409 running_total += trb_buff_len;
3411 /* Calculate length for next transfer */
3412 addr += trb_buff_len;
3413 trb_buff_len = urb->transfer_buffer_length - running_total;
3414 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3415 trb_buff_len = TRB_MAX_BUFF_SIZE;
3416 } while (num_trbs > 0);
3418 check_trb_math(urb, num_trbs, running_total);
3419 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3420 start_cycle, start_trb);
3424 /* Caller must have locked xhci->lock */
3425 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3426 struct urb *urb, int slot_id, unsigned int ep_index)
3428 struct xhci_ring *ep_ring;
3431 struct usb_ctrlrequest *setup;
3432 struct xhci_generic_trb *start_trb;
3434 u32 field, length_field, remainder;
3435 struct urb_priv *urb_priv;
3438 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3443 * Need to copy setup packet into setup TRB, so we can't use the setup
3446 if (!urb->setup_packet)
3449 /* 1 TRB for setup, 1 for status */
3452 * Don't need to check if we need additional event data and normal TRBs,
3453 * since data in control transfers will never get bigger than 16MB
3454 * XXX: can we get a buffer that crosses 64KB boundaries?
3456 if (urb->transfer_buffer_length > 0)
3458 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3459 ep_index, urb->stream_id,
3460 num_trbs, urb, 0, mem_flags);
3464 urb_priv = urb->hcpriv;
3465 td = urb_priv->td[0];
3468 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3469 * until we've finished creating all the other TRBs. The ring's cycle
3470 * state may change as we enqueue the other TRBs, so save it too.
3472 start_trb = &ep_ring->enqueue->generic;
3473 start_cycle = ep_ring->cycle_state;
3475 /* Queue setup TRB - see section 6.4.1.2.1 */
3476 /* FIXME better way to translate setup_packet into two u32 fields? */
3477 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3479 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3480 if (start_cycle == 0)
3483 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3484 if (xhci->hci_version >= 0x100) {
3485 if (urb->transfer_buffer_length > 0) {
3486 if (setup->bRequestType & USB_DIR_IN)
3487 field |= TRB_TX_TYPE(TRB_DATA_IN);
3489 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3493 queue_trb(xhci, ep_ring, true,
3494 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3495 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3496 TRB_LEN(8) | TRB_INTR_TARGET(0),
3497 /* Immediate data in pointer */
3500 /* If there's data, queue data TRBs */
3501 /* Only set interrupt on short packet for IN endpoints */
3502 if (usb_urb_dir_in(urb))
3503 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3505 field = TRB_TYPE(TRB_DATA);
3507 remainder = xhci_td_remainder(xhci, 0,
3508 urb->transfer_buffer_length,
3509 urb->transfer_buffer_length,
3512 length_field = TRB_LEN(urb->transfer_buffer_length) |
3513 TRB_TD_SIZE(remainder) |
3516 if (urb->transfer_buffer_length > 0) {
3517 if (setup->bRequestType & USB_DIR_IN)
3518 field |= TRB_DIR_IN;
3519 queue_trb(xhci, ep_ring, true,
3520 lower_32_bits(urb->transfer_dma),
3521 upper_32_bits(urb->transfer_dma),
3523 field | ep_ring->cycle_state);
3526 /* Save the DMA address of the last TRB in the TD */
3527 td->last_trb = ep_ring->enqueue;
3529 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3530 /* If the device sent data, the status stage is an OUT transfer */
3531 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3535 queue_trb(xhci, ep_ring, false,
3539 /* Event on completion */
3540 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3542 giveback_first_trb(xhci, slot_id, ep_index, 0,
3543 start_cycle, start_trb);
3547 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3548 struct urb *urb, int i)
3553 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3554 td_len = urb->iso_frame_desc[i].length;
3556 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3565 * The transfer burst count field of the isochronous TRB defines the number of
3566 * bursts that are required to move all packets in this TD. Only SuperSpeed
3567 * devices can burst up to bMaxBurst number of packets per service interval.
3568 * This field is zero based, meaning a value of zero in the field means one
3569 * burst. Basically, for everything but SuperSpeed devices, this field will be
3570 * zero. Only xHCI 1.0 host controllers support this field.
3572 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3573 struct usb_device *udev,
3574 struct urb *urb, unsigned int total_packet_count)
3576 unsigned int max_burst;
3578 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3581 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3582 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3586 * Returns the number of packets in the last "burst" of packets. This field is
3587 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3588 * the last burst packet count is equal to the total number of packets in the
3589 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3590 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3591 * contain 1 to (bMaxBurst + 1) packets.
3593 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3594 struct usb_device *udev,
3595 struct urb *urb, unsigned int total_packet_count)
3597 unsigned int max_burst;
3598 unsigned int residue;
3600 if (xhci->hci_version < 0x100)
3603 switch (udev->speed) {
3604 case USB_SPEED_SUPER:
3605 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3606 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3607 residue = total_packet_count % (max_burst + 1);
3608 /* If residue is zero, the last burst contains (max_burst + 1)
3609 * number of packets, but the TLBPC field is zero-based.
3615 if (total_packet_count == 0)
3617 return total_packet_count - 1;
3622 * Calculates Frame ID field of the isochronous TRB identifies the
3623 * target frame that the Interval associated with this Isochronous
3624 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3626 * Returns actual frame id on success, negative value on error.
3628 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3629 struct urb *urb, int index)
3631 int start_frame, ist, ret = 0;
3632 int start_frame_id, end_frame_id, current_frame_id;
3634 if (urb->dev->speed == USB_SPEED_LOW ||
3635 urb->dev->speed == USB_SPEED_FULL)
3636 start_frame = urb->start_frame + index * urb->interval;
3638 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3640 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3642 * If bit [3] of IST is cleared to '0', software can add a TRB no
3643 * later than IST[2:0] Microframes before that TRB is scheduled to
3645 * If bit [3] of IST is set to '1', software can add a TRB no later
3646 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3648 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3649 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3652 /* Software shall not schedule an Isoch TD with a Frame ID value that
3653 * is less than the Start Frame ID or greater than the End Frame ID,
3656 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3657 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3659 * Both the End Frame ID and Start Frame ID values are calculated
3660 * in microframes. When software determines the valid Frame ID value;
3661 * The End Frame ID value should be rounded down to the nearest Frame
3662 * boundary, and the Start Frame ID value should be rounded up to the
3663 * nearest Frame boundary.
3665 current_frame_id = readl(&xhci->run_regs->microframe_index);
3666 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3667 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3669 start_frame &= 0x7ff;
3670 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3671 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3673 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3674 __func__, index, readl(&xhci->run_regs->microframe_index),
3675 start_frame_id, end_frame_id, start_frame);
3677 if (start_frame_id < end_frame_id) {
3678 if (start_frame > end_frame_id ||
3679 start_frame < start_frame_id)
3681 } else if (start_frame_id > end_frame_id) {
3682 if ((start_frame > end_frame_id &&
3683 start_frame < start_frame_id))
3690 if (ret == -EINVAL || start_frame == start_frame_id) {
3691 start_frame = start_frame_id + 1;
3692 if (urb->dev->speed == USB_SPEED_LOW ||
3693 urb->dev->speed == USB_SPEED_FULL)
3694 urb->start_frame = start_frame;
3696 urb->start_frame = start_frame << 3;
3702 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3703 start_frame, current_frame_id, index,
3704 start_frame_id, end_frame_id);
3705 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3712 /* This is for isoc transfer */
3713 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3714 struct urb *urb, int slot_id, unsigned int ep_index)
3716 struct xhci_ring *ep_ring;
3717 struct urb_priv *urb_priv;
3719 int num_tds, trbs_per_td;
3720 struct xhci_generic_trb *start_trb;
3723 u32 field, length_field;
3724 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3725 u64 start_addr, addr;
3727 bool more_trbs_coming;
3728 struct xhci_virt_ep *xep;
3730 xep = &xhci->devs[slot_id]->eps[ep_index];
3731 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3733 num_tds = urb->number_of_packets;
3735 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3739 start_addr = (u64) urb->transfer_dma;
3740 start_trb = &ep_ring->enqueue->generic;
3741 start_cycle = ep_ring->cycle_state;
3743 urb_priv = urb->hcpriv;
3744 /* Queue the first TRB, even if it's zero-length */
3745 for (i = 0; i < num_tds; i++) {
3746 unsigned int total_packet_count;
3747 unsigned int burst_count;
3748 unsigned int residue;
3752 addr = start_addr + urb->iso_frame_desc[i].offset;
3753 td_len = urb->iso_frame_desc[i].length;
3754 td_remain_len = td_len;
3755 total_packet_count = DIV_ROUND_UP(td_len,
3757 usb_endpoint_maxp(&urb->ep->desc)));
3758 /* A zero-length transfer still involves at least one packet. */
3759 if (total_packet_count == 0)
3760 total_packet_count++;
3761 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3762 total_packet_count);
3763 residue = xhci_get_last_burst_packet_count(xhci,
3764 urb->dev, urb, total_packet_count);
3766 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3768 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3769 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3776 td = urb_priv->td[i];
3777 for (j = 0; j < trbs_per_td; j++) {
3783 field = TRB_TBC(burst_count) |
3785 /* Queue the isoc TRB */
3786 field |= TRB_TYPE(TRB_ISOC);
3788 /* Calculate Frame ID and SIA fields */
3789 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3790 HCC_CFC(xhci->hcc_params)) {
3791 frame_id = xhci_get_isoc_frame_id(xhci,
3795 field |= TRB_FRAME_ID(frame_id);
3802 if (start_cycle == 0)
3805 field |= ep_ring->cycle_state;
3808 /* Queue other normal TRBs */
3809 field |= TRB_TYPE(TRB_NORMAL);
3810 field |= ep_ring->cycle_state;
3813 /* Only set interrupt on short packet for IN EPs */
3814 if (usb_urb_dir_in(urb))
3817 /* Chain all the TRBs together; clear the chain bit in
3818 * the last TRB to indicate it's the last TRB in the
3821 if (j < trbs_per_td - 1) {
3823 more_trbs_coming = true;
3825 td->last_trb = ep_ring->enqueue;
3827 if (xhci->hci_version == 0x100 &&
3830 /* Set BEI bit except for the last td */
3831 if (i < num_tds - 1)
3834 more_trbs_coming = false;
3837 /* Calculate TRB length */
3838 trb_buff_len = TRB_MAX_BUFF_SIZE -
3839 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3840 if (trb_buff_len > td_remain_len)
3841 trb_buff_len = td_remain_len;
3843 /* Set the TRB length, TD size, & interrupter fields. */
3844 remainder = xhci_td_remainder(xhci, running_total,
3845 trb_buff_len, td_len,
3846 urb, trbs_per_td - j - 1);
3848 length_field = TRB_LEN(trb_buff_len) |
3849 TRB_TD_SIZE(remainder) |
3852 queue_trb(xhci, ep_ring, more_trbs_coming,
3853 lower_32_bits(addr),
3854 upper_32_bits(addr),
3857 running_total += trb_buff_len;
3859 addr += trb_buff_len;
3860 td_remain_len -= trb_buff_len;
3863 /* Check TD length */
3864 if (running_total != td_len) {
3865 xhci_err(xhci, "ISOC TD length unmatch\n");
3871 /* store the next frame id */
3872 if (HCC_CFC(xhci->hcc_params))
3873 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3875 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3876 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3877 usb_amd_quirk_pll_disable();
3879 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3881 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3882 start_cycle, start_trb);
3885 /* Clean up a partially enqueued isoc transfer. */
3887 for (i--; i >= 0; i--)
3888 list_del_init(&urb_priv->td[i]->td_list);
3890 /* Use the first TD as a temporary variable to turn the TDs we've queued
3891 * into No-ops with a software-owned cycle bit. That way the hardware
3892 * won't accidentally start executing bogus TDs when we partially
3893 * overwrite them. td->first_trb and td->start_seg are already set.
3895 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3896 /* Every TRB except the first & last will have its cycle bit flipped. */
3897 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3899 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3900 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3901 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3902 ep_ring->cycle_state = start_cycle;
3903 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3904 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3909 * Check transfer ring to guarantee there is enough room for the urb.
3910 * Update ISO URB start_frame and interval.
3911 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3912 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3913 * Contiguous Frame ID is not supported by HC.
3915 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3916 struct urb *urb, int slot_id, unsigned int ep_index)
3918 struct xhci_virt_device *xdev;
3919 struct xhci_ring *ep_ring;
3920 struct xhci_ep_ctx *ep_ctx;
3924 int num_tds, num_trbs, i;
3926 struct xhci_virt_ep *xep;
3929 xdev = xhci->devs[slot_id];
3930 xep = &xhci->devs[slot_id]->eps[ep_index];
3931 ep_ring = xdev->eps[ep_index].ring;
3932 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3935 num_tds = urb->number_of_packets;
3936 for (i = 0; i < num_tds; i++)
3937 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3939 /* Check the ring to guarantee there is enough room for the whole urb.
3940 * Do not insert any td of the urb to the ring if the check failed.
3942 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3943 num_trbs, mem_flags);
3948 * Check interval value. This should be done before we start to
3949 * calculate the start frame value.
3951 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3952 ep_interval = urb->interval;
3953 /* Convert to microframes */
3954 if (urb->dev->speed == USB_SPEED_LOW ||
3955 urb->dev->speed == USB_SPEED_FULL)
3957 /* FIXME change this to a warning and a suggestion to use the new API
3958 * to set the polling interval (once the API is added).
3960 if (xhci_interval != ep_interval) {
3961 dev_dbg_ratelimited(&urb->dev->dev,
3962 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3963 ep_interval, ep_interval == 1 ? "" : "s",
3964 xhci_interval, xhci_interval == 1 ? "" : "s");
3965 urb->interval = xhci_interval;
3966 /* Convert back to frames for LS/FS devices */
3967 if (urb->dev->speed == USB_SPEED_LOW ||
3968 urb->dev->speed == USB_SPEED_FULL)
3972 /* Calculate the start frame and put it in urb->start_frame. */
3973 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3974 if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
3976 urb->start_frame = xep->next_frame_id;
3977 goto skip_start_over;
3981 start_frame = readl(&xhci->run_regs->microframe_index);
3982 start_frame &= 0x3fff;
3984 * Round up to the next frame and consider the time before trb really
3985 * gets scheduled by hardare.
3987 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3988 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3990 start_frame += ist + XHCI_CFC_DELAY;
3991 start_frame = roundup(start_frame, 8);
3994 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
3995 * is greate than 8 microframes.
3997 if (urb->dev->speed == USB_SPEED_LOW ||
3998 urb->dev->speed == USB_SPEED_FULL) {
3999 start_frame = roundup(start_frame, urb->interval << 3);
4000 urb->start_frame = start_frame >> 3;
4002 start_frame = roundup(start_frame, urb->interval);
4003 urb->start_frame = start_frame;
4007 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4009 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4012 /**** Command Ring Operations ****/
4014 /* Generic function for queueing a command TRB on the command ring.
4015 * Check to make sure there's room on the command ring for one command TRB.
4016 * Also check that there's room reserved for commands that must not fail.
4017 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4018 * then only check for the number of reserved spots.
4019 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4020 * because the command event handler may want to resubmit a failed command.
4022 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4023 u32 field1, u32 field2,
4024 u32 field3, u32 field4, bool command_must_succeed)
4026 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4029 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4030 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4031 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4035 if (!command_must_succeed)
4038 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4039 reserved_trbs, GFP_ATOMIC);
4041 xhci_err(xhci, "ERR: No room for command on command ring\n");
4042 if (command_must_succeed)
4043 xhci_err(xhci, "ERR: Reserved TRB counting for "
4044 "unfailable commands failed.\n");
4048 cmd->command_trb = xhci->cmd_ring->enqueue;
4049 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4051 /* if there are no other commands queued we start the timeout timer */
4052 if (xhci->cmd_list.next == &cmd->cmd_list &&
4053 !timer_pending(&xhci->cmd_timer)) {
4054 xhci->current_cmd = cmd;
4055 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
4058 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4059 field4 | xhci->cmd_ring->cycle_state);
4063 /* Queue a slot enable or disable request on the command ring */
4064 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4065 u32 trb_type, u32 slot_id)
4067 return queue_command(xhci, cmd, 0, 0, 0,
4068 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4071 /* Queue an address device command TRB */
4072 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4073 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4075 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4076 upper_32_bits(in_ctx_ptr), 0,
4077 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4078 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4081 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4082 u32 field1, u32 field2, u32 field3, u32 field4)
4084 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4087 /* Queue a reset device command TRB */
4088 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4091 return queue_command(xhci, cmd, 0, 0, 0,
4092 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4096 /* Queue a configure endpoint command TRB */
4097 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4098 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4099 u32 slot_id, bool command_must_succeed)
4101 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4102 upper_32_bits(in_ctx_ptr), 0,
4103 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4104 command_must_succeed);
4107 /* Queue an evaluate context command TRB */
4108 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4109 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4111 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4112 upper_32_bits(in_ctx_ptr), 0,
4113 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4114 command_must_succeed);
4118 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4119 * activity on an endpoint that is about to be suspended.
4121 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4122 int slot_id, unsigned int ep_index, int suspend)
4124 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4125 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4126 u32 type = TRB_TYPE(TRB_STOP_RING);
4127 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4129 return queue_command(xhci, cmd, 0, 0, 0,
4130 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4133 /* Set Transfer Ring Dequeue Pointer command */
4134 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4135 unsigned int slot_id, unsigned int ep_index,
4136 unsigned int stream_id,
4137 struct xhci_dequeue_state *deq_state)
4140 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4141 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4142 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4144 u32 type = TRB_TYPE(TRB_SET_DEQ);
4145 struct xhci_virt_ep *ep;
4146 struct xhci_command *cmd;
4149 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4150 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4151 deq_state->new_deq_seg,
4152 (unsigned long long)deq_state->new_deq_seg->dma,
4153 deq_state->new_deq_ptr,
4154 (unsigned long long)xhci_trb_virt_to_dma(
4155 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4156 deq_state->new_cycle_state);
4158 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4159 deq_state->new_deq_ptr);
4161 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4162 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4163 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4166 ep = &xhci->devs[slot_id]->eps[ep_index];
4167 if ((ep->ep_state & SET_DEQ_PENDING)) {
4168 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4169 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4173 /* This function gets called from contexts where it cannot sleep */
4174 cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
4176 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n");
4180 ep->queued_deq_seg = deq_state->new_deq_seg;
4181 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4183 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4184 ret = queue_command(xhci, cmd,
4185 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4186 upper_32_bits(addr), trb_stream_id,
4187 trb_slot_id | trb_ep_index | type, false);
4189 xhci_free_command(xhci, cmd);
4193 /* Stop the TD queueing code from ringing the doorbell until
4194 * this command completes. The HC won't set the dequeue pointer
4195 * if the ring is running, and ringing the doorbell starts the
4198 ep->ep_state |= SET_DEQ_PENDING;
4201 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4202 int slot_id, unsigned int ep_index)
4204 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4205 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4206 u32 type = TRB_TYPE(TRB_RESET_EP);
4208 return queue_command(xhci, cmd, 0, 0, 0,
4209 trb_slot_id | trb_ep_index | type, false);