2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/irq.h>
25 #include <linux/log2.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/slab.h>
29 #include <linux/dmi.h>
32 #include "xhci-trace.h"
34 #define DRIVER_AUTHOR "Sarah Sharp"
35 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
37 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
38 static int link_quirk;
39 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
40 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
42 /* TODO: copied from ehci-hcd.c - can this be refactored? */
44 * xhci_handshake - spin reading hc until handshake completes or fails
45 * @ptr: address of hc register to be read
46 * @mask: bits to look at in result of read
47 * @done: value of those bits when handshake succeeds
48 * @usec: timeout in microseconds
50 * Returns negative errno, or zero on success
52 * Success happens when the "mask" bits have the specified value (hardware
53 * handshake done). There are two failure modes: "usec" have passed (major
54 * hardware flakeout), or the register reads as all-ones (hardware removed).
56 int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
57 u32 mask, u32 done, int usec)
62 result = xhci_readl(xhci, ptr);
63 if (result == ~(u32)0) /* card removed */
75 * Disable interrupts and begin the xHCI halting process.
77 void xhci_quiesce(struct xhci_hcd *xhci)
84 halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
88 cmd = xhci_readl(xhci, &xhci->op_regs->command);
90 xhci_writel(xhci, cmd, &xhci->op_regs->command);
94 * Force HC into halt state.
96 * Disable any IRQs and clear the run/stop bit.
97 * HC will complete any current and actively pipelined transactions, and
98 * should halt within 16 ms of the run/stop bit being cleared.
99 * Read HC Halted bit in the status register to see when the HC is finished.
101 int xhci_halt(struct xhci_hcd *xhci)
104 xhci_dbg(xhci, "// Halt the HC\n");
107 ret = xhci_handshake(xhci, &xhci->op_regs->status,
108 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
110 xhci->xhc_state |= XHCI_STATE_HALTED;
111 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
113 xhci_warn(xhci, "Host not halted after %u microseconds.\n",
119 * Set the run bit and wait for the host to be running.
121 static int xhci_start(struct xhci_hcd *xhci)
126 temp = xhci_readl(xhci, &xhci->op_regs->command);
128 xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
130 xhci_writel(xhci, temp, &xhci->op_regs->command);
133 * Wait for the HCHalted Status bit to be 0 to indicate the host is
136 ret = xhci_handshake(xhci, &xhci->op_regs->status,
137 STS_HALT, 0, XHCI_MAX_HALT_USEC);
138 if (ret == -ETIMEDOUT)
139 xhci_err(xhci, "Host took too long to start, "
140 "waited %u microseconds.\n",
143 xhci->xhc_state &= ~XHCI_STATE_HALTED;
150 * This resets pipelines, timers, counters, state machines, etc.
151 * Transactions will be terminated immediately, and operational registers
152 * will be set to their defaults.
154 int xhci_reset(struct xhci_hcd *xhci)
160 state = xhci_readl(xhci, &xhci->op_regs->status);
161 if ((state & STS_HALT) == 0) {
162 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
166 xhci_dbg(xhci, "// Reset the HC\n");
167 command = xhci_readl(xhci, &xhci->op_regs->command);
168 command |= CMD_RESET;
169 xhci_writel(xhci, command, &xhci->op_regs->command);
171 ret = xhci_handshake(xhci, &xhci->op_regs->command,
172 CMD_RESET, 0, 10 * 1000 * 1000);
176 xhci_dbg(xhci, "Wait for controller to be ready for doorbell rings\n");
178 * xHCI cannot write to any doorbells or operational registers other
179 * than status until the "Controller Not Ready" flag is cleared.
181 ret = xhci_handshake(xhci, &xhci->op_regs->status,
182 STS_CNR, 0, 10 * 1000 * 1000);
184 for (i = 0; i < 2; ++i) {
185 xhci->bus_state[i].port_c_suspend = 0;
186 xhci->bus_state[i].suspended_ports = 0;
187 xhci->bus_state[i].resuming_ports = 0;
194 static int xhci_free_msi(struct xhci_hcd *xhci)
198 if (!xhci->msix_entries)
201 for (i = 0; i < xhci->msix_count; i++)
202 if (xhci->msix_entries[i].vector)
203 free_irq(xhci->msix_entries[i].vector,
211 static int xhci_setup_msi(struct xhci_hcd *xhci)
214 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
216 ret = pci_enable_msi(pdev);
218 xhci_dbg(xhci, "failed to allocate MSI entry\n");
222 ret = request_irq(pdev->irq, xhci_msi_irq,
223 0, "xhci_hcd", xhci_to_hcd(xhci));
225 xhci_dbg(xhci, "disable MSI interrupt\n");
226 pci_disable_msi(pdev);
234 * free all IRQs request
236 static void xhci_free_irq(struct xhci_hcd *xhci)
238 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
241 /* return if using legacy interrupt */
242 if (xhci_to_hcd(xhci)->irq > 0)
245 ret = xhci_free_msi(xhci);
249 free_irq(pdev->irq, xhci_to_hcd(xhci));
257 static int xhci_setup_msix(struct xhci_hcd *xhci)
260 struct usb_hcd *hcd = xhci_to_hcd(xhci);
261 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
264 * calculate number of msi-x vectors supported.
265 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
266 * with max number of interrupters based on the xhci HCSPARAMS1.
267 * - num_online_cpus: maximum msi-x vectors per CPUs core.
268 * Add additional 1 vector to ensure always available interrupt.
270 xhci->msix_count = min(num_online_cpus() + 1,
271 HCS_MAX_INTRS(xhci->hcs_params1));
274 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
276 if (!xhci->msix_entries) {
277 xhci_err(xhci, "Failed to allocate MSI-X entries\n");
281 for (i = 0; i < xhci->msix_count; i++) {
282 xhci->msix_entries[i].entry = i;
283 xhci->msix_entries[i].vector = 0;
286 ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
288 xhci_dbg(xhci, "Failed to enable MSI-X\n");
292 for (i = 0; i < xhci->msix_count; i++) {
293 ret = request_irq(xhci->msix_entries[i].vector,
295 0, "xhci_hcd", xhci_to_hcd(xhci));
300 hcd->msix_enabled = 1;
304 xhci_dbg(xhci, "disable MSI-X interrupt\n");
306 pci_disable_msix(pdev);
308 kfree(xhci->msix_entries);
309 xhci->msix_entries = NULL;
313 /* Free any IRQs and disable MSI-X */
314 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
316 struct usb_hcd *hcd = xhci_to_hcd(xhci);
317 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
321 if (xhci->msix_entries) {
322 pci_disable_msix(pdev);
323 kfree(xhci->msix_entries);
324 xhci->msix_entries = NULL;
326 pci_disable_msi(pdev);
329 hcd->msix_enabled = 0;
333 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
337 if (xhci->msix_entries) {
338 for (i = 0; i < xhci->msix_count; i++)
339 synchronize_irq(xhci->msix_entries[i].vector);
343 static int xhci_try_enable_msi(struct usb_hcd *hcd)
345 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
346 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
350 * Some Fresco Logic host controllers advertise MSI, but fail to
351 * generate interrupts. Don't even try to enable MSI.
353 if (xhci->quirks & XHCI_BROKEN_MSI)
356 /* unregister the legacy interrupt */
358 free_irq(hcd->irq, hcd);
361 ret = xhci_setup_msix(xhci);
363 /* fall back to msi*/
364 ret = xhci_setup_msi(xhci);
367 /* hcd->irq is 0, we have MSI */
371 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
376 /* fall back to legacy interrupt*/
377 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
378 hcd->irq_descr, hcd);
380 xhci_err(xhci, "request interrupt %d failed\n",
384 hcd->irq = pdev->irq;
390 static int xhci_try_enable_msi(struct usb_hcd *hcd)
395 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
399 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
405 static void compliance_mode_recovery(unsigned long arg)
407 struct xhci_hcd *xhci;
412 xhci = (struct xhci_hcd *)arg;
414 for (i = 0; i < xhci->num_usb3_ports; i++) {
415 temp = xhci_readl(xhci, xhci->usb3_ports[i]);
416 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
418 * Compliance Mode Detected. Letting USB Core
419 * handle the Warm Reset
421 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
422 "Compliance mode detected->port %d",
424 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
425 "Attempting compliance mode recovery");
426 hcd = xhci->shared_hcd;
428 if (hcd->state == HC_STATE_SUSPENDED)
429 usb_hcd_resume_root_hub(hcd);
431 usb_hcd_poll_rh_status(hcd);
435 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
436 mod_timer(&xhci->comp_mode_recovery_timer,
437 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
441 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
442 * that causes ports behind that hardware to enter compliance mode sometimes.
443 * The quirk creates a timer that polls every 2 seconds the link state of
444 * each host controller's port and recovers it by issuing a Warm reset
445 * if Compliance mode is detected, otherwise the port will become "dead" (no
446 * device connections or disconnections will be detected anymore). Becasue no
447 * status event is generated when entering compliance mode (per xhci spec),
448 * this quirk is needed on systems that have the failing hardware installed.
450 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
452 xhci->port_status_u0 = 0;
453 init_timer(&xhci->comp_mode_recovery_timer);
455 xhci->comp_mode_recovery_timer.data = (unsigned long) xhci;
456 xhci->comp_mode_recovery_timer.function = compliance_mode_recovery;
457 xhci->comp_mode_recovery_timer.expires = jiffies +
458 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
460 set_timer_slack(&xhci->comp_mode_recovery_timer,
461 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
462 add_timer(&xhci->comp_mode_recovery_timer);
463 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
464 "Compliance mode recovery timer initialized");
468 * This function identifies the systems that have installed the SN65LVPE502CP
469 * USB3.0 re-driver and that need the Compliance Mode Quirk.
471 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
473 bool xhci_compliance_mode_recovery_timer_quirk_check(void)
475 const char *dmi_product_name, *dmi_sys_vendor;
477 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
478 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
479 if (!dmi_product_name || !dmi_sys_vendor)
482 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
485 if (strstr(dmi_product_name, "Z420") ||
486 strstr(dmi_product_name, "Z620") ||
487 strstr(dmi_product_name, "Z820") ||
488 strstr(dmi_product_name, "Z1 Workstation"))
494 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
496 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
501 * Initialize memory for HCD and xHC (one-time init).
503 * Program the PAGESIZE register, initialize the device context array, create
504 * device contexts (?), set up a command ring segment (or two?), create event
505 * ring (one for now).
507 int xhci_init(struct usb_hcd *hcd)
509 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
512 xhci_dbg(xhci, "xhci_init\n");
513 spin_lock_init(&xhci->lock);
514 if (xhci->hci_version == 0x95 && link_quirk) {
515 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
516 "QUIRK: Not clearing Link TRB chain bits.");
517 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
519 xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
521 retval = xhci_mem_init(xhci, GFP_KERNEL);
522 xhci_dbg(xhci, "Finished xhci_init\n");
524 /* Initializing Compliance Mode Recovery Data If Needed */
525 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
526 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
527 compliance_mode_recovery_timer_init(xhci);
533 /*-------------------------------------------------------------------------*/
536 static int xhci_run_finished(struct xhci_hcd *xhci)
538 if (xhci_start(xhci)) {
542 xhci->shared_hcd->state = HC_STATE_RUNNING;
543 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
545 if (xhci->quirks & XHCI_NEC_HOST)
546 xhci_ring_cmd_db(xhci);
548 xhci_dbg(xhci, "Finished xhci_run for USB3 roothub\n");
553 * Start the HC after it was halted.
555 * This function is called by the USB core when the HC driver is added.
556 * Its opposite is xhci_stop().
558 * xhci_init() must be called once before this function can be called.
559 * Reset the HC, enable device slot contexts, program DCBAAP, and
560 * set command ring pointer and event ring pointer.
562 * Setup MSI-X vectors and enable interrupts.
564 int xhci_run(struct usb_hcd *hcd)
569 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
571 /* Start the xHCI host controller running only after the USB 2.0 roothub
575 hcd->uses_new_polling = 1;
576 if (!usb_hcd_is_primary_hcd(hcd))
577 return xhci_run_finished(xhci);
579 xhci_dbg(xhci, "xhci_run\n");
581 ret = xhci_try_enable_msi(hcd);
585 xhci_dbg(xhci, "Command ring memory map follows:\n");
586 xhci_debug_ring(xhci, xhci->cmd_ring);
587 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
588 xhci_dbg_cmd_ptrs(xhci);
590 xhci_dbg(xhci, "ERST memory map follows:\n");
591 xhci_dbg_erst(xhci, &xhci->erst);
592 xhci_dbg(xhci, "Event ring:\n");
593 xhci_debug_ring(xhci, xhci->event_ring);
594 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
595 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
596 temp_64 &= ~ERST_PTR_MASK;
597 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
599 xhci_dbg(xhci, "// Set the interrupt modulation register\n");
600 temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
601 temp &= ~ER_IRQ_INTERVAL_MASK;
603 xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
605 /* Set the HCD state before we enable the irqs */
606 temp = xhci_readl(xhci, &xhci->op_regs->command);
608 xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
610 xhci_writel(xhci, temp, &xhci->op_regs->command);
612 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
613 xhci_dbg(xhci, "// Enabling event ring interrupter %p by writing 0x%x to irq_pending\n",
614 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
615 xhci_writel(xhci, ER_IRQ_ENABLE(temp),
616 &xhci->ir_set->irq_pending);
617 xhci_print_ir_set(xhci, 0);
619 if (xhci->quirks & XHCI_NEC_HOST)
620 xhci_queue_vendor_command(xhci, 0, 0, 0,
621 TRB_TYPE(TRB_NEC_GET_FW));
623 xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n");
627 static void xhci_only_stop_hcd(struct usb_hcd *hcd)
629 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
631 spin_lock_irq(&xhci->lock);
634 /* The shared_hcd is going to be deallocated shortly (the USB core only
635 * calls this function when allocation fails in usb_add_hcd(), or
636 * usb_remove_hcd() is called). So we need to unset xHCI's pointer.
638 xhci->shared_hcd = NULL;
639 spin_unlock_irq(&xhci->lock);
645 * This function is called by the USB core when the HC driver is removed.
646 * Its opposite is xhci_run().
648 * Disable device contexts, disable IRQs, and quiesce the HC.
649 * Reset the HC, finish any completed transactions, and cleanup memory.
651 void xhci_stop(struct usb_hcd *hcd)
654 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
656 if (!usb_hcd_is_primary_hcd(hcd)) {
657 xhci_only_stop_hcd(xhci->shared_hcd);
661 spin_lock_irq(&xhci->lock);
662 /* Make sure the xHC is halted for a USB3 roothub
663 * (xhci_stop() could be called as part of failed init).
667 spin_unlock_irq(&xhci->lock);
669 xhci_cleanup_msix(xhci);
671 /* Deleting Compliance Mode Recovery Timer */
672 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
673 (!(xhci_all_ports_seen_u0(xhci)))) {
674 del_timer_sync(&xhci->comp_mode_recovery_timer);
675 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
676 "%s: compliance mode recovery timer deleted",
680 if (xhci->quirks & XHCI_AMD_PLL_FIX)
683 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
684 temp = xhci_readl(xhci, &xhci->op_regs->status);
685 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
686 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
687 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
688 &xhci->ir_set->irq_pending);
689 xhci_print_ir_set(xhci, 0);
691 xhci_dbg(xhci, "cleaning up memory\n");
692 xhci_mem_cleanup(xhci);
693 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
694 xhci_readl(xhci, &xhci->op_regs->status));
698 * Shutdown HC (not bus-specific)
700 * This is called when the machine is rebooting or halting. We assume that the
701 * machine will be powered off, and the HC's internal state will be reset.
702 * Don't bother to free memory.
704 * This will only ever be called with the main usb_hcd (the USB3 roothub).
706 void xhci_shutdown(struct usb_hcd *hcd)
708 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
710 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
711 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
713 spin_lock_irq(&xhci->lock);
715 spin_unlock_irq(&xhci->lock);
717 xhci_cleanup_msix(xhci);
719 xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
720 xhci_readl(xhci, &xhci->op_regs->status));
724 static void xhci_save_registers(struct xhci_hcd *xhci)
726 xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command);
727 xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification);
728 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
729 xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg);
730 xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size);
731 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
732 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
733 xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
734 xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control);
737 static void xhci_restore_registers(struct xhci_hcd *xhci)
739 xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command);
740 xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
741 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
742 xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg);
743 xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size);
744 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
745 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
746 xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
747 xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control);
750 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
754 /* step 2: initialize command ring buffer */
755 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
756 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
757 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
758 xhci->cmd_ring->dequeue) &
759 (u64) ~CMD_RING_RSVD_BITS) |
760 xhci->cmd_ring->cycle_state;
761 xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n",
762 (long unsigned long) val_64);
763 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
767 * The whole command ring must be cleared to zero when we suspend the host.
769 * The host doesn't save the command ring pointer in the suspend well, so we
770 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
771 * aligned, because of the reserved bits in the command ring dequeue pointer
772 * register. Therefore, we can't just set the dequeue pointer back in the
773 * middle of the ring (TRBs are 16-byte aligned).
775 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
777 struct xhci_ring *ring;
778 struct xhci_segment *seg;
780 ring = xhci->cmd_ring;
784 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
785 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
786 cpu_to_le32(~TRB_CYCLE);
788 } while (seg != ring->deq_seg);
790 /* Reset the software enqueue and dequeue pointers */
791 ring->deq_seg = ring->first_seg;
792 ring->dequeue = ring->first_seg->trbs;
793 ring->enq_seg = ring->deq_seg;
794 ring->enqueue = ring->dequeue;
796 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
798 * Ring is now zeroed, so the HW should look for change of ownership
799 * when the cycle bit is set to 1.
801 ring->cycle_state = 1;
804 * Reset the hardware dequeue pointer.
805 * Yes, this will need to be re-written after resume, but we're paranoid
806 * and want to make sure the hardware doesn't access bogus memory
807 * because, say, the BIOS or an SMI started the host without changing
808 * the command ring pointers.
810 xhci_set_cmd_ring_deq(xhci);
814 * Stop HC (not bus-specific)
816 * This is called when the machine transition into S3/S4 mode.
819 int xhci_suspend(struct xhci_hcd *xhci)
822 struct usb_hcd *hcd = xhci_to_hcd(xhci);
825 if (hcd->state != HC_STATE_SUSPENDED ||
826 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
829 /* Don't poll the roothubs on bus suspend. */
830 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
831 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
832 del_timer_sync(&hcd->rh_timer);
834 spin_lock_irq(&xhci->lock);
835 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
836 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
837 /* step 1: stop endpoint */
838 /* skipped assuming that port suspend has done */
840 /* step 2: clear Run/Stop bit */
841 command = xhci_readl(xhci, &xhci->op_regs->command);
843 xhci_writel(xhci, command, &xhci->op_regs->command);
844 if (xhci_handshake(xhci, &xhci->op_regs->status,
845 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC)) {
846 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
847 spin_unlock_irq(&xhci->lock);
850 xhci_clear_command_ring(xhci);
852 /* step 3: save registers */
853 xhci_save_registers(xhci);
855 /* step 4: set CSS flag */
856 command = xhci_readl(xhci, &xhci->op_regs->command);
858 xhci_writel(xhci, command, &xhci->op_regs->command);
859 if (xhci_handshake(xhci, &xhci->op_regs->status,
860 STS_SAVE, 0, 10 * 1000)) {
861 xhci_warn(xhci, "WARN: xHC save state timeout\n");
862 spin_unlock_irq(&xhci->lock);
865 spin_unlock_irq(&xhci->lock);
868 * Deleting Compliance Mode Recovery Timer because the xHCI Host
869 * is about to be suspended.
871 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
872 (!(xhci_all_ports_seen_u0(xhci)))) {
873 del_timer_sync(&xhci->comp_mode_recovery_timer);
874 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
875 "%s: compliance mode recovery timer deleted",
879 /* step 5: remove core well power */
880 /* synchronize irq when using MSI-X */
881 xhci_msix_sync_irqs(xhci);
887 * start xHC (not bus-specific)
889 * This is called when the machine transition from S3/S4 mode.
892 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
894 u32 command, temp = 0;
895 struct usb_hcd *hcd = xhci_to_hcd(xhci);
896 struct usb_hcd *secondary_hcd;
898 bool comp_timer_running = false;
900 /* Wait a bit if either of the roothubs need to settle from the
901 * transition into bus suspend.
903 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
905 xhci->bus_state[1].next_statechange))
908 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
909 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
911 spin_lock_irq(&xhci->lock);
912 if (xhci->quirks & XHCI_RESET_ON_RESUME)
916 /* step 1: restore register */
917 xhci_restore_registers(xhci);
918 /* step 2: initialize command ring buffer */
919 xhci_set_cmd_ring_deq(xhci);
920 /* step 3: restore state and start state*/
921 /* step 3: set CRS flag */
922 command = xhci_readl(xhci, &xhci->op_regs->command);
924 xhci_writel(xhci, command, &xhci->op_regs->command);
925 if (xhci_handshake(xhci, &xhci->op_regs->status,
926 STS_RESTORE, 0, 10 * 1000)) {
927 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
928 spin_unlock_irq(&xhci->lock);
931 temp = xhci_readl(xhci, &xhci->op_regs->status);
934 /* If restore operation fails, re-initialize the HC during resume */
935 if ((temp & STS_SRE) || hibernated) {
937 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
938 !(xhci_all_ports_seen_u0(xhci))) {
939 del_timer_sync(&xhci->comp_mode_recovery_timer);
940 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
941 "Compliance Mode Recovery Timer deleted!");
944 /* Let the USB core know _both_ roothubs lost power. */
945 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
946 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
948 xhci_dbg(xhci, "Stop HCD\n");
951 spin_unlock_irq(&xhci->lock);
952 xhci_cleanup_msix(xhci);
954 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
955 temp = xhci_readl(xhci, &xhci->op_regs->status);
956 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
957 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
958 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
959 &xhci->ir_set->irq_pending);
960 xhci_print_ir_set(xhci, 0);
962 xhci_dbg(xhci, "cleaning up memory\n");
963 xhci_mem_cleanup(xhci);
964 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
965 xhci_readl(xhci, &xhci->op_regs->status));
967 /* USB core calls the PCI reinit and start functions twice:
968 * first with the primary HCD, and then with the secondary HCD.
969 * If we don't do the same, the host will never be started.
971 if (!usb_hcd_is_primary_hcd(hcd))
974 secondary_hcd = xhci->shared_hcd;
976 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
977 retval = xhci_init(hcd->primary_hcd);
980 comp_timer_running = true;
982 xhci_dbg(xhci, "Start the primary HCD\n");
983 retval = xhci_run(hcd->primary_hcd);
985 xhci_dbg(xhci, "Start the secondary HCD\n");
986 retval = xhci_run(secondary_hcd);
988 hcd->state = HC_STATE_SUSPENDED;
989 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
993 /* step 4: set Run/Stop bit */
994 command = xhci_readl(xhci, &xhci->op_regs->command);
996 xhci_writel(xhci, command, &xhci->op_regs->command);
997 xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT,
1000 /* step 5: walk topology and initialize portsc,
1001 * portpmsc and portli
1003 /* this is done in bus_resume */
1005 /* step 6: restart each of the previously
1006 * Running endpoints by ringing their doorbells
1009 spin_unlock_irq(&xhci->lock);
1013 usb_hcd_resume_root_hub(hcd);
1014 usb_hcd_resume_root_hub(xhci->shared_hcd);
1018 * If system is subject to the Quirk, Compliance Mode Timer needs to
1019 * be re-initialized Always after a system resume. Ports are subject
1020 * to suffer the Compliance Mode issue again. It doesn't matter if
1021 * ports have entered previously to U0 before system's suspension.
1023 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1024 compliance_mode_recovery_timer_init(xhci);
1026 /* Re-enable port polling. */
1027 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1028 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1029 usb_hcd_poll_rh_status(hcd);
1033 #endif /* CONFIG_PM */
1035 /*-------------------------------------------------------------------------*/
1038 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1039 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1040 * value to right shift 1 for the bitmask.
1042 * Index = (epnum * 2) + direction - 1,
1043 * where direction = 0 for OUT, 1 for IN.
1044 * For control endpoints, the IN index is used (OUT index is unused), so
1045 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1047 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1050 if (usb_endpoint_xfer_control(desc))
1051 index = (unsigned int) (usb_endpoint_num(desc)*2);
1053 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1054 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1058 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1059 * address from the XHCI endpoint index.
1061 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1063 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1064 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1065 return direction | number;
1068 /* Find the flag for this endpoint (for use in the control context). Use the
1069 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1072 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1074 return 1 << (xhci_get_endpoint_index(desc) + 1);
1077 /* Find the flag for this endpoint (for use in the control context). Use the
1078 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1081 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1083 return 1 << (ep_index + 1);
1086 /* Compute the last valid endpoint context index. Basically, this is the
1087 * endpoint index plus one. For slot contexts with more than valid endpoint,
1088 * we find the most significant bit set in the added contexts flags.
1089 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1090 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1092 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1094 return fls(added_ctxs) - 1;
1097 /* Returns 1 if the arguments are OK;
1098 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1100 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1101 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1103 struct xhci_hcd *xhci;
1104 struct xhci_virt_device *virt_dev;
1106 if (!hcd || (check_ep && !ep) || !udev) {
1107 pr_debug("xHCI %s called with invalid args\n", func);
1110 if (!udev->parent) {
1111 pr_debug("xHCI %s called for root hub\n", func);
1115 xhci = hcd_to_xhci(hcd);
1116 if (check_virt_dev) {
1117 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1118 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1123 virt_dev = xhci->devs[udev->slot_id];
1124 if (virt_dev->udev != udev) {
1125 xhci_dbg(xhci, "xHCI %s called with udev and "
1126 "virt_dev does not match\n", func);
1131 if (xhci->xhc_state & XHCI_STATE_HALTED)
1137 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1138 struct usb_device *udev, struct xhci_command *command,
1139 bool ctx_change, bool must_succeed);
1142 * Full speed devices may have a max packet size greater than 8 bytes, but the
1143 * USB core doesn't know that until it reads the first 8 bytes of the
1144 * descriptor. If the usb_device's max packet size changes after that point,
1145 * we need to issue an evaluate context command and wait on it.
1147 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1148 unsigned int ep_index, struct urb *urb)
1150 struct xhci_container_ctx *in_ctx;
1151 struct xhci_container_ctx *out_ctx;
1152 struct xhci_input_control_ctx *ctrl_ctx;
1153 struct xhci_ep_ctx *ep_ctx;
1154 int max_packet_size;
1155 int hw_max_packet_size;
1158 out_ctx = xhci->devs[slot_id]->out_ctx;
1159 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1160 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1161 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1162 if (hw_max_packet_size != max_packet_size) {
1163 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1164 "Max Packet Size for ep 0 changed.");
1165 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1166 "Max packet size in usb_device = %d",
1168 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1169 "Max packet size in xHCI HW = %d",
1170 hw_max_packet_size);
1171 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1172 "Issuing evaluate context command.");
1174 /* Set up the input context flags for the command */
1175 /* FIXME: This won't work if a non-default control endpoint
1176 * changes max packet sizes.
1178 in_ctx = xhci->devs[slot_id]->in_ctx;
1179 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1181 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1185 /* Set up the modified control endpoint 0 */
1186 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1187 xhci->devs[slot_id]->out_ctx, ep_index);
1189 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1190 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1191 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1193 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1194 ctrl_ctx->drop_flags = 0;
1196 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1197 xhci_dbg_ctx(xhci, in_ctx, ep_index);
1198 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1199 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1201 ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
1204 /* Clean up the input context for later use by bandwidth
1207 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1213 * non-error returns are a promise to giveback() the urb later
1214 * we drop ownership so next owner (or urb unlink) can get it
1216 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1218 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1219 struct xhci_td *buffer;
1220 unsigned long flags;
1222 unsigned int slot_id, ep_index;
1223 struct urb_priv *urb_priv;
1226 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1227 true, true, __func__) <= 0)
1230 slot_id = urb->dev->slot_id;
1231 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1233 if (!HCD_HW_ACCESSIBLE(hcd)) {
1234 if (!in_interrupt())
1235 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1240 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1241 size = urb->number_of_packets;
1245 urb_priv = kzalloc(sizeof(struct urb_priv) +
1246 size * sizeof(struct xhci_td *), mem_flags);
1250 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1256 for (i = 0; i < size; i++) {
1257 urb_priv->td[i] = buffer;
1261 urb_priv->length = size;
1262 urb_priv->td_cnt = 0;
1263 urb->hcpriv = urb_priv;
1265 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1266 /* Check to see if the max packet size for the default control
1267 * endpoint changed during FS device enumeration
1269 if (urb->dev->speed == USB_SPEED_FULL) {
1270 ret = xhci_check_maxpacket(xhci, slot_id,
1273 xhci_urb_free_priv(xhci, urb_priv);
1279 /* We have a spinlock and interrupts disabled, so we must pass
1280 * atomic context to this function, which may allocate memory.
1282 spin_lock_irqsave(&xhci->lock, flags);
1283 if (xhci->xhc_state & XHCI_STATE_DYING)
1285 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1289 spin_unlock_irqrestore(&xhci->lock, flags);
1290 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1291 spin_lock_irqsave(&xhci->lock, flags);
1292 if (xhci->xhc_state & XHCI_STATE_DYING)
1294 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1295 EP_GETTING_STREAMS) {
1296 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1297 "is transitioning to using streams.\n");
1299 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1300 EP_GETTING_NO_STREAMS) {
1301 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1302 "is transitioning to "
1303 "not having streams.\n");
1306 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1311 spin_unlock_irqrestore(&xhci->lock, flags);
1312 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1313 spin_lock_irqsave(&xhci->lock, flags);
1314 if (xhci->xhc_state & XHCI_STATE_DYING)
1316 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1320 spin_unlock_irqrestore(&xhci->lock, flags);
1322 spin_lock_irqsave(&xhci->lock, flags);
1323 if (xhci->xhc_state & XHCI_STATE_DYING)
1325 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1329 spin_unlock_irqrestore(&xhci->lock, flags);
1334 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1335 "non-responsive xHCI host.\n",
1336 urb->ep->desc.bEndpointAddress, urb);
1339 xhci_urb_free_priv(xhci, urb_priv);
1341 spin_unlock_irqrestore(&xhci->lock, flags);
1345 /* Get the right ring for the given URB.
1346 * If the endpoint supports streams, boundary check the URB's stream ID.
1347 * If the endpoint doesn't support streams, return the singular endpoint ring.
1349 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1352 unsigned int slot_id;
1353 unsigned int ep_index;
1354 unsigned int stream_id;
1355 struct xhci_virt_ep *ep;
1357 slot_id = urb->dev->slot_id;
1358 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1359 stream_id = urb->stream_id;
1360 ep = &xhci->devs[slot_id]->eps[ep_index];
1361 /* Common case: no streams */
1362 if (!(ep->ep_state & EP_HAS_STREAMS))
1365 if (stream_id == 0) {
1367 "WARN: Slot ID %u, ep index %u has streams, "
1368 "but URB has no stream ID.\n",
1373 if (stream_id < ep->stream_info->num_streams)
1374 return ep->stream_info->stream_rings[stream_id];
1377 "WARN: Slot ID %u, ep index %u has "
1378 "stream IDs 1 to %u allocated, "
1379 "but stream ID %u is requested.\n",
1381 ep->stream_info->num_streams - 1,
1387 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1388 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1389 * should pick up where it left off in the TD, unless a Set Transfer Ring
1390 * Dequeue Pointer is issued.
1392 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1393 * the ring. Since the ring is a contiguous structure, they can't be physically
1394 * removed. Instead, there are two options:
1396 * 1) If the HC is in the middle of processing the URB to be canceled, we
1397 * simply move the ring's dequeue pointer past those TRBs using the Set
1398 * Transfer Ring Dequeue Pointer command. This will be the common case,
1399 * when drivers timeout on the last submitted URB and attempt to cancel.
1401 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1402 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1403 * HC will need to invalidate the any TRBs it has cached after the stop
1404 * endpoint command, as noted in the xHCI 0.95 errata.
1406 * 3) The TD may have completed by the time the Stop Endpoint Command
1407 * completes, so software needs to handle that case too.
1409 * This function should protect against the TD enqueueing code ringing the
1410 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1411 * It also needs to account for multiple cancellations on happening at the same
1412 * time for the same endpoint.
1414 * Note that this function can be called in any context, or so says
1415 * usb_hcd_unlink_urb()
1417 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1419 unsigned long flags;
1422 struct xhci_hcd *xhci;
1423 struct urb_priv *urb_priv;
1425 unsigned int ep_index;
1426 struct xhci_ring *ep_ring;
1427 struct xhci_virt_ep *ep;
1429 xhci = hcd_to_xhci(hcd);
1430 spin_lock_irqsave(&xhci->lock, flags);
1431 /* Make sure the URB hasn't completed or been unlinked already */
1432 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1433 if (ret || !urb->hcpriv)
1435 temp = xhci_readl(xhci, &xhci->op_regs->status);
1436 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1437 xhci_dbg(xhci, "HW died, freeing TD.\n");
1438 urb_priv = urb->hcpriv;
1439 for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
1440 td = urb_priv->td[i];
1441 if (!list_empty(&td->td_list))
1442 list_del_init(&td->td_list);
1443 if (!list_empty(&td->cancelled_td_list))
1444 list_del_init(&td->cancelled_td_list);
1447 usb_hcd_unlink_urb_from_ep(hcd, urb);
1448 spin_unlock_irqrestore(&xhci->lock, flags);
1449 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1450 xhci_urb_free_priv(xhci, urb_priv);
1453 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
1454 (xhci->xhc_state & XHCI_STATE_HALTED)) {
1455 xhci_dbg(xhci, "Ep 0x%x: URB %p to be canceled on "
1456 "non-responsive xHCI host.\n",
1457 urb->ep->desc.bEndpointAddress, urb);
1458 /* Let the stop endpoint command watchdog timer (which set this
1459 * state) finish cleaning up the endpoint TD lists. We must
1460 * have caught it in the middle of dropping a lock and giving
1466 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1467 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1468 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1474 urb_priv = urb->hcpriv;
1475 i = urb_priv->td_cnt;
1476 if (i < urb_priv->length)
1477 xhci_dbg(xhci, "Cancel URB %p, dev %s, ep 0x%x, "
1478 "starting at offset 0x%llx\n",
1479 urb, urb->dev->devpath,
1480 urb->ep->desc.bEndpointAddress,
1481 (unsigned long long) xhci_trb_virt_to_dma(
1482 urb_priv->td[i]->start_seg,
1483 urb_priv->td[i]->first_trb));
1485 for (; i < urb_priv->length; i++) {
1486 td = urb_priv->td[i];
1487 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1490 /* Queue a stop endpoint command, but only if this is
1491 * the first cancellation to be handled.
1493 if (!(ep->ep_state & EP_HALT_PENDING)) {
1494 ep->ep_state |= EP_HALT_PENDING;
1495 ep->stop_cmds_pending++;
1496 ep->stop_cmd_timer.expires = jiffies +
1497 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1498 add_timer(&ep->stop_cmd_timer);
1499 xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0);
1500 xhci_ring_cmd_db(xhci);
1503 spin_unlock_irqrestore(&xhci->lock, flags);
1507 /* Drop an endpoint from a new bandwidth configuration for this device.
1508 * Only one call to this function is allowed per endpoint before
1509 * check_bandwidth() or reset_bandwidth() must be called.
1510 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1511 * add the endpoint to the schedule with possibly new parameters denoted by a
1512 * different endpoint descriptor in usb_host_endpoint.
1513 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1516 * The USB core will not allow URBs to be queued to an endpoint that is being
1517 * disabled, so there's no need for mutual exclusion to protect
1518 * the xhci->devs[slot_id] structure.
1520 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1521 struct usb_host_endpoint *ep)
1523 struct xhci_hcd *xhci;
1524 struct xhci_container_ctx *in_ctx, *out_ctx;
1525 struct xhci_input_control_ctx *ctrl_ctx;
1526 struct xhci_slot_ctx *slot_ctx;
1527 unsigned int last_ctx;
1528 unsigned int ep_index;
1529 struct xhci_ep_ctx *ep_ctx;
1531 u32 new_add_flags, new_drop_flags, new_slot_info;
1534 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1537 xhci = hcd_to_xhci(hcd);
1538 if (xhci->xhc_state & XHCI_STATE_DYING)
1541 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1542 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1543 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1544 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1545 __func__, drop_flag);
1549 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1550 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1551 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1553 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1558 ep_index = xhci_get_endpoint_index(&ep->desc);
1559 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1560 /* If the HC already knows the endpoint is disabled,
1561 * or the HCD has noted it is disabled, ignore this request
1563 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1564 cpu_to_le32(EP_STATE_DISABLED)) ||
1565 le32_to_cpu(ctrl_ctx->drop_flags) &
1566 xhci_get_endpoint_flag(&ep->desc)) {
1567 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1572 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1573 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1575 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1576 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1578 last_ctx = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags));
1579 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1580 /* Update the last valid endpoint context, if we deleted the last one */
1581 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) >
1582 LAST_CTX(last_ctx)) {
1583 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1584 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
1586 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
1588 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1590 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1591 (unsigned int) ep->desc.bEndpointAddress,
1593 (unsigned int) new_drop_flags,
1594 (unsigned int) new_add_flags,
1595 (unsigned int) new_slot_info);
1599 /* Add an endpoint to a new possible bandwidth configuration for this device.
1600 * Only one call to this function is allowed per endpoint before
1601 * check_bandwidth() or reset_bandwidth() must be called.
1602 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1603 * add the endpoint to the schedule with possibly new parameters denoted by a
1604 * different endpoint descriptor in usb_host_endpoint.
1605 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1608 * The USB core will not allow URBs to be queued to an endpoint until the
1609 * configuration or alt setting is installed in the device, so there's no need
1610 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1612 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1613 struct usb_host_endpoint *ep)
1615 struct xhci_hcd *xhci;
1616 struct xhci_container_ctx *in_ctx, *out_ctx;
1617 unsigned int ep_index;
1618 struct xhci_slot_ctx *slot_ctx;
1619 struct xhci_input_control_ctx *ctrl_ctx;
1621 unsigned int last_ctx;
1622 u32 new_add_flags, new_drop_flags, new_slot_info;
1623 struct xhci_virt_device *virt_dev;
1626 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1628 /* So we won't queue a reset ep command for a root hub */
1632 xhci = hcd_to_xhci(hcd);
1633 if (xhci->xhc_state & XHCI_STATE_DYING)
1636 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1637 last_ctx = xhci_last_valid_endpoint(added_ctxs);
1638 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1639 /* FIXME when we have to issue an evaluate endpoint command to
1640 * deal with ep0 max packet size changing once we get the
1643 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1644 __func__, added_ctxs);
1648 virt_dev = xhci->devs[udev->slot_id];
1649 in_ctx = virt_dev->in_ctx;
1650 out_ctx = virt_dev->out_ctx;
1651 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1653 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1658 ep_index = xhci_get_endpoint_index(&ep->desc);
1659 /* If this endpoint is already in use, and the upper layers are trying
1660 * to add it again without dropping it, reject the addition.
1662 if (virt_dev->eps[ep_index].ring &&
1663 !(le32_to_cpu(ctrl_ctx->drop_flags) &
1664 xhci_get_endpoint_flag(&ep->desc))) {
1665 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1666 "without dropping it.\n",
1667 (unsigned int) ep->desc.bEndpointAddress);
1671 /* If the HCD has already noted the endpoint is enabled,
1672 * ignore this request.
1674 if (le32_to_cpu(ctrl_ctx->add_flags) &
1675 xhci_get_endpoint_flag(&ep->desc)) {
1676 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1682 * Configuration and alternate setting changes must be done in
1683 * process context, not interrupt context (or so documenation
1684 * for usb_set_interface() and usb_set_configuration() claim).
1686 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1687 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1688 __func__, ep->desc.bEndpointAddress);
1692 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1693 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1695 /* If xhci_endpoint_disable() was called for this endpoint, but the
1696 * xHC hasn't been notified yet through the check_bandwidth() call,
1697 * this re-adds a new state for the endpoint from the new endpoint
1698 * descriptors. We must drop and re-add this endpoint, so we leave the
1701 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1703 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1704 /* Update the last valid endpoint context, if we just added one past */
1705 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) <
1706 LAST_CTX(last_ctx)) {
1707 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1708 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
1710 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
1712 /* Store the usb_device pointer for later use */
1715 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1716 (unsigned int) ep->desc.bEndpointAddress,
1718 (unsigned int) new_drop_flags,
1719 (unsigned int) new_add_flags,
1720 (unsigned int) new_slot_info);
1724 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1726 struct xhci_input_control_ctx *ctrl_ctx;
1727 struct xhci_ep_ctx *ep_ctx;
1728 struct xhci_slot_ctx *slot_ctx;
1731 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1733 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1738 /* When a device's add flag and drop flag are zero, any subsequent
1739 * configure endpoint command will leave that endpoint's state
1740 * untouched. Make sure we don't leave any old state in the input
1741 * endpoint contexts.
1743 ctrl_ctx->drop_flags = 0;
1744 ctrl_ctx->add_flags = 0;
1745 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1746 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1747 /* Endpoint 0 is always valid */
1748 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1749 for (i = 1; i < 31; ++i) {
1750 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1751 ep_ctx->ep_info = 0;
1752 ep_ctx->ep_info2 = 0;
1754 ep_ctx->tx_info = 0;
1758 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1759 struct usb_device *udev, u32 *cmd_status)
1763 switch (*cmd_status) {
1765 dev_warn(&udev->dev, "Not enough host controller resources "
1766 "for new device state.\n");
1768 /* FIXME: can we allocate more resources for the HC? */
1771 case COMP_2ND_BW_ERR:
1772 dev_warn(&udev->dev, "Not enough bandwidth "
1773 "for new device state.\n");
1775 /* FIXME: can we go back to the old state? */
1778 /* the HCD set up something wrong */
1779 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1781 "and endpoint is not disabled.\n");
1785 dev_warn(&udev->dev, "ERROR: Incompatible device for endpoint "
1786 "configure command.\n");
1790 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1791 "Successful Endpoint Configure command");
1795 xhci_err(xhci, "ERROR: unexpected command completion "
1796 "code 0x%x.\n", *cmd_status);
1803 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1804 struct usb_device *udev, u32 *cmd_status)
1807 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1809 switch (*cmd_status) {
1811 dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
1812 "context command.\n");
1816 dev_warn(&udev->dev, "WARN: slot not enabled for"
1817 "evaluate context command.\n");
1820 case COMP_CTX_STATE:
1821 dev_warn(&udev->dev, "WARN: invalid context state for "
1822 "evaluate context command.\n");
1823 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1827 dev_warn(&udev->dev, "ERROR: Incompatible device for evaluate "
1828 "context command.\n");
1832 /* Max Exit Latency too large error */
1833 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1837 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1838 "Successful evaluate context command");
1842 xhci_err(xhci, "ERROR: unexpected command completion "
1843 "code 0x%x.\n", *cmd_status);
1850 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1851 struct xhci_input_control_ctx *ctrl_ctx)
1853 u32 valid_add_flags;
1854 u32 valid_drop_flags;
1856 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1857 * (bit 1). The default control endpoint is added during the Address
1858 * Device command and is never removed until the slot is disabled.
1860 valid_add_flags = ctrl_ctx->add_flags >> 2;
1861 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1863 /* Use hweight32 to count the number of ones in the add flags, or
1864 * number of endpoints added. Don't count endpoints that are changed
1865 * (both added and dropped).
1867 return hweight32(valid_add_flags) -
1868 hweight32(valid_add_flags & valid_drop_flags);
1871 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1872 struct xhci_input_control_ctx *ctrl_ctx)
1874 u32 valid_add_flags;
1875 u32 valid_drop_flags;
1877 valid_add_flags = ctrl_ctx->add_flags >> 2;
1878 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1880 return hweight32(valid_drop_flags) -
1881 hweight32(valid_add_flags & valid_drop_flags);
1885 * We need to reserve the new number of endpoints before the configure endpoint
1886 * command completes. We can't subtract the dropped endpoints from the number
1887 * of active endpoints until the command completes because we can oversubscribe
1888 * the host in this case:
1890 * - the first configure endpoint command drops more endpoints than it adds
1891 * - a second configure endpoint command that adds more endpoints is queued
1892 * - the first configure endpoint command fails, so the config is unchanged
1893 * - the second command may succeed, even though there isn't enough resources
1895 * Must be called with xhci->lock held.
1897 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
1898 struct xhci_input_control_ctx *ctrl_ctx)
1902 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
1903 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
1904 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1905 "Not enough ep ctxs: "
1906 "%u active, need to add %u, limit is %u.",
1907 xhci->num_active_eps, added_eps,
1908 xhci->limit_active_eps);
1911 xhci->num_active_eps += added_eps;
1912 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1913 "Adding %u ep ctxs, %u now active.", added_eps,
1914 xhci->num_active_eps);
1919 * The configure endpoint was failed by the xHC for some other reason, so we
1920 * need to revert the resources that failed configuration would have used.
1922 * Must be called with xhci->lock held.
1924 static void xhci_free_host_resources(struct xhci_hcd *xhci,
1925 struct xhci_input_control_ctx *ctrl_ctx)
1929 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
1930 xhci->num_active_eps -= num_failed_eps;
1931 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1932 "Removing %u failed ep ctxs, %u now active.",
1934 xhci->num_active_eps);
1938 * Now that the command has completed, clean up the active endpoint count by
1939 * subtracting out the endpoints that were dropped (but not changed).
1941 * Must be called with xhci->lock held.
1943 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
1944 struct xhci_input_control_ctx *ctrl_ctx)
1946 u32 num_dropped_eps;
1948 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
1949 xhci->num_active_eps -= num_dropped_eps;
1950 if (num_dropped_eps)
1951 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1952 "Removing %u dropped ep ctxs, %u now active.",
1954 xhci->num_active_eps);
1957 static unsigned int xhci_get_block_size(struct usb_device *udev)
1959 switch (udev->speed) {
1961 case USB_SPEED_FULL:
1963 case USB_SPEED_HIGH:
1965 case USB_SPEED_SUPER:
1967 case USB_SPEED_UNKNOWN:
1968 case USB_SPEED_WIRELESS:
1970 /* Should never happen */
1976 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
1978 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
1980 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
1985 /* If we are changing a LS/FS device under a HS hub,
1986 * make sure (if we are activating a new TT) that the HS bus has enough
1987 * bandwidth for this new TT.
1989 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
1990 struct xhci_virt_device *virt_dev,
1993 struct xhci_interval_bw_table *bw_table;
1994 struct xhci_tt_bw_info *tt_info;
1996 /* Find the bandwidth table for the root port this TT is attached to. */
1997 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
1998 tt_info = virt_dev->tt_info;
1999 /* If this TT already had active endpoints, the bandwidth for this TT
2000 * has already been added. Removing all periodic endpoints (and thus
2001 * making the TT enactive) will only decrease the bandwidth used.
2005 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2006 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2010 /* Not sure why we would have no new active endpoints...
2012 * Maybe because of an Evaluate Context change for a hub update or a
2013 * control endpoint 0 max packet size change?
2014 * FIXME: skip the bandwidth calculation in that case.
2019 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2020 struct xhci_virt_device *virt_dev)
2022 unsigned int bw_reserved;
2024 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2025 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2028 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2029 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2036 * This algorithm is a very conservative estimate of the worst-case scheduling
2037 * scenario for any one interval. The hardware dynamically schedules the
2038 * packets, so we can't tell which microframe could be the limiting factor in
2039 * the bandwidth scheduling. This only takes into account periodic endpoints.
2041 * Obviously, we can't solve an NP complete problem to find the minimum worst
2042 * case scenario. Instead, we come up with an estimate that is no less than
2043 * the worst case bandwidth used for any one microframe, but may be an
2046 * We walk the requirements for each endpoint by interval, starting with the
2047 * smallest interval, and place packets in the schedule where there is only one
2048 * possible way to schedule packets for that interval. In order to simplify
2049 * this algorithm, we record the largest max packet size for each interval, and
2050 * assume all packets will be that size.
2052 * For interval 0, we obviously must schedule all packets for each interval.
2053 * The bandwidth for interval 0 is just the amount of data to be transmitted
2054 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2055 * the number of packets).
2057 * For interval 1, we have two possible microframes to schedule those packets
2058 * in. For this algorithm, if we can schedule the same number of packets for
2059 * each possible scheduling opportunity (each microframe), we will do so. The
2060 * remaining number of packets will be saved to be transmitted in the gaps in
2061 * the next interval's scheduling sequence.
2063 * As we move those remaining packets to be scheduled with interval 2 packets,
2064 * we have to double the number of remaining packets to transmit. This is
2065 * because the intervals are actually powers of 2, and we would be transmitting
2066 * the previous interval's packets twice in this interval. We also have to be
2067 * sure that when we look at the largest max packet size for this interval, we
2068 * also look at the largest max packet size for the remaining packets and take
2069 * the greater of the two.
2071 * The algorithm continues to evenly distribute packets in each scheduling
2072 * opportunity, and push the remaining packets out, until we get to the last
2073 * interval. Then those packets and their associated overhead are just added
2074 * to the bandwidth used.
2076 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2077 struct xhci_virt_device *virt_dev,
2080 unsigned int bw_reserved;
2081 unsigned int max_bandwidth;
2082 unsigned int bw_used;
2083 unsigned int block_size;
2084 struct xhci_interval_bw_table *bw_table;
2085 unsigned int packet_size = 0;
2086 unsigned int overhead = 0;
2087 unsigned int packets_transmitted = 0;
2088 unsigned int packets_remaining = 0;
2091 if (virt_dev->udev->speed == USB_SPEED_SUPER)
2092 return xhci_check_ss_bw(xhci, virt_dev);
2094 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2095 max_bandwidth = HS_BW_LIMIT;
2096 /* Convert percent of bus BW reserved to blocks reserved */
2097 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2099 max_bandwidth = FS_BW_LIMIT;
2100 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2103 bw_table = virt_dev->bw_table;
2104 /* We need to translate the max packet size and max ESIT payloads into
2105 * the units the hardware uses.
2107 block_size = xhci_get_block_size(virt_dev->udev);
2109 /* If we are manipulating a LS/FS device under a HS hub, double check
2110 * that the HS bus has enough bandwidth if we are activing a new TT.
2112 if (virt_dev->tt_info) {
2113 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2114 "Recalculating BW for rootport %u",
2115 virt_dev->real_port);
2116 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2117 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2118 "newly activated TT.\n");
2121 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2122 "Recalculating BW for TT slot %u port %u",
2123 virt_dev->tt_info->slot_id,
2124 virt_dev->tt_info->ttport);
2126 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2127 "Recalculating BW for rootport %u",
2128 virt_dev->real_port);
2131 /* Add in how much bandwidth will be used for interval zero, or the
2132 * rounded max ESIT payload + number of packets * largest overhead.
2134 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2135 bw_table->interval_bw[0].num_packets *
2136 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2138 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2139 unsigned int bw_added;
2140 unsigned int largest_mps;
2141 unsigned int interval_overhead;
2144 * How many packets could we transmit in this interval?
2145 * If packets didn't fit in the previous interval, we will need
2146 * to transmit that many packets twice within this interval.
2148 packets_remaining = 2 * packets_remaining +
2149 bw_table->interval_bw[i].num_packets;
2151 /* Find the largest max packet size of this or the previous
2154 if (list_empty(&bw_table->interval_bw[i].endpoints))
2157 struct xhci_virt_ep *virt_ep;
2158 struct list_head *ep_entry;
2160 ep_entry = bw_table->interval_bw[i].endpoints.next;
2161 virt_ep = list_entry(ep_entry,
2162 struct xhci_virt_ep, bw_endpoint_list);
2163 /* Convert to blocks, rounding up */
2164 largest_mps = DIV_ROUND_UP(
2165 virt_ep->bw_info.max_packet_size,
2168 if (largest_mps > packet_size)
2169 packet_size = largest_mps;
2171 /* Use the larger overhead of this or the previous interval. */
2172 interval_overhead = xhci_get_largest_overhead(
2173 &bw_table->interval_bw[i]);
2174 if (interval_overhead > overhead)
2175 overhead = interval_overhead;
2177 /* How many packets can we evenly distribute across
2178 * (1 << (i + 1)) possible scheduling opportunities?
2180 packets_transmitted = packets_remaining >> (i + 1);
2182 /* Add in the bandwidth used for those scheduled packets */
2183 bw_added = packets_transmitted * (overhead + packet_size);
2185 /* How many packets do we have remaining to transmit? */
2186 packets_remaining = packets_remaining % (1 << (i + 1));
2188 /* What largest max packet size should those packets have? */
2189 /* If we've transmitted all packets, don't carry over the
2190 * largest packet size.
2192 if (packets_remaining == 0) {
2195 } else if (packets_transmitted > 0) {
2196 /* Otherwise if we do have remaining packets, and we've
2197 * scheduled some packets in this interval, take the
2198 * largest max packet size from endpoints with this
2201 packet_size = largest_mps;
2202 overhead = interval_overhead;
2204 /* Otherwise carry over packet_size and overhead from the last
2205 * time we had a remainder.
2207 bw_used += bw_added;
2208 if (bw_used > max_bandwidth) {
2209 xhci_warn(xhci, "Not enough bandwidth. "
2210 "Proposed: %u, Max: %u\n",
2211 bw_used, max_bandwidth);
2216 * Ok, we know we have some packets left over after even-handedly
2217 * scheduling interval 15. We don't know which microframes they will
2218 * fit into, so we over-schedule and say they will be scheduled every
2221 if (packets_remaining > 0)
2222 bw_used += overhead + packet_size;
2224 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2225 unsigned int port_index = virt_dev->real_port - 1;
2227 /* OK, we're manipulating a HS device attached to a
2228 * root port bandwidth domain. Include the number of active TTs
2229 * in the bandwidth used.
2231 bw_used += TT_HS_OVERHEAD *
2232 xhci->rh_bw[port_index].num_active_tts;
2235 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2236 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2237 "Available: %u " "percent",
2238 bw_used, max_bandwidth, bw_reserved,
2239 (max_bandwidth - bw_used - bw_reserved) * 100 /
2242 bw_used += bw_reserved;
2243 if (bw_used > max_bandwidth) {
2244 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2245 bw_used, max_bandwidth);
2249 bw_table->bw_used = bw_used;
2253 static bool xhci_is_async_ep(unsigned int ep_type)
2255 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2256 ep_type != ISOC_IN_EP &&
2257 ep_type != INT_IN_EP);
2260 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2262 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2265 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2267 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2269 if (ep_bw->ep_interval == 0)
2270 return SS_OVERHEAD_BURST +
2271 (ep_bw->mult * ep_bw->num_packets *
2272 (SS_OVERHEAD + mps));
2273 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2274 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2275 1 << ep_bw->ep_interval);
2279 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2280 struct xhci_bw_info *ep_bw,
2281 struct xhci_interval_bw_table *bw_table,
2282 struct usb_device *udev,
2283 struct xhci_virt_ep *virt_ep,
2284 struct xhci_tt_bw_info *tt_info)
2286 struct xhci_interval_bw *interval_bw;
2287 int normalized_interval;
2289 if (xhci_is_async_ep(ep_bw->type))
2292 if (udev->speed == USB_SPEED_SUPER) {
2293 if (xhci_is_sync_in_ep(ep_bw->type))
2294 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2295 xhci_get_ss_bw_consumed(ep_bw);
2297 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2298 xhci_get_ss_bw_consumed(ep_bw);
2302 /* SuperSpeed endpoints never get added to intervals in the table, so
2303 * this check is only valid for HS/FS/LS devices.
2305 if (list_empty(&virt_ep->bw_endpoint_list))
2307 /* For LS/FS devices, we need to translate the interval expressed in
2308 * microframes to frames.
2310 if (udev->speed == USB_SPEED_HIGH)
2311 normalized_interval = ep_bw->ep_interval;
2313 normalized_interval = ep_bw->ep_interval - 3;
2315 if (normalized_interval == 0)
2316 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2317 interval_bw = &bw_table->interval_bw[normalized_interval];
2318 interval_bw->num_packets -= ep_bw->num_packets;
2319 switch (udev->speed) {
2321 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2323 case USB_SPEED_FULL:
2324 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2326 case USB_SPEED_HIGH:
2327 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2329 case USB_SPEED_SUPER:
2330 case USB_SPEED_UNKNOWN:
2331 case USB_SPEED_WIRELESS:
2332 /* Should never happen because only LS/FS/HS endpoints will get
2333 * added to the endpoint list.
2338 tt_info->active_eps -= 1;
2339 list_del_init(&virt_ep->bw_endpoint_list);
2342 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2343 struct xhci_bw_info *ep_bw,
2344 struct xhci_interval_bw_table *bw_table,
2345 struct usb_device *udev,
2346 struct xhci_virt_ep *virt_ep,
2347 struct xhci_tt_bw_info *tt_info)
2349 struct xhci_interval_bw *interval_bw;
2350 struct xhci_virt_ep *smaller_ep;
2351 int normalized_interval;
2353 if (xhci_is_async_ep(ep_bw->type))
2356 if (udev->speed == USB_SPEED_SUPER) {
2357 if (xhci_is_sync_in_ep(ep_bw->type))
2358 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2359 xhci_get_ss_bw_consumed(ep_bw);
2361 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2362 xhci_get_ss_bw_consumed(ep_bw);
2366 /* For LS/FS devices, we need to translate the interval expressed in
2367 * microframes to frames.
2369 if (udev->speed == USB_SPEED_HIGH)
2370 normalized_interval = ep_bw->ep_interval;
2372 normalized_interval = ep_bw->ep_interval - 3;
2374 if (normalized_interval == 0)
2375 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2376 interval_bw = &bw_table->interval_bw[normalized_interval];
2377 interval_bw->num_packets += ep_bw->num_packets;
2378 switch (udev->speed) {
2380 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2382 case USB_SPEED_FULL:
2383 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2385 case USB_SPEED_HIGH:
2386 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2388 case USB_SPEED_SUPER:
2389 case USB_SPEED_UNKNOWN:
2390 case USB_SPEED_WIRELESS:
2391 /* Should never happen because only LS/FS/HS endpoints will get
2392 * added to the endpoint list.
2398 tt_info->active_eps += 1;
2399 /* Insert the endpoint into the list, largest max packet size first. */
2400 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2402 if (ep_bw->max_packet_size >=
2403 smaller_ep->bw_info.max_packet_size) {
2404 /* Add the new ep before the smaller endpoint */
2405 list_add_tail(&virt_ep->bw_endpoint_list,
2406 &smaller_ep->bw_endpoint_list);
2410 /* Add the new endpoint at the end of the list. */
2411 list_add_tail(&virt_ep->bw_endpoint_list,
2412 &interval_bw->endpoints);
2415 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2416 struct xhci_virt_device *virt_dev,
2419 struct xhci_root_port_bw_info *rh_bw_info;
2420 if (!virt_dev->tt_info)
2423 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2424 if (old_active_eps == 0 &&
2425 virt_dev->tt_info->active_eps != 0) {
2426 rh_bw_info->num_active_tts += 1;
2427 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2428 } else if (old_active_eps != 0 &&
2429 virt_dev->tt_info->active_eps == 0) {
2430 rh_bw_info->num_active_tts -= 1;
2431 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2435 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2436 struct xhci_virt_device *virt_dev,
2437 struct xhci_container_ctx *in_ctx)
2439 struct xhci_bw_info ep_bw_info[31];
2441 struct xhci_input_control_ctx *ctrl_ctx;
2442 int old_active_eps = 0;
2444 if (virt_dev->tt_info)
2445 old_active_eps = virt_dev->tt_info->active_eps;
2447 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
2449 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2454 for (i = 0; i < 31; i++) {
2455 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2458 /* Make a copy of the BW info in case we need to revert this */
2459 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2460 sizeof(ep_bw_info[i]));
2461 /* Drop the endpoint from the interval table if the endpoint is
2462 * being dropped or changed.
2464 if (EP_IS_DROPPED(ctrl_ctx, i))
2465 xhci_drop_ep_from_interval_table(xhci,
2466 &virt_dev->eps[i].bw_info,
2472 /* Overwrite the information stored in the endpoints' bw_info */
2473 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2474 for (i = 0; i < 31; i++) {
2475 /* Add any changed or added endpoints to the interval table */
2476 if (EP_IS_ADDED(ctrl_ctx, i))
2477 xhci_add_ep_to_interval_table(xhci,
2478 &virt_dev->eps[i].bw_info,
2485 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2486 /* Ok, this fits in the bandwidth we have.
2487 * Update the number of active TTs.
2489 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2493 /* We don't have enough bandwidth for this, revert the stored info. */
2494 for (i = 0; i < 31; i++) {
2495 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2498 /* Drop the new copies of any added or changed endpoints from
2499 * the interval table.
2501 if (EP_IS_ADDED(ctrl_ctx, i)) {
2502 xhci_drop_ep_from_interval_table(xhci,
2503 &virt_dev->eps[i].bw_info,
2509 /* Revert the endpoint back to its old information */
2510 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2511 sizeof(ep_bw_info[i]));
2512 /* Add any changed or dropped endpoints back into the table */
2513 if (EP_IS_DROPPED(ctrl_ctx, i))
2514 xhci_add_ep_to_interval_table(xhci,
2515 &virt_dev->eps[i].bw_info,
2525 /* Issue a configure endpoint command or evaluate context command
2526 * and wait for it to finish.
2528 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2529 struct usb_device *udev,
2530 struct xhci_command *command,
2531 bool ctx_change, bool must_succeed)
2535 unsigned long flags;
2536 struct xhci_container_ctx *in_ctx;
2537 struct xhci_input_control_ctx *ctrl_ctx;
2538 struct completion *cmd_completion;
2540 struct xhci_virt_device *virt_dev;
2541 union xhci_trb *cmd_trb;
2543 spin_lock_irqsave(&xhci->lock, flags);
2544 virt_dev = xhci->devs[udev->slot_id];
2547 in_ctx = command->in_ctx;
2549 in_ctx = virt_dev->in_ctx;
2550 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
2552 spin_unlock_irqrestore(&xhci->lock, flags);
2553 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2558 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2559 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2560 spin_unlock_irqrestore(&xhci->lock, flags);
2561 xhci_warn(xhci, "Not enough host resources, "
2562 "active endpoint contexts = %u\n",
2563 xhci->num_active_eps);
2566 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2567 xhci_reserve_bandwidth(xhci, virt_dev, in_ctx)) {
2568 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2569 xhci_free_host_resources(xhci, ctrl_ctx);
2570 spin_unlock_irqrestore(&xhci->lock, flags);
2571 xhci_warn(xhci, "Not enough bandwidth\n");
2576 cmd_completion = command->completion;
2577 cmd_status = &command->status;
2578 command->command_trb = xhci->cmd_ring->enqueue;
2580 /* Enqueue pointer can be left pointing to the link TRB,
2581 * we must handle that
2583 if (TRB_TYPE_LINK_LE32(command->command_trb->link.control))
2584 command->command_trb =
2585 xhci->cmd_ring->enq_seg->next->trbs;
2587 list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
2589 cmd_completion = &virt_dev->cmd_completion;
2590 cmd_status = &virt_dev->cmd_status;
2592 init_completion(cmd_completion);
2594 cmd_trb = xhci->cmd_ring->dequeue;
2596 ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
2597 udev->slot_id, must_succeed);
2599 ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
2600 udev->slot_id, must_succeed);
2603 list_del(&command->cmd_list);
2604 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2605 xhci_free_host_resources(xhci, ctrl_ctx);
2606 spin_unlock_irqrestore(&xhci->lock, flags);
2607 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2608 "FIXME allocate a new ring segment");
2611 xhci_ring_cmd_db(xhci);
2612 spin_unlock_irqrestore(&xhci->lock, flags);
2614 /* Wait for the configure endpoint command to complete */
2615 timeleft = wait_for_completion_interruptible_timeout(
2617 XHCI_CMD_DEFAULT_TIMEOUT);
2618 if (timeleft <= 0) {
2619 xhci_warn(xhci, "%s while waiting for %s command\n",
2620 timeleft == 0 ? "Timeout" : "Signal",
2622 "configure endpoint" :
2623 "evaluate context");
2624 /* cancel the configure endpoint command */
2625 ret = xhci_cancel_cmd(xhci, command, cmd_trb);
2632 ret = xhci_configure_endpoint_result(xhci, udev, cmd_status);
2634 ret = xhci_evaluate_context_result(xhci, udev, cmd_status);
2636 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2637 spin_lock_irqsave(&xhci->lock, flags);
2638 /* If the command failed, remove the reserved resources.
2639 * Otherwise, clean up the estimate to include dropped eps.
2642 xhci_free_host_resources(xhci, ctrl_ctx);
2644 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2645 spin_unlock_irqrestore(&xhci->lock, flags);
2650 /* Called after one or more calls to xhci_add_endpoint() or
2651 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2652 * to call xhci_reset_bandwidth().
2654 * Since we are in the middle of changing either configuration or
2655 * installing a new alt setting, the USB core won't allow URBs to be
2656 * enqueued for any endpoint on the old config or interface. Nothing
2657 * else should be touching the xhci->devs[slot_id] structure, so we
2658 * don't need to take the xhci->lock for manipulating that.
2660 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2664 struct xhci_hcd *xhci;
2665 struct xhci_virt_device *virt_dev;
2666 struct xhci_input_control_ctx *ctrl_ctx;
2667 struct xhci_slot_ctx *slot_ctx;
2669 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2672 xhci = hcd_to_xhci(hcd);
2673 if (xhci->xhc_state & XHCI_STATE_DYING)
2676 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2677 virt_dev = xhci->devs[udev->slot_id];
2679 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2680 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
2682 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2686 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2687 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2688 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2690 /* Don't issue the command if there's no endpoints to update. */
2691 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2692 ctrl_ctx->drop_flags == 0)
2695 xhci_dbg(xhci, "New Input Control Context:\n");
2696 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2697 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2698 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2700 ret = xhci_configure_endpoint(xhci, udev, NULL,
2703 /* Callee should call reset_bandwidth() */
2707 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2708 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2709 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2711 /* Free any rings that were dropped, but not changed. */
2712 for (i = 1; i < 31; ++i) {
2713 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2714 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))))
2715 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2717 xhci_zero_in_ctx(xhci, virt_dev);
2719 * Install any rings for completely new endpoints or changed endpoints,
2720 * and free or cache any old rings from changed endpoints.
2722 for (i = 1; i < 31; ++i) {
2723 if (!virt_dev->eps[i].new_ring)
2725 /* Only cache or free the old ring if it exists.
2726 * It may not if this is the first add of an endpoint.
2728 if (virt_dev->eps[i].ring) {
2729 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2731 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2732 virt_dev->eps[i].new_ring = NULL;
2738 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2740 struct xhci_hcd *xhci;
2741 struct xhci_virt_device *virt_dev;
2744 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2747 xhci = hcd_to_xhci(hcd);
2749 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2750 virt_dev = xhci->devs[udev->slot_id];
2751 /* Free any rings allocated for added endpoints */
2752 for (i = 0; i < 31; ++i) {
2753 if (virt_dev->eps[i].new_ring) {
2754 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2755 virt_dev->eps[i].new_ring = NULL;
2758 xhci_zero_in_ctx(xhci, virt_dev);
2761 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2762 struct xhci_container_ctx *in_ctx,
2763 struct xhci_container_ctx *out_ctx,
2764 struct xhci_input_control_ctx *ctrl_ctx,
2765 u32 add_flags, u32 drop_flags)
2767 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2768 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2769 xhci_slot_copy(xhci, in_ctx, out_ctx);
2770 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2772 xhci_dbg(xhci, "Input Context:\n");
2773 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2776 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2777 unsigned int slot_id, unsigned int ep_index,
2778 struct xhci_dequeue_state *deq_state)
2780 struct xhci_input_control_ctx *ctrl_ctx;
2781 struct xhci_container_ctx *in_ctx;
2782 struct xhci_ep_ctx *ep_ctx;
2786 in_ctx = xhci->devs[slot_id]->in_ctx;
2787 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
2789 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2794 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2795 xhci->devs[slot_id]->out_ctx, ep_index);
2796 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2797 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2798 deq_state->new_deq_ptr);
2800 xhci_warn(xhci, "WARN Cannot submit config ep after "
2801 "reset ep command\n");
2802 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2803 deq_state->new_deq_seg,
2804 deq_state->new_deq_ptr);
2807 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2809 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2810 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2811 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2812 added_ctxs, added_ctxs);
2815 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2816 struct usb_device *udev, unsigned int ep_index)
2818 struct xhci_dequeue_state deq_state;
2819 struct xhci_virt_ep *ep;
2821 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2822 "Cleaning up stalled endpoint ring");
2823 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2824 /* We need to move the HW's dequeue pointer past this TD,
2825 * or it will attempt to resend it on the next doorbell ring.
2827 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2828 ep_index, ep->stopped_stream, ep->stopped_td,
2831 /* HW with the reset endpoint quirk will use the saved dequeue state to
2832 * issue a configure endpoint command later.
2834 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2835 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2836 "Queueing new dequeue state");
2837 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2838 ep_index, ep->stopped_stream, &deq_state);
2840 /* Better hope no one uses the input context between now and the
2841 * reset endpoint completion!
2842 * XXX: No idea how this hardware will react when stream rings
2845 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2846 "Setting up input context for "
2847 "configure endpoint command");
2848 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2849 ep_index, &deq_state);
2853 /* Deal with stalled endpoints. The core should have sent the control message
2854 * to clear the halt condition. However, we need to make the xHCI hardware
2855 * reset its sequence number, since a device will expect a sequence number of
2856 * zero after the halt condition is cleared.
2857 * Context: in_interrupt
2859 void xhci_endpoint_reset(struct usb_hcd *hcd,
2860 struct usb_host_endpoint *ep)
2862 struct xhci_hcd *xhci;
2863 struct usb_device *udev;
2864 unsigned int ep_index;
2865 unsigned long flags;
2867 struct xhci_virt_ep *virt_ep;
2869 xhci = hcd_to_xhci(hcd);
2870 udev = (struct usb_device *) ep->hcpriv;
2871 /* Called with a root hub endpoint (or an endpoint that wasn't added
2872 * with xhci_add_endpoint()
2876 ep_index = xhci_get_endpoint_index(&ep->desc);
2877 virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2878 if (!virt_ep->stopped_td) {
2879 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2880 "Endpoint 0x%x not halted, refusing to reset.",
2881 ep->desc.bEndpointAddress);
2884 if (usb_endpoint_xfer_control(&ep->desc)) {
2885 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2886 "Control endpoint stall already handled.");
2890 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2891 "Queueing reset endpoint command");
2892 spin_lock_irqsave(&xhci->lock, flags);
2893 ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index);
2895 * Can't change the ring dequeue pointer until it's transitioned to the
2896 * stopped state, which is only upon a successful reset endpoint
2897 * command. Better hope that last command worked!
2900 xhci_cleanup_stalled_ring(xhci, udev, ep_index);
2901 kfree(virt_ep->stopped_td);
2902 xhci_ring_cmd_db(xhci);
2904 virt_ep->stopped_td = NULL;
2905 virt_ep->stopped_trb = NULL;
2906 virt_ep->stopped_stream = 0;
2907 spin_unlock_irqrestore(&xhci->lock, flags);
2910 xhci_warn(xhci, "FIXME allocate a new ring segment\n");
2913 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2914 struct usb_device *udev, struct usb_host_endpoint *ep,
2915 unsigned int slot_id)
2918 unsigned int ep_index;
2919 unsigned int ep_state;
2923 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
2926 if (ep->ss_ep_comp.bmAttributes == 0) {
2927 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
2928 " descriptor for ep 0x%x does not support streams\n",
2929 ep->desc.bEndpointAddress);
2933 ep_index = xhci_get_endpoint_index(&ep->desc);
2934 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2935 if (ep_state & EP_HAS_STREAMS ||
2936 ep_state & EP_GETTING_STREAMS) {
2937 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
2938 "already has streams set up.\n",
2939 ep->desc.bEndpointAddress);
2940 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
2941 "dynamic stream context array reallocation.\n");
2944 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
2945 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
2946 "endpoint 0x%x; URBs are pending.\n",
2947 ep->desc.bEndpointAddress);
2953 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
2954 unsigned int *num_streams, unsigned int *num_stream_ctxs)
2956 unsigned int max_streams;
2958 /* The stream context array size must be a power of two */
2959 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
2961 * Find out how many primary stream array entries the host controller
2962 * supports. Later we may use secondary stream arrays (similar to 2nd
2963 * level page entries), but that's an optional feature for xHCI host
2964 * controllers. xHCs must support at least 4 stream IDs.
2966 max_streams = HCC_MAX_PSA(xhci->hcc_params);
2967 if (*num_stream_ctxs > max_streams) {
2968 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
2970 *num_stream_ctxs = max_streams;
2971 *num_streams = max_streams;
2975 /* Returns an error code if one of the endpoint already has streams.
2976 * This does not change any data structures, it only checks and gathers
2979 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
2980 struct usb_device *udev,
2981 struct usb_host_endpoint **eps, unsigned int num_eps,
2982 unsigned int *num_streams, u32 *changed_ep_bitmask)
2984 unsigned int max_streams;
2985 unsigned int endpoint_flag;
2989 for (i = 0; i < num_eps; i++) {
2990 ret = xhci_check_streams_endpoint(xhci, udev,
2991 eps[i], udev->slot_id);
2995 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
2996 if (max_streams < (*num_streams - 1)) {
2997 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
2998 eps[i]->desc.bEndpointAddress,
3000 *num_streams = max_streams+1;
3003 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3004 if (*changed_ep_bitmask & endpoint_flag)
3006 *changed_ep_bitmask |= endpoint_flag;
3011 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3012 struct usb_device *udev,
3013 struct usb_host_endpoint **eps, unsigned int num_eps)
3015 u32 changed_ep_bitmask = 0;
3016 unsigned int slot_id;
3017 unsigned int ep_index;
3018 unsigned int ep_state;
3021 slot_id = udev->slot_id;
3022 if (!xhci->devs[slot_id])
3025 for (i = 0; i < num_eps; i++) {
3026 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3027 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3028 /* Are streams already being freed for the endpoint? */
3029 if (ep_state & EP_GETTING_NO_STREAMS) {
3030 xhci_warn(xhci, "WARN Can't disable streams for "
3032 "streams are being disabled already\n",
3033 eps[i]->desc.bEndpointAddress);
3036 /* Are there actually any streams to free? */
3037 if (!(ep_state & EP_HAS_STREAMS) &&
3038 !(ep_state & EP_GETTING_STREAMS)) {
3039 xhci_warn(xhci, "WARN Can't disable streams for "
3041 "streams are already disabled!\n",
3042 eps[i]->desc.bEndpointAddress);
3043 xhci_warn(xhci, "WARN xhci_free_streams() called "
3044 "with non-streams endpoint\n");
3047 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3049 return changed_ep_bitmask;
3053 * The USB device drivers use this function (though the HCD interface in USB
3054 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3055 * coordinate mass storage command queueing across multiple endpoints (basically
3056 * a stream ID == a task ID).
3058 * Setting up streams involves allocating the same size stream context array
3059 * for each endpoint and issuing a configure endpoint command for all endpoints.
3061 * Don't allow the call to succeed if one endpoint only supports one stream
3062 * (which means it doesn't support streams at all).
3064 * Drivers may get less stream IDs than they asked for, if the host controller
3065 * hardware or endpoints claim they can't support the number of requested
3068 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3069 struct usb_host_endpoint **eps, unsigned int num_eps,
3070 unsigned int num_streams, gfp_t mem_flags)
3073 struct xhci_hcd *xhci;
3074 struct xhci_virt_device *vdev;
3075 struct xhci_command *config_cmd;
3076 struct xhci_input_control_ctx *ctrl_ctx;
3077 unsigned int ep_index;
3078 unsigned int num_stream_ctxs;
3079 unsigned long flags;
3080 u32 changed_ep_bitmask = 0;
3085 /* Add one to the number of streams requested to account for
3086 * stream 0 that is reserved for xHCI usage.
3089 xhci = hcd_to_xhci(hcd);
3090 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3093 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3095 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3098 ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
3100 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3102 xhci_free_command(xhci, config_cmd);
3106 /* Check to make sure all endpoints are not already configured for
3107 * streams. While we're at it, find the maximum number of streams that
3108 * all the endpoints will support and check for duplicate endpoints.
3110 spin_lock_irqsave(&xhci->lock, flags);
3111 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3112 num_eps, &num_streams, &changed_ep_bitmask);
3114 xhci_free_command(xhci, config_cmd);
3115 spin_unlock_irqrestore(&xhci->lock, flags);
3118 if (num_streams <= 1) {
3119 xhci_warn(xhci, "WARN: endpoints can't handle "
3120 "more than one stream.\n");
3121 xhci_free_command(xhci, config_cmd);
3122 spin_unlock_irqrestore(&xhci->lock, flags);
3125 vdev = xhci->devs[udev->slot_id];
3126 /* Mark each endpoint as being in transition, so
3127 * xhci_urb_enqueue() will reject all URBs.
3129 for (i = 0; i < num_eps; i++) {
3130 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3131 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3133 spin_unlock_irqrestore(&xhci->lock, flags);
3135 /* Setup internal data structures and allocate HW data structures for
3136 * streams (but don't install the HW structures in the input context
3137 * until we're sure all memory allocation succeeded).
3139 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3140 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3141 num_stream_ctxs, num_streams);
3143 for (i = 0; i < num_eps; i++) {
3144 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3145 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3147 num_streams, mem_flags);
3148 if (!vdev->eps[ep_index].stream_info)
3150 /* Set maxPstreams in endpoint context and update deq ptr to
3151 * point to stream context array. FIXME
3155 /* Set up the input context for a configure endpoint command. */
3156 for (i = 0; i < num_eps; i++) {
3157 struct xhci_ep_ctx *ep_ctx;
3159 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3160 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3162 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3163 vdev->out_ctx, ep_index);
3164 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3165 vdev->eps[ep_index].stream_info);
3167 /* Tell the HW to drop its old copy of the endpoint context info
3168 * and add the updated copy from the input context.
3170 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3171 vdev->out_ctx, ctrl_ctx,
3172 changed_ep_bitmask, changed_ep_bitmask);
3174 /* Issue and wait for the configure endpoint command */
3175 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3178 /* xHC rejected the configure endpoint command for some reason, so we
3179 * leave the old ring intact and free our internal streams data
3185 spin_lock_irqsave(&xhci->lock, flags);
3186 for (i = 0; i < num_eps; i++) {
3187 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3188 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3189 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3190 udev->slot_id, ep_index);
3191 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3193 xhci_free_command(xhci, config_cmd);
3194 spin_unlock_irqrestore(&xhci->lock, flags);
3196 /* Subtract 1 for stream 0, which drivers can't use */
3197 return num_streams - 1;
3200 /* If it didn't work, free the streams! */
3201 for (i = 0; i < num_eps; i++) {
3202 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3203 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3204 vdev->eps[ep_index].stream_info = NULL;
3205 /* FIXME Unset maxPstreams in endpoint context and
3206 * update deq ptr to point to normal string ring.
3208 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3209 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3210 xhci_endpoint_zero(xhci, vdev, eps[i]);
3212 xhci_free_command(xhci, config_cmd);
3216 /* Transition the endpoint from using streams to being a "normal" endpoint
3219 * Modify the endpoint context state, submit a configure endpoint command,
3220 * and free all endpoint rings for streams if that completes successfully.
3222 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3223 struct usb_host_endpoint **eps, unsigned int num_eps,
3227 struct xhci_hcd *xhci;
3228 struct xhci_virt_device *vdev;
3229 struct xhci_command *command;
3230 struct xhci_input_control_ctx *ctrl_ctx;
3231 unsigned int ep_index;
3232 unsigned long flags;
3233 u32 changed_ep_bitmask;
3235 xhci = hcd_to_xhci(hcd);
3236 vdev = xhci->devs[udev->slot_id];
3238 /* Set up a configure endpoint command to remove the streams rings */
3239 spin_lock_irqsave(&xhci->lock, flags);
3240 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3241 udev, eps, num_eps);
3242 if (changed_ep_bitmask == 0) {
3243 spin_unlock_irqrestore(&xhci->lock, flags);
3247 /* Use the xhci_command structure from the first endpoint. We may have
3248 * allocated too many, but the driver may call xhci_free_streams() for
3249 * each endpoint it grouped into one call to xhci_alloc_streams().
3251 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3252 command = vdev->eps[ep_index].stream_info->free_streams_command;
3253 ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx);
3255 spin_unlock_irqrestore(&xhci->lock, flags);
3256 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3261 for (i = 0; i < num_eps; i++) {
3262 struct xhci_ep_ctx *ep_ctx;
3264 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3265 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3266 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3267 EP_GETTING_NO_STREAMS;
3269 xhci_endpoint_copy(xhci, command->in_ctx,
3270 vdev->out_ctx, ep_index);
3271 xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx,
3272 &vdev->eps[ep_index]);
3274 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3275 vdev->out_ctx, ctrl_ctx,
3276 changed_ep_bitmask, changed_ep_bitmask);
3277 spin_unlock_irqrestore(&xhci->lock, flags);
3279 /* Issue and wait for the configure endpoint command,
3280 * which must succeed.
3282 ret = xhci_configure_endpoint(xhci, udev, command,
3285 /* xHC rejected the configure endpoint command for some reason, so we
3286 * leave the streams rings intact.
3291 spin_lock_irqsave(&xhci->lock, flags);
3292 for (i = 0; i < num_eps; i++) {
3293 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3294 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3295 vdev->eps[ep_index].stream_info = NULL;
3296 /* FIXME Unset maxPstreams in endpoint context and
3297 * update deq ptr to point to normal string ring.
3299 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3300 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3302 spin_unlock_irqrestore(&xhci->lock, flags);
3308 * Deletes endpoint resources for endpoints that were active before a Reset
3309 * Device command, or a Disable Slot command. The Reset Device command leaves
3310 * the control endpoint intact, whereas the Disable Slot command deletes it.
3312 * Must be called with xhci->lock held.
3314 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3315 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3318 unsigned int num_dropped_eps = 0;
3319 unsigned int drop_flags = 0;
3321 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3322 if (virt_dev->eps[i].ring) {
3323 drop_flags |= 1 << i;
3327 xhci->num_active_eps -= num_dropped_eps;
3328 if (num_dropped_eps)
3329 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3330 "Dropped %u ep ctxs, flags = 0x%x, "
3332 num_dropped_eps, drop_flags,
3333 xhci->num_active_eps);
3337 * This submits a Reset Device Command, which will set the device state to 0,
3338 * set the device address to 0, and disable all the endpoints except the default
3339 * control endpoint. The USB core should come back and call
3340 * xhci_address_device(), and then re-set up the configuration. If this is
3341 * called because of a usb_reset_and_verify_device(), then the old alternate
3342 * settings will be re-installed through the normal bandwidth allocation
3345 * Wait for the Reset Device command to finish. Remove all structures
3346 * associated with the endpoints that were disabled. Clear the input device
3347 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3349 * If the virt_dev to be reset does not exist or does not match the udev,
3350 * it means the device is lost, possibly due to the xHC restore error and
3351 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3352 * re-allocate the device.
3354 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3357 unsigned long flags;
3358 struct xhci_hcd *xhci;
3359 unsigned int slot_id;
3360 struct xhci_virt_device *virt_dev;
3361 struct xhci_command *reset_device_cmd;
3363 int last_freed_endpoint;
3364 struct xhci_slot_ctx *slot_ctx;
3365 int old_active_eps = 0;
3367 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3370 xhci = hcd_to_xhci(hcd);
3371 slot_id = udev->slot_id;
3372 virt_dev = xhci->devs[slot_id];
3374 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3375 "not exist. Re-allocate the device\n", slot_id);
3376 ret = xhci_alloc_dev(hcd, udev);
3383 if (virt_dev->udev != udev) {
3384 /* If the virt_dev and the udev does not match, this virt_dev
3385 * may belong to another udev.
3386 * Re-allocate the device.
3388 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3389 "not match the udev. Re-allocate the device\n",
3391 ret = xhci_alloc_dev(hcd, udev);
3398 /* If device is not setup, there is no point in resetting it */
3399 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3400 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3401 SLOT_STATE_DISABLED)
3404 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3405 /* Allocate the command structure that holds the struct completion.
3406 * Assume we're in process context, since the normal device reset
3407 * process has to wait for the device anyway. Storage devices are
3408 * reset as part of error handling, so use GFP_NOIO instead of
3411 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3412 if (!reset_device_cmd) {
3413 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3417 /* Attempt to submit the Reset Device command to the command ring */
3418 spin_lock_irqsave(&xhci->lock, flags);
3419 reset_device_cmd->command_trb = xhci->cmd_ring->enqueue;
3421 /* Enqueue pointer can be left pointing to the link TRB,
3422 * we must handle that
3424 if (TRB_TYPE_LINK_LE32(reset_device_cmd->command_trb->link.control))
3425 reset_device_cmd->command_trb =
3426 xhci->cmd_ring->enq_seg->next->trbs;
3428 list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list);
3429 ret = xhci_queue_reset_device(xhci, slot_id);
3431 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3432 list_del(&reset_device_cmd->cmd_list);
3433 spin_unlock_irqrestore(&xhci->lock, flags);
3434 goto command_cleanup;
3436 xhci_ring_cmd_db(xhci);
3437 spin_unlock_irqrestore(&xhci->lock, flags);
3439 /* Wait for the Reset Device command to finish */
3440 timeleft = wait_for_completion_interruptible_timeout(
3441 reset_device_cmd->completion,
3442 USB_CTRL_SET_TIMEOUT);
3443 if (timeleft <= 0) {
3444 xhci_warn(xhci, "%s while waiting for reset device command\n",
3445 timeleft == 0 ? "Timeout" : "Signal");
3446 spin_lock_irqsave(&xhci->lock, flags);
3447 /* The timeout might have raced with the event ring handler, so
3448 * only delete from the list if the item isn't poisoned.
3450 if (reset_device_cmd->cmd_list.next != LIST_POISON1)
3451 list_del(&reset_device_cmd->cmd_list);
3452 spin_unlock_irqrestore(&xhci->lock, flags);
3454 goto command_cleanup;
3457 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3458 * unless we tried to reset a slot ID that wasn't enabled,
3459 * or the device wasn't in the addressed or configured state.
3461 ret = reset_device_cmd->status;
3463 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3464 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3465 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3467 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3468 xhci_dbg(xhci, "Not freeing device rings.\n");
3469 /* Don't treat this as an error. May change my mind later. */
3471 goto command_cleanup;
3473 xhci_dbg(xhci, "Successful reset device command.\n");
3476 if (xhci_is_vendor_info_code(xhci, ret))
3478 xhci_warn(xhci, "Unknown completion code %u for "
3479 "reset device command.\n", ret);
3481 goto command_cleanup;
3484 /* Free up host controller endpoint resources */
3485 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3486 spin_lock_irqsave(&xhci->lock, flags);
3487 /* Don't delete the default control endpoint resources */
3488 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3489 spin_unlock_irqrestore(&xhci->lock, flags);
3492 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3493 last_freed_endpoint = 1;
3494 for (i = 1; i < 31; ++i) {
3495 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3497 if (ep->ep_state & EP_HAS_STREAMS) {
3498 xhci_free_stream_info(xhci, ep->stream_info);
3499 ep->stream_info = NULL;
3500 ep->ep_state &= ~EP_HAS_STREAMS;
3504 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3505 last_freed_endpoint = i;
3507 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3508 xhci_drop_ep_from_interval_table(xhci,
3509 &virt_dev->eps[i].bw_info,
3514 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3516 /* If necessary, update the number of active TTs on this root port */
3517 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3519 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3520 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3524 xhci_free_command(xhci, reset_device_cmd);
3529 * At this point, the struct usb_device is about to go away, the device has
3530 * disconnected, and all traffic has been stopped and the endpoints have been
3531 * disabled. Free any HC data structures associated with that device.
3533 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3535 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3536 struct xhci_virt_device *virt_dev;
3537 unsigned long flags;
3541 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3542 /* If the host is halted due to driver unload, we still need to free the
3545 if (ret <= 0 && ret != -ENODEV)
3548 virt_dev = xhci->devs[udev->slot_id];
3550 /* Stop any wayward timer functions (which may grab the lock) */
3551 for (i = 0; i < 31; ++i) {
3552 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3553 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3556 if (udev->usb2_hw_lpm_enabled) {
3557 xhci_set_usb2_hardware_lpm(hcd, udev, 0);
3558 udev->usb2_hw_lpm_enabled = 0;
3561 spin_lock_irqsave(&xhci->lock, flags);
3562 /* Don't disable the slot if the host controller is dead. */
3563 state = xhci_readl(xhci, &xhci->op_regs->status);
3564 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3565 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3566 xhci_free_virt_device(xhci, udev->slot_id);
3567 spin_unlock_irqrestore(&xhci->lock, flags);
3571 if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
3572 spin_unlock_irqrestore(&xhci->lock, flags);
3573 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3576 xhci_ring_cmd_db(xhci);
3577 spin_unlock_irqrestore(&xhci->lock, flags);
3579 * Event command completion handler will free any data structures
3580 * associated with the slot. XXX Can free sleep?
3585 * Checks if we have enough host controller resources for the default control
3588 * Must be called with xhci->lock held.
3590 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3592 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3593 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3594 "Not enough ep ctxs: "
3595 "%u active, need to add 1, limit is %u.",
3596 xhci->num_active_eps, xhci->limit_active_eps);
3599 xhci->num_active_eps += 1;
3600 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3601 "Adding 1 ep ctx, %u now active.",
3602 xhci->num_active_eps);
3608 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3609 * timed out, or allocating memory failed. Returns 1 on success.
3611 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3613 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3614 unsigned long flags;
3617 union xhci_trb *cmd_trb;
3619 spin_lock_irqsave(&xhci->lock, flags);
3620 cmd_trb = xhci->cmd_ring->dequeue;
3621 ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
3623 spin_unlock_irqrestore(&xhci->lock, flags);
3624 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3627 xhci_ring_cmd_db(xhci);
3628 spin_unlock_irqrestore(&xhci->lock, flags);
3630 /* XXX: how much time for xHC slot assignment? */
3631 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
3632 XHCI_CMD_DEFAULT_TIMEOUT);
3633 if (timeleft <= 0) {
3634 xhci_warn(xhci, "%s while waiting for a slot\n",
3635 timeleft == 0 ? "Timeout" : "Signal");
3636 /* cancel the enable slot request */
3637 return xhci_cancel_cmd(xhci, NULL, cmd_trb);
3640 if (!xhci->slot_id) {
3641 xhci_err(xhci, "Error while assigning device slot ID\n");
3645 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3646 spin_lock_irqsave(&xhci->lock, flags);
3647 ret = xhci_reserve_host_control_ep_resources(xhci);
3649 spin_unlock_irqrestore(&xhci->lock, flags);
3650 xhci_warn(xhci, "Not enough host resources, "
3651 "active endpoint contexts = %u\n",
3652 xhci->num_active_eps);
3655 spin_unlock_irqrestore(&xhci->lock, flags);
3657 /* Use GFP_NOIO, since this function can be called from
3658 * xhci_discover_or_reset_device(), which may be called as part of
3659 * mass storage driver error handling.
3661 if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) {
3662 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3665 udev->slot_id = xhci->slot_id;
3666 /* Is this a LS or FS device under a HS hub? */
3667 /* Hub or peripherial? */
3671 /* Disable slot, if we can do it without mem alloc */
3672 spin_lock_irqsave(&xhci->lock, flags);
3673 if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
3674 xhci_ring_cmd_db(xhci);
3675 spin_unlock_irqrestore(&xhci->lock, flags);
3680 * Issue an Address Device command (which will issue a SetAddress request to
3682 * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
3683 * we should only issue and wait on one address command at the same time.
3685 * We add one to the device address issued by the hardware because the USB core
3686 * uses address 1 for the root hubs (even though they're not really devices).
3688 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3690 unsigned long flags;
3692 struct xhci_virt_device *virt_dev;
3694 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3695 struct xhci_slot_ctx *slot_ctx;
3696 struct xhci_input_control_ctx *ctrl_ctx;
3698 union xhci_trb *cmd_trb;
3700 if (!udev->slot_id) {
3701 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3702 "Bad Slot ID %d", udev->slot_id);
3706 virt_dev = xhci->devs[udev->slot_id];
3708 if (WARN_ON(!virt_dev)) {
3710 * In plug/unplug torture test with an NEC controller,
3711 * a zero-dereference was observed once due to virt_dev = 0.
3712 * Print useful debug rather than crash if it is observed again!
3714 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3719 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3720 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
3722 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3727 * If this is the first Set Address since device plug-in or
3728 * virt_device realloaction after a resume with an xHCI power loss,
3729 * then set up the slot context.
3731 if (!slot_ctx->dev_info)
3732 xhci_setup_addressable_virt_dev(xhci, udev);
3733 /* Otherwise, update the control endpoint ring enqueue pointer. */
3735 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3736 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3737 ctrl_ctx->drop_flags = 0;
3739 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3740 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3742 spin_lock_irqsave(&xhci->lock, flags);
3743 cmd_trb = xhci->cmd_ring->dequeue;
3744 ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma,
3747 spin_unlock_irqrestore(&xhci->lock, flags);
3748 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3749 "FIXME: allocate a command ring segment");
3752 xhci_ring_cmd_db(xhci);
3753 spin_unlock_irqrestore(&xhci->lock, flags);
3755 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3756 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
3757 XHCI_CMD_DEFAULT_TIMEOUT);
3758 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3759 * the SetAddress() "recovery interval" required by USB and aborting the
3760 * command on a timeout.
3762 if (timeleft <= 0) {
3763 xhci_warn(xhci, "%s while waiting for address device command\n",
3764 timeleft == 0 ? "Timeout" : "Signal");
3765 /* cancel the address device command */
3766 ret = xhci_cancel_cmd(xhci, NULL, cmd_trb);
3772 switch (virt_dev->cmd_status) {
3773 case COMP_CTX_STATE:
3775 xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
3780 dev_warn(&udev->dev, "Device not responding to set address.\n");
3784 dev_warn(&udev->dev, "ERROR: Incompatible device for address "
3785 "device command.\n");
3789 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3790 "Successful Address Device command");
3793 xhci_err(xhci, "ERROR: unexpected command completion "
3794 "code 0x%x.\n", virt_dev->cmd_status);
3795 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3796 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3803 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3804 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3805 "Op regs DCBAA ptr = %#016llx", temp_64);
3806 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3807 "Slot ID %d dcbaa entry @%p = %#016llx",
3809 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3810 (unsigned long long)
3811 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3812 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3813 "Output Context DMA address = %#08llx",
3814 (unsigned long long)virt_dev->out_ctx->dma);
3815 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3816 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3817 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3818 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3820 * USB core uses address 1 for the roothubs, so we add one to the
3821 * address given back to us by the HC.
3823 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3824 /* Use kernel assigned address for devices; store xHC assigned
3825 * address locally. */
3826 virt_dev->address = (le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK)
3828 /* Zero the input context control for later use */
3829 ctrl_ctx->add_flags = 0;
3830 ctrl_ctx->drop_flags = 0;
3832 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3833 "Internal device address = %d", virt_dev->address);
3839 * Transfer the port index into real index in the HW port status
3840 * registers. Caculate offset between the port's PORTSC register
3841 * and port status base. Divide the number of per port register
3842 * to get the real index. The raw port number bases 1.
3844 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
3846 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3847 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
3848 __le32 __iomem *addr;
3851 if (hcd->speed != HCD_USB3)
3852 addr = xhci->usb2_ports[port1 - 1];
3854 addr = xhci->usb3_ports[port1 - 1];
3856 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
3861 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
3862 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
3864 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
3865 struct usb_device *udev, u16 max_exit_latency)
3867 struct xhci_virt_device *virt_dev;
3868 struct xhci_command *command;
3869 struct xhci_input_control_ctx *ctrl_ctx;
3870 struct xhci_slot_ctx *slot_ctx;
3871 unsigned long flags;
3874 spin_lock_irqsave(&xhci->lock, flags);
3875 if (max_exit_latency == xhci->devs[udev->slot_id]->current_mel) {
3876 spin_unlock_irqrestore(&xhci->lock, flags);
3880 /* Attempt to issue an Evaluate Context command to change the MEL. */
3881 virt_dev = xhci->devs[udev->slot_id];
3882 command = xhci->lpm_command;
3883 ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx);
3885 spin_unlock_irqrestore(&xhci->lock, flags);
3886 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3891 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
3892 spin_unlock_irqrestore(&xhci->lock, flags);
3894 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3895 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
3896 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
3897 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
3899 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
3900 "Set up evaluate context for LPM MEL change.");
3901 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
3902 xhci_dbg_ctx(xhci, command->in_ctx, 0);
3904 /* Issue and wait for the evaluate context command. */
3905 ret = xhci_configure_endpoint(xhci, udev, command,
3907 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
3908 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
3911 spin_lock_irqsave(&xhci->lock, flags);
3912 virt_dev->current_mel = max_exit_latency;
3913 spin_unlock_irqrestore(&xhci->lock, flags);
3918 #ifdef CONFIG_PM_RUNTIME
3920 /* BESL to HIRD Encoding array for USB2 LPM */
3921 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
3922 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
3924 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
3925 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
3926 struct usb_device *udev)
3928 int u2del, besl, besl_host;
3929 int besl_device = 0;
3932 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
3933 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
3935 if (field & USB_BESL_SUPPORT) {
3936 for (besl_host = 0; besl_host < 16; besl_host++) {
3937 if (xhci_besl_encoding[besl_host] >= u2del)
3940 /* Use baseline BESL value as default */
3941 if (field & USB_BESL_BASELINE_VALID)
3942 besl_device = USB_GET_BESL_BASELINE(field);
3943 else if (field & USB_BESL_DEEP_VALID)
3944 besl_device = USB_GET_BESL_DEEP(field);
3949 besl_host = (u2del - 51) / 75 + 1;
3952 besl = besl_host + besl_device;
3959 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
3960 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
3967 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
3969 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
3970 l1 = udev->l1_params.timeout / 256;
3972 /* device has preferred BESLD */
3973 if (field & USB_BESL_DEEP_VALID) {
3974 besld = USB_GET_BESL_DEEP(field);
3978 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
3981 static int xhci_usb2_software_lpm_test(struct usb_hcd *hcd,
3982 struct usb_device *udev)
3984 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3985 struct dev_info *dev_info;
3986 __le32 __iomem **port_array;
3987 __le32 __iomem *addr, *pm_addr;
3989 unsigned int port_num;
3990 unsigned long flags;
3994 if (hcd->speed == HCD_USB3 || !xhci->sw_lpm_support ||
3998 /* we only support lpm for non-hub device connected to root hub yet */
3999 if (!udev->parent || udev->parent->parent ||
4000 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4003 spin_lock_irqsave(&xhci->lock, flags);
4005 /* Look for devices in lpm_failed_devs list */
4006 dev_id = le16_to_cpu(udev->descriptor.idVendor) << 16 |
4007 le16_to_cpu(udev->descriptor.idProduct);
4008 list_for_each_entry(dev_info, &xhci->lpm_failed_devs, list) {
4009 if (dev_info->dev_id == dev_id) {
4015 port_array = xhci->usb2_ports;
4016 port_num = udev->portnum - 1;
4018 if (port_num > HCS_MAX_PORTS(xhci->hcs_params1)) {
4019 xhci_dbg(xhci, "invalid port number %d\n", udev->portnum);
4025 * Test USB 2.0 software LPM.
4026 * FIXME: some xHCI 1.0 hosts may implement a new register to set up
4027 * hardware-controlled USB 2.0 LPM. See section 5.4.11 and 4.23.5.1.1.1
4028 * in the June 2011 errata release.
4030 xhci_dbg(xhci, "test port %d software LPM\n", port_num);
4032 * Set L1 Device Slot and HIRD/BESL.
4033 * Check device's USB 2.0 extension descriptor to determine whether
4034 * HIRD or BESL shoule be used. See USB2.0 LPM errata.
4036 pm_addr = port_array[port_num] + PORTPMSC;
4037 hird = xhci_calculate_hird_besl(xhci, udev);
4038 temp = PORT_L1DS(udev->slot_id) | PORT_HIRD(hird);
4039 xhci_writel(xhci, temp, pm_addr);
4041 /* Set port link state to U2(L1) */
4042 addr = port_array[port_num];
4043 xhci_set_link_state(xhci, port_array, port_num, XDEV_U2);
4046 spin_unlock_irqrestore(&xhci->lock, flags);
4048 spin_lock_irqsave(&xhci->lock, flags);
4050 /* Check L1 Status */
4051 ret = xhci_handshake(xhci, pm_addr,
4052 PORT_L1S_MASK, PORT_L1S_SUCCESS, 125);
4053 if (ret != -ETIMEDOUT) {
4054 /* enter L1 successfully */
4055 temp = xhci_readl(xhci, addr);
4056 xhci_dbg(xhci, "port %d entered L1 state, port status 0x%x\n",
4060 temp = xhci_readl(xhci, pm_addr);
4061 xhci_dbg(xhci, "port %d software lpm failed, L1 status %d\n",
4062 port_num, temp & PORT_L1S_MASK);
4066 /* Resume the port */
4067 xhci_set_link_state(xhci, port_array, port_num, XDEV_U0);
4069 spin_unlock_irqrestore(&xhci->lock, flags);
4071 spin_lock_irqsave(&xhci->lock, flags);
4074 xhci_test_and_clear_bit(xhci, port_array, port_num, PORT_PLC);
4076 /* Check PORTSC to make sure the device is in the right state */
4078 temp = xhci_readl(xhci, addr);
4079 xhci_dbg(xhci, "resumed port %d status 0x%x\n", port_num, temp);
4080 if (!(temp & PORT_CONNECT) || !(temp & PORT_PE) ||
4081 (temp & PORT_PLS_MASK) != XDEV_U0) {
4082 xhci_dbg(xhci, "port L1 resume fail\n");
4088 /* Insert dev to lpm_failed_devs list */
4089 xhci_warn(xhci, "device LPM test failed, may disconnect and "
4091 dev_info = kzalloc(sizeof(struct dev_info), GFP_ATOMIC);
4096 dev_info->dev_id = dev_id;
4097 INIT_LIST_HEAD(&dev_info->list);
4098 list_add(&dev_info->list, &xhci->lpm_failed_devs);
4100 xhci_ring_device(xhci, udev->slot_id);
4104 spin_unlock_irqrestore(&xhci->lock, flags);
4108 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4109 struct usb_device *udev, int enable)
4111 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4112 __le32 __iomem **port_array;
4113 __le32 __iomem *pm_addr, *hlpm_addr;
4114 u32 pm_val, hlpm_val, field;
4115 unsigned int port_num;
4116 unsigned long flags;
4117 int hird, exit_latency;
4120 if (hcd->speed == HCD_USB3 || !xhci->hw_lpm_support ||
4124 if (!udev->parent || udev->parent->parent ||
4125 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4128 if (udev->usb2_hw_lpm_capable != 1)
4131 spin_lock_irqsave(&xhci->lock, flags);
4133 port_array = xhci->usb2_ports;
4134 port_num = udev->portnum - 1;
4135 pm_addr = port_array[port_num] + PORTPMSC;
4136 pm_val = xhci_readl(xhci, pm_addr);
4137 hlpm_addr = port_array[port_num] + PORTHLPMC;
4138 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4140 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4141 enable ? "enable" : "disable", port_num);
4144 /* Host supports BESL timeout instead of HIRD */
4145 if (udev->usb2_hw_lpm_besl_capable) {
4146 /* if device doesn't have a preferred BESL value use a
4147 * default one which works with mixed HIRD and BESL
4148 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4150 if ((field & USB_BESL_SUPPORT) &&
4151 (field & USB_BESL_BASELINE_VALID))
4152 hird = USB_GET_BESL_BASELINE(field);
4154 hird = udev->l1_params.besl;
4156 exit_latency = xhci_besl_encoding[hird];
4157 spin_unlock_irqrestore(&xhci->lock, flags);
4159 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4160 * input context for link powermanagement evaluate
4161 * context commands. It is protected by hcd->bandwidth
4162 * mutex and is shared by all devices. We need to set
4163 * the max ext latency in USB 2 BESL LPM as well, so
4164 * use the same mutex and xhci_change_max_exit_latency()
4166 mutex_lock(hcd->bandwidth_mutex);
4167 ret = xhci_change_max_exit_latency(xhci, udev,
4169 mutex_unlock(hcd->bandwidth_mutex);
4173 spin_lock_irqsave(&xhci->lock, flags);
4175 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4176 xhci_writel(xhci, hlpm_val, hlpm_addr);
4178 xhci_readl(xhci, hlpm_addr);
4180 hird = xhci_calculate_hird_besl(xhci, udev);
4183 pm_val &= ~PORT_HIRD_MASK;
4184 pm_val |= PORT_HIRD(hird) | PORT_RWE;
4185 xhci_writel(xhci, pm_val, pm_addr);
4186 pm_val = xhci_readl(xhci, pm_addr);
4188 xhci_writel(xhci, pm_val, pm_addr);
4190 xhci_readl(xhci, pm_addr);
4192 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK);
4193 xhci_writel(xhci, pm_val, pm_addr);
4195 xhci_readl(xhci, pm_addr);
4196 if (udev->usb2_hw_lpm_besl_capable) {
4197 spin_unlock_irqrestore(&xhci->lock, flags);
4198 mutex_lock(hcd->bandwidth_mutex);
4199 xhci_change_max_exit_latency(xhci, udev, 0);
4200 mutex_unlock(hcd->bandwidth_mutex);
4205 spin_unlock_irqrestore(&xhci->lock, flags);
4209 /* check if a usb2 port supports a given extened capability protocol
4210 * only USB2 ports extended protocol capability values are cached.
4211 * Return 1 if capability is supported
4213 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4214 unsigned capability)
4216 u32 port_offset, port_count;
4219 for (i = 0; i < xhci->num_ext_caps; i++) {
4220 if (xhci->ext_caps[i] & capability) {
4221 /* port offsets starts at 1 */
4222 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4223 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4224 if (port >= port_offset &&
4225 port < port_offset + port_count)
4232 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4234 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4236 int portnum = udev->portnum - 1;
4238 ret = xhci_usb2_software_lpm_test(hcd, udev);
4240 xhci_dbg(xhci, "software LPM test succeed\n");
4241 if (xhci->hw_lpm_support == 1 &&
4242 xhci_check_usb2_port_capability(xhci, portnum, XHCI_HLC)) {
4243 udev->usb2_hw_lpm_capable = 1;
4244 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4245 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4246 if (xhci_check_usb2_port_capability(xhci, portnum,
4248 udev->usb2_hw_lpm_besl_capable = 1;
4249 ret = xhci_set_usb2_hardware_lpm(hcd, udev, 1);
4251 udev->usb2_hw_lpm_enabled = 1;
4260 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4261 struct usb_device *udev, int enable)
4266 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4271 #endif /* CONFIG_PM_RUNTIME */
4273 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4276 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4277 static unsigned long long xhci_service_interval_to_ns(
4278 struct usb_endpoint_descriptor *desc)
4280 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4283 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4284 enum usb3_link_state state)
4286 unsigned long long sel;
4287 unsigned long long pel;
4288 unsigned int max_sel_pel;
4293 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4294 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4295 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4296 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4300 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4301 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4302 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4306 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4308 return USB3_LPM_DISABLED;
4311 if (sel <= max_sel_pel && pel <= max_sel_pel)
4312 return USB3_LPM_DEVICE_INITIATED;
4314 if (sel > max_sel_pel)
4315 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4316 "due to long SEL %llu ms\n",
4319 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4320 "due to long PEL %llu ms\n",
4322 return USB3_LPM_DISABLED;
4325 /* Returns the hub-encoded U1 timeout value.
4326 * The U1 timeout should be the maximum of the following values:
4327 * - For control endpoints, U1 system exit latency (SEL) * 3
4328 * - For bulk endpoints, U1 SEL * 5
4329 * - For interrupt endpoints:
4330 * - Notification EPs, U1 SEL * 3
4331 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4332 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4334 static u16 xhci_calculate_intel_u1_timeout(struct usb_device *udev,
4335 struct usb_endpoint_descriptor *desc)
4337 unsigned long long timeout_ns;
4341 ep_type = usb_endpoint_type(desc);
4343 case USB_ENDPOINT_XFER_CONTROL:
4344 timeout_ns = udev->u1_params.sel * 3;
4346 case USB_ENDPOINT_XFER_BULK:
4347 timeout_ns = udev->u1_params.sel * 5;
4349 case USB_ENDPOINT_XFER_INT:
4350 intr_type = usb_endpoint_interrupt_type(desc);
4351 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4352 timeout_ns = udev->u1_params.sel * 3;
4355 /* Otherwise the calculation is the same as isoc eps */
4356 case USB_ENDPOINT_XFER_ISOC:
4357 timeout_ns = xhci_service_interval_to_ns(desc);
4358 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4359 if (timeout_ns < udev->u1_params.sel * 2)
4360 timeout_ns = udev->u1_params.sel * 2;
4366 /* The U1 timeout is encoded in 1us intervals. */
4367 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4368 /* Don't return a timeout of zero, because that's USB3_LPM_DISABLED. */
4369 if (timeout_ns == USB3_LPM_DISABLED)
4372 /* If the necessary timeout value is bigger than what we can set in the
4373 * USB 3.0 hub, we have to disable hub-initiated U1.
4375 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4377 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4378 "due to long timeout %llu ms\n", timeout_ns);
4379 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4382 /* Returns the hub-encoded U2 timeout value.
4383 * The U2 timeout should be the maximum of:
4384 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4385 * - largest bInterval of any active periodic endpoint (to avoid going
4386 * into lower power link states between intervals).
4387 * - the U2 Exit Latency of the device
4389 static u16 xhci_calculate_intel_u2_timeout(struct usb_device *udev,
4390 struct usb_endpoint_descriptor *desc)
4392 unsigned long long timeout_ns;
4393 unsigned long long u2_del_ns;
4395 timeout_ns = 10 * 1000 * 1000;
4397 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4398 (xhci_service_interval_to_ns(desc) > timeout_ns))
4399 timeout_ns = xhci_service_interval_to_ns(desc);
4401 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4402 if (u2_del_ns > timeout_ns)
4403 timeout_ns = u2_del_ns;
4405 /* The U2 timeout is encoded in 256us intervals */
4406 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4407 /* If the necessary timeout value is bigger than what we can set in the
4408 * USB 3.0 hub, we have to disable hub-initiated U2.
4410 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4412 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4413 "due to long timeout %llu ms\n", timeout_ns);
4414 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4417 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4418 struct usb_device *udev,
4419 struct usb_endpoint_descriptor *desc,
4420 enum usb3_link_state state,
4423 if (state == USB3_LPM_U1) {
4424 if (xhci->quirks & XHCI_INTEL_HOST)
4425 return xhci_calculate_intel_u1_timeout(udev, desc);
4427 if (xhci->quirks & XHCI_INTEL_HOST)
4428 return xhci_calculate_intel_u2_timeout(udev, desc);
4431 return USB3_LPM_DISABLED;
4434 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4435 struct usb_device *udev,
4436 struct usb_endpoint_descriptor *desc,
4437 enum usb3_link_state state,
4442 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4443 desc, state, timeout);
4445 /* If we found we can't enable hub-initiated LPM, or
4446 * the U1 or U2 exit latency was too high to allow
4447 * device-initiated LPM as well, just stop searching.
4449 if (alt_timeout == USB3_LPM_DISABLED ||
4450 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4451 *timeout = alt_timeout;
4454 if (alt_timeout > *timeout)
4455 *timeout = alt_timeout;
4459 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4460 struct usb_device *udev,
4461 struct usb_host_interface *alt,
4462 enum usb3_link_state state,
4467 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4468 if (xhci_update_timeout_for_endpoint(xhci, udev,
4469 &alt->endpoint[j].desc, state, timeout))
4476 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4477 enum usb3_link_state state)
4479 struct usb_device *parent;
4480 unsigned int num_hubs;
4482 if (state == USB3_LPM_U2)
4485 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4486 for (parent = udev->parent, num_hubs = 0; parent->parent;
4487 parent = parent->parent)
4493 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4494 " below second-tier hub.\n");
4495 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4496 "to decrease power consumption.\n");
4500 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4501 struct usb_device *udev,
4502 enum usb3_link_state state)
4504 if (xhci->quirks & XHCI_INTEL_HOST)
4505 return xhci_check_intel_tier_policy(udev, state);
4509 /* Returns the U1 or U2 timeout that should be enabled.
4510 * If the tier check or timeout setting functions return with a non-zero exit
4511 * code, that means the timeout value has been finalized and we shouldn't look
4512 * at any more endpoints.
4514 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4515 struct usb_device *udev, enum usb3_link_state state)
4517 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4518 struct usb_host_config *config;
4521 u16 timeout = USB3_LPM_DISABLED;
4523 if (state == USB3_LPM_U1)
4525 else if (state == USB3_LPM_U2)
4528 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4533 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4536 /* Gather some information about the currently installed configuration
4537 * and alternate interface settings.
4539 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4543 config = udev->actconfig;
4547 for (i = 0; i < USB_MAXINTERFACES; i++) {
4548 struct usb_driver *driver;
4549 struct usb_interface *intf = config->interface[i];
4554 /* Check if any currently bound drivers want hub-initiated LPM
4557 if (intf->dev.driver) {
4558 driver = to_usb_driver(intf->dev.driver);
4559 if (driver && driver->disable_hub_initiated_lpm) {
4560 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4561 "at request of driver %s\n",
4562 state_name, driver->name);
4563 return xhci_get_timeout_no_hub_lpm(udev, state);
4567 /* Not sure how this could happen... */
4568 if (!intf->cur_altsetting)
4571 if (xhci_update_timeout_for_interface(xhci, udev,
4572 intf->cur_altsetting,
4579 static int calculate_max_exit_latency(struct usb_device *udev,
4580 enum usb3_link_state state_changed,
4581 u16 hub_encoded_timeout)
4583 unsigned long long u1_mel_us = 0;
4584 unsigned long long u2_mel_us = 0;
4585 unsigned long long mel_us = 0;
4591 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4592 hub_encoded_timeout == USB3_LPM_DISABLED);
4593 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4594 hub_encoded_timeout == USB3_LPM_DISABLED);
4596 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4597 hub_encoded_timeout != USB3_LPM_DISABLED);
4598 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4599 hub_encoded_timeout != USB3_LPM_DISABLED);
4601 /* If U1 was already enabled and we're not disabling it,
4602 * or we're going to enable U1, account for the U1 max exit latency.
4604 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4606 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4607 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4609 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4611 if (u1_mel_us > u2_mel_us)
4615 /* xHCI host controller max exit latency field is only 16 bits wide. */
4616 if (mel_us > MAX_EXIT) {
4617 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4618 "is too big.\n", mel_us);
4624 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4625 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4626 struct usb_device *udev, enum usb3_link_state state)
4628 struct xhci_hcd *xhci;
4629 u16 hub_encoded_timeout;
4633 xhci = hcd_to_xhci(hcd);
4634 /* The LPM timeout values are pretty host-controller specific, so don't
4635 * enable hub-initiated timeouts unless the vendor has provided
4636 * information about their timeout algorithm.
4638 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4639 !xhci->devs[udev->slot_id])
4640 return USB3_LPM_DISABLED;
4642 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4643 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4645 /* Max Exit Latency is too big, disable LPM. */
4646 hub_encoded_timeout = USB3_LPM_DISABLED;
4650 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4653 return hub_encoded_timeout;
4656 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4657 struct usb_device *udev, enum usb3_link_state state)
4659 struct xhci_hcd *xhci;
4663 xhci = hcd_to_xhci(hcd);
4664 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4665 !xhci->devs[udev->slot_id])
4668 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4669 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4674 #else /* CONFIG_PM */
4676 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4677 struct usb_device *udev, enum usb3_link_state state)
4679 return USB3_LPM_DISABLED;
4682 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4683 struct usb_device *udev, enum usb3_link_state state)
4687 #endif /* CONFIG_PM */
4689 /*-------------------------------------------------------------------------*/
4691 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4692 * internal data structures for the device.
4694 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4695 struct usb_tt *tt, gfp_t mem_flags)
4697 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4698 struct xhci_virt_device *vdev;
4699 struct xhci_command *config_cmd;
4700 struct xhci_input_control_ctx *ctrl_ctx;
4701 struct xhci_slot_ctx *slot_ctx;
4702 unsigned long flags;
4703 unsigned think_time;
4706 /* Ignore root hubs */
4710 vdev = xhci->devs[hdev->slot_id];
4712 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4715 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4717 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4720 ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
4722 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4724 xhci_free_command(xhci, config_cmd);
4728 spin_lock_irqsave(&xhci->lock, flags);
4729 if (hdev->speed == USB_SPEED_HIGH &&
4730 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4731 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4732 xhci_free_command(xhci, config_cmd);
4733 spin_unlock_irqrestore(&xhci->lock, flags);
4737 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4738 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4739 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4740 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4742 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4743 if (xhci->hci_version > 0x95) {
4744 xhci_dbg(xhci, "xHCI version %x needs hub "
4745 "TT think time and number of ports\n",
4746 (unsigned int) xhci->hci_version);
4747 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4748 /* Set TT think time - convert from ns to FS bit times.
4749 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4750 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4752 * xHCI 1.0: this field shall be 0 if the device is not a
4755 think_time = tt->think_time;
4756 if (think_time != 0)
4757 think_time = (think_time / 666) - 1;
4758 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4759 slot_ctx->tt_info |=
4760 cpu_to_le32(TT_THINK_TIME(think_time));
4762 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4763 "TT think time or number of ports\n",
4764 (unsigned int) xhci->hci_version);
4766 slot_ctx->dev_state = 0;
4767 spin_unlock_irqrestore(&xhci->lock, flags);
4769 xhci_dbg(xhci, "Set up %s for hub device.\n",
4770 (xhci->hci_version > 0x95) ?
4771 "configure endpoint" : "evaluate context");
4772 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4773 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4775 /* Issue and wait for the configure endpoint or
4776 * evaluate context command.
4778 if (xhci->hci_version > 0x95)
4779 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4782 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4785 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4786 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4788 xhci_free_command(xhci, config_cmd);
4792 int xhci_get_frame(struct usb_hcd *hcd)
4794 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4795 /* EHCI mods by the periodic size. Why? */
4796 return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
4799 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4801 struct xhci_hcd *xhci;
4802 struct device *dev = hcd->self.controller;
4806 /* Accept arbitrarily long scatter-gather lists */
4807 hcd->self.sg_tablesize = ~0;
4808 /* XHCI controllers don't stop the ep queue on short packets :| */
4809 hcd->self.no_stop_on_short = 1;
4811 if (usb_hcd_is_primary_hcd(hcd)) {
4812 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
4815 *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
4816 xhci->main_hcd = hcd;
4817 /* Mark the first roothub as being USB 2.0.
4818 * The xHCI driver will register the USB 3.0 roothub.
4820 hcd->speed = HCD_USB2;
4821 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4823 * USB 2.0 roothub under xHCI has an integrated TT,
4824 * (rate matching hub) as opposed to having an OHCI/UHCI
4825 * companion controller.
4829 /* xHCI private pointer was set in xhci_pci_probe for the second
4830 * registered roothub.
4832 xhci = hcd_to_xhci(hcd);
4833 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4834 if (HCC_64BIT_ADDR(temp)) {
4835 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4836 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
4838 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
4843 xhci->cap_regs = hcd->regs;
4844 xhci->op_regs = hcd->regs +
4845 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
4846 xhci->run_regs = hcd->regs +
4847 (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4848 /* Cache read-only capability registers */
4849 xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
4850 xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
4851 xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
4852 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
4853 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4854 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4855 xhci_print_registers(xhci);
4857 get_quirks(dev, xhci);
4859 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4860 * success event after a short transfer. This quirk will ignore such
4863 if (xhci->hci_version > 0x96)
4864 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4866 /* Make sure the HC is halted. */
4867 retval = xhci_halt(xhci);
4871 xhci_dbg(xhci, "Resetting HCD\n");
4872 /* Reset the internal HC memory state and registers. */
4873 retval = xhci_reset(xhci);
4876 xhci_dbg(xhci, "Reset complete\n");
4878 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4879 if (HCC_64BIT_ADDR(temp)) {
4880 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4881 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
4883 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
4886 xhci_dbg(xhci, "Calling HCD init\n");
4887 /* Initialize HCD and host controller data structures. */
4888 retval = xhci_init(hcd);
4891 xhci_dbg(xhci, "Called HCD init\n");
4898 MODULE_DESCRIPTION(DRIVER_DESC);
4899 MODULE_AUTHOR(DRIVER_AUTHOR);
4900 MODULE_LICENSE("GPL");
4902 static int __init xhci_hcd_init(void)
4906 retval = xhci_register_pci();
4908 pr_debug("Problem registering PCI driver.\n");
4911 retval = xhci_register_plat();
4913 pr_debug("Problem registering platform driver.\n");
4917 * Check the compiler generated sizes of structures that must be laid
4918 * out in specific ways for hardware access.
4920 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
4921 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
4922 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
4923 /* xhci_device_control has eight fields, and also
4924 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
4926 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
4927 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
4928 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
4929 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
4930 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
4931 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
4932 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
4935 xhci_unregister_pci();
4938 module_init(xhci_hcd_init);
4940 static void __exit xhci_hcd_cleanup(void)
4942 xhci_unregister_pci();
4943 xhci_unregister_plat();
4945 module_exit(xhci_hcd_cleanup);