2 * MUSB OTG controller driver for Blackfin Processors
4 * Copyright 2006-2008 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
14 #include <linux/init.h>
15 #include <linux/list.h>
16 #include <linux/gpio.h>
18 #include <linux/err.h>
19 #include <linux/platform_device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/prefetch.h>
22 #include <linux/usb/nop-usb-xceiv.h>
24 #include <asm/cacheflush.h>
26 #include "musb_core.h"
27 #include "musbhsdma.h"
32 struct platform_device *musb;
34 #define glue_to_musb(g) platform_get_drvdata(g->musb)
37 * Load an endpoint's FIFO
39 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
41 struct musb *musb = hw_ep->musb;
42 void __iomem *fifo = hw_ep->fifo;
43 void __iomem *epio = hw_ep->regs;
44 u8 epnum = hw_ep->epnum;
48 musb_writew(epio, MUSB_TXCOUNT, len);
50 dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
51 hw_ep->epnum, fifo, len, src, epio);
53 dump_fifo_data(src, len);
55 if (!ANOMALY_05000380 && epnum != 0) {
58 flush_dcache_range((unsigned long)src,
59 (unsigned long)(src + len));
61 /* Setup DMA address register */
63 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
66 dma_reg = (u32)src >> 16;
67 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
70 /* Setup DMA count register */
71 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
72 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
76 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
77 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
80 /* Wait for compelete */
81 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
84 /* acknowledge dma interrupt */
85 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
89 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
94 if (unlikely((unsigned long)src & 0x01))
95 outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
97 outsw((unsigned long)fifo, src, (len + 1) >> 1);
101 * Unload an endpoint's FIFO
103 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
105 struct musb *musb = hw_ep->musb;
106 void __iomem *fifo = hw_ep->fifo;
107 u8 epnum = hw_ep->epnum;
109 if (ANOMALY_05000467 && epnum != 0) {
112 invalidate_dcache_range((unsigned long)dst,
113 (unsigned long)(dst + len));
115 /* Setup DMA address register */
117 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
120 dma_reg = (u32)dst >> 16;
121 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
124 /* Setup DMA count register */
125 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
126 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
130 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
131 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
134 /* Wait for compelete */
135 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
138 /* acknowledge dma interrupt */
139 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
143 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
147 /* Read the last byte of packet with odd size from address fifo + 4
148 * to trigger 1 byte access to EP0 FIFO.
151 *dst = (u8)inw((unsigned long)fifo + 4);
153 if (unlikely((unsigned long)dst & 0x01))
154 insw_8((unsigned long)fifo, dst, len >> 1);
156 insw((unsigned long)fifo, dst, len >> 1);
159 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
162 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
163 'R', hw_ep->epnum, fifo, len, dst);
165 dump_fifo_data(dst, len);
168 static irqreturn_t blackfin_interrupt(int irq, void *__hci)
171 irqreturn_t retval = IRQ_NONE;
172 struct musb *musb = __hci;
174 spin_lock_irqsave(&musb->lock, flags);
176 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
177 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
178 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
180 if (musb->int_usb || musb->int_tx || musb->int_rx) {
181 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
182 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
183 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
184 retval = musb_interrupt(musb);
187 /* Start sampling ID pin, when plug is removed from MUSB */
188 if ((musb->xceiv->state == OTG_STATE_B_IDLE
189 || musb->xceiv->state == OTG_STATE_A_WAIT_BCON) ||
190 (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
191 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
192 musb->a_wait_bcon = TIMER_DELAY;
195 spin_unlock_irqrestore(&musb->lock, flags);
200 static void musb_conn_timer_handler(unsigned long _musb)
202 struct musb *musb = (void *)_musb;
207 spin_lock_irqsave(&musb->lock, flags);
208 switch (musb->xceiv->state) {
209 case OTG_STATE_A_IDLE:
210 case OTG_STATE_A_WAIT_BCON:
211 /* Start a new session */
212 val = musb_readw(musb->mregs, MUSB_DEVCTL);
213 val &= ~MUSB_DEVCTL_SESSION;
214 musb_writew(musb->mregs, MUSB_DEVCTL, val);
215 val |= MUSB_DEVCTL_SESSION;
216 musb_writew(musb->mregs, MUSB_DEVCTL, val);
217 /* Check if musb is host or peripheral. */
218 val = musb_readw(musb->mregs, MUSB_DEVCTL);
220 if (!(val & MUSB_DEVCTL_BDEVICE)) {
221 gpio_set_value(musb->config->gpio_vrsel, 1);
222 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
224 gpio_set_value(musb->config->gpio_vrsel, 0);
225 /* Ignore VBUSERROR and SUSPEND IRQ */
226 val = musb_readb(musb->mregs, MUSB_INTRUSBE);
227 val &= ~MUSB_INTR_VBUSERROR;
228 musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
230 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
231 musb_writeb(musb->mregs, MUSB_INTRUSB, val);
232 musb->xceiv->state = OTG_STATE_B_IDLE;
234 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
236 case OTG_STATE_B_IDLE:
238 * Start a new session. It seems that MUSB needs taking
239 * some time to recognize the type of the plug inserted?
241 val = musb_readw(musb->mregs, MUSB_DEVCTL);
242 val |= MUSB_DEVCTL_SESSION;
243 musb_writew(musb->mregs, MUSB_DEVCTL, val);
244 val = musb_readw(musb->mregs, MUSB_DEVCTL);
246 if (!(val & MUSB_DEVCTL_BDEVICE)) {
247 gpio_set_value(musb->config->gpio_vrsel, 1);
248 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
250 gpio_set_value(musb->config->gpio_vrsel, 0);
252 /* Ignore VBUSERROR and SUSPEND IRQ */
253 val = musb_readb(musb->mregs, MUSB_INTRUSBE);
254 val &= ~MUSB_INTR_VBUSERROR;
255 musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
257 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
258 musb_writeb(musb->mregs, MUSB_INTRUSB, val);
260 /* Toggle the Soft Conn bit, so that we can response to
261 * the inserting of either A-plug or B-plug.
264 val = musb_readb(musb->mregs, MUSB_POWER);
265 val &= ~MUSB_POWER_SOFTCONN;
266 musb_writeb(musb->mregs, MUSB_POWER, val);
269 val = musb_readb(musb->mregs, MUSB_POWER);
270 val |= MUSB_POWER_SOFTCONN;
271 musb_writeb(musb->mregs, MUSB_POWER, val);
274 /* The delay time is set to 1/4 second by default,
275 * shortening it, if accelerating A-plug detection
276 * is needed in OTG mode.
278 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
282 dev_dbg(musb->controller, "%s state not handled\n",
283 usb_otg_state_string(musb->xceiv->state));
286 spin_unlock_irqrestore(&musb->lock, flags);
288 dev_dbg(musb->controller, "state is %s\n",
289 usb_otg_state_string(musb->xceiv->state));
292 static void bfin_musb_enable(struct musb *musb)
294 /* REVISIT is this really correct ? */
297 static void bfin_musb_disable(struct musb *musb)
301 static void bfin_musb_set_vbus(struct musb *musb, int is_on)
303 int value = musb->config->gpio_vrsel_active;
306 gpio_set_value(musb->config->gpio_vrsel, value);
308 dev_dbg(musb->controller, "VBUS %s, devctl %02x "
309 /* otg %3x conf %08x prcm %08x */ "\n",
310 usb_otg_state_string(musb->xceiv->state),
311 musb_readb(musb->mregs, MUSB_DEVCTL));
314 static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
319 static int bfin_musb_vbus_status(struct musb *musb)
324 static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
329 static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
330 u16 packet_sz, u8 *mode,
331 dma_addr_t *dma_addr, u32 *len)
333 struct musb_dma_channel *musb_channel = channel->private_data;
336 * Anomaly 05000450 might cause data corruption when using DMA
337 * MODE 1 transmits with short packet. So to work around this,
338 * we truncate all MODE 1 transfers down to a multiple of the
339 * max packet size, and then do the last short packet transfer
340 * (if there is any) using MODE 0.
342 if (ANOMALY_05000450) {
343 if (musb_channel->transmit && *mode == 1)
344 *len = *len - (*len % packet_sz);
350 static void bfin_musb_reg_init(struct musb *musb)
352 if (ANOMALY_05000346) {
353 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
357 if (ANOMALY_05000347) {
358 bfin_write_USB_APHY_CNTRL(0x0);
362 /* Configure PLL oscillator register */
363 bfin_write_USB_PLLOSC_CTRL(0x3080 |
364 ((480/musb->config->clkin) << 1));
367 bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
370 bfin_write_USB_EP_NI0_RXMAXP(64);
373 bfin_write_USB_EP_NI0_TXMAXP(64);
376 /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
377 bfin_write_USB_GLOBINTR(0x7);
380 bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
381 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
382 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
383 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
384 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
388 static int bfin_musb_init(struct musb *musb)
392 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
393 * and OTG HOST modes, while rev 1.1 and greater require PE7 to
394 * be low for DEVICE mode and high for HOST mode. We set it high
395 * here because we are in host mode
398 if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
399 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
400 musb->config->gpio_vrsel);
403 gpio_direction_output(musb->config->gpio_vrsel, 0);
405 usb_nop_xceiv_register();
406 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
407 if (IS_ERR_OR_NULL(musb->xceiv)) {
408 gpio_free(musb->config->gpio_vrsel);
409 return -EPROBE_DEFER;
412 bfin_musb_reg_init(musb);
414 setup_timer(&musb_conn_timer, musb_conn_timer_handler,
415 (unsigned long) musb);
417 musb->xceiv->set_power = bfin_musb_set_power;
419 musb->isr = blackfin_interrupt;
420 musb->double_buffer_not_ok = true;
425 static int bfin_musb_exit(struct musb *musb)
427 gpio_free(musb->config->gpio_vrsel);
429 usb_put_phy(musb->xceiv);
430 usb_nop_xceiv_unregister();
434 static const struct musb_platform_ops bfin_ops = {
435 .init = bfin_musb_init,
436 .exit = bfin_musb_exit,
438 .enable = bfin_musb_enable,
439 .disable = bfin_musb_disable,
441 .set_mode = bfin_musb_set_mode,
443 .vbus_status = bfin_musb_vbus_status,
444 .set_vbus = bfin_musb_set_vbus,
446 .adjust_channel_params = bfin_musb_adjust_channel_params,
449 static u64 bfin_dmamask = DMA_BIT_MASK(32);
451 static int bfin_probe(struct platform_device *pdev)
453 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
454 struct platform_device *musb;
455 struct bfin_glue *glue;
459 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
461 dev_err(&pdev->dev, "failed to allocate glue context\n");
465 musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
467 dev_err(&pdev->dev, "failed to allocate musb device\n");
471 musb->dev.parent = &pdev->dev;
472 musb->dev.dma_mask = &bfin_dmamask;
473 musb->dev.coherent_dma_mask = bfin_dmamask;
475 glue->dev = &pdev->dev;
478 pdata->platform_ops = &bfin_ops;
480 platform_set_drvdata(pdev, glue);
482 ret = platform_device_add_resources(musb, pdev->resource,
483 pdev->num_resources);
485 dev_err(&pdev->dev, "failed to add resources\n");
489 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
491 dev_err(&pdev->dev, "failed to add platform_data\n");
495 ret = platform_device_add(musb);
497 dev_err(&pdev->dev, "failed to register musb device\n");
504 platform_device_put(musb);
513 static int bfin_remove(struct platform_device *pdev)
515 struct bfin_glue *glue = platform_get_drvdata(pdev);
517 platform_device_unregister(glue->musb);
524 static int bfin_suspend(struct device *dev)
526 struct bfin_glue *glue = dev_get_drvdata(dev);
527 struct musb *musb = glue_to_musb(glue);
529 if (is_host_active(musb))
531 * During hibernate gpio_vrsel will change from high to low
532 * low which will generate wakeup event resume the system
533 * immediately. Set it to 0 before hibernate to avoid this
536 gpio_set_value(musb->config->gpio_vrsel, 0);
541 static int bfin_resume(struct device *dev)
543 struct bfin_glue *glue = dev_get_drvdata(dev);
544 struct musb *musb = glue_to_musb(glue);
546 bfin_musb_reg_init(musb);
551 static struct dev_pm_ops bfin_pm_ops = {
552 .suspend = bfin_suspend,
553 .resume = bfin_resume,
556 #define DEV_PM_OPS &bfin_pm_ops
558 #define DEV_PM_OPS NULL
561 static struct platform_driver bfin_driver = {
563 .remove = __exit_p(bfin_remove),
565 .name = "musb-blackfin",
570 MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
571 MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
572 MODULE_LICENSE("GPL v2");
573 module_platform_driver(bfin_driver);