2 * Texas Instruments DA8xx/OMAP-L1x "glue layer"
4 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
6 * Based on the DaVinci "glue layer" code.
7 * Copyright (C) 2005-2006 by Texas Instruments
9 * This file is part of the Inventra Controller Driver for Linux.
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
34 #include <linux/platform_device.h>
35 #include <linux/dma-mapping.h>
37 #include <mach/da8xx.h>
40 #include "musb_core.h"
43 * DA8XX specific definitions
46 /* USB 2.0 OTG module registers */
47 #define DA8XX_USB_REVISION_REG 0x00
48 #define DA8XX_USB_CTRL_REG 0x04
49 #define DA8XX_USB_STAT_REG 0x08
50 #define DA8XX_USB_EMULATION_REG 0x0c
51 #define DA8XX_USB_MODE_REG 0x10 /* Transparent, CDC, [Generic] RNDIS */
52 #define DA8XX_USB_AUTOREQ_REG 0x14
53 #define DA8XX_USB_SRP_FIX_TIME_REG 0x18
54 #define DA8XX_USB_TEARDOWN_REG 0x1c
55 #define DA8XX_USB_INTR_SRC_REG 0x20
56 #define DA8XX_USB_INTR_SRC_SET_REG 0x24
57 #define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
58 #define DA8XX_USB_INTR_MASK_REG 0x2c
59 #define DA8XX_USB_INTR_MASK_SET_REG 0x30
60 #define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
61 #define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
62 #define DA8XX_USB_END_OF_INTR_REG 0x3c
63 #define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
65 /* Control register bits */
66 #define DA8XX_SOFT_RESET_MASK 1
68 #define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */
69 #define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */
71 /* USB interrupt register bits */
72 #define DA8XX_INTR_USB_SHIFT 16
73 #define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
74 /* interrupts and DRVVBUS interrupt */
75 #define DA8XX_INTR_DRVVBUS 0x100
76 #define DA8XX_INTR_RX_SHIFT 8
77 #define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
78 #define DA8XX_INTR_TX_SHIFT 0
79 #define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
81 #define DA8XX_MENTOR_CORE_OFFSET 0x400
83 #define CFGCHIP2 IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG)
87 struct platform_device *musb;
92 * REVISIT (PM): we should be able to keep the PHY in low power mode most
93 * of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
94 * and, when in host mode, autosuspending idle root ports... PHY_PLLON
95 * (overriding SUSPENDM?) then likely needs to stay off.
98 static inline void phy_on(void)
100 u32 cfgchip2 = __raw_readl(CFGCHIP2);
103 * Start the on-chip PHY and its PLL.
105 cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
106 cfgchip2 |= CFGCHIP2_PHY_PLLON;
107 __raw_writel(cfgchip2, CFGCHIP2);
109 pr_info("Waiting for USB PHY clock good...\n");
110 while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
114 static inline void phy_off(void)
116 u32 cfgchip2 = __raw_readl(CFGCHIP2);
119 * Ensure that USB 1.1 reference clock is not being sourced from
120 * USB 2.0 PHY. Otherwise do not power down the PHY.
122 if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) &&
123 (cfgchip2 & CFGCHIP2_USB1SUSPENDM)) {
124 pr_warning("USB 1.1 clocked from USB 2.0 PHY -- "
125 "can't power it down\n");
130 * Power down the on-chip PHY.
132 cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
133 __raw_writel(cfgchip2, CFGCHIP2);
137 * Because we don't set CTRL.UINT, it's "important" to:
138 * - not read/write INTRUSB/INTRUSBE (except during
139 * initial setup, as a workaround);
140 * - use INTSET/INTCLR instead.
144 * da8xx_musb_enable - enable interrupts
146 static void da8xx_musb_enable(struct musb *musb)
148 void __iomem *reg_base = musb->ctrl_base;
151 /* Workaround: setup IRQs through both register sets. */
152 mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
153 ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
155 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
157 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
158 if (is_otg_enabled(musb))
159 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
160 DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
164 * da8xx_musb_disable - disable HDRC and flush interrupts
166 static void da8xx_musb_disable(struct musb *musb)
168 void __iomem *reg_base = musb->ctrl_base;
170 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
171 DA8XX_INTR_USB_MASK |
172 DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
173 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
174 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
177 #define portstate(stmt) stmt
179 static void da8xx_musb_set_vbus(struct musb *musb, int is_on)
181 WARN_ON(is_on && is_peripheral_active(musb));
184 #define POLL_SECONDS 2
186 static struct timer_list otg_workaround;
188 static void otg_timer(unsigned long _musb)
190 struct musb *musb = (void *)_musb;
191 void __iomem *mregs = musb->mregs;
196 * We poll because DaVinci's won't expose several OTG-critical
197 * status change events (from the transceiver) otherwise.
199 devctl = musb_readb(mregs, MUSB_DEVCTL);
200 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
201 otg_state_string(musb->xceiv->state));
203 spin_lock_irqsave(&musb->lock, flags);
204 switch (musb->xceiv->state) {
205 case OTG_STATE_A_WAIT_BCON:
206 devctl &= ~MUSB_DEVCTL_SESSION;
207 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
209 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
210 if (devctl & MUSB_DEVCTL_BDEVICE) {
211 musb->xceiv->state = OTG_STATE_B_IDLE;
214 musb->xceiv->state = OTG_STATE_A_IDLE;
218 case OTG_STATE_A_WAIT_VFALL:
220 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
221 * RTL seems to mis-handle session "start" otherwise (or in
222 * our case "recover"), in routine "VBUS was valid by the time
223 * VBUSERR got reported during enumeration" cases.
225 if (devctl & MUSB_DEVCTL_VBUS) {
226 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
229 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
230 musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
231 MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
233 case OTG_STATE_B_IDLE:
234 if (!is_peripheral_enabled(musb))
238 * There's no ID-changed IRQ, so we have no good way to tell
239 * when to switch to the A-Default state machine (by setting
240 * the DEVCTL.Session bit).
242 * Workaround: whenever we're in B_IDLE, try setting the
243 * session flag every few seconds. If it works, ID was
244 * grounded and we're now in the A-Default state machine.
246 * NOTE: setting the session flag is _supposed_ to trigger
247 * SRP but clearly it doesn't.
249 musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION);
250 devctl = musb_readb(mregs, MUSB_DEVCTL);
251 if (devctl & MUSB_DEVCTL_BDEVICE)
252 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
254 musb->xceiv->state = OTG_STATE_A_IDLE;
259 spin_unlock_irqrestore(&musb->lock, flags);
262 static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
264 static unsigned long last_timer;
266 if (!is_otg_enabled(musb))
270 timeout = jiffies + msecs_to_jiffies(3);
272 /* Never idle if active, or when VBUS timeout is not set as host */
273 if (musb->is_active || (musb->a_wait_bcon == 0 &&
274 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
275 dev_dbg(musb->controller, "%s active, deleting timer\n",
276 otg_state_string(musb->xceiv->state));
277 del_timer(&otg_workaround);
278 last_timer = jiffies;
282 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
283 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
286 last_timer = timeout;
288 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
289 otg_state_string(musb->xceiv->state),
290 jiffies_to_msecs(timeout - jiffies));
291 mod_timer(&otg_workaround, timeout);
294 static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
296 struct musb *musb = hci;
297 void __iomem *reg_base = musb->ctrl_base;
298 struct usb_otg *otg = musb->xceiv->otg;
300 irqreturn_t ret = IRQ_NONE;
303 spin_lock_irqsave(&musb->lock, flags);
306 * NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through
307 * the Mentor registers (except for setup), use the TI ones and EOI.
310 /* Acknowledge and handle non-CPPI interrupts */
311 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
315 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
316 dev_dbg(musb->controller, "USB IRQ %08x\n", status);
318 musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
319 musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
320 musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
323 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
324 * DA8xx's missing ID change IRQ. We need an ID change IRQ to
325 * switch appropriately between halves of the OTG state machine.
326 * Managing DEVCTL.Session per Mentor docs requires that we know its
327 * value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
328 * Also, DRVVBUS pulses for SRP (but not at 5 V)...
330 if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
331 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
332 void __iomem *mregs = musb->mregs;
333 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
336 err = is_host_enabled(musb) && (musb->int_usb &
337 MUSB_INTR_VBUSERROR);
340 * The Mentor core doesn't debounce VBUS as needed
341 * to cope with device connect current spikes. This
342 * means it's not uncommon for bus-powered devices
343 * to get VBUS errors during enumeration.
345 * This is a workaround, but newer RTL from Mentor
346 * seems to allow a better one: "re"-starting sessions
347 * without waiting for VBUS to stop registering in
350 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
351 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
352 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
353 WARNING("VBUS error workaround (delay coming)\n");
354 } else if (is_host_enabled(musb) && drvvbus) {
357 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
358 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
359 del_timer(&otg_workaround);
364 musb->xceiv->state = OTG_STATE_B_IDLE;
365 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
368 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
369 drvvbus ? "on" : "off",
370 otg_state_string(musb->xceiv->state),
376 if (musb->int_tx || musb->int_rx || musb->int_usb)
377 ret |= musb_interrupt(musb);
380 /* EOI needs to be written for the IRQ to be re-asserted. */
381 if (ret == IRQ_HANDLED || status)
382 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
384 /* Poll for ID change */
385 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
386 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
388 spin_unlock_irqrestore(&musb->lock, flags);
393 static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
395 u32 cfgchip2 = __raw_readl(CFGCHIP2);
397 cfgchip2 &= ~CFGCHIP2_OTGMODE;
399 case MUSB_HOST: /* Force VBUS valid, ID = 0 */
400 cfgchip2 |= CFGCHIP2_FORCE_HOST;
402 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
403 cfgchip2 |= CFGCHIP2_FORCE_DEVICE;
405 case MUSB_OTG: /* Don't override the VBUS/ID comparators */
406 cfgchip2 |= CFGCHIP2_NO_OVERRIDE;
409 dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
412 __raw_writel(cfgchip2, CFGCHIP2);
416 static int da8xx_musb_init(struct musb *musb)
418 void __iomem *reg_base = musb->ctrl_base;
421 musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
423 /* Returns zero if e.g. not clocked */
424 rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
428 usb_nop_xceiv_register();
429 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
430 if (IS_ERR_OR_NULL(musb->xceiv))
433 if (is_host_enabled(musb))
434 setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
436 /* Reset the controller */
437 musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
439 /* Start the on-chip PHY and its PLL. */
444 /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
445 pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
446 rev, __raw_readl(CFGCHIP2),
447 musb_readb(reg_base, DA8XX_USB_CTRL_REG));
449 musb->isr = da8xx_musb_interrupt;
455 static int da8xx_musb_exit(struct musb *musb)
457 if (is_host_enabled(musb))
458 del_timer_sync(&otg_workaround);
462 usb_put_phy(musb->xceiv);
463 usb_nop_xceiv_unregister();
468 static const struct musb_platform_ops da8xx_ops = {
469 .init = da8xx_musb_init,
470 .exit = da8xx_musb_exit,
472 .enable = da8xx_musb_enable,
473 .disable = da8xx_musb_disable,
475 .set_mode = da8xx_musb_set_mode,
476 .try_idle = da8xx_musb_try_idle,
478 .set_vbus = da8xx_musb_set_vbus,
481 static u64 da8xx_dmamask = DMA_BIT_MASK(32);
483 static int __devinit da8xx_probe(struct platform_device *pdev)
485 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
486 struct platform_device *musb;
487 struct da8xx_glue *glue;
493 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
495 dev_err(&pdev->dev, "failed to allocate glue context\n");
499 musb = platform_device_alloc("musb-hdrc", -1);
501 dev_err(&pdev->dev, "failed to allocate musb device\n");
505 clk = clk_get(&pdev->dev, "usb20");
507 dev_err(&pdev->dev, "failed to get clock\n");
512 ret = clk_enable(clk);
514 dev_err(&pdev->dev, "failed to enable clock\n");
518 musb->dev.parent = &pdev->dev;
519 musb->dev.dma_mask = &da8xx_dmamask;
520 musb->dev.coherent_dma_mask = da8xx_dmamask;
522 glue->dev = &pdev->dev;
526 pdata->platform_ops = &da8xx_ops;
528 platform_set_drvdata(pdev, glue);
530 ret = platform_device_add_resources(musb, pdev->resource,
531 pdev->num_resources);
533 dev_err(&pdev->dev, "failed to add resources\n");
537 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
539 dev_err(&pdev->dev, "failed to add platform_data\n");
543 ret = platform_device_add(musb);
545 dev_err(&pdev->dev, "failed to register musb device\n");
558 platform_device_put(musb);
567 static int __devexit da8xx_remove(struct platform_device *pdev)
569 struct da8xx_glue *glue = platform_get_drvdata(pdev);
571 platform_device_del(glue->musb);
572 platform_device_put(glue->musb);
573 clk_disable(glue->clk);
580 static struct platform_driver da8xx_driver = {
581 .probe = da8xx_probe,
582 .remove = __devexit_p(da8xx_remove),
584 .name = "musb-da8xx",
588 MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer");
589 MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>");
590 MODULE_LICENSE("GPL v2");
592 static int __init da8xx_init(void)
594 return platform_driver_register(&da8xx_driver);
596 module_init(da8xx_init);
598 static void __exit da8xx_exit(void)
600 platform_driver_unregister(&da8xx_driver);
602 module_exit(da8xx_exit);