1 #include <linux/device.h>
2 #include <linux/dma-mapping.h>
3 #include <linux/dmaengine.h>
4 #include <linux/sizes.h>
5 #include <linux/platform_device.h>
10 #define RNDIS_REG(x) (0x80 + ((x - 1) * 4))
12 #define EP_MODE_AUTOREG_NONE 0
13 #define EP_MODE_AUTOREG_ALL_NEOP 1
14 #define EP_MODE_AUTOREG_ALWAYS 3
16 #define EP_MODE_DMA_TRANSPARENT 0
17 #define EP_MODE_DMA_RNDIS 1
18 #define EP_MODE_DMA_GEN_RNDIS 3
20 #define USB_CTRL_TX_MODE 0x70
21 #define USB_CTRL_RX_MODE 0x74
22 #define USB_CTRL_AUTOREQ 0xd0
23 #define USB_TDOWN 0xd8
25 struct cppi41_dma_channel {
26 struct dma_channel channel;
27 struct cppi41_dma_controller *controller;
28 struct musb_hw_ep *hw_ep;
41 struct list_head tx_check;
44 #define MUSB_DMA_NUM_CHANNELS 15
46 struct cppi41_dma_controller {
47 struct dma_controller controller;
48 struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
49 struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
51 struct hrtimer early_tx;
52 struct list_head early_tx_list;
58 static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
63 if (cppi41_channel->is_tx)
65 if (!is_host_active(cppi41_channel->controller->musb))
68 csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
69 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
71 cppi41_channel->usb_toggle = toggle;
74 static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
76 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
77 struct musb *musb = hw_ep->musb;
81 if (cppi41_channel->is_tx)
83 if (!is_host_active(musb))
86 musb_ep_select(musb->mregs, hw_ep->epnum);
87 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
88 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
91 * AM335x Advisory 1.0.13: Due to internal synchronisation error the
92 * data toggle may reset from DATA1 to DATA0 during receiving data from
93 * more than one endpoint.
95 if (!toggle && toggle == cppi41_channel->usb_toggle) {
96 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE;
97 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);
98 dev_dbg(cppi41_channel->controller->musb->controller,
99 "Restoring DATA1 toggle.\n");
102 cppi41_channel->usb_toggle = toggle;
105 static bool musb_is_tx_fifo_empty(struct musb_hw_ep *hw_ep)
107 u8 epnum = hw_ep->epnum;
108 struct musb *musb = hw_ep->musb;
109 void __iomem *epio = musb->endpoints[epnum].regs;
112 musb_ep_select(musb->mregs, hw_ep->epnum);
113 csr = musb_readw(epio, MUSB_TXCSR);
114 if (csr & MUSB_TXCSR_TXPKTRDY)
119 static void cppi41_dma_callback(void *private_data);
121 static void cppi41_trans_done(struct cppi41_dma_channel *cppi41_channel)
123 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
124 struct musb *musb = hw_ep->musb;
126 if (!cppi41_channel->prog_len ||
127 (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)) {
130 cppi41_channel->channel.actual_len =
131 cppi41_channel->transferred;
132 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
133 cppi41_channel->channel.rx_packet_done = true;
134 musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx);
136 /* next iteration, reload */
137 struct dma_chan *dc = cppi41_channel->dc;
138 struct dma_async_tx_descriptor *dma_desc;
139 enum dma_transfer_direction direction;
142 void __iomem *epio = cppi41_channel->hw_ep->regs;
144 cppi41_channel->buf_addr += cppi41_channel->packet_sz;
146 remain_bytes = cppi41_channel->total_len;
147 remain_bytes -= cppi41_channel->transferred;
148 remain_bytes = min(remain_bytes, cppi41_channel->packet_sz);
149 cppi41_channel->prog_len = remain_bytes;
151 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV
153 dma_desc = dmaengine_prep_slave_single(dc,
154 cppi41_channel->buf_addr,
157 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
158 if (WARN_ON(!dma_desc))
161 dma_desc->callback = cppi41_dma_callback;
162 dma_desc->callback_param = &cppi41_channel->channel;
163 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
164 dma_async_issue_pending(dc);
166 if (!cppi41_channel->is_tx) {
167 musb_ep_select(musb->mregs, hw_ep->epnum);
168 csr = musb_readw(epio, MUSB_RXCSR);
169 csr |= MUSB_RXCSR_H_REQPKT;
170 musb_writew(epio, MUSB_RXCSR, csr);
175 static enum hrtimer_restart cppi41_recheck_tx_req(struct hrtimer *timer)
177 struct cppi41_dma_controller *controller;
178 struct cppi41_dma_channel *cppi41_channel, *n;
181 enum hrtimer_restart ret = HRTIMER_NORESTART;
183 controller = container_of(timer, struct cppi41_dma_controller,
185 musb = controller->musb;
187 spin_lock_irqsave(&musb->lock, flags);
188 list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list,
191 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
193 empty = musb_is_tx_fifo_empty(hw_ep);
195 list_del_init(&cppi41_channel->tx_check);
196 cppi41_trans_done(cppi41_channel);
200 if (!list_empty(&controller->early_tx_list)) {
201 ret = HRTIMER_RESTART;
202 hrtimer_forward_now(&controller->early_tx,
203 ktime_set(0, 50 * NSEC_PER_USEC));
206 spin_unlock_irqrestore(&musb->lock, flags);
210 static void cppi41_dma_callback(void *private_data)
212 struct dma_channel *channel = private_data;
213 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
214 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
215 struct musb *musb = hw_ep->musb;
217 struct dma_tx_state txstate;
221 spin_lock_irqsave(&musb->lock, flags);
223 dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
225 transferred = cppi41_channel->prog_len - txstate.residue;
226 cppi41_channel->transferred += transferred;
228 dev_dbg(musb->controller, "DMA transfer done on hw_ep=%d bytes=%d/%d\n",
229 hw_ep->epnum, cppi41_channel->transferred,
230 cppi41_channel->total_len);
232 update_rx_toggle(cppi41_channel);
234 if (cppi41_channel->transferred == cppi41_channel->total_len ||
235 transferred < cppi41_channel->packet_sz)
236 cppi41_channel->prog_len = 0;
238 empty = musb_is_tx_fifo_empty(hw_ep);
240 cppi41_trans_done(cppi41_channel);
242 struct cppi41_dma_controller *controller;
244 * On AM335x it has been observed that the TX interrupt fires
245 * too early that means the TXFIFO is not yet empty but the DMA
246 * engine says that it is done with the transfer. We don't
247 * receive a FIFO empty interrupt so the only thing we can do is
248 * to poll for the bit. On HS it usually takes 2us, on FS around
249 * 110us - 150us depending on the transfer size.
250 * We spin on HS (no longer than than 25us and setup a timer on
251 * FS to check for the bit and complete the transfer.
253 controller = cppi41_channel->controller;
255 if (musb->g.speed == USB_SPEED_HIGH) {
259 empty = musb_is_tx_fifo_empty(hw_ep);
268 empty = musb_is_tx_fifo_empty(hw_ep);
270 cppi41_trans_done(cppi41_channel);
274 list_add_tail(&cppi41_channel->tx_check,
275 &controller->early_tx_list);
276 if (!hrtimer_is_queued(&controller->early_tx)) {
277 unsigned long usecs = cppi41_channel->total_len / 10;
279 hrtimer_start_range_ns(&controller->early_tx,
280 ktime_set(0, usecs * NSEC_PER_USEC),
286 spin_unlock_irqrestore(&musb->lock, flags);
289 static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old)
293 shift = (ep - 1) * 2;
294 old &= ~(3 << shift);
295 old |= mode << shift;
299 static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel,
302 struct cppi41_dma_controller *controller = cppi41_channel->controller;
307 if (cppi41_channel->is_tx)
308 old_mode = controller->tx_mode;
310 old_mode = controller->rx_mode;
311 port = cppi41_channel->port_num;
312 new_mode = update_ep_mode(port, mode, old_mode);
314 if (new_mode == old_mode)
316 if (cppi41_channel->is_tx) {
317 controller->tx_mode = new_mode;
318 musb_writel(controller->musb->ctrl_base, USB_CTRL_TX_MODE,
321 controller->rx_mode = new_mode;
322 musb_writel(controller->musb->ctrl_base, USB_CTRL_RX_MODE,
327 static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel,
330 struct cppi41_dma_controller *controller = cppi41_channel->controller;
335 old_mode = controller->auto_req;
336 port = cppi41_channel->port_num;
337 new_mode = update_ep_mode(port, mode, old_mode);
339 if (new_mode == old_mode)
341 controller->auto_req = new_mode;
342 musb_writel(controller->musb->ctrl_base, USB_CTRL_AUTOREQ, new_mode);
345 static bool cppi41_configure_channel(struct dma_channel *channel,
346 u16 packet_sz, u8 mode,
347 dma_addr_t dma_addr, u32 len)
349 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
350 struct dma_chan *dc = cppi41_channel->dc;
351 struct dma_async_tx_descriptor *dma_desc;
352 enum dma_transfer_direction direction;
353 struct musb *musb = cppi41_channel->controller->musb;
354 unsigned use_gen_rndis = 0;
356 dev_dbg(musb->controller,
357 "configure ep%d/%x packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
358 cppi41_channel->port_num, RNDIS_REG(cppi41_channel->port_num),
359 packet_sz, mode, (unsigned long long) dma_addr,
360 len, cppi41_channel->is_tx);
362 cppi41_channel->buf_addr = dma_addr;
363 cppi41_channel->total_len = len;
364 cppi41_channel->transferred = 0;
365 cppi41_channel->packet_sz = packet_sz;
368 * Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more
369 * than max packet size at a time.
371 if (cppi41_channel->is_tx)
376 if (len > packet_sz) {
377 musb_writel(musb->ctrl_base,
378 RNDIS_REG(cppi41_channel->port_num), len);
380 cppi41_set_dma_mode(cppi41_channel,
381 EP_MODE_DMA_GEN_RNDIS);
384 cppi41_set_autoreq_mode(cppi41_channel,
385 EP_MODE_AUTOREG_ALL_NEOP);
387 musb_writel(musb->ctrl_base,
388 RNDIS_REG(cppi41_channel->port_num), 0);
389 cppi41_set_dma_mode(cppi41_channel,
390 EP_MODE_DMA_TRANSPARENT);
391 cppi41_set_autoreq_mode(cppi41_channel,
392 EP_MODE_AUTOREG_NONE);
396 cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT);
397 cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREG_NONE);
398 len = min_t(u32, packet_sz, len);
400 cppi41_channel->prog_len = len;
401 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
402 dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
403 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
407 dma_desc->callback = cppi41_dma_callback;
408 dma_desc->callback_param = channel;
409 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
410 cppi41_channel->channel.rx_packet_done = false;
412 save_rx_toggle(cppi41_channel);
413 dma_async_issue_pending(dc);
417 static struct dma_channel *cppi41_dma_channel_allocate(struct dma_controller *c,
418 struct musb_hw_ep *hw_ep, u8 is_tx)
420 struct cppi41_dma_controller *controller = container_of(c,
421 struct cppi41_dma_controller, controller);
422 struct cppi41_dma_channel *cppi41_channel = NULL;
423 u8 ch_num = hw_ep->epnum - 1;
425 if (ch_num >= MUSB_DMA_NUM_CHANNELS)
429 cppi41_channel = &controller->tx_channel[ch_num];
431 cppi41_channel = &controller->rx_channel[ch_num];
433 if (!cppi41_channel->dc)
436 if (cppi41_channel->is_allocated)
439 cppi41_channel->hw_ep = hw_ep;
440 cppi41_channel->is_allocated = 1;
442 return &cppi41_channel->channel;
445 static void cppi41_dma_channel_release(struct dma_channel *channel)
447 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
449 if (cppi41_channel->is_allocated) {
450 cppi41_channel->is_allocated = 0;
451 channel->status = MUSB_DMA_STATUS_FREE;
452 channel->actual_len = 0;
456 static int cppi41_dma_channel_program(struct dma_channel *channel,
457 u16 packet_sz, u8 mode,
458 dma_addr_t dma_addr, u32 len)
461 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
464 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
465 channel->status == MUSB_DMA_STATUS_BUSY);
467 if (is_host_active(cppi41_channel->controller->musb)) {
468 if (cppi41_channel->is_tx)
469 hb_mult = cppi41_channel->hw_ep->out_qh->hb_mult;
471 hb_mult = cppi41_channel->hw_ep->in_qh->hb_mult;
474 channel->status = MUSB_DMA_STATUS_BUSY;
475 channel->actual_len = 0;
478 packet_sz = hb_mult * (packet_sz & 0x7FF);
480 ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len);
482 channel->status = MUSB_DMA_STATUS_FREE;
487 static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
488 void *buf, u32 length)
490 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
491 struct cppi41_dma_controller *controller = cppi41_channel->controller;
492 struct musb *musb = controller->musb;
494 if (is_host_active(musb)) {
498 if (cppi41_channel->hw_ep->ep_in.type != USB_ENDPOINT_XFER_BULK)
500 if (cppi41_channel->is_tx)
502 /* AM335x Advisory 1.0.13. No workaround for device RX mode */
506 static int cppi41_dma_channel_abort(struct dma_channel *channel)
508 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
509 struct cppi41_dma_controller *controller = cppi41_channel->controller;
510 struct musb *musb = controller->musb;
511 void __iomem *epio = cppi41_channel->hw_ep->regs;
517 is_tx = cppi41_channel->is_tx;
518 dev_dbg(musb->controller, "abort channel=%d, is_tx=%d\n",
519 cppi41_channel->port_num, is_tx);
521 if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
524 list_del_init(&cppi41_channel->tx_check);
526 csr = musb_readw(epio, MUSB_TXCSR);
527 csr &= ~MUSB_TXCSR_DMAENAB;
528 musb_writew(epio, MUSB_TXCSR, csr);
530 csr = musb_readw(epio, MUSB_RXCSR);
531 csr &= ~(MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_DMAENAB);
532 musb_writew(epio, MUSB_RXCSR, csr);
534 csr = musb_readw(epio, MUSB_RXCSR);
535 if (csr & MUSB_RXCSR_RXPKTRDY) {
536 csr |= MUSB_RXCSR_FLUSHFIFO;
537 musb_writew(epio, MUSB_RXCSR, csr);
538 musb_writew(epio, MUSB_RXCSR, csr);
542 tdbit = 1 << cppi41_channel->port_num;
547 musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
548 ret = dmaengine_terminate_all(cppi41_channel->dc);
549 } while (ret == -EAGAIN);
551 musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
554 csr = musb_readw(epio, MUSB_TXCSR);
555 if (csr & MUSB_TXCSR_TXPKTRDY) {
556 csr |= MUSB_TXCSR_FLUSHFIFO;
557 musb_writew(epio, MUSB_TXCSR, csr);
561 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
565 static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl)
570 for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) {
571 dc = ctrl->tx_channel[i].dc;
573 dma_release_channel(dc);
574 dc = ctrl->rx_channel[i].dc;
576 dma_release_channel(dc);
580 static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller)
582 cppi41_release_all_dma_chans(controller);
585 static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
587 struct musb *musb = controller->musb;
588 struct device *dev = musb->controller;
589 struct device_node *np = dev->of_node;
590 struct cppi41_dma_channel *cppi41_channel;
595 count = of_property_count_strings(np, "dma-names");
599 for (i = 0; i < count; i++) {
601 struct dma_channel *musb_dma;
606 ret = of_property_read_string_index(np, "dma-names", i, &str);
609 if (!strncmp(str, "tx", 2))
611 else if (!strncmp(str, "rx", 2))
614 dev_err(dev, "Wrong dmatype %s\n", str);
617 ret = kstrtouint(str + 2, 0, &port);
622 if (port > MUSB_DMA_NUM_CHANNELS || !port)
625 cppi41_channel = &controller->tx_channel[port - 1];
627 cppi41_channel = &controller->rx_channel[port - 1];
629 cppi41_channel->controller = controller;
630 cppi41_channel->port_num = port;
631 cppi41_channel->is_tx = is_tx;
632 INIT_LIST_HEAD(&cppi41_channel->tx_check);
634 musb_dma = &cppi41_channel->channel;
635 musb_dma->private_data = cppi41_channel;
636 musb_dma->status = MUSB_DMA_STATUS_FREE;
637 musb_dma->max_len = SZ_4M;
639 dc = dma_request_slave_channel(dev, str);
641 dev_err(dev, "Failed to request %s.\n", str);
645 cppi41_channel->dc = dc;
649 cppi41_release_all_dma_chans(controller);
653 void dma_controller_destroy(struct dma_controller *c)
655 struct cppi41_dma_controller *controller = container_of(c,
656 struct cppi41_dma_controller, controller);
658 hrtimer_cancel(&controller->early_tx);
659 cppi41_dma_controller_stop(controller);
663 struct dma_controller *dma_controller_create(struct musb *musb,
666 struct cppi41_dma_controller *controller;
669 if (!musb->controller->of_node) {
670 dev_err(musb->controller, "Need DT for the DMA engine.\n");
674 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
678 hrtimer_init(&controller->early_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
679 controller->early_tx.function = cppi41_recheck_tx_req;
680 INIT_LIST_HEAD(&controller->early_tx_list);
681 controller->musb = musb;
683 controller->controller.channel_alloc = cppi41_dma_channel_allocate;
684 controller->controller.channel_release = cppi41_dma_channel_release;
685 controller->controller.channel_program = cppi41_dma_channel_program;
686 controller->controller.channel_abort = cppi41_dma_channel_abort;
687 controller->controller.is_compatible = cppi41_is_compatible;
689 ret = cppi41_dma_controller_start(controller);
692 return &controller->controller;
697 if (ret == -EPROBE_DEFER)