1 #include <linux/device.h>
2 #include <linux/dma-mapping.h>
3 #include <linux/dmaengine.h>
4 #include <linux/sizes.h>
5 #include <linux/platform_device.h>
10 #define RNDIS_REG(x) (0x80 + ((x - 1) * 4))
12 #define EP_MODE_AUTOREG_NONE 0
13 #define EP_MODE_AUTOREG_ALL_NEOP 1
14 #define EP_MODE_AUTOREG_ALWAYS 3
16 #define EP_MODE_DMA_TRANSPARENT 0
17 #define EP_MODE_DMA_RNDIS 1
18 #define EP_MODE_DMA_GEN_RNDIS 3
20 #define USB_CTRL_TX_MODE 0x70
21 #define USB_CTRL_RX_MODE 0x74
22 #define USB_CTRL_AUTOREQ 0xd0
23 #define USB_TDOWN 0xd8
25 struct cppi41_dma_channel {
26 struct dma_channel channel;
27 struct cppi41_dma_controller *controller;
28 struct musb_hw_ep *hw_ep;
41 struct list_head tx_check;
45 #define MUSB_DMA_NUM_CHANNELS 15
47 struct cppi41_dma_controller {
48 struct dma_controller controller;
49 struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
50 struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
52 struct hrtimer early_tx;
53 struct list_head early_tx_list;
59 static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
64 if (cppi41_channel->is_tx)
66 if (!is_host_active(cppi41_channel->controller->musb))
69 csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
70 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
72 cppi41_channel->usb_toggle = toggle;
75 static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
77 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
78 struct musb *musb = hw_ep->musb;
82 if (cppi41_channel->is_tx)
84 if (!is_host_active(musb))
87 musb_ep_select(musb->mregs, hw_ep->epnum);
88 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
89 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
92 * AM335x Advisory 1.0.13: Due to internal synchronisation error the
93 * data toggle may reset from DATA1 to DATA0 during receiving data from
94 * more than one endpoint.
96 if (!toggle && toggle == cppi41_channel->usb_toggle) {
97 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE;
98 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);
99 dev_dbg(cppi41_channel->controller->musb->controller,
100 "Restoring DATA1 toggle.\n");
103 cppi41_channel->usb_toggle = toggle;
106 static bool musb_is_tx_fifo_empty(struct musb_hw_ep *hw_ep)
108 u8 epnum = hw_ep->epnum;
109 struct musb *musb = hw_ep->musb;
110 void __iomem *epio = musb->endpoints[epnum].regs;
113 musb_ep_select(musb->mregs, hw_ep->epnum);
114 csr = musb_readw(epio, MUSB_TXCSR);
115 if (csr & MUSB_TXCSR_TXPKTRDY)
120 static void cppi41_dma_callback(void *private_data);
122 static void cppi41_trans_done(struct cppi41_dma_channel *cppi41_channel)
124 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
125 struct musb *musb = hw_ep->musb;
126 void __iomem *epio = hw_ep->regs;
129 if (!cppi41_channel->prog_len ||
130 (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)) {
133 cppi41_channel->channel.actual_len =
134 cppi41_channel->transferred;
135 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
136 cppi41_channel->channel.rx_packet_done = true;
139 * transmit ZLP using PIO mode for transfers which size is
140 * multiple of EP packet size.
142 if (cppi41_channel->tx_zlp && (cppi41_channel->transferred %
143 cppi41_channel->packet_sz) == 0) {
144 musb_ep_select(musb->mregs, hw_ep->epnum);
145 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY;
146 musb_writew(epio, MUSB_TXCSR, csr);
148 musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx);
150 /* next iteration, reload */
151 struct dma_chan *dc = cppi41_channel->dc;
152 struct dma_async_tx_descriptor *dma_desc;
153 enum dma_transfer_direction direction;
156 cppi41_channel->buf_addr += cppi41_channel->packet_sz;
158 remain_bytes = cppi41_channel->total_len;
159 remain_bytes -= cppi41_channel->transferred;
160 remain_bytes = min(remain_bytes, cppi41_channel->packet_sz);
161 cppi41_channel->prog_len = remain_bytes;
163 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV
165 dma_desc = dmaengine_prep_slave_single(dc,
166 cppi41_channel->buf_addr,
169 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
170 if (WARN_ON(!dma_desc))
173 dma_desc->callback = cppi41_dma_callback;
174 dma_desc->callback_param = &cppi41_channel->channel;
175 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
176 dma_async_issue_pending(dc);
178 if (!cppi41_channel->is_tx) {
179 musb_ep_select(musb->mregs, hw_ep->epnum);
180 csr = musb_readw(epio, MUSB_RXCSR);
181 csr |= MUSB_RXCSR_H_REQPKT;
182 musb_writew(epio, MUSB_RXCSR, csr);
187 static enum hrtimer_restart cppi41_recheck_tx_req(struct hrtimer *timer)
189 struct cppi41_dma_controller *controller;
190 struct cppi41_dma_channel *cppi41_channel, *n;
193 enum hrtimer_restart ret = HRTIMER_NORESTART;
195 controller = container_of(timer, struct cppi41_dma_controller,
197 musb = controller->musb;
199 spin_lock_irqsave(&musb->lock, flags);
200 list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list,
203 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
205 empty = musb_is_tx_fifo_empty(hw_ep);
207 list_del_init(&cppi41_channel->tx_check);
208 cppi41_trans_done(cppi41_channel);
212 if (!list_empty(&controller->early_tx_list)) {
213 ret = HRTIMER_RESTART;
214 hrtimer_forward_now(&controller->early_tx,
215 ktime_set(0, 50 * NSEC_PER_USEC));
218 spin_unlock_irqrestore(&musb->lock, flags);
222 static void cppi41_dma_callback(void *private_data)
224 struct dma_channel *channel = private_data;
225 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
226 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
227 struct musb *musb = hw_ep->musb;
229 struct dma_tx_state txstate;
233 spin_lock_irqsave(&musb->lock, flags);
235 dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
237 transferred = cppi41_channel->prog_len - txstate.residue;
238 cppi41_channel->transferred += transferred;
240 dev_dbg(musb->controller, "DMA transfer done on hw_ep=%d bytes=%d/%d\n",
241 hw_ep->epnum, cppi41_channel->transferred,
242 cppi41_channel->total_len);
244 update_rx_toggle(cppi41_channel);
246 if (cppi41_channel->transferred == cppi41_channel->total_len ||
247 transferred < cppi41_channel->packet_sz)
248 cppi41_channel->prog_len = 0;
250 empty = musb_is_tx_fifo_empty(hw_ep);
252 cppi41_trans_done(cppi41_channel);
254 struct cppi41_dma_controller *controller;
256 * On AM335x it has been observed that the TX interrupt fires
257 * too early that means the TXFIFO is not yet empty but the DMA
258 * engine says that it is done with the transfer. We don't
259 * receive a FIFO empty interrupt so the only thing we can do is
260 * to poll for the bit. On HS it usually takes 2us, on FS around
261 * 110us - 150us depending on the transfer size.
262 * We spin on HS (no longer than than 25us and setup a timer on
263 * FS to check for the bit and complete the transfer.
265 controller = cppi41_channel->controller;
267 if (musb->g.speed == USB_SPEED_HIGH) {
271 empty = musb_is_tx_fifo_empty(hw_ep);
280 empty = musb_is_tx_fifo_empty(hw_ep);
282 cppi41_trans_done(cppi41_channel);
286 list_add_tail(&cppi41_channel->tx_check,
287 &controller->early_tx_list);
288 if (!hrtimer_is_queued(&controller->early_tx)) {
289 unsigned long usecs = cppi41_channel->total_len / 10;
291 hrtimer_start_range_ns(&controller->early_tx,
292 ktime_set(0, usecs * NSEC_PER_USEC),
298 spin_unlock_irqrestore(&musb->lock, flags);
301 static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old)
305 shift = (ep - 1) * 2;
306 old &= ~(3 << shift);
307 old |= mode << shift;
311 static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel,
314 struct cppi41_dma_controller *controller = cppi41_channel->controller;
319 if (cppi41_channel->is_tx)
320 old_mode = controller->tx_mode;
322 old_mode = controller->rx_mode;
323 port = cppi41_channel->port_num;
324 new_mode = update_ep_mode(port, mode, old_mode);
326 if (new_mode == old_mode)
328 if (cppi41_channel->is_tx) {
329 controller->tx_mode = new_mode;
330 musb_writel(controller->musb->ctrl_base, USB_CTRL_TX_MODE,
333 controller->rx_mode = new_mode;
334 musb_writel(controller->musb->ctrl_base, USB_CTRL_RX_MODE,
339 static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel,
342 struct cppi41_dma_controller *controller = cppi41_channel->controller;
347 old_mode = controller->auto_req;
348 port = cppi41_channel->port_num;
349 new_mode = update_ep_mode(port, mode, old_mode);
351 if (new_mode == old_mode)
353 controller->auto_req = new_mode;
354 musb_writel(controller->musb->ctrl_base, USB_CTRL_AUTOREQ, new_mode);
357 static bool cppi41_configure_channel(struct dma_channel *channel,
358 u16 packet_sz, u8 mode,
359 dma_addr_t dma_addr, u32 len)
361 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
362 struct dma_chan *dc = cppi41_channel->dc;
363 struct dma_async_tx_descriptor *dma_desc;
364 enum dma_transfer_direction direction;
365 struct musb *musb = cppi41_channel->controller->musb;
366 unsigned use_gen_rndis = 0;
368 dev_dbg(musb->controller,
369 "configure ep%d/%x packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
370 cppi41_channel->port_num, RNDIS_REG(cppi41_channel->port_num),
371 packet_sz, mode, (unsigned long long) dma_addr,
372 len, cppi41_channel->is_tx);
374 cppi41_channel->buf_addr = dma_addr;
375 cppi41_channel->total_len = len;
376 cppi41_channel->transferred = 0;
377 cppi41_channel->packet_sz = packet_sz;
378 cppi41_channel->tx_zlp = (cppi41_channel->is_tx && mode) ? 1 : 0;
381 * Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more
382 * than max packet size at a time.
384 if (cppi41_channel->is_tx)
389 if (len > packet_sz) {
390 musb_writel(musb->ctrl_base,
391 RNDIS_REG(cppi41_channel->port_num), len);
393 cppi41_set_dma_mode(cppi41_channel,
394 EP_MODE_DMA_GEN_RNDIS);
397 cppi41_set_autoreq_mode(cppi41_channel,
398 EP_MODE_AUTOREG_ALL_NEOP);
400 musb_writel(musb->ctrl_base,
401 RNDIS_REG(cppi41_channel->port_num), 0);
402 cppi41_set_dma_mode(cppi41_channel,
403 EP_MODE_DMA_TRANSPARENT);
404 cppi41_set_autoreq_mode(cppi41_channel,
405 EP_MODE_AUTOREG_NONE);
409 cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT);
410 cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREG_NONE);
411 len = min_t(u32, packet_sz, len);
413 cppi41_channel->prog_len = len;
414 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
415 dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
416 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
420 dma_desc->callback = cppi41_dma_callback;
421 dma_desc->callback_param = channel;
422 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
423 cppi41_channel->channel.rx_packet_done = false;
425 save_rx_toggle(cppi41_channel);
426 dma_async_issue_pending(dc);
430 static struct dma_channel *cppi41_dma_channel_allocate(struct dma_controller *c,
431 struct musb_hw_ep *hw_ep, u8 is_tx)
433 struct cppi41_dma_controller *controller = container_of(c,
434 struct cppi41_dma_controller, controller);
435 struct cppi41_dma_channel *cppi41_channel = NULL;
436 u8 ch_num = hw_ep->epnum - 1;
438 if (ch_num >= MUSB_DMA_NUM_CHANNELS)
442 cppi41_channel = &controller->tx_channel[ch_num];
444 cppi41_channel = &controller->rx_channel[ch_num];
446 if (!cppi41_channel->dc)
449 if (cppi41_channel->is_allocated)
452 cppi41_channel->hw_ep = hw_ep;
453 cppi41_channel->is_allocated = 1;
455 return &cppi41_channel->channel;
458 static void cppi41_dma_channel_release(struct dma_channel *channel)
460 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
462 if (cppi41_channel->is_allocated) {
463 cppi41_channel->is_allocated = 0;
464 channel->status = MUSB_DMA_STATUS_FREE;
465 channel->actual_len = 0;
469 static int cppi41_dma_channel_program(struct dma_channel *channel,
470 u16 packet_sz, u8 mode,
471 dma_addr_t dma_addr, u32 len)
474 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
477 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
478 channel->status == MUSB_DMA_STATUS_BUSY);
480 if (is_host_active(cppi41_channel->controller->musb)) {
481 if (cppi41_channel->is_tx)
482 hb_mult = cppi41_channel->hw_ep->out_qh->hb_mult;
484 hb_mult = cppi41_channel->hw_ep->in_qh->hb_mult;
487 channel->status = MUSB_DMA_STATUS_BUSY;
488 channel->actual_len = 0;
491 packet_sz = hb_mult * (packet_sz & 0x7FF);
493 ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len);
495 channel->status = MUSB_DMA_STATUS_FREE;
500 static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
501 void *buf, u32 length)
503 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
504 struct cppi41_dma_controller *controller = cppi41_channel->controller;
505 struct musb *musb = controller->musb;
507 if (is_host_active(musb)) {
511 if (cppi41_channel->hw_ep->ep_in.type != USB_ENDPOINT_XFER_BULK)
513 if (cppi41_channel->is_tx)
515 /* AM335x Advisory 1.0.13. No workaround for device RX mode */
519 static int cppi41_dma_channel_abort(struct dma_channel *channel)
521 struct cppi41_dma_channel *cppi41_channel = channel->private_data;
522 struct cppi41_dma_controller *controller = cppi41_channel->controller;
523 struct musb *musb = controller->musb;
524 void __iomem *epio = cppi41_channel->hw_ep->regs;
530 is_tx = cppi41_channel->is_tx;
531 dev_dbg(musb->controller, "abort channel=%d, is_tx=%d\n",
532 cppi41_channel->port_num, is_tx);
534 if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
537 list_del_init(&cppi41_channel->tx_check);
539 csr = musb_readw(epio, MUSB_TXCSR);
540 csr &= ~MUSB_TXCSR_DMAENAB;
541 musb_writew(epio, MUSB_TXCSR, csr);
543 csr = musb_readw(epio, MUSB_RXCSR);
544 csr &= ~(MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_DMAENAB);
545 musb_writew(epio, MUSB_RXCSR, csr);
547 csr = musb_readw(epio, MUSB_RXCSR);
548 if (csr & MUSB_RXCSR_RXPKTRDY) {
549 csr |= MUSB_RXCSR_FLUSHFIFO;
550 musb_writew(epio, MUSB_RXCSR, csr);
551 musb_writew(epio, MUSB_RXCSR, csr);
555 tdbit = 1 << cppi41_channel->port_num;
560 musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
561 ret = dmaengine_terminate_all(cppi41_channel->dc);
562 } while (ret == -EAGAIN);
564 musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
567 csr = musb_readw(epio, MUSB_TXCSR);
568 if (csr & MUSB_TXCSR_TXPKTRDY) {
569 csr |= MUSB_TXCSR_FLUSHFIFO;
570 musb_writew(epio, MUSB_TXCSR, csr);
574 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
578 static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl)
583 for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) {
584 dc = ctrl->tx_channel[i].dc;
586 dma_release_channel(dc);
587 dc = ctrl->rx_channel[i].dc;
589 dma_release_channel(dc);
593 static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller)
595 cppi41_release_all_dma_chans(controller);
598 static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
600 struct musb *musb = controller->musb;
601 struct device *dev = musb->controller;
602 struct device_node *np = dev->of_node;
603 struct cppi41_dma_channel *cppi41_channel;
608 count = of_property_count_strings(np, "dma-names");
612 for (i = 0; i < count; i++) {
614 struct dma_channel *musb_dma;
619 ret = of_property_read_string_index(np, "dma-names", i, &str);
622 if (!strncmp(str, "tx", 2))
624 else if (!strncmp(str, "rx", 2))
627 dev_err(dev, "Wrong dmatype %s\n", str);
630 ret = kstrtouint(str + 2, 0, &port);
635 if (port > MUSB_DMA_NUM_CHANNELS || !port)
638 cppi41_channel = &controller->tx_channel[port - 1];
640 cppi41_channel = &controller->rx_channel[port - 1];
642 cppi41_channel->controller = controller;
643 cppi41_channel->port_num = port;
644 cppi41_channel->is_tx = is_tx;
645 INIT_LIST_HEAD(&cppi41_channel->tx_check);
647 musb_dma = &cppi41_channel->channel;
648 musb_dma->private_data = cppi41_channel;
649 musb_dma->status = MUSB_DMA_STATUS_FREE;
650 musb_dma->max_len = SZ_4M;
652 dc = dma_request_slave_channel(dev, str);
654 dev_err(dev, "Failed to request %s.\n", str);
658 cppi41_channel->dc = dc;
662 cppi41_release_all_dma_chans(controller);
666 void dma_controller_destroy(struct dma_controller *c)
668 struct cppi41_dma_controller *controller = container_of(c,
669 struct cppi41_dma_controller, controller);
671 hrtimer_cancel(&controller->early_tx);
672 cppi41_dma_controller_stop(controller);
676 struct dma_controller *dma_controller_create(struct musb *musb,
679 struct cppi41_dma_controller *controller;
682 if (!musb->controller->of_node) {
683 dev_err(musb->controller, "Need DT for the DMA engine.\n");
687 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
691 hrtimer_init(&controller->early_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
692 controller->early_tx.function = cppi41_recheck_tx_req;
693 INIT_LIST_HEAD(&controller->early_tx_list);
694 controller->musb = musb;
696 controller->controller.channel_alloc = cppi41_dma_channel_allocate;
697 controller->controller.channel_release = cppi41_dma_channel_release;
698 controller->controller.channel_program = cppi41_dma_channel_program;
699 controller->controller.channel_abort = cppi41_dma_channel_abort;
700 controller->controller.is_compatible = cppi41_is_compatible;
702 ret = cppi41_dma_controller_start(controller);
705 return &controller->controller;
710 if (ret == -EPROBE_DEFER)