1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
23 #include <linux/slab.h>
24 #include <linux/interrupt.h>
25 #include <linux/err.h>
26 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/uaccess.h>
30 #include <linux/debugfs.h>
31 #include <linux/seq_file.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/of_device.h>
35 #include <linux/reset.h>
37 #include <linux/usb.h>
38 #include <linux/usb/otg.h>
39 #include <linux/usb/of.h>
40 #include <linux/usb/ulpi.h>
41 #include <linux/usb/gadget.h>
42 #include <linux/usb/hcd.h>
43 #include <linux/usb/msm_hsusb.h>
44 #include <linux/usb/msm_hsusb_hw.h>
45 #include <linux/regulator/consumer.h>
47 #define MSM_USB_BASE (motg->regs)
48 #define DRIVER_NAME "msm_otg"
50 #define ULPI_IO_TIMEOUT_USEC (10 * 1000)
51 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
53 #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
54 #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
55 #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
56 #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
58 #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
59 #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
60 #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
61 #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
63 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
64 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
65 #define USB_PHY_SUSP_DIG_VOL 500000 /* uV */
73 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
78 ret = regulator_set_voltage(motg->vddcx,
79 motg->vdd_levels[VDD_LEVEL_MIN],
80 motg->vdd_levels[VDD_LEVEL_MAX]);
82 dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
86 ret = regulator_enable(motg->vddcx);
88 dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
90 ret = regulator_set_voltage(motg->vddcx, 0,
91 motg->vdd_levels[VDD_LEVEL_MAX]);
93 dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
94 ret = regulator_disable(motg->vddcx);
96 dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
102 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
107 rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN,
108 USB_PHY_3P3_VOL_MAX);
110 dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n");
113 rc = regulator_enable(motg->v3p3);
115 dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
118 rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN,
119 USB_PHY_1P8_VOL_MAX);
121 dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n");
124 rc = regulator_enable(motg->v1p8);
126 dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
133 regulator_disable(motg->v1p8);
135 regulator_disable(motg->v3p3);
140 static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on)
145 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_HPM_LOAD);
147 pr_err("Could not set HPM for v1p8\n");
150 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_HPM_LOAD);
152 pr_err("Could not set HPM for v3p3\n");
153 regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
157 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
159 pr_err("Could not set LPM for v1p8\n");
160 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_LPM_LOAD);
162 pr_err("Could not set LPM for v3p3\n");
165 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
166 return ret < 0 ? ret : 0;
169 static int ulpi_read(struct usb_phy *phy, u32 reg)
171 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
174 /* initiate read operation */
175 writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
178 /* wait for completion */
179 while (cnt < ULPI_IO_TIMEOUT_USEC) {
180 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
186 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
187 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
188 readl(USB_ULPI_VIEWPORT));
191 return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
194 static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
196 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
199 /* initiate write operation */
200 writel(ULPI_RUN | ULPI_WRITE |
201 ULPI_ADDR(reg) | ULPI_DATA(val),
204 /* wait for completion */
205 while (cnt < ULPI_IO_TIMEOUT_USEC) {
206 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
212 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
213 dev_err(phy->dev, "ulpi_write: timeout\n");
219 static struct usb_phy_io_ops msm_otg_io_ops = {
224 static void ulpi_init(struct msm_otg *motg)
226 struct msm_otg_platform_data *pdata = motg->pdata;
227 int *seq = pdata->phy_init_seq, idx;
228 u32 addr = ULPI_EXT_VENDOR_SPECIFIC;
230 for (idx = 0; idx < pdata->phy_init_sz; idx++) {
234 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
235 seq[idx], addr + idx);
236 ulpi_write(&motg->phy, seq[idx], addr + idx);
240 static int msm_phy_notify_disconnect(struct usb_phy *phy,
241 enum usb_device_speed speed)
243 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
246 if (motg->manual_pullup) {
247 val = ULPI_MISC_A_VBUSVLDEXT | ULPI_MISC_A_VBUSVLDEXTSEL;
248 usb_phy_io_write(phy, val, ULPI_CLR(ULPI_MISC_A));
252 * Put the transceiver in non-driving mode. Otherwise host
253 * may not detect soft-disconnection.
255 val = ulpi_read(phy, ULPI_FUNC_CTRL);
256 val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
257 val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
258 ulpi_write(phy, val, ULPI_FUNC_CTRL);
263 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
268 ret = reset_control_assert(motg->link_rst);
270 ret = reset_control_deassert(motg->link_rst);
273 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
274 assert ? "assert" : "deassert");
279 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
284 ret = reset_control_reset(motg->phy_rst);
287 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
292 static int msm_link_reset(struct msm_otg *motg)
297 ret = msm_otg_link_clk_reset(motg, 1);
301 /* wait for 1ms delay as suggested in HPG. */
302 usleep_range(1000, 1200);
304 ret = msm_otg_link_clk_reset(motg, 0);
308 if (motg->phy_number)
309 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
311 /* put transceiver in serial mode as part of reset */
312 val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
313 writel(val | PORTSC_PTS_SERIAL, USB_PORTSC);
318 static int msm_otg_reset(struct usb_phy *phy)
320 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
323 writel(USBCMD_RESET, USB_USBCMD);
324 while (cnt < LINK_RESET_TIMEOUT_USEC) {
325 if (!(readl(USB_USBCMD) & USBCMD_RESET))
330 if (cnt >= LINK_RESET_TIMEOUT_USEC)
333 /* select ULPI phy and clear other status/control bits in PORTSC */
334 writel(PORTSC_PTS_ULPI, USB_PORTSC);
336 writel(0x0, USB_AHBBURST);
337 writel(0x08, USB_AHBMODE);
339 if (motg->phy_number)
340 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
344 static void msm_phy_reset(struct msm_otg *motg)
348 if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY) {
349 msm_otg_phy_clk_reset(motg);
354 if (motg->phy_number)
355 addr = USB_PHY_CTRL2;
357 /* Assert USB PHY_POR */
358 writel(readl(addr) | PHY_POR_ASSERT, addr);
361 * wait for minimum 10 microseconds as suggested in HPG.
362 * Use a slightly larger value since the exact value didn't
363 * work 100% of the time.
367 /* Deassert USB PHY_POR */
368 writel(readl(addr) & ~PHY_POR_ASSERT, addr);
371 static int msm_usb_reset(struct usb_phy *phy)
373 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
376 if (!IS_ERR(motg->core_clk))
377 clk_prepare_enable(motg->core_clk);
379 ret = msm_link_reset(motg);
381 dev_err(phy->dev, "phy_reset failed\n");
385 ret = msm_otg_reset(&motg->phy);
387 dev_err(phy->dev, "link reset failed\n");
393 /* Reset USB PHY after performing USB Link RESET */
396 if (!IS_ERR(motg->core_clk))
397 clk_disable_unprepare(motg->core_clk);
402 static int msm_phy_init(struct usb_phy *phy)
404 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
405 struct msm_otg_platform_data *pdata = motg->pdata;
406 u32 val, ulpi_val = 0;
408 /* Program USB PHY Override registers. */
412 * It is recommended in HPG to reset USB PHY after programming
413 * USB PHY Override registers.
417 if (pdata->otg_control == OTG_PHY_CONTROL) {
418 val = readl(USB_OTGSC);
419 if (pdata->mode == USB_DR_MODE_OTG) {
420 ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
421 val |= OTGSC_IDIE | OTGSC_BSVIE;
422 } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) {
423 ulpi_val = ULPI_INT_SESS_VALID;
426 writel(val, USB_OTGSC);
427 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
428 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
431 if (motg->manual_pullup) {
432 val = ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT;
433 ulpi_write(phy, val, ULPI_SET(ULPI_MISC_A));
435 val = readl(USB_GENCONFIG_2);
436 val |= GENCONFIG_2_SESS_VLD_CTRL_EN;
437 writel(val, USB_GENCONFIG_2);
439 val = readl(USB_USBCMD);
440 val |= USBCMD_SESS_VLD_CTRL;
441 writel(val, USB_USBCMD);
443 val = ulpi_read(phy, ULPI_FUNC_CTRL);
444 val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
445 val |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
446 ulpi_write(phy, val, ULPI_FUNC_CTRL);
449 if (motg->phy_number)
450 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
455 #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
456 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
460 static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high)
462 int max_vol = motg->vdd_levels[VDD_LEVEL_MAX];
467 min_vol = motg->vdd_levels[VDD_LEVEL_MIN];
469 min_vol = motg->vdd_levels[VDD_LEVEL_NONE];
471 ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol);
473 pr_err("Cannot set vddcx voltage\n");
477 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
482 static int msm_otg_suspend(struct msm_otg *motg)
484 struct usb_phy *phy = &motg->phy;
485 struct usb_bus *bus = phy->otg->host;
486 struct msm_otg_platform_data *pdata = motg->pdata;
490 if (atomic_read(&motg->in_lpm))
493 disable_irq(motg->irq);
495 * Chipidea 45-nm PHY suspend sequence:
497 * Interrupt Latch Register auto-clear feature is not present
498 * in all PHY versions. Latch register is clear on read type.
499 * Clear latch register to avoid spurious wakeup from
500 * low power mode (LPM).
502 * PHY comparators are disabled when PHY enters into low power
503 * mode (LPM). Keep PHY comparators ON in LPM only when we expect
504 * VBUS/Id notifications from USB PHY. Otherwise turn off USB
505 * PHY comparators. This save significant amount of power.
507 * PLL is not turned off when PHY enters into low power mode (LPM).
508 * Disable PLL for maximum power savings.
511 if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
512 ulpi_read(phy, 0x14);
513 if (pdata->otg_control == OTG_PHY_CONTROL)
514 ulpi_write(phy, 0x01, 0x30);
515 ulpi_write(phy, 0x08, 0x09);
519 * PHY may take some time or even fail to enter into low power
520 * mode (LPM). Hence poll for 500 msec and reset the PHY and link
523 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
524 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
525 if (readl(USB_PORTSC) & PORTSC_PHCD)
531 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
532 dev_err(phy->dev, "Unable to suspend PHY\n");
534 enable_irq(motg->irq);
539 * PHY has capability to generate interrupt asynchronously in low
540 * power mode (LPM). This interrupt is level triggered. So USB IRQ
541 * line must be disabled till async interrupt enable bit is cleared
542 * in USBCMD register. Assert STP (ULPI interface STOP signal) to
543 * block data communication from PHY.
545 writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
548 if (motg->phy_number)
549 addr = USB_PHY_CTRL2;
551 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
552 motg->pdata->otg_control == OTG_PMIC_CONTROL)
553 writel(readl(addr) | PHY_RETEN, addr);
555 clk_disable_unprepare(motg->pclk);
556 clk_disable_unprepare(motg->clk);
557 if (!IS_ERR(motg->core_clk))
558 clk_disable_unprepare(motg->core_clk);
560 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
561 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
562 msm_hsusb_ldo_set_mode(motg, 0);
563 msm_hsusb_config_vddcx(motg, 0);
566 if (device_may_wakeup(phy->dev))
567 enable_irq_wake(motg->irq);
569 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
571 atomic_set(&motg->in_lpm, 1);
572 enable_irq(motg->irq);
574 dev_info(phy->dev, "USB in low power mode\n");
579 static int msm_otg_resume(struct msm_otg *motg)
581 struct usb_phy *phy = &motg->phy;
582 struct usb_bus *bus = phy->otg->host;
587 if (!atomic_read(&motg->in_lpm))
590 clk_prepare_enable(motg->pclk);
591 clk_prepare_enable(motg->clk);
592 if (!IS_ERR(motg->core_clk))
593 clk_prepare_enable(motg->core_clk);
595 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
596 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
599 if (motg->phy_number)
600 addr = USB_PHY_CTRL2;
602 msm_hsusb_ldo_set_mode(motg, 1);
603 msm_hsusb_config_vddcx(motg, 1);
604 writel(readl(addr) & ~PHY_RETEN, addr);
607 temp = readl(USB_USBCMD);
608 temp &= ~ASYNC_INTR_CTRL;
609 temp &= ~ULPI_STP_CTRL;
610 writel(temp, USB_USBCMD);
613 * PHY comes out of low power mode (LPM) in case of wakeup
614 * from asynchronous interrupt.
616 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
617 goto skip_phy_resume;
619 writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
620 while (cnt < PHY_RESUME_TIMEOUT_USEC) {
621 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
627 if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
629 * This is a fatal error. Reset the link and
630 * PHY. USB state can not be restored. Re-insertion
631 * of USB cable is the only way to get USB working.
633 dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n");
638 if (device_may_wakeup(phy->dev))
639 disable_irq_wake(motg->irq);
641 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
643 atomic_set(&motg->in_lpm, 0);
645 if (motg->async_int) {
647 pm_runtime_put(phy->dev);
648 enable_irq(motg->irq);
651 dev_info(phy->dev, "USB exited from low power mode\n");
657 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
659 if (motg->cur_power == mA)
662 /* TODO: Notify PMIC about available current */
663 dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
664 motg->cur_power = mA;
667 static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
669 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
672 * Gadget driver uses set_power method to notify about the
673 * available current based on suspend/configured states.
675 * IDEV_CHG can be drawn irrespective of suspend/un-configured
676 * states when CDP/ACA is connected.
678 if (motg->chg_type == USB_SDP_CHARGER)
679 msm_otg_notify_charger(motg, mA);
684 static void msm_otg_start_host(struct usb_phy *phy, int on)
686 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
687 struct msm_otg_platform_data *pdata = motg->pdata;
693 hcd = bus_to_hcd(phy->otg->host);
696 dev_dbg(phy->dev, "host on\n");
698 if (pdata->vbus_power)
699 pdata->vbus_power(1);
701 * Some boards have a switch cotrolled by gpio
702 * to enable/disable internal HUB. Enable internal
703 * HUB before kicking the host.
705 if (pdata->setup_gpio)
706 pdata->setup_gpio(OTG_STATE_A_HOST);
708 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
709 device_wakeup_enable(hcd->self.controller);
712 dev_dbg(phy->dev, "host off\n");
717 if (pdata->setup_gpio)
718 pdata->setup_gpio(OTG_STATE_UNDEFINED);
719 if (pdata->vbus_power)
720 pdata->vbus_power(0);
724 static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
726 struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
730 * Fail host registration if this board can support
731 * only peripheral configuration.
733 if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) {
734 dev_info(otg->usb_phy->dev, "Host mode is not supported\n");
739 if (otg->state == OTG_STATE_A_HOST) {
740 pm_runtime_get_sync(otg->usb_phy->dev);
741 msm_otg_start_host(otg->usb_phy, 0);
743 otg->state = OTG_STATE_UNDEFINED;
744 schedule_work(&motg->sm_work);
752 hcd = bus_to_hcd(host);
753 hcd->power_budget = motg->pdata->power_budget;
756 dev_dbg(otg->usb_phy->dev, "host driver registered w/ tranceiver\n");
759 * Kick the state machine work, if peripheral is not supported
760 * or peripheral is already registered with us.
762 if (motg->pdata->mode == USB_DR_MODE_HOST || otg->gadget) {
763 pm_runtime_get_sync(otg->usb_phy->dev);
764 schedule_work(&motg->sm_work);
770 static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
772 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
773 struct msm_otg_platform_data *pdata = motg->pdata;
775 if (!phy->otg->gadget)
779 dev_dbg(phy->dev, "gadget on\n");
781 * Some boards have a switch cotrolled by gpio
782 * to enable/disable internal HUB. Disable internal
783 * HUB before kicking the gadget.
785 if (pdata->setup_gpio)
786 pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
787 usb_gadget_vbus_connect(phy->otg->gadget);
789 dev_dbg(phy->dev, "gadget off\n");
790 usb_gadget_vbus_disconnect(phy->otg->gadget);
791 if (pdata->setup_gpio)
792 pdata->setup_gpio(OTG_STATE_UNDEFINED);
797 static int msm_otg_set_peripheral(struct usb_otg *otg,
798 struct usb_gadget *gadget)
800 struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
803 * Fail peripheral registration if this board can support
804 * only host configuration.
806 if (motg->pdata->mode == USB_DR_MODE_HOST) {
807 dev_info(otg->usb_phy->dev, "Peripheral mode is not supported\n");
812 if (otg->state == OTG_STATE_B_PERIPHERAL) {
813 pm_runtime_get_sync(otg->usb_phy->dev);
814 msm_otg_start_peripheral(otg->usb_phy, 0);
816 otg->state = OTG_STATE_UNDEFINED;
817 schedule_work(&motg->sm_work);
824 otg->gadget = gadget;
825 dev_dbg(otg->usb_phy->dev,
826 "peripheral driver registered w/ tranceiver\n");
829 * Kick the state machine work, if host is not supported
830 * or host is already registered with us.
832 if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL || otg->host) {
833 pm_runtime_get_sync(otg->usb_phy->dev);
834 schedule_work(&motg->sm_work);
840 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
842 struct usb_phy *phy = &motg->phy;
846 switch (motg->pdata->phy_type) {
847 case CI_45NM_INTEGRATED_PHY:
848 chg_det = ulpi_read(phy, 0x34);
849 ret = chg_det & (1 << 4);
851 case SNPS_28NM_INTEGRATED_PHY:
852 chg_det = ulpi_read(phy, 0x87);
861 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
863 struct usb_phy *phy = &motg->phy;
866 switch (motg->pdata->phy_type) {
867 case CI_45NM_INTEGRATED_PHY:
868 chg_det = ulpi_read(phy, 0x34);
869 /* Turn off charger block */
870 chg_det |= ~(1 << 1);
871 ulpi_write(phy, chg_det, 0x34);
873 /* control chg block via ULPI */
874 chg_det &= ~(1 << 3);
875 ulpi_write(phy, chg_det, 0x34);
876 /* put it in host mode for enabling D- source */
877 chg_det &= ~(1 << 2);
878 ulpi_write(phy, chg_det, 0x34);
879 /* Turn on chg detect block */
880 chg_det &= ~(1 << 1);
881 ulpi_write(phy, chg_det, 0x34);
883 /* enable chg detection */
884 chg_det &= ~(1 << 0);
885 ulpi_write(phy, chg_det, 0x34);
887 case SNPS_28NM_INTEGRATED_PHY:
889 * Configure DM as current source, DP as current sink
890 * and enable battery charging comparators.
892 ulpi_write(phy, 0x8, 0x85);
893 ulpi_write(phy, 0x2, 0x85);
894 ulpi_write(phy, 0x1, 0x85);
901 static bool msm_chg_check_primary_det(struct msm_otg *motg)
903 struct usb_phy *phy = &motg->phy;
907 switch (motg->pdata->phy_type) {
908 case CI_45NM_INTEGRATED_PHY:
909 chg_det = ulpi_read(phy, 0x34);
910 ret = chg_det & (1 << 4);
912 case SNPS_28NM_INTEGRATED_PHY:
913 chg_det = ulpi_read(phy, 0x87);
922 static void msm_chg_enable_primary_det(struct msm_otg *motg)
924 struct usb_phy *phy = &motg->phy;
927 switch (motg->pdata->phy_type) {
928 case CI_45NM_INTEGRATED_PHY:
929 chg_det = ulpi_read(phy, 0x34);
930 /* enable chg detection */
931 chg_det &= ~(1 << 0);
932 ulpi_write(phy, chg_det, 0x34);
934 case SNPS_28NM_INTEGRATED_PHY:
936 * Configure DP as current source, DM as current sink
937 * and enable battery charging comparators.
939 ulpi_write(phy, 0x2, 0x85);
940 ulpi_write(phy, 0x1, 0x85);
947 static bool msm_chg_check_dcd(struct msm_otg *motg)
949 struct usb_phy *phy = &motg->phy;
953 switch (motg->pdata->phy_type) {
954 case CI_45NM_INTEGRATED_PHY:
955 line_state = ulpi_read(phy, 0x15);
956 ret = !(line_state & 1);
958 case SNPS_28NM_INTEGRATED_PHY:
959 line_state = ulpi_read(phy, 0x87);
960 ret = line_state & 2;
968 static void msm_chg_disable_dcd(struct msm_otg *motg)
970 struct usb_phy *phy = &motg->phy;
973 switch (motg->pdata->phy_type) {
974 case CI_45NM_INTEGRATED_PHY:
975 chg_det = ulpi_read(phy, 0x34);
976 chg_det &= ~(1 << 5);
977 ulpi_write(phy, chg_det, 0x34);
979 case SNPS_28NM_INTEGRATED_PHY:
980 ulpi_write(phy, 0x10, 0x86);
987 static void msm_chg_enable_dcd(struct msm_otg *motg)
989 struct usb_phy *phy = &motg->phy;
992 switch (motg->pdata->phy_type) {
993 case CI_45NM_INTEGRATED_PHY:
994 chg_det = ulpi_read(phy, 0x34);
995 /* Turn on D+ current source */
997 ulpi_write(phy, chg_det, 0x34);
999 case SNPS_28NM_INTEGRATED_PHY:
1000 /* Data contact detection enable */
1001 ulpi_write(phy, 0x10, 0x85);
1008 static void msm_chg_block_on(struct msm_otg *motg)
1010 struct usb_phy *phy = &motg->phy;
1011 u32 func_ctrl, chg_det;
1013 /* put the controller in non-driving mode */
1014 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1015 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1016 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
1017 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1019 switch (motg->pdata->phy_type) {
1020 case CI_45NM_INTEGRATED_PHY:
1021 chg_det = ulpi_read(phy, 0x34);
1022 /* control chg block via ULPI */
1023 chg_det &= ~(1 << 3);
1024 ulpi_write(phy, chg_det, 0x34);
1025 /* Turn on chg detect block */
1026 chg_det &= ~(1 << 1);
1027 ulpi_write(phy, chg_det, 0x34);
1030 case SNPS_28NM_INTEGRATED_PHY:
1031 /* Clear charger detecting control bits */
1032 ulpi_write(phy, 0x3F, 0x86);
1033 /* Clear alt interrupt latch and enable bits */
1034 ulpi_write(phy, 0x1F, 0x92);
1035 ulpi_write(phy, 0x1F, 0x95);
1043 static void msm_chg_block_off(struct msm_otg *motg)
1045 struct usb_phy *phy = &motg->phy;
1046 u32 func_ctrl, chg_det;
1048 switch (motg->pdata->phy_type) {
1049 case CI_45NM_INTEGRATED_PHY:
1050 chg_det = ulpi_read(phy, 0x34);
1051 /* Turn off charger block */
1052 chg_det |= ~(1 << 1);
1053 ulpi_write(phy, chg_det, 0x34);
1055 case SNPS_28NM_INTEGRATED_PHY:
1056 /* Clear charger detecting control bits */
1057 ulpi_write(phy, 0x3F, 0x86);
1058 /* Clear alt interrupt latch and enable bits */
1059 ulpi_write(phy, 0x1F, 0x92);
1060 ulpi_write(phy, 0x1F, 0x95);
1066 /* put the controller in normal mode */
1067 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1068 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1069 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1070 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1073 #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
1074 #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
1075 #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
1076 #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
1077 static void msm_chg_detect_work(struct work_struct *w)
1079 struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1080 struct usb_phy *phy = &motg->phy;
1081 bool is_dcd, tmout, vout;
1082 unsigned long delay;
1084 dev_dbg(phy->dev, "chg detection work\n");
1085 switch (motg->chg_state) {
1086 case USB_CHG_STATE_UNDEFINED:
1087 pm_runtime_get_sync(phy->dev);
1088 msm_chg_block_on(motg);
1089 msm_chg_enable_dcd(motg);
1090 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1091 motg->dcd_retries = 0;
1092 delay = MSM_CHG_DCD_POLL_TIME;
1094 case USB_CHG_STATE_WAIT_FOR_DCD:
1095 is_dcd = msm_chg_check_dcd(motg);
1096 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1097 if (is_dcd || tmout) {
1098 msm_chg_disable_dcd(motg);
1099 msm_chg_enable_primary_det(motg);
1100 delay = MSM_CHG_PRIMARY_DET_TIME;
1101 motg->chg_state = USB_CHG_STATE_DCD_DONE;
1103 delay = MSM_CHG_DCD_POLL_TIME;
1106 case USB_CHG_STATE_DCD_DONE:
1107 vout = msm_chg_check_primary_det(motg);
1109 msm_chg_enable_secondary_det(motg);
1110 delay = MSM_CHG_SECONDARY_DET_TIME;
1111 motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1113 motg->chg_type = USB_SDP_CHARGER;
1114 motg->chg_state = USB_CHG_STATE_DETECTED;
1118 case USB_CHG_STATE_PRIMARY_DONE:
1119 vout = msm_chg_check_secondary_det(motg);
1121 motg->chg_type = USB_DCP_CHARGER;
1123 motg->chg_type = USB_CDP_CHARGER;
1124 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1126 case USB_CHG_STATE_SECONDARY_DONE:
1127 motg->chg_state = USB_CHG_STATE_DETECTED;
1128 case USB_CHG_STATE_DETECTED:
1129 msm_chg_block_off(motg);
1130 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1131 schedule_work(&motg->sm_work);
1137 schedule_delayed_work(&motg->chg_work, delay);
1141 * We support OTG, Peripheral only and Host only configurations. In case
1142 * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1143 * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1144 * enabled when switch is controlled by user and default mode is supplied
1145 * by board file, which can be changed by userspace later.
1147 static void msm_otg_init_sm(struct msm_otg *motg)
1149 struct msm_otg_platform_data *pdata = motg->pdata;
1150 u32 otgsc = readl(USB_OTGSC);
1152 switch (pdata->mode) {
1153 case USB_DR_MODE_OTG:
1154 if (pdata->otg_control == OTG_PHY_CONTROL) {
1155 if (otgsc & OTGSC_ID)
1156 set_bit(ID, &motg->inputs);
1158 clear_bit(ID, &motg->inputs);
1160 if (otgsc & OTGSC_BSV)
1161 set_bit(B_SESS_VLD, &motg->inputs);
1163 clear_bit(B_SESS_VLD, &motg->inputs);
1164 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1165 set_bit(ID, &motg->inputs);
1166 clear_bit(B_SESS_VLD, &motg->inputs);
1169 case USB_DR_MODE_HOST:
1170 clear_bit(ID, &motg->inputs);
1172 case USB_DR_MODE_PERIPHERAL:
1173 set_bit(ID, &motg->inputs);
1174 if (otgsc & OTGSC_BSV)
1175 set_bit(B_SESS_VLD, &motg->inputs);
1177 clear_bit(B_SESS_VLD, &motg->inputs);
1184 static void msm_otg_sm_work(struct work_struct *w)
1186 struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1187 struct usb_otg *otg = motg->phy.otg;
1189 switch (otg->state) {
1190 case OTG_STATE_UNDEFINED:
1191 dev_dbg(otg->usb_phy->dev, "OTG_STATE_UNDEFINED state\n");
1192 msm_otg_reset(otg->usb_phy);
1193 msm_otg_init_sm(motg);
1194 otg->state = OTG_STATE_B_IDLE;
1196 case OTG_STATE_B_IDLE:
1197 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_IDLE state\n");
1198 if (!test_bit(ID, &motg->inputs) && otg->host) {
1199 /* disable BSV bit */
1200 writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1201 msm_otg_start_host(otg->usb_phy, 1);
1202 otg->state = OTG_STATE_A_HOST;
1203 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1204 switch (motg->chg_state) {
1205 case USB_CHG_STATE_UNDEFINED:
1206 msm_chg_detect_work(&motg->chg_work.work);
1208 case USB_CHG_STATE_DETECTED:
1209 switch (motg->chg_type) {
1210 case USB_DCP_CHARGER:
1211 msm_otg_notify_charger(motg,
1214 case USB_CDP_CHARGER:
1215 msm_otg_notify_charger(motg,
1217 msm_otg_start_peripheral(otg->usb_phy,
1220 = OTG_STATE_B_PERIPHERAL;
1222 case USB_SDP_CHARGER:
1223 msm_otg_notify_charger(motg, IUNIT);
1224 msm_otg_start_peripheral(otg->usb_phy,
1227 = OTG_STATE_B_PERIPHERAL;
1238 * If charger detection work is pending, decrement
1239 * the pm usage counter to balance with the one that
1240 * is incremented in charger detection work.
1242 if (cancel_delayed_work_sync(&motg->chg_work)) {
1243 pm_runtime_put_sync(otg->usb_phy->dev);
1244 msm_otg_reset(otg->usb_phy);
1246 msm_otg_notify_charger(motg, 0);
1247 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1248 motg->chg_type = USB_INVALID_CHARGER;
1251 if (otg->state == OTG_STATE_B_IDLE)
1252 pm_runtime_put_sync(otg->usb_phy->dev);
1254 case OTG_STATE_B_PERIPHERAL:
1255 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1256 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1257 !test_bit(ID, &motg->inputs)) {
1258 msm_otg_notify_charger(motg, 0);
1259 msm_otg_start_peripheral(otg->usb_phy, 0);
1260 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1261 motg->chg_type = USB_INVALID_CHARGER;
1262 otg->state = OTG_STATE_B_IDLE;
1263 msm_otg_reset(otg->usb_phy);
1267 case OTG_STATE_A_HOST:
1268 dev_dbg(otg->usb_phy->dev, "OTG_STATE_A_HOST state\n");
1269 if (test_bit(ID, &motg->inputs)) {
1270 msm_otg_start_host(otg->usb_phy, 0);
1271 otg->state = OTG_STATE_B_IDLE;
1272 msm_otg_reset(otg->usb_phy);
1281 static irqreturn_t msm_otg_irq(int irq, void *data)
1283 struct msm_otg *motg = data;
1284 struct usb_phy *phy = &motg->phy;
1287 if (atomic_read(&motg->in_lpm)) {
1288 disable_irq_nosync(irq);
1289 motg->async_int = 1;
1290 pm_runtime_get(phy->dev);
1294 otgsc = readl(USB_OTGSC);
1295 if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1298 if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1299 if (otgsc & OTGSC_ID)
1300 set_bit(ID, &motg->inputs);
1302 clear_bit(ID, &motg->inputs);
1303 dev_dbg(phy->dev, "ID set/clear\n");
1304 pm_runtime_get_noresume(phy->dev);
1305 } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1306 if (otgsc & OTGSC_BSV)
1307 set_bit(B_SESS_VLD, &motg->inputs);
1309 clear_bit(B_SESS_VLD, &motg->inputs);
1310 dev_dbg(phy->dev, "BSV set/clear\n");
1311 pm_runtime_get_noresume(phy->dev);
1314 writel(otgsc, USB_OTGSC);
1315 schedule_work(&motg->sm_work);
1319 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1321 struct msm_otg *motg = s->private;
1322 struct usb_otg *otg = motg->phy.otg;
1324 switch (otg->state) {
1325 case OTG_STATE_A_HOST:
1326 seq_puts(s, "host\n");
1328 case OTG_STATE_B_PERIPHERAL:
1329 seq_puts(s, "peripheral\n");
1332 seq_puts(s, "none\n");
1339 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1341 return single_open(file, msm_otg_mode_show, inode->i_private);
1344 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1345 size_t count, loff_t *ppos)
1347 struct seq_file *s = file->private_data;
1348 struct msm_otg *motg = s->private;
1350 struct usb_otg *otg = motg->phy.otg;
1352 enum usb_dr_mode req_mode;
1354 memset(buf, 0x00, sizeof(buf));
1356 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1361 if (!strncmp(buf, "host", 4)) {
1362 req_mode = USB_DR_MODE_HOST;
1363 } else if (!strncmp(buf, "peripheral", 10)) {
1364 req_mode = USB_DR_MODE_PERIPHERAL;
1365 } else if (!strncmp(buf, "none", 4)) {
1366 req_mode = USB_DR_MODE_UNKNOWN;
1373 case USB_DR_MODE_UNKNOWN:
1374 switch (otg->state) {
1375 case OTG_STATE_A_HOST:
1376 case OTG_STATE_B_PERIPHERAL:
1377 set_bit(ID, &motg->inputs);
1378 clear_bit(B_SESS_VLD, &motg->inputs);
1384 case USB_DR_MODE_PERIPHERAL:
1385 switch (otg->state) {
1386 case OTG_STATE_B_IDLE:
1387 case OTG_STATE_A_HOST:
1388 set_bit(ID, &motg->inputs);
1389 set_bit(B_SESS_VLD, &motg->inputs);
1395 case USB_DR_MODE_HOST:
1396 switch (otg->state) {
1397 case OTG_STATE_B_IDLE:
1398 case OTG_STATE_B_PERIPHERAL:
1399 clear_bit(ID, &motg->inputs);
1409 pm_runtime_get_sync(otg->usb_phy->dev);
1410 schedule_work(&motg->sm_work);
1415 static const struct file_operations msm_otg_mode_fops = {
1416 .open = msm_otg_mode_open,
1418 .write = msm_otg_mode_write,
1419 .llseek = seq_lseek,
1420 .release = single_release,
1423 static struct dentry *msm_otg_dbg_root;
1424 static struct dentry *msm_otg_dbg_mode;
1426 static int msm_otg_debugfs_init(struct msm_otg *motg)
1428 msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1430 if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1433 msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1434 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1435 if (!msm_otg_dbg_mode) {
1436 debugfs_remove(msm_otg_dbg_root);
1437 msm_otg_dbg_root = NULL;
1444 static void msm_otg_debugfs_cleanup(void)
1446 debugfs_remove(msm_otg_dbg_mode);
1447 debugfs_remove(msm_otg_dbg_root);
1450 static const struct of_device_id msm_otg_dt_match[] = {
1452 .compatible = "qcom,usb-otg-ci",
1453 .data = (void *) CI_45NM_INTEGRATED_PHY
1456 .compatible = "qcom,usb-otg-snps",
1457 .data = (void *) SNPS_28NM_INTEGRATED_PHY
1461 MODULE_DEVICE_TABLE(of, msm_otg_dt_match);
1463 static int msm_otg_vbus_notifier(struct notifier_block *nb, unsigned long event,
1466 struct msm_usb_cable *vbus = container_of(nb, struct msm_usb_cable, nb);
1467 struct msm_otg *motg = container_of(vbus, struct msm_otg, vbus);
1470 set_bit(B_SESS_VLD, &motg->inputs);
1472 clear_bit(B_SESS_VLD, &motg->inputs);
1474 schedule_work(&motg->sm_work);
1479 static int msm_otg_id_notifier(struct notifier_block *nb, unsigned long event,
1482 struct msm_usb_cable *id = container_of(nb, struct msm_usb_cable, nb);
1483 struct msm_otg *motg = container_of(id, struct msm_otg, id);
1486 clear_bit(ID, &motg->inputs);
1488 set_bit(ID, &motg->inputs);
1490 schedule_work(&motg->sm_work);
1495 static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
1497 struct msm_otg_platform_data *pdata;
1498 struct extcon_dev *ext_id, *ext_vbus;
1499 const struct of_device_id *id;
1500 struct device_node *node = pdev->dev.of_node;
1501 struct property *prop;
1502 int len, ret, words;
1505 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1509 motg->pdata = pdata;
1511 id = of_match_device(msm_otg_dt_match, &pdev->dev);
1512 pdata->phy_type = (enum msm_usb_phy_type) id->data;
1514 motg->link_rst = devm_reset_control_get(&pdev->dev, "link");
1515 if (IS_ERR(motg->link_rst))
1516 return PTR_ERR(motg->link_rst);
1518 motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy");
1519 if (IS_ERR(motg->phy_rst))
1520 motg->phy_rst = NULL;
1522 pdata->mode = of_usb_get_dr_mode(node);
1523 if (pdata->mode == USB_DR_MODE_UNKNOWN)
1524 pdata->mode = USB_DR_MODE_OTG;
1526 pdata->otg_control = OTG_PHY_CONTROL;
1527 if (!of_property_read_u32(node, "qcom,otg-control", &val))
1528 if (val == OTG_PMIC_CONTROL)
1529 pdata->otg_control = val;
1531 if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2)
1532 motg->phy_number = val;
1534 motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL;
1535 motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN;
1536 motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX;
1538 if (of_get_property(node, "qcom,vdd-levels", &len) &&
1539 len == sizeof(tmp)) {
1540 of_property_read_u32_array(node, "qcom,vdd-levels",
1541 tmp, len / sizeof(*tmp));
1542 motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE];
1543 motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN];
1544 motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX];
1547 motg->manual_pullup = of_property_read_bool(node, "qcom,manual-pullup");
1549 ext_id = ERR_PTR(-ENODEV);
1550 ext_vbus = ERR_PTR(-ENODEV);
1551 if (of_property_read_bool(node, "extcon")) {
1553 /* Each one of them is not mandatory */
1554 ext_vbus = extcon_get_edev_by_phandle(&pdev->dev, 0);
1555 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
1556 return PTR_ERR(ext_vbus);
1558 ext_id = extcon_get_edev_by_phandle(&pdev->dev, 1);
1559 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
1560 return PTR_ERR(ext_id);
1563 if (!IS_ERR(ext_vbus)) {
1564 motg->vbus.nb.notifier_call = msm_otg_vbus_notifier;
1565 ret = extcon_register_interest(&motg->vbus.conn, ext_vbus->name,
1566 "USB", &motg->vbus.nb);
1568 dev_err(&pdev->dev, "register VBUS notifier failed\n");
1572 ret = extcon_get_cable_state(ext_vbus, "USB");
1574 set_bit(B_SESS_VLD, &motg->inputs);
1576 clear_bit(B_SESS_VLD, &motg->inputs);
1579 if (!IS_ERR(ext_id)) {
1580 motg->id.nb.notifier_call = msm_otg_id_notifier;
1581 ret = extcon_register_interest(&motg->id.conn, ext_id->name,
1582 "USB-HOST", &motg->id.nb);
1584 dev_err(&pdev->dev, "register ID notifier failed\n");
1588 ret = extcon_get_cable_state(ext_id, "USB-HOST");
1590 clear_bit(ID, &motg->inputs);
1592 set_bit(ID, &motg->inputs);
1595 prop = of_find_property(node, "qcom,phy-init-sequence", &len);
1599 words = len / sizeof(u32);
1601 if (words >= ULPI_EXT_VENDOR_SPECIFIC) {
1602 dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words);
1606 pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1607 if (!pdata->phy_init_seq)
1610 ret = of_property_read_u32_array(node, "qcom,phy-init-sequence",
1611 pdata->phy_init_seq, words);
1613 pdata->phy_init_sz = words;
1618 static int msm_otg_probe(struct platform_device *pdev)
1620 struct regulator_bulk_data regs[3];
1622 struct device_node *np = pdev->dev.of_node;
1623 struct msm_otg_platform_data *pdata;
1624 struct resource *res;
1625 struct msm_otg *motg;
1626 struct usb_phy *phy;
1627 void __iomem *phy_select;
1629 motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
1633 pdata = dev_get_platdata(&pdev->dev);
1637 ret = msm_otg_read_dt(pdev, motg);
1642 motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
1648 phy->dev = &pdev->dev;
1650 motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk");
1651 if (IS_ERR(motg->clk)) {
1652 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1653 return PTR_ERR(motg->clk);
1657 * If USB Core is running its protocol engine based on CORE CLK,
1658 * CORE CLK must be running at >55Mhz for correct HSUSB
1659 * operation and USB core cannot tolerate frequency changes on
1662 motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk");
1663 if (IS_ERR(motg->pclk)) {
1664 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1665 return PTR_ERR(motg->pclk);
1669 * USB core clock is not present on all MSM chips. This
1670 * clock is introduced to remove the dependency on AXI
1673 motg->core_clk = devm_clk_get(&pdev->dev,
1674 np ? "alt_core" : "usb_hs_core_clk");
1676 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1679 motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1684 * NOTE: The PHYs can be multiplexed between the chipidea controller
1685 * and the dwc3 controller, using a single bit. It is important that
1686 * the dwc3 driver does not set this bit in an incompatible way.
1688 if (motg->phy_number) {
1689 phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4);
1692 /* Enable second PHY with the OTG port */
1693 writel(0x1, phy_select);
1696 dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1698 motg->irq = platform_get_irq(pdev, 0);
1699 if (motg->irq < 0) {
1700 dev_err(&pdev->dev, "platform_get_irq failed\n");
1704 regs[0].supply = "vddcx";
1705 regs[1].supply = "v3p3";
1706 regs[2].supply = "v1p8";
1708 ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs);
1712 motg->vddcx = regs[0].consumer;
1713 motg->v3p3 = regs[1].consumer;
1714 motg->v1p8 = regs[2].consumer;
1716 clk_set_rate(motg->clk, 60000000);
1718 clk_prepare_enable(motg->clk);
1719 clk_prepare_enable(motg->pclk);
1721 if (!IS_ERR(motg->core_clk))
1722 clk_prepare_enable(motg->core_clk);
1724 ret = msm_hsusb_init_vddcx(motg, 1);
1726 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1730 ret = msm_hsusb_ldo_init(motg, 1);
1732 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1735 ret = msm_hsusb_ldo_set_mode(motg, 1);
1737 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1741 writel(0, USB_USBINTR);
1742 writel(0, USB_OTGSC);
1744 INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1745 INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1746 ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED,
1749 dev_err(&pdev->dev, "request irq failed\n");
1753 phy->init = msm_phy_init;
1754 phy->set_power = msm_otg_set_power;
1755 phy->notify_disconnect = msm_phy_notify_disconnect;
1756 phy->type = USB_PHY_TYPE_USB2;
1758 phy->io_ops = &msm_otg_io_ops;
1760 phy->otg->usb_phy = &motg->phy;
1761 phy->otg->set_host = msm_otg_set_host;
1762 phy->otg->set_peripheral = msm_otg_set_peripheral;
1766 ret = usb_add_phy_dev(&motg->phy);
1768 dev_err(&pdev->dev, "usb_add_phy failed\n");
1772 platform_set_drvdata(pdev, motg);
1773 device_init_wakeup(&pdev->dev, 1);
1775 if (motg->pdata->mode == USB_DR_MODE_OTG &&
1776 motg->pdata->otg_control == OTG_USER_CONTROL) {
1777 ret = msm_otg_debugfs_init(motg);
1779 dev_dbg(&pdev->dev, "Can not create mode change file\n");
1782 pm_runtime_set_active(&pdev->dev);
1783 pm_runtime_enable(&pdev->dev);
1788 msm_hsusb_ldo_init(motg, 0);
1790 msm_hsusb_init_vddcx(motg, 0);
1792 clk_disable_unprepare(motg->pclk);
1793 clk_disable_unprepare(motg->clk);
1794 if (!IS_ERR(motg->core_clk))
1795 clk_disable_unprepare(motg->core_clk);
1799 static int msm_otg_remove(struct platform_device *pdev)
1801 struct msm_otg *motg = platform_get_drvdata(pdev);
1802 struct usb_phy *phy = &motg->phy;
1805 if (phy->otg->host || phy->otg->gadget)
1808 if (motg->id.conn.edev)
1809 extcon_unregister_interest(&motg->id.conn);
1810 if (motg->vbus.conn.edev)
1811 extcon_unregister_interest(&motg->vbus.conn);
1813 msm_otg_debugfs_cleanup();
1814 cancel_delayed_work_sync(&motg->chg_work);
1815 cancel_work_sync(&motg->sm_work);
1817 pm_runtime_resume(&pdev->dev);
1819 device_init_wakeup(&pdev->dev, 0);
1820 pm_runtime_disable(&pdev->dev);
1822 usb_remove_phy(phy);
1823 disable_irq(motg->irq);
1826 * Put PHY in low power mode.
1828 ulpi_read(phy, 0x14);
1829 ulpi_write(phy, 0x08, 0x09);
1831 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1832 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1833 if (readl(USB_PORTSC) & PORTSC_PHCD)
1838 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1839 dev_err(phy->dev, "Unable to suspend PHY\n");
1841 clk_disable_unprepare(motg->pclk);
1842 clk_disable_unprepare(motg->clk);
1843 if (!IS_ERR(motg->core_clk))
1844 clk_disable_unprepare(motg->core_clk);
1845 msm_hsusb_ldo_init(motg, 0);
1847 pm_runtime_set_suspended(&pdev->dev);
1853 static int msm_otg_runtime_idle(struct device *dev)
1855 struct msm_otg *motg = dev_get_drvdata(dev);
1856 struct usb_otg *otg = motg->phy.otg;
1858 dev_dbg(dev, "OTG runtime idle\n");
1861 * It is observed some times that a spurious interrupt
1862 * comes when PHY is put into LPM immediately after PHY reset.
1863 * This 1 sec delay also prevents entering into LPM immediately
1864 * after asynchronous interrupt.
1866 if (otg->state != OTG_STATE_UNDEFINED)
1867 pm_schedule_suspend(dev, 1000);
1872 static int msm_otg_runtime_suspend(struct device *dev)
1874 struct msm_otg *motg = dev_get_drvdata(dev);
1876 dev_dbg(dev, "OTG runtime suspend\n");
1877 return msm_otg_suspend(motg);
1880 static int msm_otg_runtime_resume(struct device *dev)
1882 struct msm_otg *motg = dev_get_drvdata(dev);
1884 dev_dbg(dev, "OTG runtime resume\n");
1885 return msm_otg_resume(motg);
1889 #ifdef CONFIG_PM_SLEEP
1890 static int msm_otg_pm_suspend(struct device *dev)
1892 struct msm_otg *motg = dev_get_drvdata(dev);
1894 dev_dbg(dev, "OTG PM suspend\n");
1895 return msm_otg_suspend(motg);
1898 static int msm_otg_pm_resume(struct device *dev)
1900 struct msm_otg *motg = dev_get_drvdata(dev);
1903 dev_dbg(dev, "OTG PM resume\n");
1905 ret = msm_otg_resume(motg);
1910 * Runtime PM Documentation recommends bringing the
1911 * device to full powered state upon resume.
1913 pm_runtime_disable(dev);
1914 pm_runtime_set_active(dev);
1915 pm_runtime_enable(dev);
1921 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1922 SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
1923 SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
1924 msm_otg_runtime_idle)
1927 static struct platform_driver msm_otg_driver = {
1928 .probe = msm_otg_probe,
1929 .remove = msm_otg_remove,
1931 .name = DRIVER_NAME,
1932 .pm = &msm_otg_dev_pm_ops,
1933 .of_match_table = msm_otg_dt_match,
1937 module_platform_driver(msm_otg_driver);
1939 MODULE_LICENSE("GPL v2");
1940 MODULE_DESCRIPTION("MSM USB transceiver driver");