drivers/usb/phy/phy-msm-usb.c

   1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15  * 02110-1301, USA.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/clk.h>
  23 #include <linux/slab.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/err.h>
  26 #include <linux/delay.h>
  27 #include <linux/io.h>
  28 #include <linux/ioport.h>
  29 #include <linux/uaccess.h>
  30 #include <linux/debugfs.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/pm_runtime.h>
  33
  34 #include <linux/usb.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/usb/ulpi.h>
  37 #include <linux/usb/gadget.h>
  38 #include <linux/usb/hcd.h>
  39 #include <linux/usb/msm_hsusb.h>
  40 #include <linux/usb/msm_hsusb_hw.h>
  41 #include <linux/regulator/consumer.h>
  42
  43 #define MSM_USB_BASE    (motg->regs)
  44 #define DRIVER_NAME     "msm_otg"
  45
  46 #define ULPI_IO_TIMEOUT_USEC    (10 * 1000)
  47
  48 #define USB_PHY_3P3_VOL_MIN     3050000 /* uV */
  49 #define USB_PHY_3P3_VOL_MAX     3300000 /* uV */
  50 #define USB_PHY_3P3_HPM_LOAD    50000   /* uA */
  51 #define USB_PHY_3P3_LPM_LOAD    4000    /* uA */
  52
  53 #define USB_PHY_1P8_VOL_MIN     1800000 /* uV */
  54 #define USB_PHY_1P8_VOL_MAX     1800000 /* uV */
  55 #define USB_PHY_1P8_HPM_LOAD    50000   /* uA */
  56 #define USB_PHY_1P8_LPM_LOAD    4000    /* uA */
  57
  58 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
  59 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
  60
  61 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
  62 {
  63         int ret = 0;
  64
  65         if (init) {
  66                 ret = regulator_set_voltage(motg->vddcx,
  67                                 USB_PHY_VDD_DIG_VOL_MIN,
  68                                 USB_PHY_VDD_DIG_VOL_MAX);
  69                 if (ret) {
  70                         dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
  71                         return ret;
  72                 }
  73
  74                 ret = regulator_enable(motg->vddcx);
  75                 if (ret)
  76                         dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
  77         } else {
  78                 ret = regulator_set_voltage(motg->vddcx, 0,
  79                         USB_PHY_VDD_DIG_VOL_MAX);
  80                 if (ret)
  81                         dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
  82                 ret = regulator_disable(motg->vddcx);
  83                 if (ret)
  84                         dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
  85         }
  86
  87         return ret;
  88 }
  89
  90 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
  91 {
  92         int rc = 0;
  93
  94         if (init) {
  95                 rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN,
  96                                 USB_PHY_3P3_VOL_MAX);
  97                 if (rc) {
  98                         dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n");
  99                         goto exit;
 100                 }
 101                 rc = regulator_enable(motg->v3p3);
 102                 if (rc) {
 103                         dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
 104                         goto exit;
 105                 }
 106                 rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN,
 107                                 USB_PHY_1P8_VOL_MAX);
 108                 if (rc) {
 109                         dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n");
 110                         goto disable_3p3;
 111                 }
 112                 rc = regulator_enable(motg->v1p8);
 113                 if (rc) {
 114                         dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
 115                         goto disable_3p3;
 116                 }
 117
 118                 return 0;
 119         }
 120
 121         regulator_disable(motg->v1p8);
 122 disable_3p3:
 123         regulator_disable(motg->v3p3);
 124 exit:
 125         return rc;
 126 }
 127
 128 static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on)
 129 {
 130         int ret = 0;
 131
 132         if (on) {
 133                 ret = regulator_set_optimum_mode(motg->v1p8,
 134                                 USB_PHY_1P8_HPM_LOAD);
 135                 if (ret < 0) {
 136                         pr_err("Could not set HPM for v1p8\n");
 137                         return ret;
 138                 }
 139                 ret = regulator_set_optimum_mode(motg->v3p3,
 140                                 USB_PHY_3P3_HPM_LOAD);
 141                 if (ret < 0) {
 142                         pr_err("Could not set HPM for v3p3\n");
 143                         regulator_set_optimum_mode(motg->v1p8,
 144                                 USB_PHY_1P8_LPM_LOAD);
 145                         return ret;
 146                 }
 147         } else {
 148                 ret = regulator_set_optimum_mode(motg->v1p8,
 149                                 USB_PHY_1P8_LPM_LOAD);
 150                 if (ret < 0)
 151                         pr_err("Could not set LPM for v1p8\n");
 152                 ret = regulator_set_optimum_mode(motg->v3p3,
 153                                 USB_PHY_3P3_LPM_LOAD);
 154                 if (ret < 0)
 155                         pr_err("Could not set LPM for v3p3\n");
 156         }
 157
 158         pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
 159         return ret < 0 ? ret : 0;
 160 }
 161
 162 static int ulpi_read(struct usb_phy *phy, u32 reg)
 163 {
 164         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 165         int cnt = 0;
 166
 167         /* initiate read operation */
 168         writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
 169                USB_ULPI_VIEWPORT);
 170
 171         /* wait for completion */
 172         while (cnt < ULPI_IO_TIMEOUT_USEC) {
 173                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
 174                         break;
 175                 udelay(1);
 176                 cnt++;
 177         }
 178
 179         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
 180                 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
 181                         readl(USB_ULPI_VIEWPORT));
 182                 return -ETIMEDOUT;
 183         }
 184         return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
 185 }
 186
 187 static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
 188 {
 189         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 190         int cnt = 0;
 191
 192         /* initiate write operation */
 193         writel(ULPI_RUN | ULPI_WRITE |
 194                ULPI_ADDR(reg) | ULPI_DATA(val),
 195                USB_ULPI_VIEWPORT);
 196
 197         /* wait for completion */
 198         while (cnt < ULPI_IO_TIMEOUT_USEC) {
 199                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
 200                         break;
 201                 udelay(1);
 202                 cnt++;
 203         }
 204
 205         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
 206                 dev_err(phy->dev, "ulpi_write: timeout\n");
 207                 return -ETIMEDOUT;
 208         }
 209         return 0;
 210 }
 211
 212 static struct usb_phy_io_ops msm_otg_io_ops = {
 213         .read = ulpi_read,
 214         .write = ulpi_write,
 215 };
 216
 217 static void ulpi_init(struct msm_otg *motg)
 218 {
 219         struct msm_otg_platform_data *pdata = motg->pdata;
 220         int *seq = pdata->phy_init_seq;
 221
 222         if (!seq)
 223                 return;
 224
 225         while (seq[0] >= 0) {
 226                 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
 227                                 seq[0], seq[1]);
 228                 ulpi_write(&motg->phy, seq[0], seq[1]);
 229                 seq += 2;
 230         }
 231 }
 232
 233 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
 234 {
 235         int ret = 0;
 236
 237         if (!motg->pdata->link_clk_reset)
 238                 return ret;
 239
 240         ret = motg->pdata->link_clk_reset(motg->clk, assert);
 241         if (ret)
 242                 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
 243                         assert ? "assert" : "deassert");
 244
 245         return ret;
 246 }
 247
 248 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
 249 {
 250         int ret = 0;
 251
 252         if (!motg->pdata->phy_clk_reset)
 253                 return ret;
 254
 255         ret = motg->pdata->phy_clk_reset(motg->phy_reset_clk);
 256         if (ret)
 257                 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
 258
 259         return ret;
 260 }
 261
 262 static int msm_otg_phy_reset(struct msm_otg *motg)
 263 {
 264         u32 val;
 265         int ret;
 266         int retries;
 267
 268         ret = msm_otg_link_clk_reset(motg, 1);
 269         if (ret)
 270                 return ret;
 271         ret = msm_otg_phy_clk_reset(motg);
 272         if (ret)
 273                 return ret;
 274         ret = msm_otg_link_clk_reset(motg, 0);
 275         if (ret)
 276                 return ret;
 277
 278         val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
 279         writel(val | PORTSC_PTS_ULPI, USB_PORTSC);
 280
 281         for (retries = 3; retries > 0; retries--) {
 282                 ret = ulpi_write(&motg->phy, ULPI_FUNC_CTRL_SUSPENDM,
 283                                 ULPI_CLR(ULPI_FUNC_CTRL));
 284                 if (!ret)
 285                         break;
 286                 ret = msm_otg_phy_clk_reset(motg);
 287                 if (ret)
 288                         return ret;
 289         }
 290         if (!retries)
 291                 return -ETIMEDOUT;
 292
 293         /* This reset calibrates the phy, if the above write succeeded */
 294         ret = msm_otg_phy_clk_reset(motg);
 295         if (ret)
 296                 return ret;
 297
 298         for (retries = 3; retries > 0; retries--) {
 299                 ret = ulpi_read(&motg->phy, ULPI_DEBUG);
 300                 if (ret != -ETIMEDOUT)
 301                         break;
 302                 ret = msm_otg_phy_clk_reset(motg);
 303                 if (ret)
 304                         return ret;
 305         }
 306         if (!retries)
 307                 return -ETIMEDOUT;
 308
 309         dev_info(motg->phy.dev, "phy_reset: success\n");
 310         return 0;
 311 }
 312
 313 #define LINK_RESET_TIMEOUT_USEC         (250 * 1000)
 314 static int msm_otg_reset(struct usb_phy *phy)
 315 {
 316         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 317         struct msm_otg_platform_data *pdata = motg->pdata;
 318         int cnt = 0;
 319         int ret;
 320         u32 val = 0;
 321         u32 ulpi_val = 0;
 322
 323         ret = msm_otg_phy_reset(motg);
 324         if (ret) {
 325                 dev_err(phy->dev, "phy_reset failed\n");
 326                 return ret;
 327         }
 328
 329         ulpi_init(motg);
 330
 331         writel(USBCMD_RESET, USB_USBCMD);
 332         while (cnt < LINK_RESET_TIMEOUT_USEC) {
 333                 if (!(readl(USB_USBCMD) & USBCMD_RESET))
 334                         break;
 335                 udelay(1);
 336                 cnt++;
 337         }
 338         if (cnt >= LINK_RESET_TIMEOUT_USEC)
 339                 return -ETIMEDOUT;
 340
 341         /* select ULPI phy */
 342         writel(0x80000000, USB_PORTSC);
 343
 344         msleep(100);
 345
 346         writel(0x0, USB_AHBBURST);
 347         writel(0x00, USB_AHBMODE);
 348
 349         if (pdata->otg_control == OTG_PHY_CONTROL) {
 350                 val = readl(USB_OTGSC);
 351                 if (pdata->mode == USB_DR_MODE_OTG) {
 352                         ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
 353                         val |= OTGSC_IDIE | OTGSC_BSVIE;
 354                 } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) {
 355                         ulpi_val = ULPI_INT_SESS_VALID;
 356                         val |= OTGSC_BSVIE;
 357                 }
 358                 writel(val, USB_OTGSC);
 359                 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
 360                 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
 361         }
 362
 363         return 0;
 364 }
 365
 366 #define PHY_SUSPEND_TIMEOUT_USEC        (500 * 1000)
 367 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
 368
 369 #ifdef CONFIG_PM
 370
 371 #define USB_PHY_SUSP_DIG_VOL  500000
 372 static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high)
 373 {
 374         int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
 375         int min_vol;
 376         int ret;
 377
 378         if (high)
 379                 min_vol = USB_PHY_VDD_DIG_VOL_MIN;
 380         else
 381                 min_vol = USB_PHY_SUSP_DIG_VOL;
 382
 383         ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol);
 384         if (ret) {
 385                 pr_err("Cannot set vddcx voltage\n");
 386                 return ret;
 387         }
 388
 389         pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
 390
 391         return ret;
 392 }
 393
 394 static int msm_otg_suspend(struct msm_otg *motg)
 395 {
 396         struct usb_phy *phy = &motg->phy;
 397         struct usb_bus *bus = phy->otg->host;
 398         struct msm_otg_platform_data *pdata = motg->pdata;
 399         int cnt = 0;
 400
 401         if (atomic_read(&motg->in_lpm))
 402                 return 0;
 403
 404         disable_irq(motg->irq);
 405         /*
 406          * Chipidea 45-nm PHY suspend sequence:
 407          *
 408          * Interrupt Latch Register auto-clear feature is not present
 409          * in all PHY versions. Latch register is clear on read type.
 410          * Clear latch register to avoid spurious wakeup from
 411          * low power mode (LPM).
 412          *
 413          * PHY comparators are disabled when PHY enters into low power
 414          * mode (LPM). Keep PHY comparators ON in LPM only when we expect
 415          * VBUS/Id notifications from USB PHY. Otherwise turn off USB
 416          * PHY comparators. This save significant amount of power.
 417          *
 418          * PLL is not turned off when PHY enters into low power mode (LPM).
 419          * Disable PLL for maximum power savings.
 420          */
 421
 422         if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
 423                 ulpi_read(phy, 0x14);
 424                 if (pdata->otg_control == OTG_PHY_CONTROL)
 425                         ulpi_write(phy, 0x01, 0x30);
 426                 ulpi_write(phy, 0x08, 0x09);
 427         }
 428
 429         /*
 430          * PHY may take some time or even fail to enter into low power
 431          * mode (LPM). Hence poll for 500 msec and reset the PHY and link
 432          * in failure case.
 433          */
 434         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
 435         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
 436                 if (readl(USB_PORTSC) & PORTSC_PHCD)
 437                         break;
 438                 udelay(1);
 439                 cnt++;
 440         }
 441
 442         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
 443                 dev_err(phy->dev, "Unable to suspend PHY\n");
 444                 msm_otg_reset(phy);
 445                 enable_irq(motg->irq);
 446                 return -ETIMEDOUT;
 447         }
 448
 449         /*
 450          * PHY has capability to generate interrupt asynchronously in low
 451          * power mode (LPM). This interrupt is level triggered. So USB IRQ
 452          * line must be disabled till async interrupt enable bit is cleared
 453          * in USBCMD register. Assert STP (ULPI interface STOP signal) to
 454          * block data communication from PHY.
 455          */
 456         writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
 457
 458         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 459                         motg->pdata->otg_control == OTG_PMIC_CONTROL)
 460                 writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL);
 461
 462         clk_disable_unprepare(motg->pclk);
 463         clk_disable_unprepare(motg->clk);
 464         if (!IS_ERR(motg->core_clk))
 465                 clk_disable_unprepare(motg->core_clk);
 466
 467         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 468                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
 469                 msm_hsusb_ldo_set_mode(motg, 0);
 470                 msm_hsusb_config_vddcx(motg, 0);
 471         }
 472
 473         if (device_may_wakeup(phy->dev))
 474                 enable_irq_wake(motg->irq);
 475         if (bus)
 476                 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 477
 478         atomic_set(&motg->in_lpm, 1);
 479         enable_irq(motg->irq);
 480
 481         dev_info(phy->dev, "USB in low power mode\n");
 482
 483         return 0;
 484 }
 485
 486 static int msm_otg_resume(struct msm_otg *motg)
 487 {
 488         struct usb_phy *phy = &motg->phy;
 489         struct usb_bus *bus = phy->otg->host;
 490         int cnt = 0;
 491         unsigned temp;
 492
 493         if (!atomic_read(&motg->in_lpm))
 494                 return 0;
 495
 496         clk_prepare_enable(motg->pclk);
 497         clk_prepare_enable(motg->clk);
 498         if (!IS_ERR(motg->core_clk))
 499                 clk_prepare_enable(motg->core_clk);
 500
 501         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 502                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
 503                 msm_hsusb_ldo_set_mode(motg, 1);
 504                 msm_hsusb_config_vddcx(motg, 1);
 505                 writel(readl(USB_PHY_CTRL) & ~PHY_RETEN, USB_PHY_CTRL);
 506         }
 507
 508         temp = readl(USB_USBCMD);
 509         temp &= ~ASYNC_INTR_CTRL;
 510         temp &= ~ULPI_STP_CTRL;
 511         writel(temp, USB_USBCMD);
 512
 513         /*
 514          * PHY comes out of low power mode (LPM) in case of wakeup
 515          * from asynchronous interrupt.
 516          */
 517         if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 518                 goto skip_phy_resume;
 519
 520         writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
 521         while (cnt < PHY_RESUME_TIMEOUT_USEC) {
 522                 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 523                         break;
 524                 udelay(1);
 525                 cnt++;
 526         }
 527
 528         if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
 529                 /*
 530                  * This is a fatal error. Reset the link and
 531                  * PHY. USB state can not be restored. Re-insertion
 532                  * of USB cable is the only way to get USB working.
 533                  */
 534                 dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n");
 535                 msm_otg_reset(phy);
 536         }
 537
 538 skip_phy_resume:
 539         if (device_may_wakeup(phy->dev))
 540                 disable_irq_wake(motg->irq);
 541         if (bus)
 542                 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 543
 544         atomic_set(&motg->in_lpm, 0);
 545
 546         if (motg->async_int) {
 547                 motg->async_int = 0;
 548                 pm_runtime_put(phy->dev);
 549                 enable_irq(motg->irq);
 550         }
 551
 552         dev_info(phy->dev, "USB exited from low power mode\n");
 553
 554         return 0;
 555 }
 556 #endif
 557
 558 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
 559 {
 560         if (motg->cur_power == mA)
 561                 return;
 562
 563         /* TODO: Notify PMIC about available current */
 564         dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
 565         motg->cur_power = mA;
 566 }
 567
 568 static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
 569 {
 570         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 571
 572         /*
 573          * Gadget driver uses set_power method to notify about the
 574          * available current based on suspend/configured states.
 575          *
 576          * IDEV_CHG can be drawn irrespective of suspend/un-configured
 577          * states when CDP/ACA is connected.
 578          */
 579         if (motg->chg_type == USB_SDP_CHARGER)
 580                 msm_otg_notify_charger(motg, mA);
 581
 582         return 0;
 583 }
 584
 585 static void msm_otg_start_host(struct usb_phy *phy, int on)
 586 {
 587         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 588         struct msm_otg_platform_data *pdata = motg->pdata;
 589         struct usb_hcd *hcd;
 590
 591         if (!phy->otg->host)
 592                 return;
 593
 594         hcd = bus_to_hcd(phy->otg->host);
 595
 596         if (on) {
 597                 dev_dbg(phy->dev, "host on\n");
 598
 599                 if (pdata->vbus_power)
 600                         pdata->vbus_power(1);
 601                 /*
 602                  * Some boards have a switch cotrolled by gpio
 603                  * to enable/disable internal HUB. Enable internal
 604                  * HUB before kicking the host.
 605                  */
 606                 if (pdata->setup_gpio)
 607                         pdata->setup_gpio(OTG_STATE_A_HOST);
 608 #ifdef CONFIG_USB
 609                 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 610                 device_wakeup_enable(hcd->self.controller);
 611 #endif
 612         } else {
 613                 dev_dbg(phy->dev, "host off\n");
 614
 615 #ifdef CONFIG_USB
 616                 usb_remove_hcd(hcd);
 617 #endif
 618                 if (pdata->setup_gpio)
 619                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 620                 if (pdata->vbus_power)
 621                         pdata->vbus_power(0);
 622         }
 623 }
 624
 625 static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
 626 {
 627         struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
 628         struct usb_hcd *hcd;
 629
 630         /*
 631          * Fail host registration if this board can support
 632          * only peripheral configuration.
 633          */
 634         if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) {
 635                 dev_info(otg->phy->dev, "Host mode is not supported\n");
 636                 return -ENODEV;
 637         }
 638
 639         if (!host) {
 640                 if (otg->phy->state == OTG_STATE_A_HOST) {
 641                         pm_runtime_get_sync(otg->phy->dev);
 642                         msm_otg_start_host(otg->phy, 0);
 643                         otg->host = NULL;
 644                         otg->phy->state = OTG_STATE_UNDEFINED;
 645                         schedule_work(&motg->sm_work);
 646                 } else {
 647                         otg->host = NULL;
 648                 }
 649
 650                 return 0;
 651         }
 652
 653         hcd = bus_to_hcd(host);
 654         hcd->power_budget = motg->pdata->power_budget;
 655
 656         otg->host = host;
 657         dev_dbg(otg->phy->dev, "host driver registered w/ tranceiver\n");
 658
 659         /*
 660          * Kick the state machine work, if peripheral is not supported
 661          * or peripheral is already registered with us.
 662          */
 663         if (motg->pdata->mode == USB_DR_MODE_HOST || otg->gadget) {
 664                 pm_runtime_get_sync(otg->phy->dev);
 665                 schedule_work(&motg->sm_work);
 666         }
 667
 668         return 0;
 669 }
 670
 671 static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
 672 {
 673         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 674         struct msm_otg_platform_data *pdata = motg->pdata;
 675
 676         if (!phy->otg->gadget)
 677                 return;
 678
 679         if (on) {
 680                 dev_dbg(phy->dev, "gadget on\n");
 681                 /*
 682                  * Some boards have a switch cotrolled by gpio
 683                  * to enable/disable internal HUB. Disable internal
 684                  * HUB before kicking the gadget.
 685                  */
 686                 if (pdata->setup_gpio)
 687                         pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
 688                 usb_gadget_vbus_connect(phy->otg->gadget);
 689         } else {
 690                 dev_dbg(phy->dev, "gadget off\n");
 691                 usb_gadget_vbus_disconnect(phy->otg->gadget);
 692                 if (pdata->setup_gpio)
 693                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 694         }
 695
 696 }
 697
 698 static int msm_otg_set_peripheral(struct usb_otg *otg,
 699                                         struct usb_gadget *gadget)
 700 {
 701         struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
 702
 703         /*
 704          * Fail peripheral registration if this board can support
 705          * only host configuration.
 706          */
 707         if (motg->pdata->mode == USB_DR_MODE_HOST) {
 708                 dev_info(otg->phy->dev, "Peripheral mode is not supported\n");
 709                 return -ENODEV;
 710         }
 711
 712         if (!gadget) {
 713                 if (otg->phy->state == OTG_STATE_B_PERIPHERAL) {
 714                         pm_runtime_get_sync(otg->phy->dev);
 715                         msm_otg_start_peripheral(otg->phy, 0);
 716                         otg->gadget = NULL;
 717                         otg->phy->state = OTG_STATE_UNDEFINED;
 718                         schedule_work(&motg->sm_work);
 719                 } else {
 720                         otg->gadget = NULL;
 721                 }
 722
 723                 return 0;
 724         }
 725         otg->gadget = gadget;
 726         dev_dbg(otg->phy->dev, "peripheral driver registered w/ tranceiver\n");
 727
 728         /*
 729          * Kick the state machine work, if host is not supported
 730          * or host is already registered with us.
 731          */
 732         if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL || otg->host) {
 733                 pm_runtime_get_sync(otg->phy->dev);
 734                 schedule_work(&motg->sm_work);
 735         }
 736
 737         return 0;
 738 }
 739
 740 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
 741 {
 742         struct usb_phy *phy = &motg->phy;
 743         u32 chg_det;
 744         bool ret = false;
 745
 746         switch (motg->pdata->phy_type) {
 747         case CI_45NM_INTEGRATED_PHY:
 748                 chg_det = ulpi_read(phy, 0x34);
 749                 ret = chg_det & (1 << 4);
 750                 break;
 751         case SNPS_28NM_INTEGRATED_PHY:
 752                 chg_det = ulpi_read(phy, 0x87);
 753                 ret = chg_det & 1;
 754                 break;
 755         default:
 756                 break;
 757         }
 758         return ret;
 759 }
 760
 761 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
 762 {
 763         struct usb_phy *phy = &motg->phy;
 764         u32 chg_det;
 765
 766         switch (motg->pdata->phy_type) {
 767         case CI_45NM_INTEGRATED_PHY:
 768                 chg_det = ulpi_read(phy, 0x34);
 769                 /* Turn off charger block */
 770                 chg_det |= ~(1 << 1);
 771                 ulpi_write(phy, chg_det, 0x34);
 772                 udelay(20);
 773                 /* control chg block via ULPI */
 774                 chg_det &= ~(1 << 3);
 775                 ulpi_write(phy, chg_det, 0x34);
 776                 /* put it in host mode for enabling D- source */
 777                 chg_det &= ~(1 << 2);
 778                 ulpi_write(phy, chg_det, 0x34);
 779                 /* Turn on chg detect block */
 780                 chg_det &= ~(1 << 1);
 781                 ulpi_write(phy, chg_det, 0x34);
 782                 udelay(20);
 783                 /* enable chg detection */
 784                 chg_det &= ~(1 << 0);
 785                 ulpi_write(phy, chg_det, 0x34);
 786                 break;
 787         case SNPS_28NM_INTEGRATED_PHY:
 788                 /*
 789                  * Configure DM as current source, DP as current sink
 790                  * and enable battery charging comparators.
 791                  */
 792                 ulpi_write(phy, 0x8, 0x85);
 793                 ulpi_write(phy, 0x2, 0x85);
 794                 ulpi_write(phy, 0x1, 0x85);
 795                 break;
 796         default:
 797                 break;
 798         }
 799 }
 800
 801 static bool msm_chg_check_primary_det(struct msm_otg *motg)
 802 {
 803         struct usb_phy *phy = &motg->phy;
 804         u32 chg_det;
 805         bool ret = false;
 806
 807         switch (motg->pdata->phy_type) {
 808         case CI_45NM_INTEGRATED_PHY:
 809                 chg_det = ulpi_read(phy, 0x34);
 810                 ret = chg_det & (1 << 4);
 811                 break;
 812         case SNPS_28NM_INTEGRATED_PHY:
 813                 chg_det = ulpi_read(phy, 0x87);
 814                 ret = chg_det & 1;
 815                 break;
 816         default:
 817                 break;
 818         }
 819         return ret;
 820 }
 821
 822 static void msm_chg_enable_primary_det(struct msm_otg *motg)
 823 {
 824         struct usb_phy *phy = &motg->phy;
 825         u32 chg_det;
 826
 827         switch (motg->pdata->phy_type) {
 828         case CI_45NM_INTEGRATED_PHY:
 829                 chg_det = ulpi_read(phy, 0x34);
 830                 /* enable chg detection */
 831                 chg_det &= ~(1 << 0);
 832                 ulpi_write(phy, chg_det, 0x34);
 833                 break;
 834         case SNPS_28NM_INTEGRATED_PHY:
 835                 /*
 836                  * Configure DP as current source, DM as current sink
 837                  * and enable battery charging comparators.
 838                  */
 839                 ulpi_write(phy, 0x2, 0x85);
 840                 ulpi_write(phy, 0x1, 0x85);
 841                 break;
 842         default:
 843                 break;
 844         }
 845 }
 846
 847 static bool msm_chg_check_dcd(struct msm_otg *motg)
 848 {
 849         struct usb_phy *phy = &motg->phy;
 850         u32 line_state;
 851         bool ret = false;
 852
 853         switch (motg->pdata->phy_type) {
 854         case CI_45NM_INTEGRATED_PHY:
 855                 line_state = ulpi_read(phy, 0x15);
 856                 ret = !(line_state & 1);
 857                 break;
 858         case SNPS_28NM_INTEGRATED_PHY:
 859                 line_state = ulpi_read(phy, 0x87);
 860                 ret = line_state & 2;
 861                 break;
 862         default:
 863                 break;
 864         }
 865         return ret;
 866 }
 867
 868 static void msm_chg_disable_dcd(struct msm_otg *motg)
 869 {
 870         struct usb_phy *phy = &motg->phy;
 871         u32 chg_det;
 872
 873         switch (motg->pdata->phy_type) {
 874         case CI_45NM_INTEGRATED_PHY:
 875                 chg_det = ulpi_read(phy, 0x34);
 876                 chg_det &= ~(1 << 5);
 877                 ulpi_write(phy, chg_det, 0x34);
 878                 break;
 879         case SNPS_28NM_INTEGRATED_PHY:
 880                 ulpi_write(phy, 0x10, 0x86);
 881                 break;
 882         default:
 883                 break;
 884         }
 885 }
 886
 887 static void msm_chg_enable_dcd(struct msm_otg *motg)
 888 {
 889         struct usb_phy *phy = &motg->phy;
 890         u32 chg_det;
 891
 892         switch (motg->pdata->phy_type) {
 893         case CI_45NM_INTEGRATED_PHY:
 894                 chg_det = ulpi_read(phy, 0x34);
 895                 /* Turn on D+ current source */
 896                 chg_det |= (1 << 5);
 897                 ulpi_write(phy, chg_det, 0x34);
 898                 break;
 899         case SNPS_28NM_INTEGRATED_PHY:
 900                 /* Data contact detection enable */
 901                 ulpi_write(phy, 0x10, 0x85);
 902                 break;
 903         default:
 904                 break;
 905         }
 906 }
 907
 908 static void msm_chg_block_on(struct msm_otg *motg)
 909 {
 910         struct usb_phy *phy = &motg->phy;
 911         u32 func_ctrl, chg_det;
 912
 913         /* put the controller in non-driving mode */
 914         func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
 915         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
 916         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
 917         ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
 918
 919         switch (motg->pdata->phy_type) {
 920         case CI_45NM_INTEGRATED_PHY:
 921                 chg_det = ulpi_read(phy, 0x34);
 922                 /* control chg block via ULPI */
 923                 chg_det &= ~(1 << 3);
 924                 ulpi_write(phy, chg_det, 0x34);
 925                 /* Turn on chg detect block */
 926                 chg_det &= ~(1 << 1);
 927                 ulpi_write(phy, chg_det, 0x34);
 928                 udelay(20);
 929                 break;
 930         case SNPS_28NM_INTEGRATED_PHY:
 931                 /* Clear charger detecting control bits */
 932                 ulpi_write(phy, 0x3F, 0x86);
 933                 /* Clear alt interrupt latch and enable bits */
 934                 ulpi_write(phy, 0x1F, 0x92);
 935                 ulpi_write(phy, 0x1F, 0x95);
 936                 udelay(100);
 937                 break;
 938         default:
 939                 break;
 940         }
 941 }
 942
 943 static void msm_chg_block_off(struct msm_otg *motg)
 944 {
 945         struct usb_phy *phy = &motg->phy;
 946         u32 func_ctrl, chg_det;
 947
 948         switch (motg->pdata->phy_type) {
 949         case CI_45NM_INTEGRATED_PHY:
 950                 chg_det = ulpi_read(phy, 0x34);
 951                 /* Turn off charger block */
 952                 chg_det |= ~(1 << 1);
 953                 ulpi_write(phy, chg_det, 0x34);
 954                 break;
 955         case SNPS_28NM_INTEGRATED_PHY:
 956                 /* Clear charger detecting control bits */
 957                 ulpi_write(phy, 0x3F, 0x86);
 958                 /* Clear alt interrupt latch and enable bits */
 959                 ulpi_write(phy, 0x1F, 0x92);
 960                 ulpi_write(phy, 0x1F, 0x95);
 961                 break;
 962         default:
 963                 break;
 964         }
 965
 966         /* put the controller in normal mode */
 967         func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
 968         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
 969         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
 970         ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
 971 }
 972
 973 #define MSM_CHG_DCD_POLL_TIME           (100 * HZ/1000) /* 100 msec */
 974 #define MSM_CHG_DCD_MAX_RETRIES         6 /* Tdcd_tmout = 6 * 100 msec */
 975 #define MSM_CHG_PRIMARY_DET_TIME        (40 * HZ/1000) /* TVDPSRC_ON */
 976 #define MSM_CHG_SECONDARY_DET_TIME      (40 * HZ/1000) /* TVDMSRC_ON */
 977 static void msm_chg_detect_work(struct work_struct *w)
 978 {
 979         struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
 980         struct usb_phy *phy = &motg->phy;
 981         bool is_dcd, tmout, vout;
 982         unsigned long delay;
 983
 984         dev_dbg(phy->dev, "chg detection work\n");
 985         switch (motg->chg_state) {
 986         case USB_CHG_STATE_UNDEFINED:
 987                 pm_runtime_get_sync(phy->dev);
 988                 msm_chg_block_on(motg);
 989                 msm_chg_enable_dcd(motg);
 990                 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
 991                 motg->dcd_retries = 0;
 992                 delay = MSM_CHG_DCD_POLL_TIME;
 993                 break;
 994         case USB_CHG_STATE_WAIT_FOR_DCD:
 995                 is_dcd = msm_chg_check_dcd(motg);
 996                 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
 997                 if (is_dcd || tmout) {
 998                         msm_chg_disable_dcd(motg);
 999                         msm_chg_enable_primary_det(motg);
1000                         delay = MSM_CHG_PRIMARY_DET_TIME;
1001                         motg->chg_state = USB_CHG_STATE_DCD_DONE;
1002                 } else {
1003                         delay = MSM_CHG_DCD_POLL_TIME;
1004                 }
1005                 break;
1006         case USB_CHG_STATE_DCD_DONE:
1007                 vout = msm_chg_check_primary_det(motg);
1008                 if (vout) {
1009                         msm_chg_enable_secondary_det(motg);
1010                         delay = MSM_CHG_SECONDARY_DET_TIME;
1011                         motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1012                 } else {
1013                         motg->chg_type = USB_SDP_CHARGER;
1014                         motg->chg_state = USB_CHG_STATE_DETECTED;
1015                         delay = 0;
1016                 }
1017                 break;
1018         case USB_CHG_STATE_PRIMARY_DONE:
1019                 vout = msm_chg_check_secondary_det(motg);
1020                 if (vout)
1021                         motg->chg_type = USB_DCP_CHARGER;
1022                 else
1023                         motg->chg_type = USB_CDP_CHARGER;
1024                 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1025                 /* fall through */
1026         case USB_CHG_STATE_SECONDARY_DONE:
1027                 motg->chg_state = USB_CHG_STATE_DETECTED;
1028         case USB_CHG_STATE_DETECTED:
1029                 msm_chg_block_off(motg);
1030                 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1031                 schedule_work(&motg->sm_work);
1032                 return;
1033         default:
1034                 return;
1035         }
1036
1037         schedule_delayed_work(&motg->chg_work, delay);
1038 }
1039
1040 /*
1041  * We support OTG, Peripheral only and Host only configurations. In case
1042  * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1043  * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1044  * enabled when switch is controlled by user and default mode is supplied
1045  * by board file, which can be changed by userspace later.
1046  */
1047 static void msm_otg_init_sm(struct msm_otg *motg)
1048 {
1049         struct msm_otg_platform_data *pdata = motg->pdata;
1050         u32 otgsc = readl(USB_OTGSC);
1051
1052         switch (pdata->mode) {
1053         case USB_DR_MODE_OTG:
1054                 if (pdata->otg_control == OTG_PHY_CONTROL) {
1055                         if (otgsc & OTGSC_ID)
1056                                 set_bit(ID, &motg->inputs);
1057                         else
1058                                 clear_bit(ID, &motg->inputs);
1059
1060                         if (otgsc & OTGSC_BSV)
1061                                 set_bit(B_SESS_VLD, &motg->inputs);
1062                         else
1063                                 clear_bit(B_SESS_VLD, &motg->inputs);
1064                 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1065                                 set_bit(ID, &motg->inputs);
1066                                 clear_bit(B_SESS_VLD, &motg->inputs);
1067                 }
1068                 break;
1069         case USB_DR_MODE_HOST:
1070                 clear_bit(ID, &motg->inputs);
1071                 break;
1072         case USB_DR_MODE_PERIPHERAL:
1073                 set_bit(ID, &motg->inputs);
1074                 if (otgsc & OTGSC_BSV)
1075                         set_bit(B_SESS_VLD, &motg->inputs);
1076                 else
1077                         clear_bit(B_SESS_VLD, &motg->inputs);
1078                 break;
1079         default:
1080                 break;
1081         }
1082 }
1083
1084 static void msm_otg_sm_work(struct work_struct *w)
1085 {
1086         struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1087         struct usb_otg *otg = motg->phy.otg;
1088
1089         switch (otg->phy->state) {
1090         case OTG_STATE_UNDEFINED:
1091                 dev_dbg(otg->phy->dev, "OTG_STATE_UNDEFINED state\n");
1092                 msm_otg_reset(otg->phy);
1093                 msm_otg_init_sm(motg);
1094                 otg->phy->state = OTG_STATE_B_IDLE;
1095                 /* FALL THROUGH */
1096         case OTG_STATE_B_IDLE:
1097                 dev_dbg(otg->phy->dev, "OTG_STATE_B_IDLE state\n");
1098                 if (!test_bit(ID, &motg->inputs) && otg->host) {
1099                         /* disable BSV bit */
1100                         writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1101                         msm_otg_start_host(otg->phy, 1);
1102                         otg->phy->state = OTG_STATE_A_HOST;
1103                 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1104                         switch (motg->chg_state) {
1105                         case USB_CHG_STATE_UNDEFINED:
1106                                 msm_chg_detect_work(&motg->chg_work.work);
1107                                 break;
1108                         case USB_CHG_STATE_DETECTED:
1109                                 switch (motg->chg_type) {
1110                                 case USB_DCP_CHARGER:
1111                                         msm_otg_notify_charger(motg,
1112                                                         IDEV_CHG_MAX);
1113                                         break;
1114                                 case USB_CDP_CHARGER:
1115                                         msm_otg_notify_charger(motg,
1116                                                         IDEV_CHG_MAX);
1117                                         msm_otg_start_peripheral(otg->phy, 1);
1118                                         otg->phy->state
1119                                                 = OTG_STATE_B_PERIPHERAL;
1120                                         break;
1121                                 case USB_SDP_CHARGER:
1122                                         msm_otg_notify_charger(motg, IUNIT);
1123                                         msm_otg_start_peripheral(otg->phy, 1);
1124                                         otg->phy->state
1125                                                 = OTG_STATE_B_PERIPHERAL;
1126                                         break;
1127                                 default:
1128                                         break;
1129                                 }
1130                                 break;
1131                         default:
1132                                 break;
1133                         }
1134                 } else {
1135                         /*
1136                          * If charger detection work is pending, decrement
1137                          * the pm usage counter to balance with the one that
1138                          * is incremented in charger detection work.
1139                          */
1140                         if (cancel_delayed_work_sync(&motg->chg_work)) {
1141                                 pm_runtime_put_sync(otg->phy->dev);
1142                                 msm_otg_reset(otg->phy);
1143                         }
1144                         msm_otg_notify_charger(motg, 0);
1145                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1146                         motg->chg_type = USB_INVALID_CHARGER;
1147                 }
1148                 pm_runtime_put_sync(otg->phy->dev);
1149                 break;
1150         case OTG_STATE_B_PERIPHERAL:
1151                 dev_dbg(otg->phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1152                 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1153                                 !test_bit(ID, &motg->inputs)) {
1154                         msm_otg_notify_charger(motg, 0);
1155                         msm_otg_start_peripheral(otg->phy, 0);
1156                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1157                         motg->chg_type = USB_INVALID_CHARGER;
1158                         otg->phy->state = OTG_STATE_B_IDLE;
1159                         msm_otg_reset(otg->phy);
1160                         schedule_work(w);
1161                 }
1162                 break;
1163         case OTG_STATE_A_HOST:
1164                 dev_dbg(otg->phy->dev, "OTG_STATE_A_HOST state\n");
1165                 if (test_bit(ID, &motg->inputs)) {
1166                         msm_otg_start_host(otg->phy, 0);
1167                         otg->phy->state = OTG_STATE_B_IDLE;
1168                         msm_otg_reset(otg->phy);
1169                         schedule_work(w);
1170                 }
1171                 break;
1172         default:
1173                 break;
1174         }
1175 }
1176
1177 static irqreturn_t msm_otg_irq(int irq, void *data)
1178 {
1179         struct msm_otg *motg = data;
1180         struct usb_phy *phy = &motg->phy;
1181         u32 otgsc = 0;
1182
1183         if (atomic_read(&motg->in_lpm)) {
1184                 disable_irq_nosync(irq);
1185                 motg->async_int = 1;
1186                 pm_runtime_get(phy->dev);
1187                 return IRQ_HANDLED;
1188         }
1189
1190         otgsc = readl(USB_OTGSC);
1191         if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1192                 return IRQ_NONE;
1193
1194         if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1195                 if (otgsc & OTGSC_ID)
1196                         set_bit(ID, &motg->inputs);
1197                 else
1198                         clear_bit(ID, &motg->inputs);
1199                 dev_dbg(phy->dev, "ID set/clear\n");
1200                 pm_runtime_get_noresume(phy->dev);
1201         } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1202                 if (otgsc & OTGSC_BSV)
1203                         set_bit(B_SESS_VLD, &motg->inputs);
1204                 else
1205                         clear_bit(B_SESS_VLD, &motg->inputs);
1206                 dev_dbg(phy->dev, "BSV set/clear\n");
1207                 pm_runtime_get_noresume(phy->dev);
1208         }
1209
1210         writel(otgsc, USB_OTGSC);
1211         schedule_work(&motg->sm_work);
1212         return IRQ_HANDLED;
1213 }
1214
1215 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1216 {
1217         struct msm_otg *motg = s->private;
1218         struct usb_otg *otg = motg->phy.otg;
1219
1220         switch (otg->phy->state) {
1221         case OTG_STATE_A_HOST:
1222                 seq_puts(s, "host\n");
1223                 break;
1224         case OTG_STATE_B_PERIPHERAL:
1225                 seq_puts(s, "peripheral\n");
1226                 break;
1227         default:
1228                 seq_puts(s, "none\n");
1229                 break;
1230         }
1231
1232         return 0;
1233 }
1234
1235 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1236 {
1237         return single_open(file, msm_otg_mode_show, inode->i_private);
1238 }
1239
1240 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1241                                 size_t count, loff_t *ppos)
1242 {
1243         struct seq_file *s = file->private_data;
1244         struct msm_otg *motg = s->private;
1245         char buf[16];
1246         struct usb_otg *otg = motg->phy.otg;
1247         int status = count;
1248         enum usb_dr_mode req_mode;
1249
1250         memset(buf, 0x00, sizeof(buf));
1251
1252         if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1253                 status = -EFAULT;
1254                 goto out;
1255         }
1256
1257         if (!strncmp(buf, "host", 4)) {
1258                 req_mode = USB_DR_MODE_HOST;
1259         } else if (!strncmp(buf, "peripheral", 10)) {
1260                 req_mode = USB_DR_MODE_PERIPHERAL;
1261         } else if (!strncmp(buf, "none", 4)) {
1262                 req_mode = USB_DR_MODE_UNKNOWN;
1263         } else {
1264                 status = -EINVAL;
1265                 goto out;
1266         }
1267
1268         switch (req_mode) {
1269         case USB_DR_MODE_UNKNOWN:
1270                 switch (otg->phy->state) {
1271                 case OTG_STATE_A_HOST:
1272                 case OTG_STATE_B_PERIPHERAL:
1273                         set_bit(ID, &motg->inputs);
1274                         clear_bit(B_SESS_VLD, &motg->inputs);
1275                         break;
1276                 default:
1277                         goto out;
1278                 }
1279                 break;
1280         case USB_DR_MODE_PERIPHERAL:
1281                 switch (otg->phy->state) {
1282                 case OTG_STATE_B_IDLE:
1283                 case OTG_STATE_A_HOST:
1284                         set_bit(ID, &motg->inputs);
1285                         set_bit(B_SESS_VLD, &motg->inputs);
1286                         break;
1287                 default:
1288                         goto out;
1289                 }
1290                 break;
1291         case USB_DR_MODE_HOST:
1292                 switch (otg->phy->state) {
1293                 case OTG_STATE_B_IDLE:
1294                 case OTG_STATE_B_PERIPHERAL:
1295                         clear_bit(ID, &motg->inputs);
1296                         break;
1297                 default:
1298                         goto out;
1299                 }
1300                 break;
1301         default:
1302                 goto out;
1303         }
1304
1305         pm_runtime_get_sync(otg->phy->dev);
1306         schedule_work(&motg->sm_work);
1307 out:
1308         return status;
1309 }
1310
1311 const struct file_operations msm_otg_mode_fops = {
1312         .open = msm_otg_mode_open,
1313         .read = seq_read,
1314         .write = msm_otg_mode_write,
1315         .llseek = seq_lseek,
1316         .release = single_release,
1317 };
1318
1319 static struct dentry *msm_otg_dbg_root;
1320 static struct dentry *msm_otg_dbg_mode;
1321
1322 static int msm_otg_debugfs_init(struct msm_otg *motg)
1323 {
1324         msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1325
1326         if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1327                 return -ENODEV;
1328
1329         msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1330                                 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1331         if (!msm_otg_dbg_mode) {
1332                 debugfs_remove(msm_otg_dbg_root);
1333                 msm_otg_dbg_root = NULL;
1334                 return -ENODEV;
1335         }
1336
1337         return 0;
1338 }
1339
1340 static void msm_otg_debugfs_cleanup(void)
1341 {
1342         debugfs_remove(msm_otg_dbg_mode);
1343         debugfs_remove(msm_otg_dbg_root);
1344 }
1345
1346 static int msm_otg_probe(struct platform_device *pdev)
1347 {
1348         struct regulator_bulk_data regs[3];
1349         int ret = 0;
1350         struct resource *res;
1351         struct msm_otg *motg;
1352         struct usb_phy *phy;
1353
1354         dev_info(&pdev->dev, "msm_otg probe\n");
1355         if (!dev_get_platdata(&pdev->dev)) {
1356                 dev_err(&pdev->dev, "No platform data given. Bailing out\n");
1357                 return -ENODEV;
1358         }
1359
1360         motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
1361         if (!motg) {
1362                 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1363                 return -ENOMEM;
1364         }
1365
1366         motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
1367                                      GFP_KERNEL);
1368         if (!motg->phy.otg) {
1369                 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1370                 return -ENOMEM;
1371         }
1372
1373         motg->pdata = dev_get_platdata(&pdev->dev);
1374         phy = &motg->phy;
1375         phy->dev = &pdev->dev;
1376
1377         motg->phy_reset_clk = devm_clk_get(&pdev->dev, "usb_phy_clk");
1378         if (IS_ERR(motg->phy_reset_clk)) {
1379                 dev_err(&pdev->dev, "failed to get usb_phy_clk\n");
1380                 return PTR_ERR(motg->phy_reset_clk);
1381         }
1382
1383         motg->clk = devm_clk_get(&pdev->dev, "usb_hs_clk");
1384         if (IS_ERR(motg->clk)) {
1385                 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1386                 return PTR_ERR(motg->clk);
1387         }
1388
1389         /*
1390          * If USB Core is running its protocol engine based on CORE CLK,
1391          * CORE CLK  must be running at >55Mhz for correct HSUSB
1392          * operation and USB core cannot tolerate frequency changes on
1393          * CORE CLK.
1394          */
1395         motg->pclk = devm_clk_get(&pdev->dev, "usb_hs_pclk");
1396         if (IS_ERR(motg->pclk)) {
1397                 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1398                 return PTR_ERR(motg->pclk);
1399         }
1400
1401         /*
1402          * USB core clock is not present on all MSM chips. This
1403          * clock is introduced to remove the dependency on AXI
1404          * bus frequency.
1405          */
1406         motg->core_clk = devm_clk_get(&pdev->dev, "usb_hs_core_clk");
1407
1408         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1409         motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1410         if (IS_ERR(motg->regs))
1411                 return PTR_ERR(motg->regs);
1412
1413         dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1414
1415         motg->irq = platform_get_irq(pdev, 0);
1416         if (!motg->irq) {
1417                 dev_err(&pdev->dev, "platform_get_irq failed\n");
1418                 return motg->irq;
1419         }
1420
1421         regs[0].supply = "vddcx";
1422         regs[1].supply = "v3p3";
1423         regs[2].supply = "v1p8";
1424
1425         ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs);
1426         if (ret)
1427                 return ret;
1428
1429         motg->vddcx = regs[0].consumer;
1430         motg->v3p3  = regs[1].consumer;
1431         motg->v1p8  = regs[2].consumer;
1432
1433         clk_set_rate(motg->clk, 60000000);
1434
1435         clk_prepare_enable(motg->clk);
1436         clk_prepare_enable(motg->pclk);
1437
1438         if (!IS_ERR(motg->core_clk))
1439                 clk_prepare_enable(motg->core_clk);
1440
1441         ret = msm_hsusb_init_vddcx(motg, 1);
1442         if (ret) {
1443                 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1444                 goto disable_clks;
1445         }
1446
1447         ret = msm_hsusb_ldo_init(motg, 1);
1448         if (ret) {
1449                 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1450                 goto disable_vddcx;
1451         }
1452         ret = msm_hsusb_ldo_set_mode(motg, 1);
1453         if (ret) {
1454                 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1455                 goto disable_ldo;
1456         }
1457
1458         writel(0, USB_USBINTR);
1459         writel(0, USB_OTGSC);
1460
1461         INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1462         INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1463         ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED,
1464                                         "msm_otg", motg);
1465         if (ret) {
1466                 dev_err(&pdev->dev, "request irq failed\n");
1467                 goto disable_ldo;
1468         }
1469
1470         phy->init = msm_otg_reset;
1471         phy->set_power = msm_otg_set_power;
1472
1473         phy->io_ops = &msm_otg_io_ops;
1474
1475         phy->otg->phy = &motg->phy;
1476         phy->otg->set_host = msm_otg_set_host;
1477         phy->otg->set_peripheral = msm_otg_set_peripheral;
1478
1479         ret = usb_add_phy(&motg->phy, USB_PHY_TYPE_USB2);
1480         if (ret) {
1481                 dev_err(&pdev->dev, "usb_add_phy failed\n");
1482                 goto disable_ldo;
1483         }
1484
1485         platform_set_drvdata(pdev, motg);
1486         device_init_wakeup(&pdev->dev, 1);
1487
1488         if (motg->pdata->mode == USB_DR_MODE_OTG &&
1489                         motg->pdata->otg_control == OTG_USER_CONTROL) {
1490                 ret = msm_otg_debugfs_init(motg);
1491                 if (ret)
1492                         dev_dbg(&pdev->dev, "Can not create mode change file\n");
1493         }
1494
1495         pm_runtime_set_active(&pdev->dev);
1496         pm_runtime_enable(&pdev->dev);
1497
1498         return 0;
1499
1500 disable_ldo:
1501         msm_hsusb_ldo_init(motg, 0);
1502 disable_vddcx:
1503         msm_hsusb_init_vddcx(motg, 0);
1504 disable_clks:
1505         clk_disable_unprepare(motg->pclk);
1506         clk_disable_unprepare(motg->clk);
1507         if (!IS_ERR(motg->core_clk))
1508                 clk_disable_unprepare(motg->core_clk);
1509         return ret;
1510 }
1511
1512 static int msm_otg_remove(struct platform_device *pdev)
1513 {
1514         struct msm_otg *motg = platform_get_drvdata(pdev);
1515         struct usb_phy *phy = &motg->phy;
1516         int cnt = 0;
1517
1518         if (phy->otg->host || phy->otg->gadget)
1519                 return -EBUSY;
1520
1521         msm_otg_debugfs_cleanup();
1522         cancel_delayed_work_sync(&motg->chg_work);
1523         cancel_work_sync(&motg->sm_work);
1524
1525         pm_runtime_resume(&pdev->dev);
1526
1527         device_init_wakeup(&pdev->dev, 0);
1528         pm_runtime_disable(&pdev->dev);
1529
1530         usb_remove_phy(phy);
1531         disable_irq(motg->irq);
1532
1533         /*
1534          * Put PHY in low power mode.
1535          */
1536         ulpi_read(phy, 0x14);
1537         ulpi_write(phy, 0x08, 0x09);
1538
1539         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1540         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1541                 if (readl(USB_PORTSC) & PORTSC_PHCD)
1542                         break;
1543                 udelay(1);
1544                 cnt++;
1545         }
1546         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1547                 dev_err(phy->dev, "Unable to suspend PHY\n");
1548
1549         clk_disable_unprepare(motg->pclk);
1550         clk_disable_unprepare(motg->clk);
1551         if (!IS_ERR(motg->core_clk))
1552                 clk_disable_unprepare(motg->core_clk);
1553         msm_hsusb_ldo_init(motg, 0);
1554
1555         pm_runtime_set_suspended(&pdev->dev);
1556
1557         return 0;
1558 }
1559
1560 #ifdef CONFIG_PM_RUNTIME
1561 static int msm_otg_runtime_idle(struct device *dev)
1562 {
1563         struct msm_otg *motg = dev_get_drvdata(dev);
1564         struct usb_otg *otg = motg->phy.otg;
1565
1566         dev_dbg(dev, "OTG runtime idle\n");
1567
1568         /*
1569          * It is observed some times that a spurious interrupt
1570          * comes when PHY is put into LPM immediately after PHY reset.
1571          * This 1 sec delay also prevents entering into LPM immediately
1572          * after asynchronous interrupt.
1573          */
1574         if (otg->phy->state != OTG_STATE_UNDEFINED)
1575                 pm_schedule_suspend(dev, 1000);
1576
1577         return -EAGAIN;
1578 }
1579
1580 static int msm_otg_runtime_suspend(struct device *dev)
1581 {
1582         struct msm_otg *motg = dev_get_drvdata(dev);
1583
1584         dev_dbg(dev, "OTG runtime suspend\n");
1585         return msm_otg_suspend(motg);
1586 }
1587
1588 static int msm_otg_runtime_resume(struct device *dev)
1589 {
1590         struct msm_otg *motg = dev_get_drvdata(dev);
1591
1592         dev_dbg(dev, "OTG runtime resume\n");
1593         return msm_otg_resume(motg);
1594 }
1595 #endif
1596
1597 #ifdef CONFIG_PM_SLEEP
1598 static int msm_otg_pm_suspend(struct device *dev)
1599 {
1600         struct msm_otg *motg = dev_get_drvdata(dev);
1601
1602         dev_dbg(dev, "OTG PM suspend\n");
1603         return msm_otg_suspend(motg);
1604 }
1605
1606 static int msm_otg_pm_resume(struct device *dev)
1607 {
1608         struct msm_otg *motg = dev_get_drvdata(dev);
1609         int ret;
1610
1611         dev_dbg(dev, "OTG PM resume\n");
1612
1613         ret = msm_otg_resume(motg);
1614         if (ret)
1615                 return ret;
1616
1617         /*
1618          * Runtime PM Documentation recommends bringing the
1619          * device to full powered state upon resume.
1620          */
1621         pm_runtime_disable(dev);
1622         pm_runtime_set_active(dev);
1623         pm_runtime_enable(dev);
1624
1625         return 0;
1626 }
1627 #endif
1628
1629 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1630         SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
1631         SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
1632                                 msm_otg_runtime_idle)
1633 };
1634
1635 static struct platform_driver msm_otg_driver = {
1636         .probe = msm_otg_probe,
1637         .remove = msm_otg_remove,
1638         .driver = {
1639                 .name = DRIVER_NAME,
1640                 .owner = THIS_MODULE,
1641                 .pm = &msm_otg_dev_pm_ops,
1642         },
1643 };
1644
1645 module_platform_driver(msm_otg_driver);
1646
1647 MODULE_LICENSE("GPL v2");
1648 MODULE_DESCRIPTION("MSM USB transceiver driver");