drivers/usb/phy/phy-msm-usb.c

   1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15  * 02110-1301, USA.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/clk.h>
  23 #include <linux/slab.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/err.h>
  26 #include <linux/delay.h>
  27 #include <linux/io.h>
  28 #include <linux/ioport.h>
  29 #include <linux/uaccess.h>
  30 #include <linux/debugfs.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/reset.h>
  36
  37 #include <linux/usb.h>
  38 #include <linux/usb/otg.h>
  39 #include <linux/usb/of.h>
  40 #include <linux/usb/ulpi.h>
  41 #include <linux/usb/gadget.h>
  42 #include <linux/usb/hcd.h>
  43 #include <linux/usb/msm_hsusb.h>
  44 #include <linux/usb/msm_hsusb_hw.h>
  45 #include <linux/regulator/consumer.h>
  46
  47 #define MSM_USB_BASE    (motg->regs)
  48 #define DRIVER_NAME     "msm_otg"
  49
  50 #define ULPI_IO_TIMEOUT_USEC    (10 * 1000)
  51 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
  52
  53 #define USB_PHY_3P3_VOL_MIN     3050000 /* uV */
  54 #define USB_PHY_3P3_VOL_MAX     3300000 /* uV */
  55 #define USB_PHY_3P3_HPM_LOAD    50000   /* uA */
  56 #define USB_PHY_3P3_LPM_LOAD    4000    /* uA */
  57
  58 #define USB_PHY_1P8_VOL_MIN     1800000 /* uV */
  59 #define USB_PHY_1P8_VOL_MAX     1800000 /* uV */
  60 #define USB_PHY_1P8_HPM_LOAD    50000   /* uA */
  61 #define USB_PHY_1P8_LPM_LOAD    4000    /* uA */
  62
  63 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
  64 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
  65 #define USB_PHY_SUSP_DIG_VOL    500000  /* uV */
  66
  67 enum vdd_levels {
  68         VDD_LEVEL_NONE = 0,
  69         VDD_LEVEL_MIN,
  70         VDD_LEVEL_MAX,
  71 };
  72
  73 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
  74 {
  75         int ret = 0;
  76
  77         if (init) {
  78                 ret = regulator_set_voltage(motg->vddcx,
  79                                 motg->vdd_levels[VDD_LEVEL_MIN],
  80                                 motg->vdd_levels[VDD_LEVEL_MAX]);
  81                 if (ret) {
  82                         dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
  83                         return ret;
  84                 }
  85
  86                 ret = regulator_enable(motg->vddcx);
  87                 if (ret)
  88                         dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
  89         } else {
  90                 ret = regulator_set_voltage(motg->vddcx, 0,
  91                                 motg->vdd_levels[VDD_LEVEL_MAX]);
  92                 if (ret)
  93                         dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
  94                 ret = regulator_disable(motg->vddcx);
  95                 if (ret)
  96                         dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
  97         }
  98
  99         return ret;
 100 }
 101
 102 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
 103 {
 104         int rc = 0;
 105
 106         if (init) {
 107                 rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN,
 108                                 USB_PHY_3P3_VOL_MAX);
 109                 if (rc) {
 110                         dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n");
 111                         goto exit;
 112                 }
 113                 rc = regulator_enable(motg->v3p3);
 114                 if (rc) {
 115                         dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
 116                         goto exit;
 117                 }
 118                 rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN,
 119                                 USB_PHY_1P8_VOL_MAX);
 120                 if (rc) {
 121                         dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n");
 122                         goto disable_3p3;
 123                 }
 124                 rc = regulator_enable(motg->v1p8);
 125                 if (rc) {
 126                         dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
 127                         goto disable_3p3;
 128                 }
 129
 130                 return 0;
 131         }
 132
 133         regulator_disable(motg->v1p8);
 134 disable_3p3:
 135         regulator_disable(motg->v3p3);
 136 exit:
 137         return rc;
 138 }
 139
 140 static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on)
 141 {
 142         int ret = 0;
 143
 144         if (on) {
 145                 ret = regulator_set_optimum_mode(motg->v1p8,
 146                                 USB_PHY_1P8_HPM_LOAD);
 147                 if (ret < 0) {
 148                         pr_err("Could not set HPM for v1p8\n");
 149                         return ret;
 150                 }
 151                 ret = regulator_set_optimum_mode(motg->v3p3,
 152                                 USB_PHY_3P3_HPM_LOAD);
 153                 if (ret < 0) {
 154                         pr_err("Could not set HPM for v3p3\n");
 155                         regulator_set_optimum_mode(motg->v1p8,
 156                                 USB_PHY_1P8_LPM_LOAD);
 157                         return ret;
 158                 }
 159         } else {
 160                 ret = regulator_set_optimum_mode(motg->v1p8,
 161                                 USB_PHY_1P8_LPM_LOAD);
 162                 if (ret < 0)
 163                         pr_err("Could not set LPM for v1p8\n");
 164                 ret = regulator_set_optimum_mode(motg->v3p3,
 165                                 USB_PHY_3P3_LPM_LOAD);
 166                 if (ret < 0)
 167                         pr_err("Could not set LPM for v3p3\n");
 168         }
 169
 170         pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
 171         return ret < 0 ? ret : 0;
 172 }
 173
 174 static int ulpi_read(struct usb_phy *phy, u32 reg)
 175 {
 176         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 177         int cnt = 0;
 178
 179         /* initiate read operation */
 180         writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
 181                USB_ULPI_VIEWPORT);
 182
 183         /* wait for completion */
 184         while (cnt < ULPI_IO_TIMEOUT_USEC) {
 185                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
 186                         break;
 187                 udelay(1);
 188                 cnt++;
 189         }
 190
 191         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
 192                 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
 193                         readl(USB_ULPI_VIEWPORT));
 194                 return -ETIMEDOUT;
 195         }
 196         return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
 197 }
 198
 199 static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
 200 {
 201         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 202         int cnt = 0;
 203
 204         /* initiate write operation */
 205         writel(ULPI_RUN | ULPI_WRITE |
 206                ULPI_ADDR(reg) | ULPI_DATA(val),
 207                USB_ULPI_VIEWPORT);
 208
 209         /* wait for completion */
 210         while (cnt < ULPI_IO_TIMEOUT_USEC) {
 211                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
 212                         break;
 213                 udelay(1);
 214                 cnt++;
 215         }
 216
 217         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
 218                 dev_err(phy->dev, "ulpi_write: timeout\n");
 219                 return -ETIMEDOUT;
 220         }
 221         return 0;
 222 }
 223
 224 static struct usb_phy_io_ops msm_otg_io_ops = {
 225         .read = ulpi_read,
 226         .write = ulpi_write,
 227 };
 228
 229 static void ulpi_init(struct msm_otg *motg)
 230 {
 231         struct msm_otg_platform_data *pdata = motg->pdata;
 232         int *seq = pdata->phy_init_seq, idx;
 233         u32 addr = ULPI_EXT_VENDOR_SPECIFIC;
 234
 235         for (idx = 0; idx < pdata->phy_init_sz; idx++) {
 236                 if (seq[idx] == -1)
 237                         continue;
 238
 239                 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
 240                                 seq[idx], addr + idx);
 241                 ulpi_write(&motg->phy, seq[idx], addr + idx);
 242         }
 243 }
 244
 245 static int msm_phy_notify_disconnect(struct usb_phy *phy,
 246                                    enum usb_device_speed speed)
 247 {
 248         int val;
 249
 250         /*
 251          * Put the transceiver in non-driving mode. Otherwise host
 252          * may not detect soft-disconnection.
 253          */
 254         val = ulpi_read(phy, ULPI_FUNC_CTRL);
 255         val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
 256         val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
 257         ulpi_write(phy, val, ULPI_FUNC_CTRL);
 258
 259         return 0;
 260 }
 261
 262 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
 263 {
 264         int ret;
 265
 266         if (motg->pdata->link_clk_reset)
 267                 ret = motg->pdata->link_clk_reset(motg->clk, assert);
 268         else if (assert)
 269                 ret = reset_control_assert(motg->link_rst);
 270         else
 271                 ret = reset_control_deassert(motg->link_rst);
 272
 273         if (ret)
 274                 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
 275                         assert ? "assert" : "deassert");
 276
 277         return ret;
 278 }
 279
 280 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
 281 {
 282         int ret;
 283
 284         if (motg->pdata->phy_clk_reset)
 285                 ret = motg->pdata->phy_clk_reset(motg->phy_reset_clk);
 286         else
 287                 ret = reset_control_reset(motg->phy_rst);
 288
 289         if (ret)
 290                 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
 291
 292         return ret;
 293 }
 294
 295 static int msm_link_reset(struct msm_otg *motg)
 296 {
 297         u32 val;
 298         int ret;
 299
 300         ret = msm_otg_link_clk_reset(motg, 1);
 301         if (ret)
 302                 return ret;
 303
 304         /* wait for 1ms delay as suggested in HPG. */
 305         usleep_range(1000, 1200);
 306
 307         ret = msm_otg_link_clk_reset(motg, 0);
 308         if (ret)
 309                 return ret;
 310
 311         if (motg->phy_number)
 312                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
 313
 314         /* put transceiver in serial mode as part of reset */
 315         val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
 316         writel(val | PORTSC_PTS_SERIAL, USB_PORTSC);
 317
 318         return 0;
 319 }
 320
 321 static int msm_otg_reset(struct usb_phy *phy)
 322 {
 323         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 324         int cnt = 0;
 325
 326         writel(USBCMD_RESET, USB_USBCMD);
 327         while (cnt < LINK_RESET_TIMEOUT_USEC) {
 328                 if (!(readl(USB_USBCMD) & USBCMD_RESET))
 329                         break;
 330                 udelay(1);
 331                 cnt++;
 332         }
 333         if (cnt >= LINK_RESET_TIMEOUT_USEC)
 334                 return -ETIMEDOUT;
 335
 336         /* select ULPI phy and clear other status/control bits in PORTSC */
 337         writel(PORTSC_PTS_ULPI, USB_PORTSC);
 338
 339         writel(0x0, USB_AHBBURST);
 340         writel(0x08, USB_AHBMODE);
 341
 342         if (motg->phy_number)
 343                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
 344         return 0;
 345 }
 346
 347 static void msm_phy_reset(struct msm_otg *motg)
 348 {
 349         void __iomem *addr;
 350
 351         if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY) {
 352                 msm_otg_phy_clk_reset(motg);
 353                 return;
 354         }
 355
 356         addr = USB_PHY_CTRL;
 357         if (motg->phy_number)
 358                 addr = USB_PHY_CTRL2;
 359
 360         /* Assert USB PHY_POR */
 361         writel(readl(addr) | PHY_POR_ASSERT, addr);
 362
 363         /*
 364          * wait for minimum 10 microseconds as suggested in HPG.
 365          * Use a slightly larger value since the exact value didn't
 366          * work 100% of the time.
 367          */
 368         udelay(12);
 369
 370         /* Deassert USB PHY_POR */
 371         writel(readl(addr) & ~PHY_POR_ASSERT, addr);
 372 }
 373
 374 static int msm_usb_reset(struct usb_phy *phy)
 375 {
 376         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 377         int ret;
 378
 379         if (!IS_ERR(motg->core_clk))
 380                 clk_prepare_enable(motg->core_clk);
 381
 382         ret = msm_link_reset(motg);
 383         if (ret) {
 384                 dev_err(phy->dev, "phy_reset failed\n");
 385                 return ret;
 386         }
 387
 388         ret = msm_otg_reset(&motg->phy);
 389         if (ret) {
 390                 dev_err(phy->dev, "link reset failed\n");
 391                 return ret;
 392         }
 393
 394         msleep(100);
 395
 396         /* Reset USB PHY after performing USB Link RESET */
 397         msm_phy_reset(motg);
 398
 399         if (!IS_ERR(motg->core_clk))
 400                 clk_disable_unprepare(motg->core_clk);
 401
 402         return 0;
 403 }
 404
 405 static int msm_phy_init(struct usb_phy *phy)
 406 {
 407         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 408         struct msm_otg_platform_data *pdata = motg->pdata;
 409         u32 val, ulpi_val = 0;
 410
 411         /* Program USB PHY Override registers. */
 412         ulpi_init(motg);
 413
 414         /*
 415          * It is recommended in HPG to reset USB PHY after programming
 416          * USB PHY Override registers.
 417          */
 418         msm_phy_reset(motg);
 419
 420         if (pdata->otg_control == OTG_PHY_CONTROL) {
 421                 val = readl(USB_OTGSC);
 422                 if (pdata->mode == USB_DR_MODE_OTG) {
 423                         ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
 424                         val |= OTGSC_IDIE | OTGSC_BSVIE;
 425                 } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) {
 426                         ulpi_val = ULPI_INT_SESS_VALID;
 427                         val |= OTGSC_BSVIE;
 428                 }
 429                 writel(val, USB_OTGSC);
 430                 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
 431                 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
 432         }
 433
 434         if (motg->phy_number)
 435                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
 436
 437         return 0;
 438 }
 439
 440 #define PHY_SUSPEND_TIMEOUT_USEC        (500 * 1000)
 441 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
 442
 443 #ifdef CONFIG_PM
 444
 445 static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high)
 446 {
 447         int max_vol = motg->vdd_levels[VDD_LEVEL_MAX];
 448         int min_vol;
 449         int ret;
 450
 451         if (high)
 452                 min_vol = motg->vdd_levels[VDD_LEVEL_MIN];
 453         else
 454                 min_vol = motg->vdd_levels[VDD_LEVEL_NONE];
 455
 456         ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol);
 457         if (ret) {
 458                 pr_err("Cannot set vddcx voltage\n");
 459                 return ret;
 460         }
 461
 462         pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
 463
 464         return ret;
 465 }
 466
 467 static int msm_otg_suspend(struct msm_otg *motg)
 468 {
 469         struct usb_phy *phy = &motg->phy;
 470         struct usb_bus *bus = phy->otg->host;
 471         struct msm_otg_platform_data *pdata = motg->pdata;
 472         void __iomem *addr;
 473         int cnt = 0;
 474
 475         if (atomic_read(&motg->in_lpm))
 476                 return 0;
 477
 478         disable_irq(motg->irq);
 479         /*
 480          * Chipidea 45-nm PHY suspend sequence:
 481          *
 482          * Interrupt Latch Register auto-clear feature is not present
 483          * in all PHY versions. Latch register is clear on read type.
 484          * Clear latch register to avoid spurious wakeup from
 485          * low power mode (LPM).
 486          *
 487          * PHY comparators are disabled when PHY enters into low power
 488          * mode (LPM). Keep PHY comparators ON in LPM only when we expect
 489          * VBUS/Id notifications from USB PHY. Otherwise turn off USB
 490          * PHY comparators. This save significant amount of power.
 491          *
 492          * PLL is not turned off when PHY enters into low power mode (LPM).
 493          * Disable PLL for maximum power savings.
 494          */
 495
 496         if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
 497                 ulpi_read(phy, 0x14);
 498                 if (pdata->otg_control == OTG_PHY_CONTROL)
 499                         ulpi_write(phy, 0x01, 0x30);
 500                 ulpi_write(phy, 0x08, 0x09);
 501         }
 502
 503         /*
 504          * PHY may take some time or even fail to enter into low power
 505          * mode (LPM). Hence poll for 500 msec and reset the PHY and link
 506          * in failure case.
 507          */
 508         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
 509         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
 510                 if (readl(USB_PORTSC) & PORTSC_PHCD)
 511                         break;
 512                 udelay(1);
 513                 cnt++;
 514         }
 515
 516         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
 517                 dev_err(phy->dev, "Unable to suspend PHY\n");
 518                 msm_otg_reset(phy);
 519                 enable_irq(motg->irq);
 520                 return -ETIMEDOUT;
 521         }
 522
 523         /*
 524          * PHY has capability to generate interrupt asynchronously in low
 525          * power mode (LPM). This interrupt is level triggered. So USB IRQ
 526          * line must be disabled till async interrupt enable bit is cleared
 527          * in USBCMD register. Assert STP (ULPI interface STOP signal) to
 528          * block data communication from PHY.
 529          */
 530         writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
 531
 532         addr = USB_PHY_CTRL;
 533         if (motg->phy_number)
 534                 addr = USB_PHY_CTRL2;
 535
 536         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 537                         motg->pdata->otg_control == OTG_PMIC_CONTROL)
 538                 writel(readl(addr) | PHY_RETEN, addr);
 539
 540         clk_disable_unprepare(motg->pclk);
 541         clk_disable_unprepare(motg->clk);
 542         if (!IS_ERR(motg->core_clk))
 543                 clk_disable_unprepare(motg->core_clk);
 544
 545         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 546                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
 547                 msm_hsusb_ldo_set_mode(motg, 0);
 548                 msm_hsusb_config_vddcx(motg, 0);
 549         }
 550
 551         if (device_may_wakeup(phy->dev))
 552                 enable_irq_wake(motg->irq);
 553         if (bus)
 554                 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 555
 556         atomic_set(&motg->in_lpm, 1);
 557         enable_irq(motg->irq);
 558
 559         dev_info(phy->dev, "USB in low power mode\n");
 560
 561         return 0;
 562 }
 563
 564 static int msm_otg_resume(struct msm_otg *motg)
 565 {
 566         struct usb_phy *phy = &motg->phy;
 567         struct usb_bus *bus = phy->otg->host;
 568         void __iomem *addr;
 569         int cnt = 0;
 570         unsigned temp;
 571
 572         if (!atomic_read(&motg->in_lpm))
 573                 return 0;
 574
 575         clk_prepare_enable(motg->pclk);
 576         clk_prepare_enable(motg->clk);
 577         if (!IS_ERR(motg->core_clk))
 578                 clk_prepare_enable(motg->core_clk);
 579
 580         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 581                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
 582
 583                 addr = USB_PHY_CTRL;
 584                 if (motg->phy_number)
 585                         addr = USB_PHY_CTRL2;
 586
 587                 msm_hsusb_ldo_set_mode(motg, 1);
 588                 msm_hsusb_config_vddcx(motg, 1);
 589                 writel(readl(addr) & ~PHY_RETEN, addr);
 590         }
 591
 592         temp = readl(USB_USBCMD);
 593         temp &= ~ASYNC_INTR_CTRL;
 594         temp &= ~ULPI_STP_CTRL;
 595         writel(temp, USB_USBCMD);
 596
 597         /*
 598          * PHY comes out of low power mode (LPM) in case of wakeup
 599          * from asynchronous interrupt.
 600          */
 601         if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 602                 goto skip_phy_resume;
 603
 604         writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
 605         while (cnt < PHY_RESUME_TIMEOUT_USEC) {
 606                 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 607                         break;
 608                 udelay(1);
 609                 cnt++;
 610         }
 611
 612         if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
 613                 /*
 614                  * This is a fatal error. Reset the link and
 615                  * PHY. USB state can not be restored. Re-insertion
 616                  * of USB cable is the only way to get USB working.
 617                  */
 618                 dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n");
 619                 msm_otg_reset(phy);
 620         }
 621
 622 skip_phy_resume:
 623         if (device_may_wakeup(phy->dev))
 624                 disable_irq_wake(motg->irq);
 625         if (bus)
 626                 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 627
 628         atomic_set(&motg->in_lpm, 0);
 629
 630         if (motg->async_int) {
 631                 motg->async_int = 0;
 632                 pm_runtime_put(phy->dev);
 633                 enable_irq(motg->irq);
 634         }
 635
 636         dev_info(phy->dev, "USB exited from low power mode\n");
 637
 638         return 0;
 639 }
 640 #endif
 641
 642 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
 643 {
 644         if (motg->cur_power == mA)
 645                 return;
 646
 647         /* TODO: Notify PMIC about available current */
 648         dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
 649         motg->cur_power = mA;
 650 }
 651
 652 static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
 653 {
 654         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 655
 656         /*
 657          * Gadget driver uses set_power method to notify about the
 658          * available current based on suspend/configured states.
 659          *
 660          * IDEV_CHG can be drawn irrespective of suspend/un-configured
 661          * states when CDP/ACA is connected.
 662          */
 663         if (motg->chg_type == USB_SDP_CHARGER)
 664                 msm_otg_notify_charger(motg, mA);
 665
 666         return 0;
 667 }
 668
 669 static void msm_otg_start_host(struct usb_phy *phy, int on)
 670 {
 671         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 672         struct msm_otg_platform_data *pdata = motg->pdata;
 673         struct usb_hcd *hcd;
 674
 675         if (!phy->otg->host)
 676                 return;
 677
 678         hcd = bus_to_hcd(phy->otg->host);
 679
 680         if (on) {
 681                 dev_dbg(phy->dev, "host on\n");
 682
 683                 if (pdata->vbus_power)
 684                         pdata->vbus_power(1);
 685                 /*
 686                  * Some boards have a switch cotrolled by gpio
 687                  * to enable/disable internal HUB. Enable internal
 688                  * HUB before kicking the host.
 689                  */
 690                 if (pdata->setup_gpio)
 691                         pdata->setup_gpio(OTG_STATE_A_HOST);
 692 #ifdef CONFIG_USB
 693                 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 694                 device_wakeup_enable(hcd->self.controller);
 695 #endif
 696         } else {
 697                 dev_dbg(phy->dev, "host off\n");
 698
 699 #ifdef CONFIG_USB
 700                 usb_remove_hcd(hcd);
 701 #endif
 702                 if (pdata->setup_gpio)
 703                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 704                 if (pdata->vbus_power)
 705                         pdata->vbus_power(0);
 706         }
 707 }
 708
 709 static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
 710 {
 711         struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
 712         struct usb_hcd *hcd;
 713
 714         /*
 715          * Fail host registration if this board can support
 716          * only peripheral configuration.
 717          */
 718         if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) {
 719                 dev_info(otg->phy->dev, "Host mode is not supported\n");
 720                 return -ENODEV;
 721         }
 722
 723         if (!host) {
 724                 if (otg->phy->state == OTG_STATE_A_HOST) {
 725                         pm_runtime_get_sync(otg->phy->dev);
 726                         msm_otg_start_host(otg->phy, 0);
 727                         otg->host = NULL;
 728                         otg->phy->state = OTG_STATE_UNDEFINED;
 729                         schedule_work(&motg->sm_work);
 730                 } else {
 731                         otg->host = NULL;
 732                 }
 733
 734                 return 0;
 735         }
 736
 737         hcd = bus_to_hcd(host);
 738         hcd->power_budget = motg->pdata->power_budget;
 739
 740         otg->host = host;
 741         dev_dbg(otg->phy->dev, "host driver registered w/ tranceiver\n");
 742
 743         /*
 744          * Kick the state machine work, if peripheral is not supported
 745          * or peripheral is already registered with us.
 746          */
 747         if (motg->pdata->mode == USB_DR_MODE_HOST || otg->gadget) {
 748                 pm_runtime_get_sync(otg->phy->dev);
 749                 schedule_work(&motg->sm_work);
 750         }
 751
 752         return 0;
 753 }
 754
 755 static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
 756 {
 757         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 758         struct msm_otg_platform_data *pdata = motg->pdata;
 759
 760         if (!phy->otg->gadget)
 761                 return;
 762
 763         if (on) {
 764                 dev_dbg(phy->dev, "gadget on\n");
 765                 /*
 766                  * Some boards have a switch cotrolled by gpio
 767                  * to enable/disable internal HUB. Disable internal
 768                  * HUB before kicking the gadget.
 769                  */
 770                 if (pdata->setup_gpio)
 771                         pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
 772                 usb_gadget_vbus_connect(phy->otg->gadget);
 773         } else {
 774                 dev_dbg(phy->dev, "gadget off\n");
 775                 usb_gadget_vbus_disconnect(phy->otg->gadget);
 776                 if (pdata->setup_gpio)
 777                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 778         }
 779
 780 }
 781
 782 static int msm_otg_set_peripheral(struct usb_otg *otg,
 783                                         struct usb_gadget *gadget)
 784 {
 785         struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
 786
 787         /*
 788          * Fail peripheral registration if this board can support
 789          * only host configuration.
 790          */
 791         if (motg->pdata->mode == USB_DR_MODE_HOST) {
 792                 dev_info(otg->phy->dev, "Peripheral mode is not supported\n");
 793                 return -ENODEV;
 794         }
 795
 796         if (!gadget) {
 797                 if (otg->phy->state == OTG_STATE_B_PERIPHERAL) {
 798                         pm_runtime_get_sync(otg->phy->dev);
 799                         msm_otg_start_peripheral(otg->phy, 0);
 800                         otg->gadget = NULL;
 801                         otg->phy->state = OTG_STATE_UNDEFINED;
 802                         schedule_work(&motg->sm_work);
 803                 } else {
 804                         otg->gadget = NULL;
 805                 }
 806
 807                 return 0;
 808         }
 809         otg->gadget = gadget;
 810         dev_dbg(otg->phy->dev, "peripheral driver registered w/ tranceiver\n");
 811
 812         /*
 813          * Kick the state machine work, if host is not supported
 814          * or host is already registered with us.
 815          */
 816         if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL || otg->host) {
 817                 pm_runtime_get_sync(otg->phy->dev);
 818                 schedule_work(&motg->sm_work);
 819         }
 820
 821         return 0;
 822 }
 823
 824 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
 825 {
 826         struct usb_phy *phy = &motg->phy;
 827         u32 chg_det;
 828         bool ret = false;
 829
 830         switch (motg->pdata->phy_type) {
 831         case CI_45NM_INTEGRATED_PHY:
 832                 chg_det = ulpi_read(phy, 0x34);
 833                 ret = chg_det & (1 << 4);
 834                 break;
 835         case SNPS_28NM_INTEGRATED_PHY:
 836                 chg_det = ulpi_read(phy, 0x87);
 837                 ret = chg_det & 1;
 838                 break;
 839         default:
 840                 break;
 841         }
 842         return ret;
 843 }
 844
 845 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
 846 {
 847         struct usb_phy *phy = &motg->phy;
 848         u32 chg_det;
 849
 850         switch (motg->pdata->phy_type) {
 851         case CI_45NM_INTEGRATED_PHY:
 852                 chg_det = ulpi_read(phy, 0x34);
 853                 /* Turn off charger block */
 854                 chg_det |= ~(1 << 1);
 855                 ulpi_write(phy, chg_det, 0x34);
 856                 udelay(20);
 857                 /* control chg block via ULPI */
 858                 chg_det &= ~(1 << 3);
 859                 ulpi_write(phy, chg_det, 0x34);
 860                 /* put it in host mode for enabling D- source */
 861                 chg_det &= ~(1 << 2);
 862                 ulpi_write(phy, chg_det, 0x34);
 863                 /* Turn on chg detect block */
 864                 chg_det &= ~(1 << 1);
 865                 ulpi_write(phy, chg_det, 0x34);
 866                 udelay(20);
 867                 /* enable chg detection */
 868                 chg_det &= ~(1 << 0);
 869                 ulpi_write(phy, chg_det, 0x34);
 870                 break;
 871         case SNPS_28NM_INTEGRATED_PHY:
 872                 /*
 873                  * Configure DM as current source, DP as current sink
 874                  * and enable battery charging comparators.
 875                  */
 876                 ulpi_write(phy, 0x8, 0x85);
 877                 ulpi_write(phy, 0x2, 0x85);
 878                 ulpi_write(phy, 0x1, 0x85);
 879                 break;
 880         default:
 881                 break;
 882         }
 883 }
 884
 885 static bool msm_chg_check_primary_det(struct msm_otg *motg)
 886 {
 887         struct usb_phy *phy = &motg->phy;
 888         u32 chg_det;
 889         bool ret = false;
 890
 891         switch (motg->pdata->phy_type) {
 892         case CI_45NM_INTEGRATED_PHY:
 893                 chg_det = ulpi_read(phy, 0x34);
 894                 ret = chg_det & (1 << 4);
 895                 break;
 896         case SNPS_28NM_INTEGRATED_PHY:
 897                 chg_det = ulpi_read(phy, 0x87);
 898                 ret = chg_det & 1;
 899                 break;
 900         default:
 901                 break;
 902         }
 903         return ret;
 904 }
 905
 906 static void msm_chg_enable_primary_det(struct msm_otg *motg)
 907 {
 908         struct usb_phy *phy = &motg->phy;
 909         u32 chg_det;
 910
 911         switch (motg->pdata->phy_type) {
 912         case CI_45NM_INTEGRATED_PHY:
 913                 chg_det = ulpi_read(phy, 0x34);
 914                 /* enable chg detection */
 915                 chg_det &= ~(1 << 0);
 916                 ulpi_write(phy, chg_det, 0x34);
 917                 break;
 918         case SNPS_28NM_INTEGRATED_PHY:
 919                 /*
 920                  * Configure DP as current source, DM as current sink
 921                  * and enable battery charging comparators.
 922                  */
 923                 ulpi_write(phy, 0x2, 0x85);
 924                 ulpi_write(phy, 0x1, 0x85);
 925                 break;
 926         default:
 927                 break;
 928         }
 929 }
 930
 931 static bool msm_chg_check_dcd(struct msm_otg *motg)
 932 {
 933         struct usb_phy *phy = &motg->phy;
 934         u32 line_state;
 935         bool ret = false;
 936
 937         switch (motg->pdata->phy_type) {
 938         case CI_45NM_INTEGRATED_PHY:
 939                 line_state = ulpi_read(phy, 0x15);
 940                 ret = !(line_state & 1);
 941                 break;
 942         case SNPS_28NM_INTEGRATED_PHY:
 943                 line_state = ulpi_read(phy, 0x87);
 944                 ret = line_state & 2;
 945                 break;
 946         default:
 947                 break;
 948         }
 949         return ret;
 950 }
 951
 952 static void msm_chg_disable_dcd(struct msm_otg *motg)
 953 {
 954         struct usb_phy *phy = &motg->phy;
 955         u32 chg_det;
 956
 957         switch (motg->pdata->phy_type) {
 958         case CI_45NM_INTEGRATED_PHY:
 959                 chg_det = ulpi_read(phy, 0x34);
 960                 chg_det &= ~(1 << 5);
 961                 ulpi_write(phy, chg_det, 0x34);
 962                 break;
 963         case SNPS_28NM_INTEGRATED_PHY:
 964                 ulpi_write(phy, 0x10, 0x86);
 965                 break;
 966         default:
 967                 break;
 968         }
 969 }
 970
 971 static void msm_chg_enable_dcd(struct msm_otg *motg)
 972 {
 973         struct usb_phy *phy = &motg->phy;
 974         u32 chg_det;
 975
 976         switch (motg->pdata->phy_type) {
 977         case CI_45NM_INTEGRATED_PHY:
 978                 chg_det = ulpi_read(phy, 0x34);
 979                 /* Turn on D+ current source */
 980                 chg_det |= (1 << 5);
 981                 ulpi_write(phy, chg_det, 0x34);
 982                 break;
 983         case SNPS_28NM_INTEGRATED_PHY:
 984                 /* Data contact detection enable */
 985                 ulpi_write(phy, 0x10, 0x85);
 986                 break;
 987         default:
 988                 break;
 989         }
 990 }
 991
 992 static void msm_chg_block_on(struct msm_otg *motg)
 993 {
 994         struct usb_phy *phy = &motg->phy;
 995         u32 func_ctrl, chg_det;
 996
 997         /* put the controller in non-driving mode */
 998         func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
 999         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1000         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
1001         ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1002
1003         switch (motg->pdata->phy_type) {
1004         case CI_45NM_INTEGRATED_PHY:
1005                 chg_det = ulpi_read(phy, 0x34);
1006                 /* control chg block via ULPI */
1007                 chg_det &= ~(1 << 3);
1008                 ulpi_write(phy, chg_det, 0x34);
1009                 /* Turn on chg detect block */
1010                 chg_det &= ~(1 << 1);
1011                 ulpi_write(phy, chg_det, 0x34);
1012                 udelay(20);
1013                 break;
1014         case SNPS_28NM_INTEGRATED_PHY:
1015                 /* Clear charger detecting control bits */
1016                 ulpi_write(phy, 0x3F, 0x86);
1017                 /* Clear alt interrupt latch and enable bits */
1018                 ulpi_write(phy, 0x1F, 0x92);
1019                 ulpi_write(phy, 0x1F, 0x95);
1020                 udelay(100);
1021                 break;
1022         default:
1023                 break;
1024         }
1025 }
1026
1027 static void msm_chg_block_off(struct msm_otg *motg)
1028 {
1029         struct usb_phy *phy = &motg->phy;
1030         u32 func_ctrl, chg_det;
1031
1032         switch (motg->pdata->phy_type) {
1033         case CI_45NM_INTEGRATED_PHY:
1034                 chg_det = ulpi_read(phy, 0x34);
1035                 /* Turn off charger block */
1036                 chg_det |= ~(1 << 1);
1037                 ulpi_write(phy, chg_det, 0x34);
1038                 break;
1039         case SNPS_28NM_INTEGRATED_PHY:
1040                 /* Clear charger detecting control bits */
1041                 ulpi_write(phy, 0x3F, 0x86);
1042                 /* Clear alt interrupt latch and enable bits */
1043                 ulpi_write(phy, 0x1F, 0x92);
1044                 ulpi_write(phy, 0x1F, 0x95);
1045                 break;
1046         default:
1047                 break;
1048         }
1049
1050         /* put the controller in normal mode */
1051         func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1052         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1053         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1054         ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1055 }
1056
1057 #define MSM_CHG_DCD_POLL_TIME           (100 * HZ/1000) /* 100 msec */
1058 #define MSM_CHG_DCD_MAX_RETRIES         6 /* Tdcd_tmout = 6 * 100 msec */
1059 #define MSM_CHG_PRIMARY_DET_TIME        (40 * HZ/1000) /* TVDPSRC_ON */
1060 #define MSM_CHG_SECONDARY_DET_TIME      (40 * HZ/1000) /* TVDMSRC_ON */
1061 static void msm_chg_detect_work(struct work_struct *w)
1062 {
1063         struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1064         struct usb_phy *phy = &motg->phy;
1065         bool is_dcd, tmout, vout;
1066         unsigned long delay;
1067
1068         dev_dbg(phy->dev, "chg detection work\n");
1069         switch (motg->chg_state) {
1070         case USB_CHG_STATE_UNDEFINED:
1071                 pm_runtime_get_sync(phy->dev);
1072                 msm_chg_block_on(motg);
1073                 msm_chg_enable_dcd(motg);
1074                 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1075                 motg->dcd_retries = 0;
1076                 delay = MSM_CHG_DCD_POLL_TIME;
1077                 break;
1078         case USB_CHG_STATE_WAIT_FOR_DCD:
1079                 is_dcd = msm_chg_check_dcd(motg);
1080                 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1081                 if (is_dcd || tmout) {
1082                         msm_chg_disable_dcd(motg);
1083                         msm_chg_enable_primary_det(motg);
1084                         delay = MSM_CHG_PRIMARY_DET_TIME;
1085                         motg->chg_state = USB_CHG_STATE_DCD_DONE;
1086                 } else {
1087                         delay = MSM_CHG_DCD_POLL_TIME;
1088                 }
1089                 break;
1090         case USB_CHG_STATE_DCD_DONE:
1091                 vout = msm_chg_check_primary_det(motg);
1092                 if (vout) {
1093                         msm_chg_enable_secondary_det(motg);
1094                         delay = MSM_CHG_SECONDARY_DET_TIME;
1095                         motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1096                 } else {
1097                         motg->chg_type = USB_SDP_CHARGER;
1098                         motg->chg_state = USB_CHG_STATE_DETECTED;
1099                         delay = 0;
1100                 }
1101                 break;
1102         case USB_CHG_STATE_PRIMARY_DONE:
1103                 vout = msm_chg_check_secondary_det(motg);
1104                 if (vout)
1105                         motg->chg_type = USB_DCP_CHARGER;
1106                 else
1107                         motg->chg_type = USB_CDP_CHARGER;
1108                 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1109                 /* fall through */
1110         case USB_CHG_STATE_SECONDARY_DONE:
1111                 motg->chg_state = USB_CHG_STATE_DETECTED;
1112         case USB_CHG_STATE_DETECTED:
1113                 msm_chg_block_off(motg);
1114                 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1115                 schedule_work(&motg->sm_work);
1116                 return;
1117         default:
1118                 return;
1119         }
1120
1121         schedule_delayed_work(&motg->chg_work, delay);
1122 }
1123
1124 /*
1125  * We support OTG, Peripheral only and Host only configurations. In case
1126  * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1127  * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1128  * enabled when switch is controlled by user and default mode is supplied
1129  * by board file, which can be changed by userspace later.
1130  */
1131 static void msm_otg_init_sm(struct msm_otg *motg)
1132 {
1133         struct msm_otg_platform_data *pdata = motg->pdata;
1134         u32 otgsc = readl(USB_OTGSC);
1135
1136         switch (pdata->mode) {
1137         case USB_DR_MODE_OTG:
1138                 if (pdata->otg_control == OTG_PHY_CONTROL) {
1139                         if (otgsc & OTGSC_ID)
1140                                 set_bit(ID, &motg->inputs);
1141                         else
1142                                 clear_bit(ID, &motg->inputs);
1143
1144                         if (otgsc & OTGSC_BSV)
1145                                 set_bit(B_SESS_VLD, &motg->inputs);
1146                         else
1147                                 clear_bit(B_SESS_VLD, &motg->inputs);
1148                 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1149                                 set_bit(ID, &motg->inputs);
1150                                 clear_bit(B_SESS_VLD, &motg->inputs);
1151                 }
1152                 break;
1153         case USB_DR_MODE_HOST:
1154                 clear_bit(ID, &motg->inputs);
1155                 break;
1156         case USB_DR_MODE_PERIPHERAL:
1157                 set_bit(ID, &motg->inputs);
1158                 if (otgsc & OTGSC_BSV)
1159                         set_bit(B_SESS_VLD, &motg->inputs);
1160                 else
1161                         clear_bit(B_SESS_VLD, &motg->inputs);
1162                 break;
1163         default:
1164                 break;
1165         }
1166 }
1167
1168 static void msm_otg_sm_work(struct work_struct *w)
1169 {
1170         struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1171         struct usb_otg *otg = motg->phy.otg;
1172
1173         switch (otg->phy->state) {
1174         case OTG_STATE_UNDEFINED:
1175                 dev_dbg(otg->phy->dev, "OTG_STATE_UNDEFINED state\n");
1176                 msm_otg_reset(otg->phy);
1177                 msm_otg_init_sm(motg);
1178                 otg->phy->state = OTG_STATE_B_IDLE;
1179                 /* FALL THROUGH */
1180         case OTG_STATE_B_IDLE:
1181                 dev_dbg(otg->phy->dev, "OTG_STATE_B_IDLE state\n");
1182                 if (!test_bit(ID, &motg->inputs) && otg->host) {
1183                         /* disable BSV bit */
1184                         writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1185                         msm_otg_start_host(otg->phy, 1);
1186                         otg->phy->state = OTG_STATE_A_HOST;
1187                 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1188                         switch (motg->chg_state) {
1189                         case USB_CHG_STATE_UNDEFINED:
1190                                 msm_chg_detect_work(&motg->chg_work.work);
1191                                 break;
1192                         case USB_CHG_STATE_DETECTED:
1193                                 switch (motg->chg_type) {
1194                                 case USB_DCP_CHARGER:
1195                                         msm_otg_notify_charger(motg,
1196                                                         IDEV_CHG_MAX);
1197                                         break;
1198                                 case USB_CDP_CHARGER:
1199                                         msm_otg_notify_charger(motg,
1200                                                         IDEV_CHG_MAX);
1201                                         msm_otg_start_peripheral(otg->phy, 1);
1202                                         otg->phy->state
1203                                                 = OTG_STATE_B_PERIPHERAL;
1204                                         break;
1205                                 case USB_SDP_CHARGER:
1206                                         msm_otg_notify_charger(motg, IUNIT);
1207                                         msm_otg_start_peripheral(otg->phy, 1);
1208                                         otg->phy->state
1209                                                 = OTG_STATE_B_PERIPHERAL;
1210                                         break;
1211                                 default:
1212                                         break;
1213                                 }
1214                                 break;
1215                         default:
1216                                 break;
1217                         }
1218                 } else {
1219                         /*
1220                          * If charger detection work is pending, decrement
1221                          * the pm usage counter to balance with the one that
1222                          * is incremented in charger detection work.
1223                          */
1224                         if (cancel_delayed_work_sync(&motg->chg_work)) {
1225                                 pm_runtime_put_sync(otg->phy->dev);
1226                                 msm_otg_reset(otg->phy);
1227                         }
1228                         msm_otg_notify_charger(motg, 0);
1229                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1230                         motg->chg_type = USB_INVALID_CHARGER;
1231                 }
1232                 pm_runtime_put_sync(otg->phy->dev);
1233                 break;
1234         case OTG_STATE_B_PERIPHERAL:
1235                 dev_dbg(otg->phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1236                 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1237                                 !test_bit(ID, &motg->inputs)) {
1238                         msm_otg_notify_charger(motg, 0);
1239                         msm_otg_start_peripheral(otg->phy, 0);
1240                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1241                         motg->chg_type = USB_INVALID_CHARGER;
1242                         otg->phy->state = OTG_STATE_B_IDLE;
1243                         msm_otg_reset(otg->phy);
1244                         schedule_work(w);
1245                 }
1246                 break;
1247         case OTG_STATE_A_HOST:
1248                 dev_dbg(otg->phy->dev, "OTG_STATE_A_HOST state\n");
1249                 if (test_bit(ID, &motg->inputs)) {
1250                         msm_otg_start_host(otg->phy, 0);
1251                         otg->phy->state = OTG_STATE_B_IDLE;
1252                         msm_otg_reset(otg->phy);
1253                         schedule_work(w);
1254                 }
1255                 break;
1256         default:
1257                 break;
1258         }
1259 }
1260
1261 static irqreturn_t msm_otg_irq(int irq, void *data)
1262 {
1263         struct msm_otg *motg = data;
1264         struct usb_phy *phy = &motg->phy;
1265         u32 otgsc = 0;
1266
1267         if (atomic_read(&motg->in_lpm)) {
1268                 disable_irq_nosync(irq);
1269                 motg->async_int = 1;
1270                 pm_runtime_get(phy->dev);
1271                 return IRQ_HANDLED;
1272         }
1273
1274         otgsc = readl(USB_OTGSC);
1275         if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1276                 return IRQ_NONE;
1277
1278         if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1279                 if (otgsc & OTGSC_ID)
1280                         set_bit(ID, &motg->inputs);
1281                 else
1282                         clear_bit(ID, &motg->inputs);
1283                 dev_dbg(phy->dev, "ID set/clear\n");
1284                 pm_runtime_get_noresume(phy->dev);
1285         } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1286                 if (otgsc & OTGSC_BSV)
1287                         set_bit(B_SESS_VLD, &motg->inputs);
1288                 else
1289                         clear_bit(B_SESS_VLD, &motg->inputs);
1290                 dev_dbg(phy->dev, "BSV set/clear\n");
1291                 pm_runtime_get_noresume(phy->dev);
1292         }
1293
1294         writel(otgsc, USB_OTGSC);
1295         schedule_work(&motg->sm_work);
1296         return IRQ_HANDLED;
1297 }
1298
1299 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1300 {
1301         struct msm_otg *motg = s->private;
1302         struct usb_otg *otg = motg->phy.otg;
1303
1304         switch (otg->phy->state) {
1305         case OTG_STATE_A_HOST:
1306                 seq_puts(s, "host\n");
1307                 break;
1308         case OTG_STATE_B_PERIPHERAL:
1309                 seq_puts(s, "peripheral\n");
1310                 break;
1311         default:
1312                 seq_puts(s, "none\n");
1313                 break;
1314         }
1315
1316         return 0;
1317 }
1318
1319 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1320 {
1321         return single_open(file, msm_otg_mode_show, inode->i_private);
1322 }
1323
1324 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1325                                 size_t count, loff_t *ppos)
1326 {
1327         struct seq_file *s = file->private_data;
1328         struct msm_otg *motg = s->private;
1329         char buf[16];
1330         struct usb_otg *otg = motg->phy.otg;
1331         int status = count;
1332         enum usb_dr_mode req_mode;
1333
1334         memset(buf, 0x00, sizeof(buf));
1335
1336         if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1337                 status = -EFAULT;
1338                 goto out;
1339         }
1340
1341         if (!strncmp(buf, "host", 4)) {
1342                 req_mode = USB_DR_MODE_HOST;
1343         } else if (!strncmp(buf, "peripheral", 10)) {
1344                 req_mode = USB_DR_MODE_PERIPHERAL;
1345         } else if (!strncmp(buf, "none", 4)) {
1346                 req_mode = USB_DR_MODE_UNKNOWN;
1347         } else {
1348                 status = -EINVAL;
1349                 goto out;
1350         }
1351
1352         switch (req_mode) {
1353         case USB_DR_MODE_UNKNOWN:
1354                 switch (otg->phy->state) {
1355                 case OTG_STATE_A_HOST:
1356                 case OTG_STATE_B_PERIPHERAL:
1357                         set_bit(ID, &motg->inputs);
1358                         clear_bit(B_SESS_VLD, &motg->inputs);
1359                         break;
1360                 default:
1361                         goto out;
1362                 }
1363                 break;
1364         case USB_DR_MODE_PERIPHERAL:
1365                 switch (otg->phy->state) {
1366                 case OTG_STATE_B_IDLE:
1367                 case OTG_STATE_A_HOST:
1368                         set_bit(ID, &motg->inputs);
1369                         set_bit(B_SESS_VLD, &motg->inputs);
1370                         break;
1371                 default:
1372                         goto out;
1373                 }
1374                 break;
1375         case USB_DR_MODE_HOST:
1376                 switch (otg->phy->state) {
1377                 case OTG_STATE_B_IDLE:
1378                 case OTG_STATE_B_PERIPHERAL:
1379                         clear_bit(ID, &motg->inputs);
1380                         break;
1381                 default:
1382                         goto out;
1383                 }
1384                 break;
1385         default:
1386                 goto out;
1387         }
1388
1389         pm_runtime_get_sync(otg->phy->dev);
1390         schedule_work(&motg->sm_work);
1391 out:
1392         return status;
1393 }
1394
1395 const struct file_operations msm_otg_mode_fops = {
1396         .open = msm_otg_mode_open,
1397         .read = seq_read,
1398         .write = msm_otg_mode_write,
1399         .llseek = seq_lseek,
1400         .release = single_release,
1401 };
1402
1403 static struct dentry *msm_otg_dbg_root;
1404 static struct dentry *msm_otg_dbg_mode;
1405
1406 static int msm_otg_debugfs_init(struct msm_otg *motg)
1407 {
1408         msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1409
1410         if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1411                 return -ENODEV;
1412
1413         msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1414                                 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1415         if (!msm_otg_dbg_mode) {
1416                 debugfs_remove(msm_otg_dbg_root);
1417                 msm_otg_dbg_root = NULL;
1418                 return -ENODEV;
1419         }
1420
1421         return 0;
1422 }
1423
1424 static void msm_otg_debugfs_cleanup(void)
1425 {
1426         debugfs_remove(msm_otg_dbg_mode);
1427         debugfs_remove(msm_otg_dbg_root);
1428 }
1429
1430 static struct of_device_id msm_otg_dt_match[] = {
1431         {
1432                 .compatible = "qcom,usb-otg-ci",
1433                 .data = (void *) CI_45NM_INTEGRATED_PHY
1434         },
1435         {
1436                 .compatible = "qcom,usb-otg-snps",
1437                 .data = (void *) SNPS_28NM_INTEGRATED_PHY
1438         },
1439         { }
1440 };
1441 MODULE_DEVICE_TABLE(of, msm_otg_dt_match);
1442
1443 static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
1444 {
1445         struct msm_otg_platform_data *pdata;
1446         const struct of_device_id *id;
1447         struct device_node *node = pdev->dev.of_node;
1448         struct property *prop;
1449         int len, ret, words;
1450         u32 val, tmp[3];
1451
1452         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1453         if (!pdata)
1454                 return -ENOMEM;
1455
1456         motg->pdata = pdata;
1457
1458         id = of_match_device(msm_otg_dt_match, &pdev->dev);
1459         pdata->phy_type = (enum msm_usb_phy_type) id->data;
1460
1461         motg->link_rst = devm_reset_control_get(&pdev->dev, "link");
1462         if (IS_ERR(motg->link_rst))
1463                 return PTR_ERR(motg->link_rst);
1464
1465         motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy");
1466         if (IS_ERR(motg->phy_rst))
1467                 return PTR_ERR(motg->phy_rst);
1468
1469         pdata->mode = of_usb_get_dr_mode(node);
1470         if (pdata->mode == USB_DR_MODE_UNKNOWN)
1471                 pdata->mode = USB_DR_MODE_OTG;
1472
1473         pdata->otg_control = OTG_PHY_CONTROL;
1474         if (!of_property_read_u32(node, "qcom,otg-control", &val))
1475                 if (val == OTG_PMIC_CONTROL)
1476                         pdata->otg_control = val;
1477
1478         if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2)
1479                 motg->phy_number = val;
1480
1481         motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL;
1482         motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN;
1483         motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX;
1484
1485         if (of_get_property(node, "qcom,vdd-levels", &len) &&
1486             len == sizeof(tmp)) {
1487                 of_property_read_u32_array(node, "qcom,vdd-levels",
1488                                            tmp, len / sizeof(*tmp));
1489                 motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE];
1490                 motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN];
1491                 motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX];
1492         }
1493
1494         prop = of_find_property(node, "qcom,phy-init-sequence", &len);
1495         if (!prop || !len)
1496                 return 0;
1497
1498         words = len / sizeof(u32);
1499
1500         if (words >= ULPI_EXT_VENDOR_SPECIFIC) {
1501                 dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words);
1502                 return 0;
1503         }
1504
1505         pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1506         if (!pdata->phy_init_seq) {
1507                 dev_warn(&pdev->dev, "No space for PHY init sequence\n");
1508                 return 0;
1509         }
1510
1511         ret = of_property_read_u32_array(node, "qcom,phy-init-sequence",
1512                                          pdata->phy_init_seq, words);
1513         if (!ret)
1514                 pdata->phy_init_sz = words;
1515
1516         return 0;
1517 }
1518
1519 static int msm_otg_probe(struct platform_device *pdev)
1520 {
1521         struct regulator_bulk_data regs[3];
1522         int ret = 0;
1523         struct device_node *np = pdev->dev.of_node;
1524         struct msm_otg_platform_data *pdata;
1525         struct resource *res;
1526         struct msm_otg *motg;
1527         struct usb_phy *phy;
1528         void __iomem *phy_select;
1529
1530         motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
1531         if (!motg) {
1532                 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1533                 return -ENOMEM;
1534         }
1535
1536         pdata = dev_get_platdata(&pdev->dev);
1537         if (!pdata) {
1538                 if (!np)
1539                         return -ENXIO;
1540                 ret = msm_otg_read_dt(pdev, motg);
1541                 if (ret)
1542                         return ret;
1543         }
1544
1545         motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
1546                                      GFP_KERNEL);
1547         if (!motg->phy.otg) {
1548                 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1549                 return -ENOMEM;
1550         }
1551
1552         phy = &motg->phy;
1553         phy->dev = &pdev->dev;
1554
1555         motg->phy_reset_clk = devm_clk_get(&pdev->dev,
1556                                            np ? "phy" : "usb_phy_clk");
1557         if (IS_ERR(motg->phy_reset_clk)) {
1558                 dev_err(&pdev->dev, "failed to get usb_phy_clk\n");
1559                 return PTR_ERR(motg->phy_reset_clk);
1560         }
1561
1562         motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk");
1563         if (IS_ERR(motg->clk)) {
1564                 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1565                 return PTR_ERR(motg->clk);
1566         }
1567
1568         /*
1569          * If USB Core is running its protocol engine based on CORE CLK,
1570          * CORE CLK  must be running at >55Mhz for correct HSUSB
1571          * operation and USB core cannot tolerate frequency changes on
1572          * CORE CLK.
1573          */
1574         motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk");
1575         if (IS_ERR(motg->pclk)) {
1576                 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1577                 return PTR_ERR(motg->pclk);
1578         }
1579
1580         /*
1581          * USB core clock is not present on all MSM chips. This
1582          * clock is introduced to remove the dependency on AXI
1583          * bus frequency.
1584          */
1585         motg->core_clk = devm_clk_get(&pdev->dev,
1586                                       np ? "alt_core" : "usb_hs_core_clk");
1587
1588         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1589         if (!res)
1590                 return -EINVAL;
1591         motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1592         if (!motg->regs)
1593                 return -ENOMEM;
1594
1595         /*
1596          * NOTE: The PHYs can be multiplexed between the chipidea controller
1597          * and the dwc3 controller, using a single bit. It is important that
1598          * the dwc3 driver does not set this bit in an incompatible way.
1599          */
1600         if (motg->phy_number) {
1601                 phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4);
1602                 if (IS_ERR(phy_select))
1603                         return PTR_ERR(phy_select);
1604                 /* Enable second PHY with the OTG port */
1605                 writel(0x1, phy_select);
1606         }
1607
1608         dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1609
1610         motg->irq = platform_get_irq(pdev, 0);
1611         if (motg->irq < 0) {
1612                 dev_err(&pdev->dev, "platform_get_irq failed\n");
1613                 return motg->irq;
1614         }
1615
1616         regs[0].supply = "vddcx";
1617         regs[1].supply = "v3p3";
1618         regs[2].supply = "v1p8";
1619
1620         ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs);
1621         if (ret)
1622                 return ret;
1623
1624         motg->vddcx = regs[0].consumer;
1625         motg->v3p3  = regs[1].consumer;
1626         motg->v1p8  = regs[2].consumer;
1627
1628         clk_set_rate(motg->clk, 60000000);
1629
1630         clk_prepare_enable(motg->clk);
1631         clk_prepare_enable(motg->pclk);
1632
1633         if (!IS_ERR(motg->core_clk))
1634                 clk_prepare_enable(motg->core_clk);
1635
1636         ret = msm_hsusb_init_vddcx(motg, 1);
1637         if (ret) {
1638                 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1639                 goto disable_clks;
1640         }
1641
1642         ret = msm_hsusb_ldo_init(motg, 1);
1643         if (ret) {
1644                 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1645                 goto disable_vddcx;
1646         }
1647         ret = msm_hsusb_ldo_set_mode(motg, 1);
1648         if (ret) {
1649                 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1650                 goto disable_ldo;
1651         }
1652
1653         writel(0, USB_USBINTR);
1654         writel(0, USB_OTGSC);
1655
1656         INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1657         INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1658         ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED,
1659                                         "msm_otg", motg);
1660         if (ret) {
1661                 dev_err(&pdev->dev, "request irq failed\n");
1662                 goto disable_ldo;
1663         }
1664
1665         phy->init = msm_phy_init;
1666         phy->set_power = msm_otg_set_power;
1667         phy->notify_disconnect = msm_phy_notify_disconnect;
1668         phy->type = USB_PHY_TYPE_USB2;
1669
1670         phy->io_ops = &msm_otg_io_ops;
1671
1672         phy->otg->phy = &motg->phy;
1673         phy->otg->set_host = msm_otg_set_host;
1674         phy->otg->set_peripheral = msm_otg_set_peripheral;
1675
1676         msm_usb_reset(phy);
1677
1678         ret = usb_add_phy_dev(&motg->phy);
1679         if (ret) {
1680                 dev_err(&pdev->dev, "usb_add_phy failed\n");
1681                 goto disable_ldo;
1682         }
1683
1684         platform_set_drvdata(pdev, motg);
1685         device_init_wakeup(&pdev->dev, 1);
1686
1687         if (motg->pdata->mode == USB_DR_MODE_OTG &&
1688                 motg->pdata->otg_control == OTG_USER_CONTROL) {
1689                 ret = msm_otg_debugfs_init(motg);
1690                 if (ret)
1691                         dev_dbg(&pdev->dev, "Can not create mode change file\n");
1692         }
1693
1694         pm_runtime_set_active(&pdev->dev);
1695         pm_runtime_enable(&pdev->dev);
1696
1697         return 0;
1698
1699 disable_ldo:
1700         msm_hsusb_ldo_init(motg, 0);
1701 disable_vddcx:
1702         msm_hsusb_init_vddcx(motg, 0);
1703 disable_clks:
1704         clk_disable_unprepare(motg->pclk);
1705         clk_disable_unprepare(motg->clk);
1706         if (!IS_ERR(motg->core_clk))
1707                 clk_disable_unprepare(motg->core_clk);
1708         return ret;
1709 }
1710
1711 static int msm_otg_remove(struct platform_device *pdev)
1712 {
1713         struct msm_otg *motg = platform_get_drvdata(pdev);
1714         struct usb_phy *phy = &motg->phy;
1715         int cnt = 0;
1716
1717         if (phy->otg->host || phy->otg->gadget)
1718                 return -EBUSY;
1719
1720         msm_otg_debugfs_cleanup();
1721         cancel_delayed_work_sync(&motg->chg_work);
1722         cancel_work_sync(&motg->sm_work);
1723
1724         pm_runtime_resume(&pdev->dev);
1725
1726         device_init_wakeup(&pdev->dev, 0);
1727         pm_runtime_disable(&pdev->dev);
1728
1729         usb_remove_phy(phy);
1730         disable_irq(motg->irq);
1731
1732         /*
1733          * Put PHY in low power mode.
1734          */
1735         ulpi_read(phy, 0x14);
1736         ulpi_write(phy, 0x08, 0x09);
1737
1738         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1739         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1740                 if (readl(USB_PORTSC) & PORTSC_PHCD)
1741                         break;
1742                 udelay(1);
1743                 cnt++;
1744         }
1745         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1746                 dev_err(phy->dev, "Unable to suspend PHY\n");
1747
1748         clk_disable_unprepare(motg->pclk);
1749         clk_disable_unprepare(motg->clk);
1750         if (!IS_ERR(motg->core_clk))
1751                 clk_disable_unprepare(motg->core_clk);
1752         msm_hsusb_ldo_init(motg, 0);
1753
1754         pm_runtime_set_suspended(&pdev->dev);
1755
1756         return 0;
1757 }
1758
1759 #ifdef CONFIG_PM_RUNTIME
1760 static int msm_otg_runtime_idle(struct device *dev)
1761 {
1762         struct msm_otg *motg = dev_get_drvdata(dev);
1763         struct usb_otg *otg = motg->phy.otg;
1764
1765         dev_dbg(dev, "OTG runtime idle\n");
1766
1767         /*
1768          * It is observed some times that a spurious interrupt
1769          * comes when PHY is put into LPM immediately after PHY reset.
1770          * This 1 sec delay also prevents entering into LPM immediately
1771          * after asynchronous interrupt.
1772          */
1773         if (otg->phy->state != OTG_STATE_UNDEFINED)
1774                 pm_schedule_suspend(dev, 1000);
1775
1776         return -EAGAIN;
1777 }
1778
1779 static int msm_otg_runtime_suspend(struct device *dev)
1780 {
1781         struct msm_otg *motg = dev_get_drvdata(dev);
1782
1783         dev_dbg(dev, "OTG runtime suspend\n");
1784         return msm_otg_suspend(motg);
1785 }
1786
1787 static int msm_otg_runtime_resume(struct device *dev)
1788 {
1789         struct msm_otg *motg = dev_get_drvdata(dev);
1790
1791         dev_dbg(dev, "OTG runtime resume\n");
1792         return msm_otg_resume(motg);
1793 }
1794 #endif
1795
1796 #ifdef CONFIG_PM_SLEEP
1797 static int msm_otg_pm_suspend(struct device *dev)
1798 {
1799         struct msm_otg *motg = dev_get_drvdata(dev);
1800
1801         dev_dbg(dev, "OTG PM suspend\n");
1802         return msm_otg_suspend(motg);
1803 }
1804
1805 static int msm_otg_pm_resume(struct device *dev)
1806 {
1807         struct msm_otg *motg = dev_get_drvdata(dev);
1808         int ret;
1809
1810         dev_dbg(dev, "OTG PM resume\n");
1811
1812         ret = msm_otg_resume(motg);
1813         if (ret)
1814                 return ret;
1815
1816         /*
1817          * Runtime PM Documentation recommends bringing the
1818          * device to full powered state upon resume.
1819          */
1820         pm_runtime_disable(dev);
1821         pm_runtime_set_active(dev);
1822         pm_runtime_enable(dev);
1823
1824         return 0;
1825 }
1826 #endif
1827
1828 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1829         SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
1830         SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
1831                                 msm_otg_runtime_idle)
1832 };
1833
1834 static struct platform_driver msm_otg_driver = {
1835         .probe = msm_otg_probe,
1836         .remove = msm_otg_remove,
1837         .driver = {
1838                 .name = DRIVER_NAME,
1839                 .owner = THIS_MODULE,
1840                 .pm = &msm_otg_dev_pm_ops,
1841                 .of_match_table = msm_otg_dt_match,
1842         },
1843 };
1844
1845 module_platform_driver(msm_otg_driver);
1846
1847 MODULE_LICENSE("GPL v2");
1848 MODULE_DESCRIPTION("MSM USB transceiver driver");