drivers/usb/phy/phy-mxs-usb.c

   1 /*
   2  * Copyright 2012-2013 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2012 Marek Vasut <marex@denx.de>
   4  * on behalf of DENX Software Engineering GmbH
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/clk.h>
  18 #include <linux/usb/otg.h>
  19 #include <linux/stmp_device.h>
  20 #include <linux/delay.h>
  21 #include <linux/err.h>
  22 #include <linux/io.h>
  23 #include <linux/of_device.h>
  24 #include <linux/regmap.h>
  25 #include <linux/mfd/syscon.h>
  26
  27 #define DRIVER_NAME "mxs_phy"
  28
  29 #define HW_USBPHY_PWD                           0x00
  30 #define HW_USBPHY_CTRL                          0x30
  31 #define HW_USBPHY_CTRL_SET                      0x34
  32 #define HW_USBPHY_CTRL_CLR                      0x38
  33
  34 #define HW_USBPHY_IP                            0x90
  35 #define HW_USBPHY_IP_SET                        0x94
  36 #define HW_USBPHY_IP_CLR                        0x98
  37
  38 #define BM_USBPHY_CTRL_SFTRST                   BIT(31)
  39 #define BM_USBPHY_CTRL_CLKGATE                  BIT(30)
  40 #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS        BIT(26)
  41 #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE     BIT(25)
  42 #define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD        BIT(20)
  43 #define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE        BIT(19)
  44 #define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL         BIT(18)
  45 #define BM_USBPHY_CTRL_ENUTMILEVEL3             BIT(15)
  46 #define BM_USBPHY_CTRL_ENUTMILEVEL2             BIT(14)
  47 #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT       BIT(1)
  48
  49 #define BM_USBPHY_IP_FIX                       (BIT(17) | BIT(18))
  50
  51 #define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)
  52
  53 /* Do disconnection between PHY and controller without vbus */
  54 #define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS    BIT(0)
  55
  56 /*
  57  * The PHY will be in messy if there is a wakeup after putting
  58  * bus to suspend (set portsc.suspendM) but before setting PHY to low
  59  * power mode (set portsc.phcd).
  60  */
  61 #define MXS_PHY_ABNORMAL_IN_SUSPEND             BIT(1)
  62
  63 /*
  64  * The SOF sends too fast after resuming, it will cause disconnection
  65  * between host and high speed device.
  66  */
  67 #define MXS_PHY_SENDING_SOF_TOO_FAST            BIT(2)
  68
  69 /*
  70  * IC has bug fixes logic, they include
  71  * MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST
  72  * which are described at above flags, the RTL will handle it
  73  * according to different versions.
  74  */
  75 #define MXS_PHY_NEED_IP_FIX                     BIT(3)
  76
  77 struct mxs_phy_data {
  78         unsigned int flags;
  79 };
  80
  81 static const struct mxs_phy_data imx23_phy_data = {
  82         .flags = MXS_PHY_ABNORMAL_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST,
  83 };
  84
  85 static const struct mxs_phy_data imx6q_phy_data = {
  86         .flags = MXS_PHY_SENDING_SOF_TOO_FAST |
  87                 MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
  88                 MXS_PHY_NEED_IP_FIX,
  89 };
  90
  91 static const struct mxs_phy_data imx6sl_phy_data = {
  92         .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
  93                 MXS_PHY_NEED_IP_FIX,
  94 };
  95
  96 static const struct of_device_id mxs_phy_dt_ids[] = {
  97         { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
  98         { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
  99         { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
 100         { /* sentinel */ }
 101 };
 102 MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
 103
 104 struct mxs_phy {
 105         struct usb_phy phy;
 106         struct clk *clk;
 107         const struct mxs_phy_data *data;
 108         struct regmap *regmap_anatop;
 109         int port_id;
 110 };
 111
 112 static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
 113 {
 114         int ret;
 115         void __iomem *base = mxs_phy->phy.io_priv;
 116
 117         ret = stmp_reset_block(base + HW_USBPHY_CTRL);
 118         if (ret)
 119                 return ret;
 120
 121         /* Power up the PHY */
 122         writel(0, base + HW_USBPHY_PWD);
 123
 124         /*
 125          * USB PHY Ctrl Setting
 126          * - Auto clock/power on
 127          * - Enable full/low speed support
 128          */
 129         writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
 130                 BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE |
 131                 BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD |
 132                 BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE |
 133                 BM_USBPHY_CTRL_ENAUTO_PWRON_PLL |
 134                 BM_USBPHY_CTRL_ENUTMILEVEL2 |
 135                 BM_USBPHY_CTRL_ENUTMILEVEL3,
 136                base + HW_USBPHY_CTRL_SET);
 137
 138         if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX)
 139                 writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET);
 140
 141         return 0;
 142 }
 143
 144 static int mxs_phy_init(struct usb_phy *phy)
 145 {
 146         int ret;
 147         struct mxs_phy *mxs_phy = to_mxs_phy(phy);
 148
 149         ret = clk_prepare_enable(mxs_phy->clk);
 150         if (ret)
 151                 return ret;
 152
 153         return mxs_phy_hw_init(mxs_phy);
 154 }
 155
 156 static void mxs_phy_shutdown(struct usb_phy *phy)
 157 {
 158         struct mxs_phy *mxs_phy = to_mxs_phy(phy);
 159
 160         writel(BM_USBPHY_CTRL_CLKGATE,
 161                phy->io_priv + HW_USBPHY_CTRL_SET);
 162
 163         clk_disable_unprepare(mxs_phy->clk);
 164 }
 165
 166 static int mxs_phy_suspend(struct usb_phy *x, int suspend)
 167 {
 168         int ret;
 169         struct mxs_phy *mxs_phy = to_mxs_phy(x);
 170
 171         if (suspend) {
 172                 writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
 173                 writel(BM_USBPHY_CTRL_CLKGATE,
 174                        x->io_priv + HW_USBPHY_CTRL_SET);
 175                 clk_disable_unprepare(mxs_phy->clk);
 176         } else {
 177                 ret = clk_prepare_enable(mxs_phy->clk);
 178                 if (ret)
 179                         return ret;
 180                 writel(BM_USBPHY_CTRL_CLKGATE,
 181                        x->io_priv + HW_USBPHY_CTRL_CLR);
 182                 writel(0, x->io_priv + HW_USBPHY_PWD);
 183         }
 184
 185         return 0;
 186 }
 187
 188 static int mxs_phy_on_connect(struct usb_phy *phy,
 189                 enum usb_device_speed speed)
 190 {
 191         dev_dbg(phy->dev, "%s device has connected\n",
 192                 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
 193
 194         if (speed == USB_SPEED_HIGH)
 195                 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
 196                        phy->io_priv + HW_USBPHY_CTRL_SET);
 197
 198         return 0;
 199 }
 200
 201 static int mxs_phy_on_disconnect(struct usb_phy *phy,
 202                 enum usb_device_speed speed)
 203 {
 204         dev_dbg(phy->dev, "%s device has disconnected\n",
 205                 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
 206
 207         if (speed == USB_SPEED_HIGH)
 208                 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
 209                        phy->io_priv + HW_USBPHY_CTRL_CLR);
 210
 211         return 0;
 212 }
 213
 214 static int mxs_phy_probe(struct platform_device *pdev)
 215 {
 216         struct resource *res;
 217         void __iomem *base;
 218         struct clk *clk;
 219         struct mxs_phy *mxs_phy;
 220         int ret;
 221         const struct of_device_id *of_id =
 222                         of_match_device(mxs_phy_dt_ids, &pdev->dev);
 223         struct device_node *np = pdev->dev.of_node;
 224
 225         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 226         base = devm_ioremap_resource(&pdev->dev, res);
 227         if (IS_ERR(base))
 228                 return PTR_ERR(base);
 229
 230         clk = devm_clk_get(&pdev->dev, NULL);
 231         if (IS_ERR(clk)) {
 232                 dev_err(&pdev->dev,
 233                         "can't get the clock, err=%ld", PTR_ERR(clk));
 234                 return PTR_ERR(clk);
 235         }
 236
 237         mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL);
 238         if (!mxs_phy) {
 239                 dev_err(&pdev->dev, "Failed to allocate USB PHY structure!\n");
 240                 return -ENOMEM;
 241         }
 242
 243         /* Some SoCs don't have anatop registers */
 244         if (of_get_property(np, "fsl,anatop", NULL)) {
 245                 mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle
 246                         (np, "fsl,anatop");
 247                 if (IS_ERR(mxs_phy->regmap_anatop)) {
 248                         dev_dbg(&pdev->dev,
 249                                 "failed to find regmap for anatop\n");
 250                         return PTR_ERR(mxs_phy->regmap_anatop);
 251                 }
 252         }
 253
 254         ret = of_alias_get_id(np, "usbphy");
 255         if (ret < 0)
 256                 dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret);
 257         mxs_phy->port_id = ret;
 258
 259         mxs_phy->phy.io_priv            = base;
 260         mxs_phy->phy.dev                = &pdev->dev;
 261         mxs_phy->phy.label              = DRIVER_NAME;
 262         mxs_phy->phy.init               = mxs_phy_init;
 263         mxs_phy->phy.shutdown           = mxs_phy_shutdown;
 264         mxs_phy->phy.set_suspend        = mxs_phy_suspend;
 265         mxs_phy->phy.notify_connect     = mxs_phy_on_connect;
 266         mxs_phy->phy.notify_disconnect  = mxs_phy_on_disconnect;
 267         mxs_phy->phy.type               = USB_PHY_TYPE_USB2;
 268
 269         mxs_phy->clk = clk;
 270         mxs_phy->data = of_id->data;
 271
 272         platform_set_drvdata(pdev, mxs_phy);
 273
 274         ret = usb_add_phy_dev(&mxs_phy->phy);
 275         if (ret)
 276                 return ret;
 277
 278         return 0;
 279 }
 280
 281 static int mxs_phy_remove(struct platform_device *pdev)
 282 {
 283         struct mxs_phy *mxs_phy = platform_get_drvdata(pdev);
 284
 285         usb_remove_phy(&mxs_phy->phy);
 286
 287         return 0;
 288 }
 289
 290 static struct platform_driver mxs_phy_driver = {
 291         .probe = mxs_phy_probe,
 292         .remove = mxs_phy_remove,
 293         .driver = {
 294                 .name = DRIVER_NAME,
 295                 .owner  = THIS_MODULE,
 296                 .of_match_table = mxs_phy_dt_ids,
 297          },
 298 };
 299
 300 static int __init mxs_phy_module_init(void)
 301 {
 302         return platform_driver_register(&mxs_phy_driver);
 303 }
 304 postcore_initcall(mxs_phy_module_init);
 305
 306 static void __exit mxs_phy_module_exit(void)
 307 {
 308         platform_driver_unregister(&mxs_phy_driver);
 309 }
 310 module_exit(mxs_phy_module_exit);
 311
 312 MODULE_ALIAS("platform:mxs-usb-phy");
 313 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
 314 MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>");
 315 MODULE_DESCRIPTION("Freescale MXS USB PHY driver");
 316 MODULE_LICENSE("GPL");