1 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
4 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
7 * Ani Joshi / Jeff Garzik
10 * Michel Danzer <michdaen@iiic.ethz.ch>
14 * Benjamin Herrenschmidt
15 * - pmac-specific PM stuff
16 * - various fixes & cleanups
18 * Andreas Hundt <andi@convergence.de>
21 * Paul Mackerras <paulus@samba.org>
22 * - Convert to new framebuffer API,
23 * fix colormap setting at 16 bits/pixel (565)
28 * Jon Smirl <jonsmirl@yahoo.com>
30 * - replace ROM BIOS search
32 * Based off of Geert's atyfb.c and vfb.c.
35 * - monitor sensing (DDC)
37 * - other platform support (only ppc/x86 supported)
38 * - hardware cursor support
40 * Please cc: your patches to brad@neruo.com.
44 * A special note of gratitude to ATI's devrel for providing documentation,
45 * example code and hardware. Thanks Nitya. -atong and brad
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/kernel.h>
52 #include <linux/errno.h>
53 #include <linux/string.h>
55 #include <linux/vmalloc.h>
56 #include <linux/delay.h>
57 #include <linux/interrupt.h>
58 #include <linux/uaccess.h>
60 #include <linux/init.h>
61 #include <linux/pci.h>
62 #include <linux/ioport.h>
63 #include <linux/console.h>
64 #include <linux/backlight.h>
67 #ifdef CONFIG_PPC_PMAC
68 #include <asm/machdep.h>
69 #include <asm/pmac_feature.h>
71 #include <asm/pci-bridge.h>
72 #include "../macmodes.h"
75 #ifdef CONFIG_PMAC_BACKLIGHT
76 #include <asm/backlight.h>
79 #ifdef CONFIG_BOOTX_TEXT
80 #include <asm/btext.h>
81 #endif /* CONFIG_BOOTX_TEXT */
87 #include <video/aty128.h>
93 #define DBG(fmt, args...) \
94 printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args);
96 #define DBG(fmt, args...)
99 #ifndef CONFIG_PPC_PMAC
101 static struct fb_var_screeninfo default_var = {
102 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
103 640, 480, 640, 480, 0, 0, 8, 0,
104 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
105 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
106 0, FB_VMODE_NONINTERLACED
109 #else /* CONFIG_PPC_PMAC */
110 /* default to 1024x768 at 75Hz on PPC - this will work
111 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
112 static struct fb_var_screeninfo default_var = {
113 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
114 1024, 768, 1024, 768, 0, 0, 8, 0,
115 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
116 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
117 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
118 FB_VMODE_NONINTERLACED
120 #endif /* CONFIG_PPC_PMAC */
122 /* default modedb mode */
123 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
124 static struct fb_videomode defaultmode = {
136 .vmode = FB_VMODE_NONINTERLACED
139 /* Chip generations */
151 /* Must match above enum */
152 static char * const r128_family[] = {
164 * PCI driver prototypes
166 static int aty128_probe(struct pci_dev *pdev,
167 const struct pci_device_id *ent);
168 static void aty128_remove(struct pci_dev *pdev);
169 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state);
170 static int aty128_pci_resume(struct pci_dev *pdev);
171 static int aty128_do_resume(struct pci_dev *pdev);
173 /* supported Rage128 chipsets */
174 static struct pci_device_id aty128_pci_tbl[] = {
175 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
177 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
179 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
181 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
183 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
185 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
187 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
189 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
223 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
225 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
227 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
229 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
231 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
233 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
239 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
241 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
243 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
245 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
247 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
249 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
251 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
253 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
255 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
257 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
259 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
261 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
263 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
265 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
267 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
272 MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
274 static struct pci_driver aty128fb_driver = {
276 .id_table = aty128_pci_tbl,
277 .probe = aty128_probe,
278 .remove = aty128_remove,
279 .suspend = aty128_pci_suspend,
280 .resume = aty128_pci_resume,
283 /* packed BIOS settings */
288 u8 accelerator_entry;
290 u16 VGA_table_offset;
291 u16 POST_table_offset;
297 u16 PCLK_ref_divider;
301 u16 MCLK_ref_divider;
305 u16 XCLK_ref_divider;
308 } __attribute__ ((packed)) PLL_BLOCK;
309 #endif /* !CONFIG_PPC */
311 /* onboard memory information */
312 struct aty128_meminfo {
326 /* various memory configurations */
327 static const struct aty128_meminfo sdr_128 =
328 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
329 static const struct aty128_meminfo sdr_64 =
330 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
331 static const struct aty128_meminfo sdr_sgram =
332 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
333 static const struct aty128_meminfo ddr_sgram =
334 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
336 static struct fb_fix_screeninfo aty128fb_fix = {
338 .type = FB_TYPE_PACKED_PIXELS,
339 .visual = FB_VISUAL_PSEUDOCOLOR,
343 .accel = FB_ACCEL_ATI_RAGE128,
346 static char *mode_option = NULL;
348 #ifdef CONFIG_PPC_PMAC
349 static int default_vmode = VMODE_1024_768_60;
350 static int default_cmode = CMODE_8;
353 static int default_crt_on = 0;
354 static int default_lcd_on = 1;
357 static bool mtrr = true;
360 #ifdef CONFIG_PMAC_BACKLIGHT
361 static int backlight = 1;
363 static int backlight = 0;
367 struct aty128_constants {
379 u32 h_total, h_sync_strt_wid;
380 u32 v_total, v_sync_strt_wid;
382 u32 offset, offset_cntl;
383 u32 xoffset, yoffset;
390 u32 feedback_divider;
394 struct aty128_ddafifo {
399 /* register values for a specific mode */
400 struct aty128fb_par {
401 struct aty128_crtc crtc;
402 struct aty128_pll pll;
403 struct aty128_ddafifo fifo_reg;
405 struct aty128_constants constants; /* PLL and others */
406 void __iomem *regbase; /* remapped mmio */
407 u32 vram_size; /* onboard video ram */
409 const struct aty128_meminfo *mem; /* onboard mem info */
411 struct { int vram; int vram_valid; } mtrr;
413 int blitter_may_be_busy;
414 int fifo_slots; /* free slots in FIFO (64 max) */
417 struct pci_dev *pdev;
418 struct fb_info *next;
422 u8 red[32]; /* see aty128fb_setcolreg */
425 u32 pseudo_palette[16]; /* used for TRUECOLOR */
429 #define round_div(n, d) ((n+(d/2))/d)
431 static int aty128fb_check_var(struct fb_var_screeninfo *var,
432 struct fb_info *info);
433 static int aty128fb_set_par(struct fb_info *info);
434 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
435 u_int transp, struct fb_info *info);
436 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
438 static int aty128fb_blank(int blank, struct fb_info *fb);
439 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg);
440 static int aty128fb_sync(struct fb_info *info);
446 static int aty128_encode_var(struct fb_var_screeninfo *var,
447 const struct aty128fb_par *par);
448 static int aty128_decode_var(struct fb_var_screeninfo *var,
449 struct aty128fb_par *par);
451 static void aty128_get_pllinfo(struct aty128fb_par *par, void __iomem *bios);
452 static void __iomem *aty128_map_ROM(struct pci_dev *pdev,
453 const struct aty128fb_par *par);
455 static void aty128_timings(struct aty128fb_par *par);
456 static void aty128_init_engine(struct aty128fb_par *par);
457 static void aty128_reset_engine(const struct aty128fb_par *par);
458 static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
459 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
460 static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
461 static void wait_for_idle(struct aty128fb_par *par);
462 static u32 depth_to_dst(u32 depth);
464 #ifdef CONFIG_FB_ATY128_BACKLIGHT
465 static void aty128_bl_set_power(struct fb_info *info, int power);
468 #define BIOS_IN8(v) (readb(bios + (v)))
469 #define BIOS_IN16(v) (readb(bios + (v)) | \
470 (readb(bios + (v) + 1) << 8))
471 #define BIOS_IN32(v) (readb(bios + (v)) | \
472 (readb(bios + (v) + 1) << 8) | \
473 (readb(bios + (v) + 2) << 16) | \
474 (readb(bios + (v) + 3) << 24))
477 static struct fb_ops aty128fb_ops = {
478 .owner = THIS_MODULE,
479 .fb_check_var = aty128fb_check_var,
480 .fb_set_par = aty128fb_set_par,
481 .fb_setcolreg = aty128fb_setcolreg,
482 .fb_pan_display = aty128fb_pan_display,
483 .fb_blank = aty128fb_blank,
484 .fb_ioctl = aty128fb_ioctl,
485 .fb_sync = aty128fb_sync,
486 .fb_fillrect = cfb_fillrect,
487 .fb_copyarea = cfb_copyarea,
488 .fb_imageblit = cfb_imageblit,
492 * Functions to read from/write to the mmio registers
493 * - endian conversions may possibly be avoided by
494 * using the other register aperture. TODO.
496 static inline u32 _aty_ld_le32(volatile unsigned int regindex,
497 const struct aty128fb_par *par)
499 return readl (par->regbase + regindex);
502 static inline void _aty_st_le32(volatile unsigned int regindex, u32 val,
503 const struct aty128fb_par *par)
505 writel (val, par->regbase + regindex);
508 static inline u8 _aty_ld_8(unsigned int regindex,
509 const struct aty128fb_par *par)
511 return readb (par->regbase + regindex);
514 static inline void _aty_st_8(unsigned int regindex, u8 val,
515 const struct aty128fb_par *par)
517 writeb (val, par->regbase + regindex);
520 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
521 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par)
522 #define aty_ld_8(regindex) _aty_ld_8(regindex, par)
523 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par)
526 * Functions to read from/write to the pll registers
529 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par)
530 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par)
533 static u32 _aty_ld_pll(unsigned int pll_index,
534 const struct aty128fb_par *par)
536 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
537 return aty_ld_le32(CLOCK_CNTL_DATA);
541 static void _aty_st_pll(unsigned int pll_index, u32 val,
542 const struct aty128fb_par *par)
544 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
545 aty_st_le32(CLOCK_CNTL_DATA, val);
549 /* return true when the PLL has completed an atomic update */
550 static int aty_pll_readupdate(const struct aty128fb_par *par)
552 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
556 static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
558 unsigned long timeout = jiffies + HZ/100; // should be more than enough
561 while (time_before(jiffies, timeout))
562 if (aty_pll_readupdate(par)) {
567 if (reset) /* reset engine?? */
568 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
572 /* tell PLL to update */
573 static void aty_pll_writeupdate(const struct aty128fb_par *par)
575 aty_pll_wait_readupdate(par);
577 aty_st_pll(PPLL_REF_DIV,
578 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
582 /* write to the scratch register to test r/w functionality */
583 static int register_test(const struct aty128fb_par *par)
588 val = aty_ld_le32(BIOS_0_SCRATCH);
590 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
591 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
592 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
594 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
598 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
604 * Accelerator engine functions
606 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
611 for (i = 0; i < 2000000; i++) {
612 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
613 if (par->fifo_slots >= entries)
616 aty128_reset_engine(par);
621 static void wait_for_idle(struct aty128fb_par *par)
625 do_wait_for_fifo(64, par);
628 for (i = 0; i < 2000000; i++) {
629 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
630 aty128_flush_pixel_cache(par);
631 par->blitter_may_be_busy = 0;
635 aty128_reset_engine(par);
640 static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
642 if (par->fifo_slots < entries)
643 do_wait_for_fifo(64, par);
644 par->fifo_slots -= entries;
648 static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
653 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
656 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
658 for (i = 0; i < 2000000; i++)
659 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
664 static void aty128_reset_engine(const struct aty128fb_par *par)
666 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
668 aty128_flush_pixel_cache(par);
670 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
671 mclk_cntl = aty_ld_pll(MCLK_CNTL);
673 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
675 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
676 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
677 aty_ld_le32(GEN_RESET_CNTL);
678 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
679 aty_ld_le32(GEN_RESET_CNTL);
681 aty_st_pll(MCLK_CNTL, mclk_cntl);
682 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
683 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
685 /* use old pio mode */
686 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
692 static void aty128_init_engine(struct aty128fb_par *par)
698 /* 3D scaler not spoken here */
699 wait_for_fifo(1, par);
700 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
702 aty128_reset_engine(par);
704 pitch_value = par->crtc.pitch;
705 if (par->crtc.bpp == 24) {
706 pitch_value = pitch_value * 3;
709 wait_for_fifo(4, par);
710 /* setup engine offset registers */
711 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
713 /* setup engine pitch registers */
714 aty_st_le32(DEFAULT_PITCH, pitch_value);
716 /* set the default scissor register to max dimensions */
717 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
719 /* set the drawing controls registers */
720 aty_st_le32(DP_GUI_MASTER_CNTL,
721 GMC_SRC_PITCH_OFFSET_DEFAULT |
722 GMC_DST_PITCH_OFFSET_DEFAULT |
723 GMC_SRC_CLIP_DEFAULT |
724 GMC_DST_CLIP_DEFAULT |
725 GMC_BRUSH_SOLIDCOLOR |
726 (depth_to_dst(par->crtc.depth) << 8) |
728 GMC_BYTE_ORDER_MSB_TO_LSB |
729 GMC_DP_CONVERSION_TEMP_6500 |
733 GMC_DST_CLR_CMP_FCN_CLEAR |
737 wait_for_fifo(8, par);
738 /* clear the line drawing registers */
739 aty_st_le32(DST_BRES_ERR, 0);
740 aty_st_le32(DST_BRES_INC, 0);
741 aty_st_le32(DST_BRES_DEC, 0);
743 /* set brush color registers */
744 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
745 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
747 /* set source color registers */
748 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
749 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
751 /* default write mask */
752 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
754 /* Wait for all the writes to be completed before returning */
759 /* convert depth values to their register representation */
760 static u32 depth_to_dst(u32 depth)
764 else if (depth <= 15)
766 else if (depth == 16)
768 else if (depth <= 24)
770 else if (depth <= 32)
777 * PLL informations retreival
782 static void __iomem *aty128_map_ROM(const struct aty128fb_par *par,
790 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
792 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
795 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
796 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
798 bios = pci_map_rom(dev, &rom_size);
801 printk(KERN_ERR "aty128fb: ROM failed to map\n");
805 /* Very simple test to make sure it appeared */
806 if (BIOS_IN16(0) != 0xaa55) {
807 printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should "
808 " be 0xaa55\n", BIOS_IN16(0));
812 /* Look for the PCI data to check the ROM type */
813 dptr = BIOS_IN16(0x18);
815 /* Check the PCI data signature. If it's wrong, we still assume a normal
816 * x86 ROM for now, until I've verified this works everywhere.
817 * The goal here is more to phase out Open Firmware images.
819 * Currently, we only look at the first PCI data, we could iteratre and
820 * deal with them all, and we should use fb_bios_start relative to start
821 * of image and not relative start of ROM, but so far, I never found a
822 * dual-image ATI card.
825 * u32 signature; + 0x00
828 * u16 reserved_1; + 0x08
830 * u8 drevision; + 0x0c
831 * u8 class_hi; + 0x0d
832 * u16 class_lo; + 0x0e
834 * u16 irevision; + 0x12
836 * u8 indicator; + 0x15
837 * u16 reserved_2; + 0x16
840 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
841 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
845 rom_type = BIOS_IN8(dptr + 0x14);
848 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
851 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
854 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
857 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n",
865 pci_unmap_rom(dev, bios);
869 static void aty128_get_pllinfo(struct aty128fb_par *par,
870 unsigned char __iomem *bios)
872 unsigned int bios_hdr;
873 unsigned int bios_pll;
875 bios_hdr = BIOS_IN16(0x48);
876 bios_pll = BIOS_IN16(bios_hdr + 0x30);
878 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
879 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
880 par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
881 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
882 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
884 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
885 par->constants.ppll_max, par->constants.ppll_min,
886 par->constants.xclk, par->constants.ref_divider,
887 par->constants.ref_clk);
892 static void __iomem *aty128_find_mem_vbios(struct aty128fb_par *par)
894 /* I simplified this code as we used to miss the signatures in
895 * a lot of case. It's now closer to XFree, we just don't check
896 * for signatures at all... Something better will have to be done
897 * if we end up having conflicts
900 unsigned char __iomem *rom_base = NULL;
902 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
903 rom_base = ioremap(segstart, 0x10000);
904 if (rom_base == NULL)
906 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
914 #endif /* ndef(__sparc__) */
916 /* fill in known card constants if pll_block is not available */
917 static void aty128_timings(struct aty128fb_par *par)
920 /* instead of a table lookup, assume OF has properly
921 * setup the PLL registers and use their values
922 * to set the XCLK values and reference divider values */
924 u32 x_mpll_ref_fb_div;
927 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
930 if (!par->constants.ref_clk)
931 par->constants.ref_clk = 2950;
934 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
935 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
936 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
937 M = x_mpll_ref_fb_div & 0x0000ff;
939 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
940 (M * PostDivSet[xclk_cntl]));
942 par->constants.ref_divider =
943 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
946 if (!par->constants.ref_divider) {
947 par->constants.ref_divider = 0x3b;
949 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
950 aty_pll_writeupdate(par);
952 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
953 aty_pll_writeupdate(par);
955 /* from documentation */
956 if (!par->constants.ppll_min)
957 par->constants.ppll_min = 12500;
958 if (!par->constants.ppll_max)
959 par->constants.ppll_max = 25000; /* 23000 on some cards? */
960 if (!par->constants.xclk)
961 par->constants.xclk = 0x1d4d; /* same as mclk */
963 par->constants.fifo_width = 128;
964 par->constants.fifo_depth = 32;
966 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
971 par->mem = &sdr_sgram;
974 par->mem = &ddr_sgram;
977 par->mem = &sdr_sgram;
987 /* Program the CRTC registers */
988 static void aty128_set_crtc(const struct aty128_crtc *crtc,
989 const struct aty128fb_par *par)
991 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
992 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
993 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
994 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
995 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
996 aty_st_le32(CRTC_PITCH, crtc->pitch);
997 aty_st_le32(CRTC_OFFSET, crtc->offset);
998 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
999 /* Disable ATOMIC updating. Is this the right place? */
1000 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
1004 static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
1005 struct aty128_crtc *crtc,
1006 const struct aty128fb_par *par)
1008 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1009 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1010 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1011 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1013 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1018 vxres = var->xres_virtual;
1019 vyres = var->yres_virtual;
1020 xoffset = var->xoffset;
1021 yoffset = var->yoffset;
1022 bpp = var->bits_per_pixel;
1023 left = var->left_margin;
1024 right = var->right_margin;
1025 upper = var->upper_margin;
1026 lower = var->lower_margin;
1027 hslen = var->hsync_len;
1028 vslen = var->vsync_len;
1035 depth = (var->green.length == 6) ? 16 : 15;
1037 /* check for mode eligibility
1038 * accept only non interlaced modes */
1039 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1042 /* convert (and round up) and validate */
1043 xres = (xres + 7) & ~7;
1044 xoffset = (xoffset + 7) & ~7;
1046 if (vxres < xres + xoffset)
1047 vxres = xres + xoffset;
1049 if (vyres < yres + yoffset)
1050 vyres = yres + yoffset;
1052 /* convert depth into ATI register depth */
1053 dst = depth_to_dst(depth);
1055 if (dst == -EINVAL) {
1056 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1060 /* convert register depth to bytes per pixel */
1061 bytpp = mode_bytpp[dst];
1063 /* make sure there is enough video ram for the mode */
1064 if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1065 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1069 h_disp = (xres >> 3) - 1;
1070 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1073 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1075 /* check to make sure h_total and v_total are in range */
1076 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1077 printk(KERN_ERR "aty128fb: invalid width ranges\n");
1081 h_sync_wid = (hslen + 7) >> 3;
1082 if (h_sync_wid == 0)
1084 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
1087 h_sync_strt = (h_disp << 3) + right;
1090 if (v_sync_wid == 0)
1092 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
1095 v_sync_strt = v_disp + lower;
1097 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1098 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1100 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1102 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1104 crtc->h_total = h_total | (h_disp << 16);
1105 crtc->v_total = v_total | (v_disp << 16);
1107 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1109 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1112 crtc->pitch = vxres >> 3;
1116 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1117 crtc->offset_cntl = 0x00010000;
1119 crtc->offset_cntl = 0;
1121 crtc->vxres = vxres;
1122 crtc->vyres = vyres;
1123 crtc->xoffset = xoffset;
1124 crtc->yoffset = yoffset;
1125 crtc->depth = depth;
1132 static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1135 /* fill in pixel info */
1136 var->red.msb_right = 0;
1137 var->green.msb_right = 0;
1138 var->blue.offset = 0;
1139 var->blue.msb_right = 0;
1140 var->transp.offset = 0;
1141 var->transp.length = 0;
1142 var->transp.msb_right = 0;
1143 switch (pix_width) {
1144 case CRTC_PIX_WIDTH_8BPP:
1145 var->bits_per_pixel = 8;
1146 var->red.offset = 0;
1147 var->red.length = 8;
1148 var->green.offset = 0;
1149 var->green.length = 8;
1150 var->blue.length = 8;
1152 case CRTC_PIX_WIDTH_15BPP:
1153 var->bits_per_pixel = 16;
1154 var->red.offset = 10;
1155 var->red.length = 5;
1156 var->green.offset = 5;
1157 var->green.length = 5;
1158 var->blue.length = 5;
1160 case CRTC_PIX_WIDTH_16BPP:
1161 var->bits_per_pixel = 16;
1162 var->red.offset = 11;
1163 var->red.length = 5;
1164 var->green.offset = 5;
1165 var->green.length = 6;
1166 var->blue.length = 5;
1168 case CRTC_PIX_WIDTH_24BPP:
1169 var->bits_per_pixel = 24;
1170 var->red.offset = 16;
1171 var->red.length = 8;
1172 var->green.offset = 8;
1173 var->green.length = 8;
1174 var->blue.length = 8;
1176 case CRTC_PIX_WIDTH_32BPP:
1177 var->bits_per_pixel = 32;
1178 var->red.offset = 16;
1179 var->red.length = 8;
1180 var->green.offset = 8;
1181 var->green.length = 8;
1182 var->blue.length = 8;
1183 var->transp.offset = 24;
1184 var->transp.length = 8;
1187 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1195 static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1196 struct fb_var_screeninfo *var)
1198 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1199 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1200 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1203 /* fun with masking */
1204 h_total = crtc->h_total & 0x1ff;
1205 h_disp = (crtc->h_total >> 16) & 0xff;
1206 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1207 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
1208 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1209 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
1210 v_total = crtc->v_total & 0x7ff;
1211 v_disp = (crtc->v_total >> 16) & 0x7ff;
1212 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1213 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1214 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
1215 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1216 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1218 /* do conversions */
1219 xres = (h_disp + 1) << 3;
1221 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1222 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1223 hslen = h_sync_wid << 3;
1224 upper = v_total - v_sync_strt - v_sync_wid;
1225 lower = v_sync_strt - v_disp;
1227 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1228 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1229 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1231 aty128_pix_width_to_var(pix_width, var);
1235 var->xres_virtual = crtc->vxres;
1236 var->yres_virtual = crtc->vyres;
1237 var->xoffset = crtc->xoffset;
1238 var->yoffset = crtc->yoffset;
1239 var->left_margin = left;
1240 var->right_margin = right;
1241 var->upper_margin = upper;
1242 var->lower_margin = lower;
1243 var->hsync_len = hslen;
1244 var->vsync_len = vslen;
1246 var->vmode = FB_VMODE_NONINTERLACED;
1251 static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1254 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) |
1256 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) |
1257 DAC_PALETTE2_SNOOP_EN));
1259 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) &
1263 static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1266 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1267 struct fb_info *info = pci_get_drvdata(par->pdev);
1271 reg = aty_ld_le32(LVDS_GEN_CNTL);
1272 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1273 reg &= ~LVDS_DISPLAY_DIS;
1274 aty_st_le32(LVDS_GEN_CNTL, reg);
1275 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1276 aty128_bl_set_power(info, FB_BLANK_UNBLANK);
1279 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1280 aty128_bl_set_power(info, FB_BLANK_POWERDOWN);
1282 reg = aty_ld_le32(LVDS_GEN_CNTL);
1283 reg |= LVDS_DISPLAY_DIS;
1284 aty_st_le32(LVDS_GEN_CNTL, reg);
1286 reg &= ~(LVDS_ON /*| LVDS_EN*/);
1287 aty_st_le32(LVDS_GEN_CNTL, reg);
1291 static void aty128_set_pll(struct aty128_pll *pll,
1292 const struct aty128fb_par *par)
1296 unsigned char post_conv[] = /* register values for post dividers */
1297 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1299 /* select PPLL_DIV_3 */
1300 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1303 aty_st_pll(PPLL_CNTL,
1304 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1306 /* write the reference divider */
1307 aty_pll_wait_readupdate(par);
1308 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1309 aty_pll_writeupdate(par);
1311 div3 = aty_ld_pll(PPLL_DIV_3);
1312 div3 &= ~PPLL_FB3_DIV_MASK;
1313 div3 |= pll->feedback_divider;
1314 div3 &= ~PPLL_POST3_DIV_MASK;
1315 div3 |= post_conv[pll->post_divider] << 16;
1317 /* write feedback and post dividers */
1318 aty_pll_wait_readupdate(par);
1319 aty_st_pll(PPLL_DIV_3, div3);
1320 aty_pll_writeupdate(par);
1322 aty_pll_wait_readupdate(par);
1323 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1324 aty_pll_writeupdate(par);
1326 /* clear the reset, just in case */
1327 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1331 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1332 const struct aty128fb_par *par)
1334 const struct aty128_constants c = par->constants;
1335 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1337 u32 vclk; /* in .01 MHz */
1341 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1343 /* adjust pixel clock if necessary */
1344 if (vclk > c.ppll_max)
1346 if (vclk * 12 < c.ppll_min)
1347 vclk = c.ppll_min/12;
1349 /* now, find an acceptable divider */
1350 for (i = 0; i < ARRAY_SIZE(post_dividers); i++) {
1351 output_freq = post_dividers[i] * vclk;
1352 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) {
1353 pll->post_divider = post_dividers[i];
1358 if (i == ARRAY_SIZE(post_dividers))
1361 /* calculate feedback divider */
1362 n = c.ref_divider * output_freq;
1365 pll->feedback_divider = round_div(n, d);
1368 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1369 "vclk_per: %d\n", pll->post_divider,
1370 pll->feedback_divider, vclk, output_freq,
1371 c.ref_divider, period_in_ps);
1377 static int aty128_pll_to_var(const struct aty128_pll *pll,
1378 struct fb_var_screeninfo *var)
1380 var->pixclock = 100000000 / pll->vclk;
1386 static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1387 const struct aty128fb_par *par)
1389 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1390 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1394 static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1395 const struct aty128_pll *pll,
1397 const struct aty128fb_par *par)
1399 const struct aty128_meminfo *m = par->mem;
1400 u32 xclk = par->constants.xclk;
1401 u32 fifo_width = par->constants.fifo_width;
1402 u32 fifo_depth = par->constants.fifo_depth;
1403 s32 x, b, p, ron, roff;
1406 /* round up to multiple of 8 */
1407 bpp = (depth+7) & ~7;
1409 n = xclk * fifo_width;
1410 d = pll->vclk * bpp;
1411 x = round_div(n, d);
1414 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1433 x = round_div(n, d);
1434 roff = x * (fifo_depth - 4);
1436 if ((ron + m->Rloop) >= roff) {
1437 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1441 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1442 p, m->Rloop, x, ron, roff);
1444 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1445 dsp->dda_on_off = ron << 16 | roff;
1452 * This actually sets the video mode.
1454 static int aty128fb_set_par(struct fb_info *info)
1456 struct aty128fb_par *par = info->par;
1460 if ((err = aty128_decode_var(&info->var, par)) != 0)
1463 if (par->blitter_may_be_busy)
1466 /* clear all registers that may interfere with mode setting */
1467 aty_st_le32(OVR_CLR, 0);
1468 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1469 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1470 aty_st_le32(OV0_SCALE_CNTL, 0);
1471 aty_st_le32(MPP_TB_CONFIG, 0);
1472 aty_st_le32(MPP_GP_CONFIG, 0);
1473 aty_st_le32(SUBPIC_CNTL, 0);
1474 aty_st_le32(VIPH_CONTROL, 0);
1475 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1476 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1477 aty_st_le32(CAP0_TRIG_CNTL, 0);
1478 aty_st_le32(CAP1_TRIG_CNTL, 0);
1480 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1482 aty128_set_crtc(&par->crtc, par);
1483 aty128_set_pll(&par->pll, par);
1484 aty128_set_fifo(&par->fifo_reg, par);
1486 config = aty_ld_le32(CNFG_CNTL) & ~3;
1488 #if defined(__BIG_ENDIAN)
1489 if (par->crtc.bpp == 32)
1490 config |= 2; /* make aperture do 32 bit swapping */
1491 else if (par->crtc.bpp == 16)
1492 config |= 1; /* make aperture do 16 bit swapping */
1495 aty_st_le32(CNFG_CNTL, config);
1496 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1498 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1499 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1500 : FB_VISUAL_DIRECTCOLOR;
1502 if (par->chip_gen == rage_M3) {
1503 aty128_set_crt_enable(par, par->crt_on);
1504 aty128_set_lcd_enable(par, par->lcd_on);
1506 if (par->accel_flags & FB_ACCELF_TEXT)
1507 aty128_init_engine(par);
1509 #ifdef CONFIG_BOOTX_TEXT
1510 btext_update_display(info->fix.smem_start,
1511 (((par->crtc.h_total>>16) & 0xff)+1)*8,
1512 ((par->crtc.v_total>>16) & 0x7ff)+1,
1514 par->crtc.vxres*par->crtc.bpp/8);
1515 #endif /* CONFIG_BOOTX_TEXT */
1521 * encode/decode the User Defined Part of the Display
1524 static int aty128_decode_var(struct fb_var_screeninfo *var,
1525 struct aty128fb_par *par)
1528 struct aty128_crtc crtc;
1529 struct aty128_pll pll;
1530 struct aty128_ddafifo fifo_reg;
1532 if ((err = aty128_var_to_crtc(var, &crtc, par)))
1535 if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1538 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1543 par->fifo_reg = fifo_reg;
1544 par->accel_flags = var->accel_flags;
1550 static int aty128_encode_var(struct fb_var_screeninfo *var,
1551 const struct aty128fb_par *par)
1555 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1558 if ((err = aty128_pll_to_var(&par->pll, var)))
1566 var->accel_flags = par->accel_flags;
1572 static int aty128fb_check_var(struct fb_var_screeninfo *var,
1573 struct fb_info *info)
1575 struct aty128fb_par par;
1578 par = *(struct aty128fb_par *)info->par;
1579 if ((err = aty128_decode_var(var, &par)) != 0)
1581 aty128_encode_var(var, &par);
1587 * Pan or Wrap the Display
1589 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
1592 struct aty128fb_par *par = fb->par;
1593 u32 xoffset, yoffset;
1597 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1598 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1600 xoffset = (var->xoffset +7) & ~7;
1601 yoffset = var->yoffset;
1603 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1606 par->crtc.xoffset = xoffset;
1607 par->crtc.yoffset = yoffset;
1609 offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3))
1612 if (par->crtc.bpp == 24)
1613 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1615 aty_st_le32(CRTC_OFFSET, offset);
1622 * Helper function to store a single palette register
1624 static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1625 struct aty128fb_par *par)
1627 if (par->chip_gen == rage_M3) {
1629 /* Note: For now, on M3, we set palette on both heads, which may
1630 * be useless. Can someone with a M3 check this ?
1632 * This code would still be useful if using the second CRTC to
1636 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) |
1637 DAC_PALETTE_ACCESS_CNTL);
1638 aty_st_8(PALETTE_INDEX, regno);
1639 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1641 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) &
1642 ~DAC_PALETTE_ACCESS_CNTL);
1645 aty_st_8(PALETTE_INDEX, regno);
1646 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1649 static int aty128fb_sync(struct fb_info *info)
1651 struct aty128fb_par *par = info->par;
1653 if (par->blitter_may_be_busy)
1659 static int aty128fb_setup(char *options)
1663 if (!options || !*options)
1666 while ((this_opt = strsep(&options, ",")) != NULL) {
1667 if (!strncmp(this_opt, "lcd:", 4)) {
1668 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1670 } else if (!strncmp(this_opt, "crt:", 4)) {
1671 default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1673 } else if (!strncmp(this_opt, "backlight:", 10)) {
1674 backlight = simple_strtoul(this_opt+10, NULL, 0);
1678 if(!strncmp(this_opt, "nomtrr", 6)) {
1683 #ifdef CONFIG_PPC_PMAC
1684 /* vmode and cmode deprecated */
1685 if (!strncmp(this_opt, "vmode:", 6)) {
1686 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1687 if (vmode > 0 && vmode <= VMODE_MAX)
1688 default_vmode = vmode;
1690 } else if (!strncmp(this_opt, "cmode:", 6)) {
1691 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1695 default_cmode = CMODE_8;
1699 default_cmode = CMODE_16;
1703 default_cmode = CMODE_32;
1708 #endif /* CONFIG_PPC_PMAC */
1709 mode_option = this_opt;
1716 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1717 #define MAX_LEVEL 0xFF
1719 static int aty128_bl_get_level_brightness(struct aty128fb_par *par,
1722 struct fb_info *info = pci_get_drvdata(par->pdev);
1725 /* Get and convert the value */
1726 /* No locking of bl_curve since we read a single value */
1727 atylevel = MAX_LEVEL -
1728 (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL);
1732 else if (atylevel > MAX_LEVEL)
1733 atylevel = MAX_LEVEL;
1738 /* We turn off the LCD completely instead of just dimming the backlight.
1739 * This provides greater power saving and the display is useless without
1742 #define BACKLIGHT_LVDS_OFF
1743 /* That one prevents proper CRT output with LCD off */
1744 #undef BACKLIGHT_DAC_OFF
1746 static int aty128_bl_update_status(struct backlight_device *bd)
1748 struct aty128fb_par *par = bl_get_data(bd);
1749 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
1752 if (bd->props.power != FB_BLANK_UNBLANK ||
1753 bd->props.fb_blank != FB_BLANK_UNBLANK ||
1757 level = bd->props.brightness;
1759 reg |= LVDS_BL_MOD_EN | LVDS_BLON;
1762 if (!(reg & LVDS_ON)) {
1764 aty_st_le32(LVDS_GEN_CNTL, reg);
1765 aty_ld_le32(LVDS_GEN_CNTL);
1768 aty_st_le32(LVDS_GEN_CNTL, reg);
1770 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1771 reg |= (aty128_bl_get_level_brightness(par, level) <<
1772 LVDS_BL_MOD_LEVEL_SHIFT);
1773 #ifdef BACKLIGHT_LVDS_OFF
1774 reg |= LVDS_ON | LVDS_EN;
1775 reg &= ~LVDS_DISPLAY_DIS;
1777 aty_st_le32(LVDS_GEN_CNTL, reg);
1778 #ifdef BACKLIGHT_DAC_OFF
1779 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
1782 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1783 reg |= (aty128_bl_get_level_brightness(par, 0) <<
1784 LVDS_BL_MOD_LEVEL_SHIFT);
1785 #ifdef BACKLIGHT_LVDS_OFF
1786 reg |= LVDS_DISPLAY_DIS;
1787 aty_st_le32(LVDS_GEN_CNTL, reg);
1788 aty_ld_le32(LVDS_GEN_CNTL);
1790 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
1792 aty_st_le32(LVDS_GEN_CNTL, reg);
1793 #ifdef BACKLIGHT_DAC_OFF
1794 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
1801 static int aty128_bl_get_brightness(struct backlight_device *bd)
1803 return bd->props.brightness;
1806 static const struct backlight_ops aty128_bl_data = {
1807 .get_brightness = aty128_bl_get_brightness,
1808 .update_status = aty128_bl_update_status,
1811 static void aty128_bl_set_power(struct fb_info *info, int power)
1814 info->bl_dev->props.power = power;
1815 backlight_update_status(info->bl_dev);
1819 static void aty128_bl_init(struct aty128fb_par *par)
1821 struct backlight_properties props;
1822 struct fb_info *info = pci_get_drvdata(par->pdev);
1823 struct backlight_device *bd;
1826 /* Could be extended to Rage128Pro LVDS output too */
1827 if (par->chip_gen != rage_M3)
1830 #ifdef CONFIG_PMAC_BACKLIGHT
1831 if (!pmac_has_backlight_type("ati"))
1835 snprintf(name, sizeof(name), "aty128bl%d", info->node);
1837 memset(&props, 0, sizeof(struct backlight_properties));
1838 props.type = BACKLIGHT_RAW;
1839 props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
1840 bd = backlight_device_register(name, info->dev, par, &aty128_bl_data,
1843 info->bl_dev = NULL;
1844 printk(KERN_WARNING "aty128: Backlight registration failed\n");
1849 fb_bl_default_curve(info, 0,
1850 63 * FB_BACKLIGHT_MAX / MAX_LEVEL,
1851 219 * FB_BACKLIGHT_MAX / MAX_LEVEL);
1853 bd->props.brightness = bd->props.max_brightness;
1854 bd->props.power = FB_BLANK_UNBLANK;
1855 backlight_update_status(bd);
1857 printk("aty128: Backlight initialized (%s)\n", name);
1865 static void aty128_bl_exit(struct backlight_device *bd)
1867 backlight_device_unregister(bd);
1868 printk("aty128: Backlight unloaded\n");
1870 #endif /* CONFIG_FB_ATY128_BACKLIGHT */
1876 #ifdef CONFIG_PPC_PMAC__disabled
1877 static void aty128_early_resume(void *data)
1879 struct aty128fb_par *par = data;
1881 if (!console_trylock())
1883 pci_restore_state(par->pdev);
1884 aty128_do_resume(par->pdev);
1887 #endif /* CONFIG_PPC_PMAC */
1889 static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
1891 struct fb_info *info = pci_get_drvdata(pdev);
1892 struct aty128fb_par *par = info->par;
1893 struct fb_var_screeninfo var;
1894 char video_card[50];
1898 /* Get the chip revision */
1899 chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;
1901 strcpy(video_card, "Rage128 XX ");
1902 video_card[8] = ent->device >> 8;
1903 video_card[9] = ent->device & 0xFF;
1905 /* range check to make sure */
1906 if (ent->driver_data < ARRAY_SIZE(r128_family))
1907 strlcat(video_card, r128_family[ent->driver_data],
1908 sizeof(video_card));
1910 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1912 if (par->vram_size % (1024 * 1024) == 0)
1913 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1915 printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1917 par->chip_gen = ent->driver_data;
1920 info->fbops = &aty128fb_ops;
1921 info->flags = FBINFO_FLAG_DEFAULT;
1923 par->lcd_on = default_lcd_on;
1924 par->crt_on = default_crt_on;
1927 #ifdef CONFIG_PPC_PMAC
1928 if (machine_is(powermac)) {
1929 /* Indicate sleep capability */
1930 if (par->chip_gen == rage_M3) {
1931 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
1932 #if 0 /* Disable the early video resume hack for now as it's causing problems,
1933 * among others we now rely on the PCI core restoring the config space
1934 * for us, which isn't the case with that hack, and that code path causes
1935 * various things to be called with interrupts off while they shouldn't.
1936 * I'm leaving the code in as it can be useful for debugging purposes
1938 pmac_set_early_video_resume(aty128_early_resume, par);
1942 /* Find default mode */
1944 if (!mac_find_mode(&var, info, mode_option, 8))
1947 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1948 default_vmode = VMODE_1024_768_60;
1950 /* iMacs need that resolution
1951 * PowerMac2,1 first r128 iMacs
1952 * PowerMac2,2 summer 2000 iMacs
1953 * PowerMac4,1 january 2001 iMacs "flower power"
1955 if (of_machine_is_compatible("PowerMac2,1") ||
1956 of_machine_is_compatible("PowerMac2,2") ||
1957 of_machine_is_compatible("PowerMac4,1"))
1958 default_vmode = VMODE_1024_768_75;
1961 if (of_machine_is_compatible("PowerBook2,2"))
1962 default_vmode = VMODE_800_600_60;
1964 /* PowerBook Firewire (Pismo), iBook Dual USB */
1965 if (of_machine_is_compatible("PowerBook3,1") ||
1966 of_machine_is_compatible("PowerBook4,1"))
1967 default_vmode = VMODE_1024_768_60;
1969 /* PowerBook Titanium */
1970 if (of_machine_is_compatible("PowerBook3,2"))
1971 default_vmode = VMODE_1152_768_60;
1973 if (default_cmode > 16)
1974 default_cmode = CMODE_32;
1975 else if (default_cmode > 8)
1976 default_cmode = CMODE_16;
1978 default_cmode = CMODE_8;
1980 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1984 #endif /* CONFIG_PPC_PMAC */
1987 if (fb_find_mode(&var, info, mode_option, NULL,
1988 0, &defaultmode, 8) == 0)
1992 var.accel_flags &= ~FB_ACCELF_TEXT;
1993 // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
1995 if (aty128fb_check_var(&var, info)) {
1996 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
2000 /* setup the DAC the way we like it */
2001 dac = aty_ld_le32(DAC_CNTL);
2002 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
2004 if (par->chip_gen == rage_M3)
2005 dac |= DAC_PALETTE2_SNOOP_EN;
2006 aty_st_le32(DAC_CNTL, dac);
2008 /* turn off bus mastering, just in case */
2009 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
2012 fb_alloc_cmap(&info->cmap, 256, 0);
2014 var.activate = FB_ACTIVATE_NOW;
2016 aty128_init_engine(par);
2020 par->lock_blank = 0;
2022 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2024 aty128_bl_init(par);
2027 if (register_framebuffer(info) < 0)
2030 fb_info(info, "%s frame buffer device on %s\n",
2031 info->fix.id, video_card);
2033 return 1; /* success! */
2037 /* register a card ++ajoshi */
2038 static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2040 unsigned long fb_addr, reg_addr;
2041 struct aty128fb_par *par;
2042 struct fb_info *info;
2045 void __iomem *bios = NULL;
2048 /* Enable device in PCI config */
2049 if ((err = pci_enable_device(pdev))) {
2050 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
2055 fb_addr = pci_resource_start(pdev, 0);
2056 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
2058 printk(KERN_ERR "aty128fb: cannot reserve frame "
2063 reg_addr = pci_resource_start(pdev, 2);
2064 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
2066 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
2070 /* We have the resources. Now virtualize them */
2071 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
2073 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
2078 info->pseudo_palette = par->pseudo_palette;
2080 /* Virtualize mmio region */
2081 info->fix.mmio_start = reg_addr;
2082 par->regbase = pci_ioremap_bar(pdev, 2);
2086 /* Grab memory size from the card */
2087 // How does this relate to the resource length from the PCI hardware?
2088 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;
2090 /* Virtualize the framebuffer */
2091 info->screen_base = ioremap(fb_addr, par->vram_size);
2092 if (!info->screen_base)
2095 /* Set up info->fix */
2096 info->fix = aty128fb_fix;
2097 info->fix.smem_start = fb_addr;
2098 info->fix.smem_len = par->vram_size;
2099 info->fix.mmio_start = reg_addr;
2101 /* If we can't test scratch registers, something is seriously wrong */
2102 if (!register_test(par)) {
2103 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
2108 bios = aty128_map_ROM(par, pdev);
2111 bios = aty128_find_mem_vbios(par);
2114 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
2116 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
2117 aty128_get_pllinfo(par, bios);
2118 pci_unmap_rom(pdev, bios);
2120 #endif /* __sparc__ */
2122 aty128_timings(par);
2123 pci_set_drvdata(pdev, info);
2125 if (!aty128_init(pdev, ent))
2130 par->mtrr.vram = mtrr_add(info->fix.smem_start,
2131 par->vram_size, MTRR_TYPE_WRCOMB, 1);
2132 par->mtrr.vram_valid = 1;
2133 /* let there be speed */
2134 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
2136 #endif /* CONFIG_MTRR */
2140 iounmap(info->screen_base);
2142 iounmap(par->regbase);
2144 framebuffer_release(info);
2146 release_mem_region(pci_resource_start(pdev, 2),
2147 pci_resource_len(pdev, 2));
2149 release_mem_region(pci_resource_start(pdev, 0),
2150 pci_resource_len(pdev, 0));
2154 static void aty128_remove(struct pci_dev *pdev)
2156 struct fb_info *info = pci_get_drvdata(pdev);
2157 struct aty128fb_par *par;
2164 unregister_framebuffer(info);
2166 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2167 aty128_bl_exit(info->bl_dev);
2171 if (par->mtrr.vram_valid)
2172 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2174 #endif /* CONFIG_MTRR */
2175 iounmap(par->regbase);
2176 iounmap(info->screen_base);
2178 release_mem_region(pci_resource_start(pdev, 0),
2179 pci_resource_len(pdev, 0));
2180 release_mem_region(pci_resource_start(pdev, 2),
2181 pci_resource_len(pdev, 2));
2182 framebuffer_release(info);
2184 #endif /* CONFIG_PCI */
2189 * Blank the display.
2191 static int aty128fb_blank(int blank, struct fb_info *fb)
2193 struct aty128fb_par *par = fb->par;
2196 if (par->lock_blank || par->asleep)
2200 case FB_BLANK_NORMAL:
2203 case FB_BLANK_VSYNC_SUSPEND:
2206 case FB_BLANK_HSYNC_SUSPEND:
2209 case FB_BLANK_POWERDOWN:
2212 case FB_BLANK_UNBLANK:
2217 aty_st_8(CRTC_EXT_CNTL+1, state);
2219 if (par->chip_gen == rage_M3) {
2220 aty128_set_crt_enable(par, par->crt_on && !blank);
2221 aty128_set_lcd_enable(par, par->lcd_on && !blank);
2228 * Set a single color register. The values supplied are already
2229 * rounded down to the hardware's capabilities (according to the
2230 * entries in the var structure). Return != 0 for invalid regno.
2232 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2233 u_int transp, struct fb_info *info)
2235 struct aty128fb_par *par = info->par;
2238 || (par->crtc.depth == 16 && regno > 63)
2239 || (par->crtc.depth == 15 && regno > 31))
2248 u32 *pal = info->pseudo_palette;
2250 switch (par->crtc.depth) {
2252 pal[regno] = (regno << 10) | (regno << 5) | regno;
2255 pal[regno] = (regno << 11) | (regno << 6) | regno;
2258 pal[regno] = (regno << 16) | (regno << 8) | regno;
2261 i = (regno << 8) | regno;
2262 pal[regno] = (i << 16) | i;
2267 if (par->crtc.depth == 16 && regno > 0) {
2269 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2270 * have 32 slots for R and B values but 64 slots for G values.
2271 * Thus the R and B values go in one slot but the G value
2272 * goes in a different slot, and we have to avoid disturbing
2273 * the other fields in the slots we touch.
2275 par->green[regno] = green;
2277 par->red[regno] = red;
2278 par->blue[regno] = blue;
2279 aty128_st_pal(regno * 8, red, par->green[regno*2],
2282 red = par->red[regno/2];
2283 blue = par->blue[regno/2];
2285 } else if (par->crtc.bpp == 16)
2287 aty128_st_pal(regno, red, green, blue, par);
2292 #define ATY_MIRROR_LCD_ON 0x00000001
2293 #define ATY_MIRROR_CRT_ON 0x00000002
2295 /* out param: u32* backlight value: 0 to 15 */
2296 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32)
2297 /* in param: u32* backlight value: 0 to 15 */
2298 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32)
2300 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
2302 struct aty128fb_par *par = info->par;
2307 case FBIO_ATY128_SET_MIRROR:
2308 if (par->chip_gen != rage_M3)
2310 rc = get_user(value, (__u32 __user *)arg);
2313 par->lcd_on = (value & 0x01) != 0;
2314 par->crt_on = (value & 0x02) != 0;
2315 if (!par->crt_on && !par->lcd_on)
2317 aty128_set_crt_enable(par, par->crt_on);
2318 aty128_set_lcd_enable(par, par->lcd_on);
2320 case FBIO_ATY128_GET_MIRROR:
2321 if (par->chip_gen != rage_M3)
2323 value = (par->crt_on << 1) | par->lcd_on;
2324 return put_user(value, (__u32 __user *)arg);
2331 * Accelerated functions
2334 static inline void aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2335 u_int width, u_int height,
2336 struct fb_info_aty128 *par)
2338 u32 save_dp_datatype, save_dp_cntl, dstval;
2340 if (!width || !height)
2343 dstval = depth_to_dst(par->current_par.crtc.depth);
2344 if (dstval == DST_24BPP) {
2348 } else if (dstval == -EINVAL) {
2349 printk("aty128fb: invalid depth or RGBA\n");
2353 wait_for_fifo(2, par);
2354 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2355 save_dp_cntl = aty_ld_le32(DP_CNTL);
2357 wait_for_fifo(6, par);
2358 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2359 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2360 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2361 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR);
2363 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2364 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2366 par->blitter_may_be_busy = 1;
2368 wait_for_fifo(2, par);
2369 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2370 aty_st_le32(DP_CNTL, save_dp_cntl);
2375 * Text mode accelerated functions
2378 static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy,
2379 int dx, int height, int width)
2382 sy *= fontheight(p);
2384 dy *= fontheight(p);
2385 width *= fontwidth(p);
2386 height *= fontheight(p);
2388 aty128_rectcopy(sx, sy, dx, dy, width, height,
2389 (struct fb_info_aty128 *)p->fb_info);
2393 static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2396 struct pci_dev *pdev = par->pdev;
2398 if (!par->pdev->pm_cap)
2401 /* Set the chip into the appropriate suspend mode (we use D2,
2402 * D3 would require a complete re-initialisation of the chip,
2403 * including PCI config registers, clocks, AGP configuration, ...)
2405 * For resume, the core will have already brought us back to D0
2408 /* Make sure CRTC2 is reset. Remove that the day we decide to
2409 * actually use CRTC2 and replace it with real code for disabling
2410 * the CRTC2 output during sleep
2412 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2415 /* Set the power management mode to be PCI based */
2416 /* Use this magic value for now */
2418 aty_st_pll(POWER_MANAGEMENT, pmgt);
2419 (void)aty_ld_pll(POWER_MANAGEMENT);
2420 aty_st_le32(BUS_CNTL1, 0x00000010);
2421 aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2424 /* Switch PCI power management to D2 */
2425 pci_set_power_state(pdev, PCI_D2);
2429 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2431 struct fb_info *info = pci_get_drvdata(pdev);
2432 struct aty128fb_par *par = info->par;
2434 /* Because we may change PCI D state ourselves, we need to
2435 * first save the config space content so the core can
2436 * restore it properly on resume.
2438 pci_save_state(pdev);
2440 /* We don't do anything but D2, for now we return 0, but
2441 * we may want to change that. How do we know if the BIOS
2442 * can properly take care of D3 ? Also, with swsusp, we
2443 * know we'll be rebooted, ...
2445 #ifndef CONFIG_PPC_PMAC
2446 /* HACK ALERT ! Once I find a proper way to say to each driver
2447 * individually what will happen with it's PCI slot, I'll change
2448 * that. On laptops, the AGP slot is just unclocked, so D2 is
2449 * expected, while on desktops, the card is powered off
2452 #endif /* CONFIG_PPC_PMAC */
2454 if (state.event == pdev->dev.power.power_state.event)
2457 printk(KERN_DEBUG "aty128fb: suspending...\n");
2461 fb_set_suspend(info, 1);
2463 /* Make sure engine is reset */
2465 aty128_reset_engine(par);
2468 /* Blank display and LCD */
2469 aty128fb_blank(FB_BLANK_POWERDOWN, info);
2473 par->lock_blank = 1;
2475 #ifdef CONFIG_PPC_PMAC
2476 /* On powermac, we have hooks to properly suspend/resume AGP now,
2477 * use them here. We'll ultimately need some generic support here,
2478 * but the generic code isn't quite ready for that yet
2480 pmac_suspend_agp_for_card(pdev);
2481 #endif /* CONFIG_PPC_PMAC */
2483 /* We need a way to make sure the fbdev layer will _not_ touch the
2484 * framebuffer before we put the chip to suspend state. On 2.4, I
2485 * used dummy fb ops, 2.5 need proper support for this at the
2488 if (state.event != PM_EVENT_ON)
2489 aty128_set_suspend(par, 1);
2493 pdev->dev.power.power_state = state;
2498 static int aty128_do_resume(struct pci_dev *pdev)
2500 struct fb_info *info = pci_get_drvdata(pdev);
2501 struct aty128fb_par *par = info->par;
2503 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2506 /* PCI state will have been restored by the core, so
2507 * we should be in D0 now with our config space fully
2512 aty128_set_suspend(par, 0);
2515 /* Restore display & engine */
2516 aty128_reset_engine(par);
2518 aty128fb_set_par(info);
2519 fb_pan_display(info, &info->var);
2520 fb_set_cmap(&info->cmap, info);
2523 fb_set_suspend(info, 0);
2526 par->lock_blank = 0;
2527 aty128fb_blank(0, info);
2529 #ifdef CONFIG_PPC_PMAC
2530 /* On powermac, we have hooks to properly suspend/resume AGP now,
2531 * use them here. We'll ultimately need some generic support here,
2532 * but the generic code isn't quite ready for that yet
2534 pmac_resume_agp_for_card(pdev);
2535 #endif /* CONFIG_PPC_PMAC */
2537 pdev->dev.power.power_state = PMSG_ON;
2539 printk(KERN_DEBUG "aty128fb: resumed !\n");
2544 static int aty128_pci_resume(struct pci_dev *pdev)
2549 rc = aty128_do_resume(pdev);
2556 static int aty128fb_init(void)
2559 char *option = NULL;
2561 if (fb_get_options("aty128fb", &option))
2563 aty128fb_setup(option);
2566 return pci_register_driver(&aty128fb_driver);
2569 static void __exit aty128fb_exit(void)
2571 pci_unregister_driver(&aty128fb_driver);
2574 module_init(aty128fb_init);
2576 module_exit(aty128fb_exit);
2578 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2579 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2580 MODULE_LICENSE("GPL");
2581 module_param(mode_option, charp, 0);
2582 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2584 module_param_named(nomtrr, mtrr, invbool, 0);
2585 MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");