2 * tdo24m - SPI-based drivers for Toppoly TDO24M series LCD panels
4 * Copyright (C) 2008 Marvell International Ltd.
5 * Eric Miao <eric.miao@marvell.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * publishhed by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spi/tdo24m.h>
19 #include <linux/lcd.h>
20 #include <linux/slab.h>
22 #define POWER_IS_ON(pwr) ((pwr) <= FB_BLANK_NORMAL)
24 #define TDO24M_SPI_BUFF_SIZE (4)
29 struct spi_device *spi_dev;
30 struct lcd_device *lcd_dev;
32 struct spi_message msg;
33 struct spi_transfer xfer;
36 int (*adj_mode)(struct tdo24m *lcd, int mode);
43 /* use bit 30, 31 as the indicator of command parameter number */
44 #define CMD0(x) ((0 << 30) | (x))
45 #define CMD1(x, x1) ((1 << 30) | ((x) << 9) | 0x100 | (x1))
46 #define CMD2(x, x1, x2) ((2 << 30) | ((x) << 18) | 0x20000 |\
47 ((x1) << 9) | 0x100 | (x2))
50 static uint32_t lcd_panel_reset[] = {
51 CMD0(0x1), /* reset */
58 static uint32_t lcd_panel_on[] = {
59 CMD0(0x29), /* Display ON */
60 CMD2(0xB8, 0xFF, 0xF9), /* Output Control */
61 CMD0(0x11), /* Sleep out */
62 CMD1(0xB0, 0x16), /* Wake */
66 static uint32_t lcd_panel_off[] = {
67 CMD0(0x28), /* Display OFF */
68 CMD2(0xB8, 0x80, 0x02), /* Output Control */
69 CMD0(0x10), /* Sleep in */
70 CMD1(0xB0, 0x00), /* Deep stand by in */
74 static uint32_t lcd_vga_pass_through_tdo24m[] = {
83 static uint32_t lcd_qvga_pass_through_tdo24m[] = {
92 static uint32_t lcd_vga_transfer_tdo24m[] = {
93 CMD1(0xcf, 0x02), /* Blanking period control (1) */
94 CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
95 CMD1(0xd1, 0x01), /* CKV timing control on/off */
96 CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
97 CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
98 CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
99 CMD1(0xd5, 0x14), /* ASW timing control (2) */
100 CMD0(0x21), /* Invert for normally black display */
101 CMD0(0x29), /* Display on */
105 static uint32_t lcd_qvga_transfer[] = {
106 CMD1(0xd6, 0x02), /* Blanking period control (1) */
107 CMD2(0xd7, 0x08, 0x04), /* Blanking period control (2) */
108 CMD1(0xd8, 0x01), /* CKV timing control on/off */
109 CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
110 CMD2(0xde, 0x05, 0x0a), /* OEV timing control */
111 CMD2(0xdf, 0x0a, 0x19), /* ASW timing control (1) */
112 CMD1(0xe0, 0x0a), /* ASW timing control (2) */
113 CMD0(0x21), /* Invert for normally black display */
114 CMD0(0x29), /* Display on */
118 static uint32_t lcd_vga_pass_through_tdo35s[] = {
126 static uint32_t lcd_qvga_pass_through_tdo35s[] = {
134 static uint32_t lcd_vga_transfer_tdo35s[] = {
135 CMD1(0xcf, 0x02), /* Blanking period control (1) */
136 CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
137 CMD1(0xd1, 0x01), /* CKV timing control on/off */
138 CMD2(0xd2, 0x00, 0x1e), /* CKV 1,2 timing control */
139 CMD2(0xd3, 0x14, 0x28), /* OEV timing control */
140 CMD2(0xd4, 0x28, 0x64), /* ASW timing control (1) */
141 CMD1(0xd5, 0x28), /* ASW timing control (2) */
142 CMD0(0x21), /* Invert for normally black display */
143 CMD0(0x29), /* Display on */
147 static uint32_t lcd_panel_config[] = {
148 CMD2(0xb8, 0xff, 0xf9), /* Output control */
149 CMD0(0x11), /* sleep out */
150 CMD1(0xba, 0x01), /* Display mode (1) */
151 CMD1(0xbb, 0x00), /* Display mode (2) */
152 CMD1(0x3a, 0x60), /* Display mode 18-bit RGB */
153 CMD1(0xbf, 0x10), /* Drive system change control */
154 CMD1(0xb1, 0x56), /* Booster operation setup */
155 CMD1(0xb2, 0x33), /* Booster mode setup */
156 CMD1(0xb3, 0x11), /* Booster frequency setup */
157 CMD1(0xb4, 0x02), /* Op amp/system clock */
158 CMD1(0xb5, 0x35), /* VCS voltage */
159 CMD1(0xb6, 0x40), /* VCOM voltage */
160 CMD1(0xb7, 0x03), /* External display signal */
161 CMD1(0xbd, 0x00), /* ASW slew rate */
162 CMD1(0xbe, 0x00), /* Dummy data for QuadData operation */
163 CMD1(0xc0, 0x11), /* Sleep out FR count (A) */
164 CMD1(0xc1, 0x11), /* Sleep out FR count (B) */
165 CMD1(0xc2, 0x11), /* Sleep out FR count (C) */
166 CMD2(0xc3, 0x20, 0x40), /* Sleep out FR count (D) */
167 CMD2(0xc4, 0x60, 0xc0), /* Sleep out FR count (E) */
168 CMD2(0xc5, 0x10, 0x20), /* Sleep out FR count (F) */
169 CMD1(0xc6, 0xc0), /* Sleep out FR count (G) */
170 CMD2(0xc7, 0x33, 0x43), /* Gamma 1 fine tuning (1) */
171 CMD1(0xc8, 0x44), /* Gamma 1 fine tuning (2) */
172 CMD1(0xc9, 0x33), /* Gamma 1 inclination adjustment */
173 CMD1(0xca, 0x00), /* Gamma 1 blue offset adjustment */
174 CMD2(0xec, 0x01, 0xf0), /* Horizontal clock cycles */
178 static int tdo24m_writes(struct tdo24m *lcd, uint32_t *array)
180 struct spi_transfer *x = &lcd->xfer;
181 uint32_t data, *p = array;
182 int nparams, err = 0;
184 for (; *p != CMD_NULL; p++) {
185 if (!lcd->color_invert && *p == CMD0(0x21))
188 nparams = (*p >> 30) & 0x3;
190 data = *p << (7 - nparams);
193 lcd->buf[0] = (data >> 8) & 0xff;
194 lcd->buf[1] = data & 0xff;
197 lcd->buf[0] = (data >> 16) & 0xff;
198 lcd->buf[1] = (data >> 8) & 0xff;
199 lcd->buf[2] = data & 0xff;
202 lcd->buf[0] = (data >> 24) & 0xff;
203 lcd->buf[1] = (data >> 16) & 0xff;
204 lcd->buf[2] = (data >> 8) & 0xff;
205 lcd->buf[3] = data & 0xff;
210 x->len = nparams + 2;
211 err = spi_sync(lcd->spi_dev, &lcd->msg);
219 static int tdo24m_adj_mode(struct tdo24m *lcd, int mode)
223 tdo24m_writes(lcd, lcd_vga_pass_through_tdo24m);
224 tdo24m_writes(lcd, lcd_panel_config);
225 tdo24m_writes(lcd, lcd_vga_transfer_tdo24m);
228 tdo24m_writes(lcd, lcd_qvga_pass_through_tdo24m);
229 tdo24m_writes(lcd, lcd_panel_config);
230 tdo24m_writes(lcd, lcd_qvga_transfer);
240 static int tdo35s_adj_mode(struct tdo24m *lcd, int mode)
244 tdo24m_writes(lcd, lcd_vga_pass_through_tdo35s);
245 tdo24m_writes(lcd, lcd_panel_config);
246 tdo24m_writes(lcd, lcd_vga_transfer_tdo35s);
249 tdo24m_writes(lcd, lcd_qvga_pass_through_tdo35s);
250 tdo24m_writes(lcd, lcd_panel_config);
251 tdo24m_writes(lcd, lcd_qvga_transfer);
261 static int tdo24m_power_on(struct tdo24m *lcd)
265 err = tdo24m_writes(lcd, lcd_panel_on);
269 err = tdo24m_writes(lcd, lcd_panel_reset);
273 err = lcd->adj_mode(lcd, lcd->mode);
278 static int tdo24m_power_off(struct tdo24m *lcd)
280 return tdo24m_writes(lcd, lcd_panel_off);
283 static int tdo24m_power(struct tdo24m *lcd, int power)
287 if (POWER_IS_ON(power) && !POWER_IS_ON(lcd->power))
288 ret = tdo24m_power_on(lcd);
289 else if (!POWER_IS_ON(power) && POWER_IS_ON(lcd->power))
290 ret = tdo24m_power_off(lcd);
299 static int tdo24m_set_power(struct lcd_device *ld, int power)
301 struct tdo24m *lcd = lcd_get_data(ld);
302 return tdo24m_power(lcd, power);
305 static int tdo24m_get_power(struct lcd_device *ld)
307 struct tdo24m *lcd = lcd_get_data(ld);
311 static int tdo24m_set_mode(struct lcd_device *ld, struct fb_videomode *m)
313 struct tdo24m *lcd = lcd_get_data(ld);
314 int mode = MODE_QVGA;
316 if (m->xres == 640 || m->xres == 480)
319 if (lcd->mode == mode)
322 return lcd->adj_mode(lcd, mode);
325 static struct lcd_ops tdo24m_ops = {
326 .get_power = tdo24m_get_power,
327 .set_power = tdo24m_set_power,
328 .set_mode = tdo24m_set_mode,
331 static int tdo24m_probe(struct spi_device *spi)
334 struct spi_message *m;
335 struct spi_transfer *x;
336 struct tdo24m_platform_data *pdata;
337 enum tdo24m_model model;
340 pdata = spi->dev.platform_data;
342 model = pdata->model;
346 spi->bits_per_word = 8;
347 spi->mode = SPI_MODE_3;
348 err = spi_setup(spi);
352 lcd = devm_kzalloc(&spi->dev, sizeof(struct tdo24m), GFP_KERNEL);
357 lcd->power = FB_BLANK_POWERDOWN;
358 lcd->mode = MODE_VGA; /* default to VGA */
360 lcd->buf = devm_kzalloc(&spi->dev, TDO24M_SPI_BUFF_SIZE, GFP_KERNEL);
361 if (lcd->buf == NULL)
370 x->tx_buf = &lcd->buf[0];
371 spi_message_add_tail(x, m);
375 lcd->color_invert = 1;
376 lcd->adj_mode = tdo24m_adj_mode;
379 lcd->adj_mode = tdo35s_adj_mode;
380 lcd->color_invert = 0;
383 dev_err(&spi->dev, "Unsupported model");
387 lcd->lcd_dev = lcd_device_register("tdo24m", &spi->dev,
389 if (IS_ERR(lcd->lcd_dev))
390 return PTR_ERR(lcd->lcd_dev);
392 dev_set_drvdata(&spi->dev, lcd);
393 err = tdo24m_power(lcd, FB_BLANK_UNBLANK);
400 lcd_device_unregister(lcd->lcd_dev);
404 static int tdo24m_remove(struct spi_device *spi)
406 struct tdo24m *lcd = dev_get_drvdata(&spi->dev);
408 tdo24m_power(lcd, FB_BLANK_POWERDOWN);
409 lcd_device_unregister(lcd->lcd_dev);
415 static int tdo24m_suspend(struct spi_device *spi, pm_message_t state)
417 struct tdo24m *lcd = dev_get_drvdata(&spi->dev);
419 return tdo24m_power(lcd, FB_BLANK_POWERDOWN);
422 static int tdo24m_resume(struct spi_device *spi)
424 struct tdo24m *lcd = dev_get_drvdata(&spi->dev);
426 return tdo24m_power(lcd, FB_BLANK_UNBLANK);
429 #define tdo24m_suspend NULL
430 #define tdo24m_resume NULL
433 /* Power down all displays on reboot, poweroff or halt */
434 static void tdo24m_shutdown(struct spi_device *spi)
436 struct tdo24m *lcd = dev_get_drvdata(&spi->dev);
438 tdo24m_power(lcd, FB_BLANK_POWERDOWN);
441 static struct spi_driver tdo24m_driver = {
444 .owner = THIS_MODULE,
446 .probe = tdo24m_probe,
447 .remove = tdo24m_remove,
448 .shutdown = tdo24m_shutdown,
449 .suspend = tdo24m_suspend,
450 .resume = tdo24m_resume,
453 module_spi_driver(tdo24m_driver);
455 MODULE_AUTHOR("Eric Miao <eric.miao@marvell.com>");
456 MODULE_DESCRIPTION("Driver for Toppoly TDO24M LCD Panel");
457 MODULE_LICENSE("GPL");
458 MODULE_ALIAS("spi:tdo24m");